LD7575

LD7575
LD7575
11/29/2007
Green-Mode PWM Controller with High-Voltage
Start-Up Circuit
REV: 04b
General Description
Features
The LD7575 is a current-mode PWM controller with
z
High-Voltage (500V) Startup Circuit
excellent power-saving operation.
It features a high-
z
Current Mode Control
voltage current source to directly supply the startup current
z
Non-Audible-Noise Green Mode Control
from bulk capacitor and further to provide a lossless startup
z
UVLO (Under Voltage Lockout)
circuit.
z
LEB (Leading-Edge Blanking) on CS Pin
blanking of the current sensing, internal slope compensation,
z
Programmable Switching Frequency
and the small package provide the users a high efficiency,
z
Internal Slope Compensation
minimum external component counts, and low cost solution
z
OVP (Over Voltage Protection) on Vcc
for AC/DC power applications.
z
OLP (Over Load Protection)
z
500mA Driving Capability
The integrated functions such as the leading-edge
Furthermore, the embedded over voltage protection, over
load protection and the special green-mode control provide
Applications
the solution for users to design a high performance power
circuit easily.
The LD7575 is offered in both SOP-8 and
DIP-8 package.
Typical Application
1
Leadtrend Technology Corporation
LD7575-DS-04b November 2007
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z
Switching AC/DC Adapter and Battery Charger
z
Open Frame Switching Power Supply
z
LCD Monitor/TV Power
LD7575
Pin Configuration
HV
NC
VCC
OUT
SOP-8 & DIP-8 (TOP VIEW)
8
7
6
5
YY:
WW:
PP:
TOP MARK
2
3
4
CS
GND
RT
1
COMP
YYWWPP
Year code
Week code
Production code
Ordering Information
Part number
Package
Top Mark
Shipping
LD7575 PS
SOP-8
PB Free
LD7575PS
2500 /tape & reel
LD7575 GS
SOP-8
Green Package
LD7575GS
2500 /tape & reel
LD7575 PN
DIP-8
PB Free
LD7575PN
3600 /tube /Carton
The LD7575 is ROHS compliant/ Green Package.
Pin Descriptions
PIN
NAME
FUNCTION
1
RT
2
COMP
3
CS
4
GND
Ground
5
OUT
Gate drive output to drive the external MOSFET
6
VCC
Supply voltage pin
7
NC
Unconnected Pin
This pin will program the switching frequency, to connect a resistor with ground to
set the switching frequency.
Voltage feedback pin (same as the COMP pin in UC384X), By connecting a
photo-coupler to close the control loop and achieve the regulation.
Current sense pin, connect to sense the MOSFET current
Connect this pin to positive terminal of bulk capacitor to provide the startup current
8
HV
for the controller. When Vcc voltage trips the UVLO(on), this HV loop will be off to
save the power loss on the startup circuit.
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LD7575
Block Diagram
HV
1mA
8V
POR
UVLO
Comparator
32V
OVP
Comparator
internal bias
& Vref
16.0V/
10.0V
VCC
27.5V
VCC OK
RT
PG
OSC
Vref OK
S
Q
R
OVP
Green-Mode
Control
PG
Vbias
S
Q
PWM
Comparator
COMP
2R
OLP
R
R
∑
+
Leading
Edge
Blanking
CS
+
Slope
Compensation
Driver
Stage
POR
OCP
Comparator
0.85V
clear
30mS
Delay
5.0V
OLP
Comparator
S
/2
Counter
PG
GND
3
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LD7575-DS-04b November 2007
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R
Q
OUT
LD7575
Absolute Maximum Ratings
Supply Voltage VCC
30V
High-Voltage Pin, HV
-0.3V~500V
COMP, RT, CS
-0.3 ~7V
Junction Temperature
150°C
Operating Ambient Temperature
-40°C to 85°C
Storage Temperature Range
-65°C to 150°C
Package Thermal Resistance (SOP-8)
160°C/W
Package Thermal Resistance (DIP-8)
100°C/W
Power Dissipation (SOP-8, at Ambient Temperature = 85°C)
400mW
Power Dissipation (DIP-8, at Ambient Temperature = 85°C)
650mW
Lead temperature (Soldering, 10sec)
260°C
ESD Voltage Protection, Human Body Model (except HV Pin)
3KV
ESD Voltage Protection, Machine Model
200V
Gate Output Current
500mA
Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.
Recommended Operating Conditions
Item
Min.
Max.
Supply Voltage Vcc
11
25
V
Vcc Capacitor
10
47
μF
Switching Frequency
50
130
KHz
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Leadtrend Technology Corporation
LD7575-DS-04b November 2007
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Unit
LD7575
Electrical Characteristics
o
(TA = +25 C unless otherwise stated, VCC=15.0V)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.5
1.0
1.5
mA
35
μA
100
μA
High-Voltage Supply (HV Pin)
High-Voltage Current Source
Vcc< UVLO(on), HV=500V
Off-State Leakage Current
Vcc> UVLO(off), HV=500V
Supply Voltage (Vcc Pin)
Startup Current
Operating Current
(with 1nF load on OUT pin)
VCOMP=0V
2.0
3.0
mA
VCOMP=3V
2.5
4.0
mA
Protection tripped (OLP, OVP)
0.5
mA
UVLO (off)
9.0
10.0
11.0
V
UVLO (on)
15.0
16.0
17.0
V
OVP Level
25.0
27.5
30.0
V
2.2
mA
Voltage Feedback (Comp Pin)
Short Circuit Current
VCOMP=0V
1.5
Open Loop Voltage
COMP pin open
6.0
V
2.35
V
Green Mode Threshold VCOMP
Current Sensing (CS Pin)
Maximum Input Voltage
0.80
Leading Edge Blanking Time
0.85
0.90
350
Input impedance
nS
1
Delay to Output
V
MΩ
100
nS
Oscillator (RT pin)
Frequency
RT=100KΩ
60.0
65.0
70.0
Green Mode Frequency
Fs=65.0KHz
Temp. Stability
(-40°C ~105°C)
3
%
Voltage Stability
(VCC=11V-25V)
1
%
Output Low Level
VCC=15V, Io=20mA
1
V
Output High Level
VCC=15V, Io=20mA
Rising Time
Load Capacitance=1000pF
50
160
nS
Falling Time
Load Capacitance=1000pF
30
60
nS
20
KHz
KHz
Gate Drive Output (OUT Pin)
9
V
OLP (Over Load Protection)
OLP Trip Level
OLP Delay Time (note)
Fs=65KHz
Note: The OLP delay time is proportional to the period of switching cycle.
frequency and the shorter OLP delay time.
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5.0
V
30
mS
So that, the lower RT value will set the higher switching
LD7575
Typical Performance Characteristics
0.90
0.89
1.3
VCS (off) (V)
HV Current Source (mA)
1.5
1.1
0.88
0.87
0.9
0.86
0.7
-40
0
40
80
0.85
120 125
-40
0
Temperature (°C)
Fig. 2
18.0
12
17.2
11.2
UVLO (off) (V)
UVLO (on) (V)
Fig. 1 HV Current Source vs. Temperature (HV=500V, Vcc=0V)
16.4
15.6
125
120
125
120
125
Temperature (°C)
VCS (off) vs. Temperature
9.6
8
-40
0
40
80
120 125
-40
0
40
80
Temperature (°C)
Fig. 4 UVLO (off ) vs. Temperature
70
26
68
24
Frequency (KHz)
Frequency (KHz)
120
10.4
Temperature (°C)
Fig. 3 UVLO (on) vs. Temperature
66
64
22
20
18
62
60
80
8.8
14.8
14.0
40
16
-40
0
40
80
120
125
-40
LD7575-DS-04b November 2007
40
80
Fig. 6 Green Mode Frequency vs. Temperature
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Leadtrend Technology Corporation
0
Temperature (°C)
Temperature (°C)
Fig. 5 Frequency vs. Temperature
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LD7575
25
Green mode frequency (KHz)
70
Frequency (KHz)
68
66
64
62
12
14
16
18
20
22
24
21
19
17
15
11
25
12
14
16
22
Fig. 7 Frequency vs. Vcc
Fig. 8 Green mode frequency vs. Vcc
35
80
30
75
70
65
24
25
120
125
120
125
25
20
15
60
10
-40
0
40
80
120 125
-40
40
0
80
Temperature (°C)
Temperature (°C)
Fig. 10
Fig. 9 Max Duty vs. Temperature
7.0
6.0
6.5
5.5
6.0
5.0
OLP (V)
VCOMP (V)
20
Vcc (V)
85
5.5
5.0
4.5
18
Vcc (V)
VCC OVP (V)
Max Duty (%)
60
11
23
VCC OVP vs. Temperature
4.5
4.0
-40
0
40
80
3.5
120 125
-40
0
Temperature (°C)
Fig. 11 VCOMP open loop voltage vs. Temperature
Fig. 12
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40
80
Temperature (°C)
OLP-Trip Level vs. Temperature
LD7575
Application Information
threshold thus the current source is on to supply a current
Operation Overview
with 1mA. Meanwhile, the Vcc supply current is as low as
As long as the green power requirement becomes a trend
100μA thus most of the HV current is utilized to charge the
and the power saving is getting more and more important for
Vcc capacitor.
the switching power supplies and switching adaptors, the
By using such configuration, the turn-on
delay time will be almost same no matter under low-line or
traditional PWM controllers are not able to support such new
high-line conditions.
requirements. Furthermore, the cost and size limitation force
Whenever the Vcc voltage is higher than UVLO(on) to
the PWM controllers need to be powerful to integrate more
power on the LD7575 and further to deliver the gate drive
functions to reduce the external part counts. The LD7575
signal, the high-voltage current source is off and the supply
is targeted on such application to provide an easy and cost
current is provided from the auxiliary winding of the
effective solution; its detail features are described as below:
transformer.
Therefore, the power losses on the startup
circuit can be eliminated and the power saving can be easily
Internal High-Voltage Startup Circuit and
achieved.
Under Voltage Lockout (UVLO)
An UVLO comparator is included to detect the voltage on
the Vcc pin to ensure the supply voltage enough to power
on the LD7575 PWM controller and in addition to drive the
Vin
power MOSFET.
As shown in Fig. 14, a hysteresis is
provided to prevent the shutdown from the voltage dip
Cbulk
D1
R1
during startup.
The turn-on and turn-off threshold level are
set at 16V and 10.0V, respectively.
C1
Vcc
HV
VCC
OUT
UVLO(on)
LD7575
UVLO(off)
CS
Comp
GND
Rs
t
Fig. 13
HV Current
Traditional circuit powers up the PWM controller through a
1mA
startup resistor to provide the startup current. However, the
startup resistor consumes significant power which is more
~ 0mA (off)
and more critical whenever the power saving requirement is
coming tight.
t
Theoretically, this startup resistor can be
very high resistance value. However, higher resistor value
Vcc current
will cause longer startup time.
Operating Current
(Supply from Auxiliary Winding)
To achieve an optimized topology, as shown in figure 13,
Startup Current
(<100uA)
LD7575 implements a high-voltage startup circuit for such
requirement. During the startup, a high-voltage current
source sinks current from the bulk capacitor to provide the
startup current as well as charge the Vcc capacitor C1.
Fig. 14
During the startup transient, the Vcc is lower than the UVLO
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LD7575
Current Sensing, Leading-edge Blanking and
the Negative Spike on CS Pin
The typical current mode PWM controller feedbacks both
current signal and voltage signal to close the control loop
and achieve regulation. The LD7575 detects the primary
MOSFET current from the CS pin, which is not only for the
peak current mode control but also for the pulse-by-pulse
current limit. The maximum voltage threshold of the current
sensing pin is set as 0.85V. Thus the MOSFET peak current
can be calculated as:
IPEAK(MAX) =
0.85 V
RS
A 350nS leading-edge blanking (LEB) time is included in the
input of CS pin to prevent the false-trigger caused by the
current spike. In the low power application, if the total pulse
width of the turn-on spikes is less than 350nS and the
negative spike on the CS pin is not exceed -0.3V, the R-C
filter (as shown in figure15) can be eliminated.
However, the total pulse width of the turn-on spike is related
to the output power, circuit design and PCB layout.
Fig. 15
It is
strongly recommended to add the small R-C filter (as shown
in figure 16) for higher power application to avoid the CS pin
damaged by the negative turn-on spike.
Output Stage and Maximum Duty-Cycle
An output stage of a CMOS buffer, with typical 500mA
driving capability, is incorporated to drive a power MOSFET
directly.
And the maximum duty-cycle of LD7575 is limited
to 75% to avoid the transformer saturation.
Voltage Feedback Loop
The voltage feedback signal is provided from the TL431 in
the secondary side through the photo-coupler to the COMP
pin of LD7575.
The input stage of LD7575, like the
UC384X, is with 2 diodes voltage offset then feeding into the
voltage divider with 1/3 ratio, that is,
V+ (PWM COMPARATOR ) =
1
× ( VCOMP − 2VF )
3
A pull-high resistor is embedded internally thus can be
Fig. 16
eliminated on the external circuit.
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LD7575
threshold 5.0V and keeps longer than 30mS (when
Oscillator and Switching Frequency
switching frequency is 65KHz), the protection is activated
Connecting a resistor from RT pin to GND according to the
and then turns off the gate output to stop the switching of
equation can program the normal switching frequency:
fSW =
power circuit.
65.0
× 100(KHz)
RT(KΩ )
The 30mS delay time is to prevent the false
trigger from the power-on and turn-off transient.
A divide-2 counter is implemented to reduce the average
power under OLP behavior.
Whenever OLP is activated,
The suggested operating frequency range of LD7575 is
the output is latched off and the divide-2 counter starts to
within 50KHz to 130KHz.
count the number of UVLO(off).
The latch is released if
the 2nd UVLO(off) point is counted then the output is
recovery to switching again.
Internal Slope Compensation
By using such protection mechanism, the average input
A fundamental issue of current mode control is the stability
power can be reduced to very low level so that the
problem when its duty-cycle is operated more than 50%. To
component temperature and stress can be controlled within
stabilize the control loop, the slope compensation is needed
the safe operating area.
in the traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In LD7575,
the
internal
slope
compensation
circuit
has
been
implemented to simplify the external circuit design.
On/Off Control
The LD7575 can be controlled to turn off by pulling COMP
pin to lower than 1.2V.
The gate output pin of LD7575 will
be disabled immediately under such condition. The off mode
can be released when the pull-low signal is removed.
Dual-Oscillator Green-Mode Operation
There
are
many
difference
topologies
has
been
implemented in different chips for the green-mode or power
saving
requirements
such
as
“burst-mode
control”,
“skipping-cycle Mode”, “variable off-time control “…etc. The
basic operation theory of all these approaches intended to
reduce the switching cycles under light-load or no-load
Fig. 17
condition either by skipping some switching pulses or
reduce the switching frequency.
OVP (Over Voltage Protection) on Vcc
The Vgs ratings of the nowadays power MOSFETs are most
with maximum 30V. To prevent the Vgs from the fault
Over Load Protection (OLP)
condition, LD7575 is implemented an OVP function on Vcc.
To protect the circuit from the damage during over load
Whenever the Vcc voltage is higher than the OVP threshold
condition or short condition, a smart OLP function is
voltage, the output gate drive circuit will be shutdown
implemented in the LD7575. Figure 17 shows the
waveforms of the OLP operation.
simultaneous thus to stop the switching of the power
Under such fault
MOSFET until the next UVLO(on).
condition, the feedback system will force the voltage loop
The Vcc OVP function in LD7575 is an auto-recovery type
toward the saturation and thus pull the voltage on COMP pin
(VCOMP) to high.
protection.
Whenever the VCOMP trips the OLP
feedback loop opened, is not released, the Vcc will tripped
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LD7575-DS-04b November 2007
If the OVP condition, usually caused by the
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LD7575
the OVP level again and re-shutdown the output.
is working as a hiccup mode.
disconnected.
The Vcc
In such single-fault condition, as show in
figure 21, the resistor R8 can provide a discharge path to
Figure 18 shows its
operation.
avoid the MOSFET from being false-triggered by the current
On the other hand, if the OVP condition is removed, the Vcc
through the gate-to-drain capacitor Cgd.
level will get back to normal level and the output is
MOSFET is always pull-low and kept in the off-state
automatically returned to the normal operation.
whenever the gate resistor is disconnected or opened in any
case.
VCC
OVP Tripped
OVP Level
UVLO(on)
UVLO(off)
t
OUT
Switching
Non-Switching
Switching
t
Fig. 18
Fault Protection
A lot of protection features have been implemented in the
LD7575 to prevent the power supply or adapter from being
damaged caused by single fault condition on the open or
Fig. 19
short condition on the pin of LD7575. Under the conditions
listed below, the gate output will be off immediately to
protect the power circuit --y
RT pin short to ground
y
RT pin floating
y
CS pin floating
Pull-Low Resistor on the Gate Pin of MOSFET
In LD7575, an anti-floating resistor is implemented on the
OUT pin to prevent the output from any uncertain state
which may causes the MOSFET working abnormally or false
triggered-on.
However, such design won’t cover the
condition of disconnection of gate resistor Rg thus it is still
strongly recommended to have a resistor connected on the
MOSFET gate terminal (as shown in figure 19) to provide
extra protection for fault condition.
This external pull-low resistor is to prevent the MOSFET
from damage during power-on under the gate resistor is
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Therefore, the
LD7575
Protection Resistor on the Hi-V Path
In some other Hi-V process and design, there may cause a
parasitic SCR between HV pin, Vcc and GND.
As shown
in figure 22, a small negative spike on the HV pin may
trigger this parasitic SCR and causes the latchup between
dV
i = Cgd ⋅ bulk
dt
Vcc and GND.
And such latchup is easy to damage the
chip because of the equivalent short-circuit which is induced
by such latchup behavior.
Thanks to the Leadtrend’s proprietary Hi-V technology,
there is no such parasitic SCR in LD7575.
Figure 23
shows the equivalent circuit of LD7575’s Hi-V structure.
So that LD7575 is with higher capability to sustain negative
voltage than similar products. However, a 10KΩ resistor is
recommended to implement on the Hi-V path to be played
the role as a current limit resistor whenever a negative
voltage is applied in any case.
Fig. 20
Fig. 21
Fig. 22
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LD7575
Reference Application Circuit --- 10W (5V/2A) Adapter
Pin < 0.15W when Pout = 0W & Vin = 264Vac
Schematic
L
AC
input
N
F1
R1A
R1B
NTC1
Z1
CX1
8
2
LD7575
COMP
HV
1
FL1
IC1
RT
RT
3
5
R9
OUT
CS
D1A~D1D
C1
VCC
6
4
GND
D2
C2
R7
R6
R4A
R4B
R8
C5
D4
C4
RS1
T1
Q1
RS2
C51
C52
R56A ZD51
R54
L51
C55
R55
R56B
R52
R53
C54
LD7575-DS-04b November 2007
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R51B
R51A
CR51
IC2
photocoupler
CY1
IC5
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Leadtrend Technology Corporation
LD7575
BOM
P/N
Component Value
Original
P/N
Component Value
Note
R1A
N/A
C1
22μF, 400V
R1B
N/A
C2
22μF, 50V
L-tec
R4A
39KΩ, 1206
C4
1000pF, 1000V, 1206
Holystone
R4B
39KΩ, 1206
C5
0.01μF, 16V, 0805
R6
2.2Ω, 1206
C51
1000pF, 50V, 0805
R7
10Ω, 1206
C52
1000μF, 10V
L-tec
R8
10KΩ, 1206
C54
470μF, 10V
L-tec
R9
10KΩ, 1206
C55
0.022μF, 16V, 0805
RS1
2.7Ω, 1206, 1%
CX1
0.1μF
X-cap
RS2
2.7Ω, 1206, 1%
CY1
2200pF
Y-cap
RT
100KΩ, 0805, 1%
D1A
1N4007
R51A
100Ω, 1206
D1B
1N4007
R51B
100Ω, 1206
D1C
1N4007
R52
2.49KΩ, 0805, 1%
D1D
1N4007
R53
2.49KΩ, 0805, 1%
D2
PS102R
R54
100Ω, 0805
D4
1N4007
R55
1KΩ, 0805
Q1
2N60B
R56A
2.7KΩ, 1206
CR51
SB540
R56B
N/A
ZD51
6V2C
NTC1
5Ω, 3A
08SP005
IC1
LD7575PS
FL1
20mH
UU9.8
IC2
EL817B
T1
EI-22
IC51
TL431
L51
2.7μH
F1
250V, 1A
Z1
N/A
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L-tec
600V, 2A
SOP-8
1%
LD7575
Package Information
SOP-8
Dimensions in Millimeters
Dimensions in Inch
Symbols
MIN
MAX
MIN
MAX
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.229
0.007
0.009
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
θ
0°
8°
0°
8°
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LD7575
Package Information
DIP-8
Dimension in Millimeters
Dimensions in Inches
Symbol
Min
Max
Min
Max
A
9.017
10.160
0.355
0.400
B
6.096
7.112
0.240
0.280
C
-----
5.334
------
0.210
D
0.356
0.584
0.014
0.023
E
1.143
1.778
0.045
0.070
F
2.337
2.743
0.092
0.108
I
2.921
3.556
0.115
0.140
J
7.366
8.255
0.29
0.325
L
0.381
------
0.015
--------
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should
verify the datasheets are current and complete before placing order.
0
□
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Leadtrend Technology Corporation
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www.leadtrend.com.tw
LD7575
Revision History
Rev.
Date
Change Notice
00
07/21/’05
Original Specification.
01
07/28/’05
1.
Page 2, Remove the unexpected code “skype.lnk” before the “ordering information”.
2.
Page 4, Recommended operating condition, change the “min. supply voltage Vcc”
from 10V to 11V since the UVLO range is from 9V to 11V.
3.
Page 9, Add the gate resistor on figure 15 and figure 16 to avoid misunderstanding.
4.
Page 11, Add the description “Figure 17 shows its operation.” In the section of “OVP
on Vcc”.
02
10/24/’05
5.
Page 13, Add “Vin=264Vac” on the title.
1.
Add DIP-8 Package
a.
Page 1 --- modify the general description “The LD7575 is offered in both
SOP-8 and DIP-8 package.”.
b.
Page 2 --- Add DIP-8 data on the “pin configuration” and “ordering
information”.
2.
c.
Page 4 --- Add DIP-8 data on the “absolute maximum rating”.
d.
Page 15 --- Add DIP-8 package drawing
Add information of HV current limit resistor and gate-to-GND resistor
a.
Page 1, 8 (figure13), 9 (figure15,16), 12, 13 --- Update the drawing, BOM and
schematics for such resistors.
b.
Page 11, 12 --- Add the sections “Pull-Low Resistor on the Gate Pin of
MOSFET”, “Protection Resistor on the Hi-V Path” and figure 19~22.
c.
Page 4 --- Add negative voltage limitation of HV pin on the “absolute maximum
rating”.
3.
Correction on the block diagram
a.
Page 3 --- Add flip-flop on the OVP loop to be matched with the OVP operation
and add the anti-floating resistor on the output.
4.
Correction on the description of Over Load Protection (OLP)
a.
Page 10 --- Original description “Whenever….30mS (when switching
frequency is 100KHz)”. Where the “100KHz” should be corrected to “65KHz”.
Continued…
17
Leadtrend Technology Corporation
LD7575-DS-04b November 2007
www.leadtrend.com.tw
LD7575
03
11/28/’05
1.
Page3, Correction on the block diagram by modifying the AND gate (following the
PWM comparator) to OR gate.
2.
Page 5, Correction on the parameters on “Gate Drive Output” because LD7575 can
support to 500mA driving capability but the parameters in the previous datasheet are
for 300mA driving current. The output high level will be updated from min. 8V to min.
9V. The rising time will be updated from max. 200nS to max. 160nS. The falling time
will be updated from max. 100nS to max. 60nS. All these parameters are for
correction and no design change on the related circuits.
04
1/22/’07
Revision: Block Diagram
04a
6/5/2007
HV=500V (supplement to HV current source/ off state leakage current)
04b
11/29/2007
Green package option
18
Leadtrend Technology Corporation
LD7575-DS-04b November 2007
www.leadtrend.com.tw
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