EXAMINATIONS  2008

EXAMINATIONS  2008
EXAMINATIONS  2008
MID-YEAR
COMP 203 / NWEN 201
COMPUTER ORGANIZATION / COMPUTER ARCHITECTURES
Time Allowed: 3 Hours (180 minutes)
Instructions:
Answer all questions.
Make sure your answers are clear and to the point.
Calculators and paper foreign language dictionaries are allowed.
No reference material is allowed.
There are 180 possible marks on the exam.
Every box with a heavy outline requires an answer.
There is an appendix listing MIPS instructions and the assembly programs
of questions 7 and 8 at the end of the script.
Topic
Marks
PART I
1
2
3
Basic Concepts and Performance
Machine Language and Buses/IO
Computer Arithmetic
14 marks
22 marks
24 marks
PART II
4
5
6
7
8
9
Logic Basics
Processor Data Path Basics
Multi Cycle Data Path
Pipelined Data Path
Memory Hierarchy
Disk and Input / Output
20 marks
15 marks
15 marks
25 marks
30 marks
15 marks
Note: Marks are shown for each question as a whole and also for their parts.
StudentId__________________
PART I
Question 1. Basic Concepts and Performance
[14 marks]
a) [9 marks] Define each of the following terms in one sentence in the context of
computer organisation.
i) CPU
ANSWER
ii) Compiler
ANSWER
iii) Memory
ANSWER
iv) Assembler
ANSWER
v) Instruction
ANSWER
vi) Control
ANSWER
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continued
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c) [5 marks] Assume a computer A is used to execute a program P. The manufacturing
manual shows that the computer CPU uses a 400MHz clock. A counting program C
shows that program P has 200 billion instructions. When the program P is executed on
computer A, the Unix command time gives the following results:
% time P (Return key)
1000u 200s 25:00 80%
Estimate the average CPI of the program P on computer A.
ANSWER
COMP 203
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continued
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Question 2. Machine Language
[22 marks]
a) [8 marks] Consider the following segment of C code:
while (i >= h)
{
f = f + A[i];
i = i - j;
}
f++;
Assume that the registers $s0, $s1, $s2, $s3, and $s4 hold integer variables f, h, i, j, and
the base address of integer array A, respectively. Insert a single instruction in each of the
four outlined spaces labelled as 1, 2, 3 and 4, so that the resulting sequence of MIPS
instructions directly corresponds to the above C code segment.
ANSWER
Loop: slt $t0, $s2, $s1
1.
add $t1, $s2, $s2
add $t1, $t1, $t1
add $t1, $t1, $s4
2.
add $s0, $s0, $t2
sub $s2, $s2, $s3
3.
Exit:
4.
COMP 203
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continued
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b) [8 marks] Given the following C procedure/function:
int exam08(int x, int y, int z)
{
int u;
u = (x + y) - (z + 6);
return u;
}
Assume that the registers $a0, $a1 and $a2 hold variables x, y and z,
respectively, that register $s1 is used to store the local variable u, and that both the
caller and the callee need to use $s1. Insert a single instruction in each of the outlined
spaces labeled as 1, 2, 3, and 4, so that the resulting sequence of MIPS instructions
directly corresponds to the above procedure/function.
ANSWER
Exam08:
addi $sp, $sp, -4
1.
add $t0, $a0, $a1
addi $t1, $a2, 6
sub $s1, $t0, $t1
2.
lw $s1, 0($sp)
3.
4.
COMP 203
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continued
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c) [2 marks] Consider the following MIPS instructions:
sltu $t0, $s2, $s1
slt $t1, $s2, $s1
Assume that
$s1 = 1110 0000 0000 0101 0000 0000 0000 1001
$s2 = 0110 0000 1001 0000 1111 0000 0000 1010
in binary. What will be the decimal values of $t0 and $t1?
ANSWER
$t0 =
$t1 =
d) [4 marks] Consider the following sequence of MIPS instructions:
lui $t1, 0x31f5
addi $t2, $t1, 0x8213
ori $t3, $t1, 0x8213
What hexadecimal values will be stored in $t1, $t2 and $t3?
(Hint: take care with the immediate operand)
ANSWER
$t1 =
$t2 =
$t3 =
COMP 203
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continued
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SPARE PAGE FOR EXTRA ANSWERS
Cross out the rough working that you do not want marked.
Specify the question number for work you do want marked.
COMP 203
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continued
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Question 3. Computer Arithmetic
[24 marks]
As discussed in the lectures, bit patterns have no inherent meaning. They may represent
signed integers, unsigned integers, floating point numbers, and even machine instructions.
For questions a) to c), you may express your answers in the form like (2i +…+ 2j + …+ 2-l +
…+ 2-k), where i, j, k l∈{-31, -30,…,0, 1,..., 31}.
Given the bit pattern below, answer questions a) to d):
1000 1111 1110 1111 0100 0000 0000 0000
What does it represent, if it is
a) [3 marks] a two’s complement integer?
ANSWER
b) [2 marks] an unsigned integer?
ANSWER
c) [4 marks] a single precision floating point number (Assuming the above bit pattern
is in IEEE 754 binary representation)?
ANSWER
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continued
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d) [5 marks] a MIPS instruction?
ANSWER
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continued
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e) [10 marks] This question concerns overflow detection and manipulation.
Suppose that A and B are two negative integers stored in registers $s1 and $s2,
respectively. Write a sequence of MIPS instructions (at most 15) to process the
following tasks:
perform C = A + B; (Store C in register $s3)
if there is no overflow, add constant 20 to C and place the result in
register $s4;
otherwise, set the most significant bit of C to 1, set the least significant
bit of C to 0, and store a carry in $s5.
Use temporary registers if necessary.
ANSWER
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continued
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PART II
Question 4. Combinational and Sequential Logic
[20 marks]
a) [15 marks] The truth table in Figure 4.1 contains opcode bit values of four MIPS
instructions as inputs (In31 to In26) and five control signals as outputs (Reg Dest, etc.).
Design and draw a single cycle data path Control Unit as a combinational logic block
using the truth table in Figure 4.1.
Note:
• The shaded instruction mnemonics should not influence your design.
• If you make simplification using “don’t care” outputs, you will get 15 marks. If you do
not make a simplification, but your answer is still correct, you will get 10 marks.
Instruc
tion
add
lw
sw
beq
In31
0
1
1
0
In30
0
0
0
0
opcode
In29 In28
0
0
0
0
1
0
0
1
Reg
In27 In26 Dest
0
0
1
1
1
0
1
1
X
0
0
X
ALU
Src
0
1
1
0
Branch Mem
Reg
ToReg Write
0
0
0
1
0
1
X
X
1
1
0
0
Figure 4.1
ANSWER
COMP 203
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continued
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b) [5 marks] Consider a D Flip-Flop in Figure 4.2 and the waveforms on its C and D
inputs in Figure 4.3. Draw the missing output Q of the flip-flop in Figure 4.3.
D
Q1
D1
D2
D latch
C1
Q2
Q
D latch
Q1
C2
Q2
C
Figure 4.2
C
D
Q
Figure 4.3
COMP 203
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continued
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Question 5. Processor Data Path Basics
[15 marks]
a) [2 marks] What is the program counter in the MIPS processor architecture and what is
it used for?
ANSWER
b) [2 marks] How is the new content of the program counter computed?
ANSWER
c) [4 marks] What is the register file in the MIPS processor architecture and what is it
used for? What is the size of the register file?
ANSWER
d) [4 marks] What is a sign extender in the MIPS processor architecture and what is it
used for?
ANSWER
COMP 203
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continued
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e) [3 marks] How is a branch offset computed?
ANSWER
COMP 203
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continued
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SPARE PAGE FOR EXTRA ANSWERS
Cross out the rough working that you do not want marked.
Specify the question number for work you do want marked.
COMP 203
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continued
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Question 6. Multi Cycle Data Path
[15 marks]
a) [2.5 marks] Give the names of 5 cycles of the MIPS Multi Cycle Data Path.
ANSWER
b) [6.5 marks] Consider the diagram in Figure 5. On the diagram, show only those lines
and components that will be used to execute the third cycle of a MIPS memory
instruction.
Trace the lines and circle the components using a coloured pen.
COMP 203
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continued
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Target
PC
M
u
x
M
u
x
Reg
Address
Data
ALU
Reg
MemData
Write
data
Instruction
register
M
u
x
Memory
Reg
Data
result
Data
Registers
4
M
u
x
M
U
X
16
Memory
Data
Register
Sign
extend
32
Shift
left 2
Figure 5 Third Cycle of a MIPS memory (sw, lw) instruction
COMP 203
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continued
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c) [6 marks] The microinstructions of the multi-cycle processor data path are given in the
table Q6.1. Table Q6.2 shows Dispatch1 table, and Table Q6.3 shows Dispatch2 table.
Table Q6.1
Add- Label
ress
1 Fetch
ALU
SRC1
SRC2
Add
PC
4
2
3 Mem1
4 LW2
Add
Add
PC
Rs
Extshft
Extend
Reg.
Con.
Read
Write
rt
6 SW2
Fetch
Write
ALU
Funcode
rs
Fetch
rt
Seq
8
9 BEQ1
Subt
10 JUMP1
Write
ALU
rs
Sequencing
Seq
Dispatch1
Dispatch2
Seq
Read
ALU
5
7 Rfrmt1
Memory PC
Write
Read
ALU
PC
rt
Fetch
Zero
Jump
addr
Table Q6.2
Fetch
Fetch
Table Q6.3
Dispatch1 Table
opcode
Label
sw
Mem1
lw
Mem1
add
Rformat1
sub
Rformat1
beq
BEQ1
Dispatch2 Table
Opcode
Label
Sw
SW2
Lw
LW2
Write the micro code sequence for the MIPS beq instruction by copying only the
appropriate microinstructions (the addresses will be sufficient) from the Table Q6 into the
Table Q6 - ANSWER provided for your answer on the facing page.
COMP 203
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continued
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Table Q6 – ANSWER
Add- Label
ress
COMP 203
ALU
SRC1
SRC2
Reg.
Con.
19
Memory PC
Write
Sequencing
continued
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Question 7: Pipelined Data Path
[25 marks]
a) [4 marks] What is pipelining and what is the expected benefit of pipelining?
ANSWER
b) [4 marks] Hazards are the main problem of pipelined processors. Name the two most
common kinds of hazards.
ANSWER
c) [5 marks] List the techniques that are used to fight against hazards?
ANSWER
COMP 203
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continued
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SPARE PAGE FOR EXTRA ANSWERS
Cross out the rough working that you do not want marked.
Specify the question number for work you do want marked.
COMP 203
21
continued
StudentId__________________
d) [12 marks] Consider the MIPS assembly program given below. At the start of the
program, all processor registers are set to zero.
#This program is constructed to test your
#understanding of pipeline hazards
#and has no other purpose.
#All registers of the Register File are
#initially set to 0.
addi $1, $0, 2
addi $2, $0, 4
addi $6, $0, 2
addi $4, $0, 8
loop:
sw
$1, 0($2)
lw
$3, 0($2)
sw
$3, 0($4)
addi $5, $5, 1
bne $5, $6, loop
add $1, $1, $1
END
i.
[6 marks] Suppose the program above is executed in a pipelined data path with
forwarding. The decision whether to branch or not is made in the second stage,
and if a branch is taken the PC is also updated in the second stage. Branch
Assumption is set to off. What will be the content of the register $1 if we execute
the program as it is?
ANSWER
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continued
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ii.
[6 marks] Rearrange the order of instructions or insert NOPs in only those
places in the program above that are needed for its correct execution in a
pipelined data path with forwarding, where the decision whether to branch or not
is made in the second stage, and if a branch is taken the PC is updated also in
the second stage. Show your working in the space provided for the answer
below.
ANSWER
COMP 203
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continued
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Question 8. Memory Hierarchy
[30 marks]
a) [2 marks] List the names of the memory hierarchy levels.
ANSWER
b) [2 marks] What are the two phenomena that the memory hierarchy is based on?
ANSWER
c) [3 marks] What is a cache memory and what is it used for?
ANSWER
d) [4 marks] What is a virtual memory, what is it used for, and what is the name of a
computer program that manages the virtual memory?
ANSWER
COMP 203
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continued
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e) [3 marks] What is a page table used for and where is it kept?
ANSWER
f) [3 marks] What is a Translation Lookaside Buffer (TLB) and what is it used for?
ANSWER
COMP 203
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continued
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g) [13 marks] Consider the MIPS assembly program given below.
#This program is constructed to test your
#understanding of caches
#and has no other purpose.
#All registers of the Register File are
#initially set to 0.
addi $1, $0, 2
addi $2, $0, 4
addi $3, $0, 3
addi $4, $0, 16
addi $6, $0, 5
loop:
sw
$1, 0($2)
addi $5, $5, 1
sw
$3, 0($4)
addi $1, $1, 1
addi $3, $3, 1
bne $5, $6, loop
addi $7, $7, 1
END
Note: There is a copy of the assembly program above given at the end of the
appendix. Tear it off and use it to help answer the question.
The program is executed in a MIPS processor having an instruction and a data cache. The
cache block sizes are 1W, only. The program loops five times and terminates successfully.
Define the optimal cache size for a program as the smallest cache size that produces the
largest number of hits.
i) [3 marks] What is the optimal size of the instruction cache? Justify your answer
briefly
ANSWER
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continued
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ii) [4 marks] How many hits and misses will produce the Instruction Cache –
Memory System in the case of the optimal instruction cache size you computed
above?
ANSWER
iii) [3 marks] What is the optimal size of the data cache? Justify your answer
briefly.
ANSWER
iv) [3 marks] How many hits and misses will produce the Data Cache – Memory
System in the case of the optimal data cache size you computed above?
ANSWER
COMP 203
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continued
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Question 9. Disk and Bus Synchronization
[15 marks]
a) [7.5 marks] A computer configuration contains a disk with the following characteristics:
• Controller latency 1 ms,
• Average seek time 5 ms,
• Rotational speed 10000 revolutions per minute, and
• Transfer rate 40 MB/s.
Calculate the average time to transfer a 16KB block from disk into main memory.
ANSWER
b) [7.5 marks] Suppose a disk read operation, which transfers a data block from disk into
the main memory takes 10 ms, and the disk controller has DMA (Direct Memory
Access) capability. A 1000 MHz processor spends 2500 clocks to initiate a disk
operation and 1500 clocks to handle a disk interrupt after the data transfer completion.
Calculate the processor overhead during one whole disk read operation.
ANSWER
***********
COMP 203
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end
APPENDIX
Commonly Used MIPS Instructions
Arithmetic and Logical Instructions
add Rdest, Rsrc1, Src2
Addition (with overflow)
addi Rdest, Rsrc1, Imm
Addition Immediate (with overflow)
addu Rdest, Rsrc1, Src2
Addition (without overflow)
and Rdest, Rsrc1, Src2
AND
andi Rdest, Rsrc1, Imm
AND Immediate. Put the logical AND of the integers from register Rsrc1 and Src2 (or Imm) into
register Rdest.
or Rdest, Rsrc1, Src2
OR
ori Rdest, Rsrc1, Imm
OR Immediate. Put the logical OR of the integers from register Rsrc1 and Src2 (or Imm) into
register Rdest.
sll Rdest, Rsrc1, Src2
Shift Left Logical
srl Rdest, Rsrc1, Src2
Shift Right Logical
sub Rdest, Rsrc1, Src2
Subtract (with overflow)
subu Rdest, Rsrc1, Src2
Subtract (without overflow) Put the difference of the integers from register Rsrc1 and Src2 into
register Rdest.
Constant-Manipulating Instructions
li Rdest, imm
Load Immediate. Move the immediate imm into register Rdest.
lui Rdest, imm
Load Upper Immediate Load the lower halfword of the immediate imm into the upper halfword of
register Rdest. The lower bits of the register are set to 0.
COMP 203
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Appendix
Comparison Instructions
slt Rdest, Rsrc1, Src2
Set Less Than
slti Rdest, Rsrc1, Imm
Set Less Than Immediate
sltu Rdest, Rsrc1, Src2
Set Less Than Unsigned
Branch and Jump Instructions
beq Rsrc1, Src2, label
Branch on Equal. Conditionally branch to the instruction at the label if the contents of register Rsrc1
equals Src2.
bne Rsrc1, Src2, label
Branch on Not Equal. Conditionally branch to the instruction at the label if the contents of register
Rsrc1 are not equal to Src2.
j label
Jump. Unconditionally jump to the instruction at the label.
jal label
Jump and Link
jalr Rsrc
Jump and Link Register. Unconditionally jump to the instruction at the label or whose address is in
register Rsrc. Save the address of the next instruction in register 31.
jr Rsrc
Jump Register. Unconditionally jump to the instruction whose address is in register Rsrc.
Load Instructions
lw Rdest, address
Load Word. Load the 32-bit quantity (word) at address into register Rdest.
lb Rdest, address
Load Byte. Load the 8-bit quantity (byte) at address into register Rdest.
Store Instructions
sw Rsrc, address
Store Word. Store the word from register Rsrc at address.
sb Rsrc, address
Store Byte. Store the byte from register Rsrc at address.
COMP 203
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Appendix
Commonly Used MIPS Fields
There are six commonly used MIPS fields: op, rs, rt, rd, shamt, and funct. The op and funct are usually used
to represent and distinguish between different operations/instructions. The following table gives the op and
funct for the commonly used MIPS instructions.
Instructions
add
sub
Lw
Sw
beq
bne
Slt
J
Jal
Jr
op
0
0
35
43
4
5
0
2
3
0
Funct
32
34
NA
NA
NA
NA
42
NA
NA
8
Registers:
COMP 203
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Appendix
Question 7.d assembly program
#This program is constructed to test your
#understanding of pipeline hazards
#and has no other purpose.
#All registers of the Register File are
#initially set to 0.
addi $1, $0, 2
addi $2, $0, 4
addi $6, $0, 2
addi $4, $0, 8
loop:
sw
$1, 0($2)
lw
$3, 0($2)
sw
$3, 0($4)
addi $5, $5, 1
bne $5, $6, loop
add $1, $1, $1
END
Question 8.g assembly program
#This program is constructed to test your
#understanding of caches
#and has no other purpose.
#All registers of the Register File are
#initially set to 0.
addi $1, $0, 2
addi $2, $0, 4
addi $3, $0, 3
addi $4, $0, 16
addi $6, $0, 5
loop:
sw
$1, 0($2)
addi $5, $5, 1
sw
$3, 0($4)
addi $1, $1, 1
addi $3, $3, 1
bne $5, $6, loop
addi $7, $7, 1
END
COMP 203
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Appendix
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