HM413

HM413
Model HM413
CAMAC FERAbus Histogramming Memory
Operating and Service Manual
NOTE: The following modifications have been made to this
unit, but are not reflected in this manual.
Pins 11 and 12 of U4 and U5 have been grounded. A Zener
diode (D10) has been added between Vcc and gnd.
Printed in U.S.A.
ORTEC® Part No. 762780
Manual Revision F
0405
$GYDQFHG0HDVXUHPHQW7HFKQRORJ\,QF
a/k/a/ ORTEC®, a subsidiary of AMETEK®, Inc.
WARRANTY
ORTEC* warrants that the items will be delivered free from defects in material or workmanship. ORTEC makes
no other warranties, express or implied, and specifically NO WARRANTY OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE.
ORTEC’s exclusive liability is limited to repairing or replacing at ORTEC’s option, items found by ORTEC to be
defective in workmanship or materials within one year from the date of delivery. ORTEC’s liability on any claim
of any kind, including negligence, loss, or damages arising out of, connected with, or from the performance or
breach thereof, or from the manufacture, sale, delivery, resale, repair, or use of any item or services covered
by this agreement or purchase order, shall in no case exceed the price allocable to the item or service furnished
or any part thereof that gives rise to the claim. In the event ORTEC fails to manufacture or deliver items called
for in this agreement or purchase order, ORTEC’s exclusive liability and buyer’s exclusive remedy shall be
release of the buyer from the obligation to pay the purchase price. In no event shall ORTEC be liable for special
or consequential damages.
Quality Control
Before being approved for shipment, each ORTEC instrument must pass a stringent set of quality control tests
designed to expose any flaws in materials or workmanship. Permanent records of these tests are maintained
for use in warranty repair and as a source of statistical information for design improvements.
Repair Service
If it becomes necessary to return this instrument for repair, it is essential that Customer Services be contacted
in advance of its return so that a Return Authorization Number can be assigned to the unit. Also, ORTEC must
be informed, either in writing, by telephone [(865) 482-4411] or by facsimile transmission [(865) 483-2133], of
the nature of the fault of the instrument being returned and of the model, serial, and revision ("Rev" on rear
panel) numbers. Failure to do so may cause unnecessary delays in getting the unit repaired. The ORTEC
standard procedure requires that instruments returned for repair pass the same quality control tests that are
used for new-production instruments. Instruments that are returned should be packed so that they will withstand
normal transit handling and must be shipped PREPAID via Air Parcel Post or United Parcel Service to the
designated ORTEC repair center. The address label and the package should include the Return Authorization
Number assigned. Instruments being returned that are damaged in transit due to inadequate packing will be
repaired at the sender's expense, and it will be the sender's responsibility to make claim with the shipper.
Instruments not in warranty should follow the same procedure and ORTEC will provide a quotation.
Damage in Transit
Shipments should be examined immediately upon receipt for evidence of external or concealed damage. The
carrier making delivery should be notified immediately of any such damage, since the carrier is normally liable
for damage in shipment. Packing materials, waybills, and other such documentation should be preserved in
order to establish claims. After such notification to the carrier, please notify ORTEC of the circumstances so
that assistance can be provided in making damage claims and in providing replacement equipment, if
necessary.
Copyright © 2005, Advanced Measurement Technology, Inc. All rights reserved.
*ORTEC® is a registered trademark of Advanced Measurement Technology, Inc. All other trademarks used herein are
the property of their respective owners.
iii
CONTENTS
SAFETY INSTRUCTIONS AND SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
SAFETY WARNINGS AND CLEANING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
1. DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1. PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2. CONTROLS AND INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3. INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4. ECL INPUTS/OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5. CAMAC COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6. REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7. ELECTRICAL AND MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
4
6
7
8
3. INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. ECL BUS PULL-DOWN RESISTOR PACKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2. CONTROL SIGNAL SWITCH SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3. JUMPER SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4. INSTALLATION IN CAMAC CRATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5. ECL BUS CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6. MONITOR MODE CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7. READOUT CONTROL MODE CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. OPERATING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1. GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2. ECL DATA TRANSFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3. MONITOR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4. READOUT CONTROL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5. AVOIDING LOCK-UP AFTER THE MASTER GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6. STARTING AND STOPPING DATA COLLECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7. CAMAC READOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
12
13
13
13
APPENDIX A. RECOMMENDED CABLE COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
iv
SAFETY INSTRUCTIONS AND SYMBOLS
This manual contains up to three levels of safety instructions that must be observed in order to avoid
personal injury and/or damage to equipment or other property. These are:
DANGER
Indicates a hazard that could result in death or serious bodily harm if the safety instruction is
not observed.
WARNING
Indicates a hazard that could result in bodily harm if the safety instruction is not observed.
CAUTION
Indicates a hazard that could result in property damage if the safety instruction is not
observed.
Please read all safety instructions carefully and make sure you understand them fully before attempting to
use this product.
In addition, the following symbol may appear on the product:
ATTENTION – Refer to Manual
DANGER – High Voltage
Please read all safety instructions carefully and make sure you understand them fully before attempting to
use this product.
v
SAFETY WARNINGS AND CLEANING INSTRUCTIONS
DANGER
Opening the cover of this instrument is likely to expose dangerous voltages. Disconnect the
instrument from all voltage sources while it is being opened.
WARNING Using this instrument in a manner not specified by the manufacturer may impair the
protection provided by the instrument.
Cleaning Instructions
To clean the instrument exterior:
Unplug the instrument from the ac power supply.
Remove loose dust on the outside of the instrument with a lint-free cloth.
Remove remaining dirt with a lint-free cloth dampened in a general-purpose detergent and water
solution. Do not use abrasive cleaners.
CAUTION To prevent moisture inside of the instrument during external cleaning, use only enough liquid
to dampen the cloth or applicator.
Allow the instrument to dry completely before reconnecting it to the power source.
vi
1
ORTEC MODEL HM413
CAMAC FERABUS HISTOGRAMMING MEMORY
1. DESCRIPTION
The ORTEC Model HM413 CAMAC FERAbus
Histogramming Memory provides histogramming of
the spectral data from ADCs equipped with the
standard FERAbus1 readout port. The Model
HM413 has two modes of operation: a) the Monitor
mode, and b) the Readout Control mode. In the
Monitor mode, the Model HM413 histograms
spectra from preselected ADCs while listening to
list-mode readouts on the FERAbus. This is an
efficient solution for monitoring the spectra from
various ADCs during a multi-parameter coincidence
experiment. It relieves the data processing
computer of the time-consuming and memoryconsuming histogramming tasks. In the Readout
Control mode, the Model HM413 functions as the
readout controller for histogramming singles
spectra from multiple ADCs. This is a powerful and
cost-effective solution when the singles spectra
from a large number of detectors must be analyzed
at high counting rates.
The histogramming memory has a length of 32,768
channels and a capacity of 16,777,215 counts per
channel (24 bits). It can be configured by CAMAC
commands to histogram two 16,384-channel ADCs,
four 8192-channel ADCs, eight 4096-channel
ADCs, sixteen 2048-channel ADCS, or thirty-two
1024-channel ADCs. CAMAC commands assign
the memory segments to histogram particular
ADCs on the basis of the Virtual Station Number of
the ADC module and the Subaddress of each ADC
within the module. Depending on the number of bits
delivered by the ADCs, each Model HM413 serves
all the ADCs located in one or two ADC modules.
The Model HM413 supports all CAMAC ADCs that
provide the standard FERAbus control and data
output formats, as defined in the ECL
Inputs/Outputs section of the Model HM413
specifications. This includes the CAMAC/FERAbus
series of ORTEC ADCs and the LeCroy 4300B 16Input ADC. All ADCs must operate in the zerosuppressed readout mode, in order to provide the
Virtual Station Number, the Subaddress, and the
1
FERA and FERAbus are trademarks of LeCroy Corporation.
Header Word that the Model HM413 uses to
identify the assigned ADCS. The Model HM413
supports both the Singles and Coincidence modes
featured in the ORTEC FERAbus ADCs. The
LeCroy 4300B operates only in the Coincidence
mode.
In the Monitor mode, the Model HM413 simply
listens to the ADC readouts occurring on the
FERAbus, while the LeCroy 4301 acts as the
readout controller for the list-mode readout (Fig.
1a). The WST (Write Strobe) signal on the ECL
Control Bus causes the Model HM413 to read each
word on the ECL Data Bus into a fast FIFO
memory. This buffer memory allows the Model
HM413 to track the readout of a crate full of ADCs
at 100 ns per word. The Model HM413 continuously
unloads the FIFO memory, and histograms only the
data corresponding to its assigned ADCs.
In the Readout Control mode, the Model HM4413
acts as the readout controller (Fig. 1b). This mode
is used for histogramming the singles spectra from
multiple ADCs. ADC data acquisition can be either
gated by the master GATE, or ungated. The GAI
gate inputs of the Model HM413 allow ECL, fast
negative NIM, TTL, or slow positive NIM logic
signals to be used for the master GATE input.
When an ADC has data ready for readout, it
generates a Readout Request (REQ) on the ECL
Control Bus. The Model HM413 enables the
readout by sending a Readout (REO) signal, via a
twisted-pair cable, to the Readout Enable (REN)
input of the first ADC in the readout loop. The
Model HM413 reads the data from the ADC in the
same way as in the Monitor mode, except that the
Model HM413 accepts and generates the
handshake signals that control the data transfer.
When the ADC has finished its readout, it sends a
PASS signal to the REN input of the next ADC. If
the next ADC is not requesting a readout, it delivers
a PASS signal to the REN input of the following
ADC. The PASS output from the last ADC is sent to
the CLI input of the Model HM413 to generate a
clear (CLR) signal on the ECL Control Bus. The
CLR signal releases all ADCs to accept the next
event. The CLI input connection is not required with
2
Fig. 1. Connecting the Model HM413 with FERAbus ADCs for (a) the Monitor Mode, and (b) the Readout Control Mode.
ORTEC ADCs operating in the Singles mode, but
is required for the Coincidence mode. Use of the
CLI signal is mandatory for the LeCroy 4300B ADC.
CAMAC controls are provided for starting and
stopping the histogramming process, for reading
the contents of a selected memory segment, and
for erasing the spectral data in the entire memory.
These functions can be executed without interfering
with the continuous operation of the FERAbus
readout, providing the F(26)-A(1) and F(24)-A(1)
commands are used to start and stop data
acquisition. When it is necessary to synchronize the
live time clocks in the ADCs with the data
acquisition in the Model HM413, the "I" command
can be used to start and stop data acquisition
simultaneously on all modules in the same crate.
Front-panel LEDs indicate when the Model HM413
is enabled to accept data, when data is accepted
for histogramming, and when a CAMAC
communication is occurring. CAMAC commands
are also provided for configuring the FERAbus
functions.
CAMAC readout of selected memory segments
proceeds as a block transfer in the Q-Stop mode.
For ADC identification, the first channel of a
segment readout contains the Segment Number
and the Virtual Station Number of the ADC. A LAM
output can be used to signal the need for readout
when the counts in one of the memory channels
have exceeded the memory capacity.
The Model HM413 automatically solves the
problem of the "occasionally missing readout
request" in the Coincidence mode. When a
standard FERAbus system operates in the zerosuppressed readout mode, the master GATE from
the readout controller (e.g., LeCroy 4301 FERA
Driver) signals the ADCs to analyze the coincident
events at their inputs, and to wait for a common
Clear (CLR) after readout. Occasionally, all of the
ADCs produce a zero response, because they fail
to detect any analog input signals. In this case, no
readout request is generated, and the standard
readout controller will not produce the Clear signal
required to release the ADCs for the next event.
The Model HM413 detects this situation, and
prevents lock-up by initiating a readout request 10
µs after the end of the master GATE signal. The
readout controller responds to the readout request
by issuing a readout command, which results in a
CLR signal being generated.
3
To facilitate making the interconnections between
the FERAbus modules, the C-ECLBUS Cable Kit is
recommended as a separately ordered accessory.
This kit contains the cables and connectors needed
for a crate full of FERAbus modules.
2. SPECIFICATIONS
2.1. PERFORMANCE
OPERATING MODES To provide the Virtual
Station Number and Subaddress information
required by the HM413, all FERAbus ADCs must
operate in the zero-suppressed readout mode.
Monitor Mode The HM413 histograms spectra
from preselected ADCs while listening to list-mode
readouts on the FERAbus. The LeCroy 4301 FERA
Driver functions as the readout controller (Fig. 1a).
Typically used for multi-parameter coincidence
measurements, with multiple ADCs providing listmode readout. Accepts either Coincidence- or
Singles-mode readouts.
Readout Control Mode The HM413 operates as
the readout controller for histogramming singles
spectra from several ADCs (Fig. 1b). Data
acquisition can be gated or ungated.
OPERATING TEMPERATURE RANGE 0 to 50(C.
2.2. CONTROLS AND INDICATORS
FAST NIM/TTL LOGIC JUMPERS Two circuit
board jumpers select the logic convention for the
GAI and CLI LEMO inputs. The fast negative NIM
logic position is towards the front of the module; the
TTL position is towards the rear. Each jumper
controls the input attached to the adjacent coaxial
cable.
CONTROL SIGNAL SWITCH The DIP switch on
the printed circuit board serves two functions: (a)
disconnection of the CLR, GATE, and WAK outputs
from the ECL Control Bus, and (b) switching the
cable termination for the REQ signal. Position
assignments and settings are in Table 1.
Table 1. Control Signal Switch.
SIGNAL
CAMAC-CONTROLLED FUNCTIONS
Histogramming start/stop, readout of selected
segments, clear memory, ADC/segment
assignments, and FERAbus functions.
MEMORY LENGTH 32,768 channels.
MEMORY CAPACITY 24 bits (16,777,215 counts
per channel).
PROGRAMMABLE MEMORY CONFIGURATIONS
Two 16,384-channel segments, four 8192-channel
segments, eight 4096-channel segments, sixteen
2048-channel segments, or thirty-two 1024-channel
segments. Selected by CAMAC commands to
match the ADCs being histogrammed.
FERABUS DATA TRANSFER RATE 100 ns per
word.
MAXIMUM NUMBER OF ADCs ON THE
FERAbus One CAMAC crate full of ADCs in the
Monitor mode. Limited to the ADCs specified by the
segment assignments in the Readout Control
mode.
REQ
CLR
GATE
WAK
+
+
+
+
Switch
Position
Number
1
2
3
4
5
6
7
8
Cable
Termination
ON
ON
—
—
—
—
—
—
No
OFF OFF
Termination
—
—
—
—
—
—
Outputs
Connected
—
—
ON
ON
ON
ON
ON
ON
Outputs
Disconnected
—
—
OFF OFF OFF OFF OFF OFF
Set all Switches: OFF for the Monitor mode, ON for the Readout
Control mode.
PD Two front-panel red LED indicators (one for the
ECL CONTROL connector, and one for the ECL
DATA connector) are turned On when the ECL pulldown resistors are installed for the ECL CONTROL
connector, or when the termination resistors are
installed for the ECL DATA connector. See ECL
Inputs/Outputs.
ANALYZE Front-panel LED indicates that the
HM413 is enabled to process data from the ADCs.
4
STORED
Front-panel LED flashes for
approximately 1 ms each time valid data is
identified and stored in the appropriate memory
segment. The relative brightness indicates the rate
at which events are being stored.
CAMAC READ Front-panel LED indicates that a
CAMAC read or write communication is in
progress.
2.3. INPUTS
GAI Front-panel LEMO connector accepts the
master GATE signal for distribution to the ADCs on
the ECL Control bus. See GATE description for
function. A circuit-board jumper selects NIMstandard fast negative logic (50- input
impedance), or TTL logic (also compatible with
NIM-standard positive logic; 1-k input
impedance). The LEMO GAI input is OR'ed with the
ECL GAI input.
CLI Front-panel LEMO connector accepts the
Clear Input (CLI) signal for distribution to the ADCs
as the CLR signal on the ECL Control bus. See the
CLI description under ECL Inputs/Outputs for
functional definition. A circuit-board jumper selects
NIM-standard fast negative logic (50- input
impedance), or TTL logic (also compatible with
NIM-standard positive logic; 1-k input
impedance). The LEMO CLI input is OR'ed with the
ECL CLI input.
2.4. ECL INPUTS/OUTPUTS
FERAbus communication with the ADCs utilizes
ECL logic levels on the front-panel CONTROL and
DATA connectors. All pull-down and termination
resistors must be removed from the HM413 when
operating in the Monitor mode, and installed when
operating in the Readout Control mode (see PD
LED, CONTROL SIGNAL SWITCH, and Fig. 1).
Only one ADC on each ECL bus should have the
pull-down and termination resistors installed. The
termination resistors are normally installed at the
receiving end for each pair of ECL signal lines. The
CLI, GAI, and REO connectors require construction
of 100-, twisted-pair cables, with a 2-pin socket
and housing (AMP 1-87756-8 and AMP 5-87456-3)
on each end.
ECL LOGIC LEVELS The nominal ECL logic levels
(into a 100- differential load) are:
Left (+) Pin
-1.8 V
-0.9V
Logic 0
Logic 1
Right (-) Pin
-0.9 V
-1.8V
For single-ended operation the (-) pin is grounded
in the receiving module.
ECL DATA INPUT Front-panel, 17- by 2-pin
connector (AMP 1-103326-7) accepts the digitized
ADC outputs in the form of single-ended ECL
signals from the ECL Data Bus. Up to 16 parallel
bits can be accepted and stored into the FIFO
memory at the time of the Write Strobe (WST)
signal. Bits are sequentially assigned, with bit 1
assigned the two pins in row 1 and bit 16 occupying
the two pins in row 16. Row 17 is not connected.
Interconnection between the HM413 and other
modules utilizing the ECL Data Bus requires the
construction of a 34-conductor ribbon cable (3M
part number 3365/34) with 17- by 2-pin headers
(3M 3414-6006 or AMP 499498-9) spaced to match
the configuration of modules. Two, removable,
termination resistor packs provide 100- input
impedances on the (+) inputs for the Readout
Control mode. The readout from the ADCs on the
ECL DATA Bus must conform to the following
format. Each ADC must operate in the zerosuppression mode and deliver two to 17 data words
during readout. The first is always a header word:
B16
B15 . . . B12
1
WRDCNT
B11 B10
0
0
B9
B8 . . . B1
0
VSN
followed by one to 16 data records, each with the
format:
B16
B15 . . . BN
B(N1) . . . B1
0
SUBADDR
DATA
according to the following definitions:
B16 The HM413 uses bit 16 to distinguish header
words from data records. For a header word
B16 = 1. For a data word B16 = 0.
WRDCNT The word count is a value from 0 to 15,
which defines the number of data records that
follow in the readout. The WRDCNT information is
not used by the HM413.
5
The 100- termination resistor (R7) on the (+)
input must be removed for the Monitor mode,
and installed for the Readout Control mode.
The (–) input is always grounded.
VSN The Virtual Station Number (0–255) identifies
the ADC module number during zero-suppressed
readout. The HM413 uses the VSN to identify the
ADC data it must histogram.
REQ The readout Request signal is both an
ECL input and an ECL output on the HM413.
When an ADC has data ready for readout, the
ADC issues an REQ signal. The HM413
recognizes the REQ signal, waits for a fixed
delay (factory set to 200 ns), then issues the
REO signal on a separate connector. In the
Readout Control mode, the REO signal is
connected to the Readout Enable (REN) input
on the first ADC in the readout chain to initiate
the readout sequence. The REO signal is not
used in the Monitor mode. In either mode, the
HM413 monitors the master GATE and CLR
lines on the ECL Control Bus. If a CLR signal is
not detected within 10 µs of the end of a master
GATE signal, the HM413 will generate an REQ
signal. This initiates a readout cycle, which
generates a CLR, thus preventing lock-up of the
analyze/readout cycle when none of the ADCs
detected an event. REQ is terminated by the
CLR signal. The REQ output can be enabled for
the Coincidence mode by the F(26)&A(2)
CAMAC command, or disabled for the Singles
mode by the F(24) & A(2) command.
Terminations of 100 on the (+) input and
ground on the (-) input must be connected by
the CONTROL SIGNAL SWITCH for the
Readout Control mode.
BN, BN-1 The value of N is determined by the
maximum subaddress provided by the ADC module
(number of ADC inputs per module).
ADC Inputs per Module: 1
2
4
8 16
BN:
B15 B15 B14 B13 B12
SUBADDR
The subaddress identifies the
individual ADC within the module having the VSN
designated in the header word. The HM413
decodes the SUBADDR to histogram ADCs in their
sequentially assigned segments of memory.
DATA
The conversion data from the ADC
identified by the SUBADDR and VSN. The number
of bits of data depends on the number of ADC
inputs per module and the number of bits in the
individual ADCS.
ECL CONTROL BUS The 8- by 2-pin connector at
the top of the front panel accommodates the ECL
Control Bus for synchronizing data acquisition
among multiple ADCS, and for controlling ECL data
transfer. A row of two pins is assigned to each
differential ECL input or output, with the top 8 rows
forming the ECL CONTROL BUS. Interconnection
between ADC modules and the HM413 requires the
construction of a 16-conductor ribbon cable (3M
part number 3365/16) with 8- by 2-pin headers (3M
3452-6006 or AMP 499497-3) spaced to match the
configuration of modules. The logic signals in the
ECL Control Bus are listed below. If a LeCroy 4301
FERA Driver is connected to the bus, the CLR,
GATE, and WAK output drivers in the HM413 must
be disconnected from the ECL Control Bus by the
CONTROL SIGNAL SWITCH for operation in the
Monitor mode.
N/C No connection.
WST The Write Strobe input is provided by the
ADC presenting data for readout on the bus.
WST indicates when each word on the ECL
Data Bus is valid, and causes the HM413 to
read the word into a FIFO memory. The leading
edge of the WST pulse must fall inside the data
pulse and must arrive at least 10 ns after the
data are valid. The minimum WST width is 40
ns. Minimum data transfer time is 100 ns/word.
CLR In the Readout Control mode the CLR
output is issued by the HM413 at the end of
ADC readout. This signal clears the ADCs and
releases them to analyze the next event.
Normally the CLR signal is generated by
connecting the PASS signal from the last ADC
in the readout loop to the CLI input on the
HM413. The CLR signal can also be generated
by the CAMAC command F(9)&A(1). The CLR
connector on the HM413 serves as an ECL
input and an ECL output. The input function
contains no termination resistors. For the
Monitor mode, the CLR output and its pull-down
resistors must be disconnected by the
CONTROL SIGNAL SWITCH. In the Readout
Control mode, the CLR output is enabled for the
Coincidence mode by the F(26)&A(2) CAMAC
command, or disabled for the Singles mode by
the F(24)&A(2) command.
6
GATE The master GATE output is distributed
to all ADCs connected to the ECL Control Bus
for gating in the Readout Control mode. The
GATE output is an ECL version of the input
provided to the HM413 on the GAI connector.
The logic 1 state enables acceptance of analog
inputs by the ADCs for conversion, and forces
all ADCs to wait for a common clear (CLR) after
readout. The master GATE signal is not
required by ORTEC ADCs operating in the
Singles mode. The GATE connector on the
HM413 serves as an ECL output and an ECL
input (see REQ). The input function contains no
termination resistors. For the Monitor mode, the
GATE output and its pull-down resistors must
be disconnected by the CONTROL SIGNAL
SWITCH. In the Readout Control mode, the
GATE output is enabled for the Coincidence
mode by the F(26)&A(2) CAMAC command, or
disabled for the Singles mode by the F(24)&A(2)
command.
WAK The Write Acknowledge output is used
only in the Readout Control mode. When an
ADC has data ready for transfer on the ECL
Data Bus, it issues a Write Strobe (WST) signal
on the ECL Control Bus. After a 35-ns delay,
the HM413 responds with a 40-ns-wide WAK
signal. The WAK signal indicates completion of
the transfer, and enables the next word to be
asserted on the bus by the ADCS. For the
Monitor mode, the WAK output and its pulldown resistors must be disconnected by the
CONTROL SIGNAL SWITCH.
GND Both pins connected to ground.
ROW 8 No connection.
CLI Front-panel 1- by 2-pin connector accepts the
Clear Input (CLI) signal for distribution to the ADCs
as the CLR signal on the ECL Control bus. This
ECL CLI input is OR'ed with the LEMO CLI input. At
the end of ADC readout, a logic 1 signal is applied
to clear the ADCs and release them to accept the
next event. CLI is normally derived from the PASS
output of the last ADC in the readout loop. CLI is
required in the Readout Control mode with LeCroy
4300B ADCS, and ORTEC ADCs set to the
Coincidence mode. CLI is not required by the
HM413 with ORTEC ADCs set to the Singles mode,
or all ADCs in the Monitor mode. Differential input
impedance is nominally 100.
GAI Front-panel 1- by 2-pin connector accepts the
master GATE signal for distribution to the ADCs on
the ECL Control bus. See GATE description for
function. Differential input impedance is nominally
100 . The ECL GAI input is OR'ed with the LEMO
GAI input.
REO Front-panel 1- by 2-pin connector provides the
Readout ECL output for initiating readout at the
REN input on the first ADC in the readout loop.
REO is used only in the Readout Control mode.
See REQ description for function. The CONTROL
PD LED is on when the REO pull-down resistors
are installed for operation in the Readout Control
mode.
N/C No connection.
2.5. CAMAC COMMANDS
Z
Initializes the module. Clears the LAM
flip-flop, disables data collection, sets
all registers to zero, disables the
coincidence mode, and clears the data
memory to zero. The Q response is
inhibited while the memory is being
cleared.
I
Inhibits the Store function as long as
the I signal is present. Used to stop and
start data acquisition simultaneously for
all ADCs and HM413 modules in the
same crate.
X
The module responds with X = I for all
valid function commands.
Q
The module responds with Q = I if the
function command can be executed
when issued.
L
A LAM is generated when the contents
of any channel exceeds the capacity of
the memory. Active only if the LAM is
enabled (see F(24) & A(O) and
F(26)&A(0)).
F(0)&A(0) Initiates reading the entire memory
segment (as specified by the Segment
Register) in the Q-Stop mode. Reads
the 24-bit (R1 to R24) data word at the
current memory address, and
increments the address by one at S2. A
Q=0 response is generated: when the
7
address pointer exceeds the current
segment block while reading a
segment. The Segment Register must
be loaded by the F(17)&A(3) command
before reading memory. Load segment
I through 32 (depending on the number
of segments selected) to read the
desired segment. The data for the first
channel in the readout is replaced with
a word that contains the Segment
Number in bits 9 to 16 and the Virtual
Station Number for the segment in bits
1 to 8. Subsequent words contain the
channel-by-channel histogram data for
the segment.
F(0)&A(0) Reads the Configuration Register (R1
to R5).
Segment Assignments
Configuration
Register Bits
Number of
Segments
Channels per
Segment
5
4
3
0
0
0
2
16,384
0
0
1
4
8,192
0
1
0
8
4,096
0
1
1
16
2,048
1
0
0
32
1,024
F(16)&A(0) Writes the memory address (W1 to
W15) to be read by a subsequent
F(0)&A(0) command.
F(17)&A(0) Writes to the VSN1 Register (W1 to
W8).
F(17)&A(l) Writes to the VSN2 Register (W1 to
W8).
F(17)&A(2) Writes to the Configuration Register
(W1 to W5).
F(17)&A(3) Writes to the Segment Register (W1 to
W8).
F(24)&A(0) Disables LAM.
F(24)&A(1) Stops the Analyze mode (data
histogramming). Data transfer on the
ECL Data Bus continues, independent
of this command.
F(24)&A(2) Disables the Coincidence mode for
operation in the Singles mode. Disables
the generation of REQ by the HM413
following the termination of the master
GATE signal. Also disables the CLR
and GATE output signals. The Z
c o m m and al s o d i s a b l e s th e
Coincidence mode.
F(1)&A(0) Tests LAM. Q = 1 if LAM is present.
F(8)&A(0) Causes the HM413 to clear the
contents of every channel of memory to
a value of zero. This takes
approximately 5 ms. No Q responses
will be generated for further commands
while clearing memory. Segment 0
must be selected via F(17)&A(3) before
issuing F(9)&A(0).
F(9)&A(l)
Generates a clear signal (CLR) on the
ECL CONTROL Bus, if positions 3 and
4 of the CONTROL SIGNAL SWITCH
are set ON for the Readout Control
mode.
F(10)&A(0) Tests and clears LAM. A Q response is
generated if a LAM is present and the
LAM is cleared.
F(26)&A(0) Enables LAM. LAM is generated when
any channel exceeds the capacity of
the memory.
F(26)&A(l) Starts the Analyze
histogramming).
mode
(data
F(26)&A(2) Enables the Coincidence mode.
Enables the master GATE and CLR
outputs. Enables the generation of an
REQ signal by the HM413 if a CLR
signal is not detected within 10 µs after
the GATE signal is terminated (see the
REQ description).
2.6. REGISTERS
CONFIGURATION REGISTER The Configuration
register is a 5-bit register that allows the operator to
enable the VSN (Virtual Station Number)
comparators for ADC identification, and select the
number of segments that the data memory is
8
divided into. Command F(1)&A(0) reads, and
F(17)&A(2) writes to the Configuration Register. The
bit assignments are:
Bit
Function
1
Disable 1st VSN comparator. Enable = 0, disable = 1.
Must always be enabled in order to accept ADC data.
2
Disable 2nd VSN comparator. Enable = 0,
disable = 1. Must be disabled when the entire
memory is assigned to a single VSN (i.e., a single
ADC module).
3
Segment select 1
4
Segment select 2
5
Segment select 3
See Segment Assignments
SEGMENT SELECT REGISTER This register
allows the operator to select an individual segment
for readout by loading the number of the segment
(1 to 32). Care should be taken not to load a value
greater than the number of segments selected by
the Configuration Register. Segments are
sequentially assigned in the order of the ADC
Subaddress numbers. The command F(17)&A(3)
writes to the Segment Select Register (W1 to W8).
VSN1 REGISTER The Virtual Station Number of
the ADC module that the HM413 will histogram in
the first half of memory must be written into this
register. This value is compared to the virtual
station number in the header words from the ADCs
to determine whether the HM413 should respond to
the data. In some cases the ADC with VSN1 will
occupy the entire data memory. The command
F(17)&A(0) writes to the VSN1 Register (W1 to W8).
To accept data, the VSN1 comparator must always
be enabled (see Configuration Register).
VSN2 REGISTER The function of this register is
the same as the VSN1 register, but it allows the
data from two separate modules to be processed.
The data that matches this register will be placed in
the top half of the data memory. The command
F(17)&A(l) writes to the VSN2 Register (W1 to W8).
The VSN2 comparator must be disabled when the
ADC with VSN1 occupies the entire data memory
(see Configuration Register).
2.7. ELECTRICAL AND MECHANICAL
POWER REQUIRED The HM413 derives its power
from a CAMAC crate supplying ±6 V. The power
required is +6 V at 2.1 A, -6 V at 1.0 A.
WEIGHT
Net 0.81 kg ( 1.8 lb).
Shipping 1.8 kg ( 4.0 lb).
DIMENSIONS
CAMAC-standard single-width
module, 1.70 X 22.15 cm (0.67 X 8.72 in.) front
panel per IEEE/583-1975.
3. INSTALLATION
After carefully unpacking the Model HM413,
thoroughly inspect it for evidence of damage in
shipment. If it has been damaged, refer to the
Warranty section for further instructions.
There are two modes of operation for the HM413,
the Monitor Mode and the Readout Control Mode.
The mode of operation must be known before
installing the instrument in the CAMAC crate, so
that the proper setup of the HM413 can be made.
Determine the mode in which the HM413 will be
used and follow the setup procedures for that
particular mode of operation. To gain access to the
setup components, remove the left side panel of
the HM413. Most of the components are located
near the front of the module.
3.1. ECL BUS PULL-DOWN RESISTOR
PACKS
FERAbus communications with the ADCs utilizes
the ECL logic levels on the front-panel CONTROL
and DATA connectors. Only one ADC on each ECL
bus should have the pull-down (PD) and
termination resistors installed, normally the ADC at
the end of the bus. All pull-down and termination
resistor packs in the HM413 should be moved to
the storage sockets when used in the Monitor
Mode, and installed in the active sockets when
operating in the Readout Control Mode. The PD
LEDs on the front panel of the modules are lit when
the resistor packs are installed. Figure 1 indicates
which modules in the chain of modules should have
the packs installed.
9
When the HM413 Module is used in the Monitor
Mode, the resistor packs should be removed and
placed in the storage sockets provided before the
module is inserted into the CAMAC crate or when
the system configuration is changed. To remove
the resistor packs, locate the resistor packs labeled
RA-1, RA-2, and RA-3. Remove the resistor packs
from their sockets and place them in the storage
sockets provided. The 100- resistor R7 must also
be removed. This resistor is mounted in plug-in
sockets on the circuit board between the DIP switch
and the ECL CONTROL connector.
When the HM413 is used in the Readout Control
Mode, the resistor packs and R7 should be
installed in the active sockets. Make sure the
orientation of the packs are correct before insertion
into the active sockets. The two 100- resistor
packs go to the bottom of the board, and the 220-
pack goes in the socket at the top of the board. On
most resistor packs, pin 1 is indicated with a dot.
3.2. CONTROL SIGNAL SWITCH
SETTINGS
There is an 8-position DIP switch that must be set
according to the mode in which the HM413 is to be
used. In the Monitor Mode, all 8 switches must be
moved to the inactive (OFF) positions. When the
HM413 is to be used as the FERA control module
in the Readout Control mode, all 8 switches must
be placed in the active (ON) position. See the
Control Signal Switch description in Section 2 for
the definition of each section of the switch. The
physical location of the DIP switch is shown on the
component assembly drawing at the end of this
manual.
3.3. JUMPER SELECTION
There are two jumpers on the board that allow the
selection of either NIM fast negative input or
positive slow NIM inputs for the CLI and GAI front
panel LEMO connectors. To select the NIM fast
negative input, the jumpers should be positioned
toward the front panel. For positive slow NIM input
selection, place the jumpers toward the rear panel.
These jumpers may be independently set for the
GAI and CLI LEMO inputs but must match the type
of logic signals that will be applied. When the
HM413 is used in the Monitor mode, the position of
these jumpers does not matter because these
functions are disabled by the Control Signal Switch.
In the Readout Control Mode, these signals are
enabled only when operating in the Coincidence
Mode.
Replace the side panel after the setup conditions
have been set.
3.4. INSTALLATION IN CAMAC CRATE
The HM413 Histogramming Memory operates on
power that must be furnished from a standard
CAMAC crate and power supply. Always turn off
the crate power before inserting or removing
the module. After all modules have been installed
in the crate, check the dc voltage levels from the
power supply to ensure that no overload exists.
The CAMAC crate and power supply is designed
for relay rack mounting. If the equipment is rack
mounted, be sure that adequate ventilation is
provided to prevent any localized heating of the
components used in the HM413 module. The
temperature should not exceed the maximum limit
of 50(C.
The Model HM413 will operate in any available slot
in the crate except number 25, which is reserved
for the crate controller. To install the module, turn
off the crate power and select an unused slot in the
crate, preferably one next to the modules which
the HM413 will be connected (see Fig.1). Slide the
module into the crate and use the jack screw at the
bottom of the front panel to move the power and
signal connector of the module into the backplane
connector of the crate.
3.5. ECL BUS CONNECTIONS
Two ECL bus interface connectors are provided on
the HM413 for high-speed transfer of ADC data.
The ECL bus is designed to permit multiple ADCs
to be connected to the bus in parallel for readout of
a large number of channels. A wiring diagram for a
multiple ADC system is shown in Fig. 1. Across the
top of all modules is an ECL CONTROL bus that
controls the readout process. This bus receives and
distributes system control signals. The bus is
formed from a 16-conductor ribbon cable mounted
with an 8- by 2-pin connector for each module.
Located across the bottom of each module is the
ECL DATA bus. This bus is formed with a 34conductor ribbon cable mounted with 17- by 2-pin
connectors for each module in the system. See
Appendix A for the details on how to construct
these two busses. Alternatively, the busses can be
constructed from the optional C-ECLBUS Cable Kit.
10
Cut the ribbon cables at the appropriate locations to
match the configuration of the modules. Trim the
ends of the ribbon cables carefully to prevent the
conductors from shorting to each other or to the
front panels of the modules.
3.6. MONITOR MODE CONNECTIONS
The connections for the Monitor Mode should be as
follows (see Fig. 1a): The HM413 modules should
be connected only to the ECL DATA and
CONTROL busses. On the first ADC module in the
chain, REN is connected to REO on the FERA
driver. On the remaining ADC modules, REN is
connected to PASS from the previous ADC unit.
The PASS output on the final ADC unit is
connected to the CLI input on the FERA driver
(usually a LeCroy 4301) to clear the ADCs in
preparation for the next event. In experiments with
an event master trigger, the PASS output from the
final ADC may be sent through the master trigger
logic to generate the Clear input for the FERA
driver. See Appendix A for information on cable
components and construction, or use the twistedpair cables from the C-ECLBUS Cable Kit.
3.7. READOUT CONTROL MODE
CONNECTIONS
The connections for the Readout Control Mode are
as follows (see Fig. lb): The HM413 is connected to
each ECL CONTROL and DATA bus in parallel
with the ADCs in the data collection system. Limit
the number of ADC modules connected to the
HM413 to the number that can be serviced by one
HM413 (one or two ADC modules). The REO signal
on the front panel of the HM413 is connected by a
twisted-pair cable to the REN input signal on the
first ADC in the system. The PASS output from the
first ADC is connected to the REN input signal of
the next ADC by twisted pair cable. This
PASS/REN method is continued for each remaining
ADC in the system. If the system is operating in the
COINCIDENCE MODE, the pass from the last ADC
is connected back to the CLI ECL differential input
on the HM413 to generate the CLR signal and to
release the ADCs for the next event. Also a GATE
signal must be supplied by the Master Trigger
Module to either the GAI LEMO connector or the
ECL GAI input on the HM413 front panel. In the
SINGLES MODE, the GAI and CLI connections are
not needed. Note that ADCs from some
manufacturers operate ONLY in the Coincidence
mode.
4. OPERATING INSTRUCTIONS
4.1. GENERAL
Before the HM413 is to be used as a
histogramming memory, there are some conditions
that must be satisfied regarding the ADC modules
that are to be serviced by the HM413. First, the
ADC(s) must be programmed for the zerosuppression mode. Second, each ADC module
must be assigned a Virtual Station Number (VSN)
that matches the VSN programmed into the
HM413. Third, the modules must be connected as
described in Section 3, Installation.
Before enabling the Analyze Mode, there are some
registers in the HM413 that must be programmed to
select the operational mode. The Configuration
Register, VSN1 Register, and VSN2 Register (if
more than one ADC is to be serviced) must be
programmed. Optionally, the Enable Coincidence
and Enable LAM modes may be programmed.
Examples of these commands are given below:
INIT (Z) command
This initializes all
modules to a power-up
state.
Inhibit (I) command
This inhibits data
collection and allows all
modules to be enabled
individually and started
simultaneously when the
Inhibit (I) is removed.
Configuration Register
N&F(17)&A(2)&(VALUE)
VALUE is an 8-bit number representing the
following conditions:
Bit 1 0 = Enable VSN 1
Bit 2 0 = Enable VSN 2
1 = Disable VSN 1
1 = Disable VSN 2
Bit 3 Segment Select 1 Bit 4 Segment Select 2 }
Bit 5 Segment Select 3 see table
below for
description
11
Bit 6 Not used
Bit 7 Not used
Bit 8 Not used
histogramming operation in the HM413 without
interfering with the continuous data conversion of
the ADCs.
Segment selection description:
When the Analyze Mode is active, the only CAMAC
functions that are allowed are the Disable Analyze
Mode command N&F(24)&A(1), the CAMAC Clear
command N&F(9)&A(1), the Test LAM command N&
F(8)&A(0), and the Test and Clear LAM command
N&F(10)&A(0).
5
0
0
0
0
Bit
4
0
0
1
1
3
0
1
0
1
Segments Selected
2 segments of 16K channels
4 segments of 8K channels
8 segments of 4K channels
16 segments of 2K channels
Examples
2 of AD114
1 of AD413
1 of LeCroy
4300B (11 Bit)
1 0 0 32 segments of 1K channels 2 of LeCroy
4300B (10 Bit)
1 0 1 Not defined
1 1 0 Not defined
1 1 1 Not defined
VSN 1 Register N&F(17)& A(O)&(VALUE)
VALUE must match the VSN of the ADC that
will be histogrammed in the bottom half of the
data memory.
VSN 2 Register N&F(17)& A(1)&(VALUE)
VALUE must match the VSN of the ADC that
will be histogrammed into the top half of
memory if applicable.
Enable LAM
N&F(26)&A(0)
This allows a LAM to be generated if the
contents of any channel in memory exceeds
the capacity of the memory.
Enable Coincidence N&F(26)&A(2)
This is necessary only when the Coincidence
Mode of data collection is to be used. Issue
the N&F(24)&A(2) command for the Singles
Mode.
Clear Memory
N&F(9)&A(0)
Clears the entire data memory to zero counts.
But, segment zero must first be selected via
N&F(17)& A(3) before issuing N&F(9)&A(0).
After the registers have been programmed, the
Analyze Mode can be enabled by CAMAC function
N&F(26)&A(1). If the CAMAC Inhibit is active, the
Analyze Mode will not start until the Inhibit is
removed. The Inhibit (I) command can be used to
start and stop data acquisition in all enabled
modules in the CAMAC crate simultaneously. This
is useful when the ADCs include live-time clocks.
On the other hand, the F(26)&A(1) and F(24)&A(1)
commands can be used to start and stop the
4.2. ECL DATA TRANSFER
The data from the ADC are transferred over an
ECL data bus. A controller or driver module
controls the transfer by an ECL CONTROL bus
connected to each ADC module in the system. The
HM413 may be used as a controller in the Readout
Control Mode.
Six different control signals are used to control the
ECL data transfer between the modules in the
system. A description of each follows, and their
relationship can be observed in Fig. 2.
REQ The Readout Request signal is asserted by
an ADC module as soon as data are ready for
readout. REQ is removed when the last data word
has been read or a Clear (CLI) command is given.
In the Coincidence mode, if none of the ADCs
receive a signal, the HM413 automatically
generates an REQ to prevent lock-up.
REO The HM413 asserts the REO following a 200ns delay after receiving the REQ signal. This signal
is used to provide a REN signal to the first ADC in
the system when the HM413 is operated in the
Readout Control mode.
REN The Readout Enable causes the ADC module
to begin readout if it has data ready to be output.
Once REN is asserted it must remain active
throughout the entire readout cycle.
PASS The PASS signal is asserted by the ADCs
when they have completed outputing their data or
if they have no data to output when the REN signal
is received. When the HM413 is in the Readout
Control Mode, the PASS output from the last ADC
in the data loop must be connected to the CLI input
on the HM413 to generate a Clear (CLI) signal after
the readout cycle is complete.
12
WST The Write Strobe is asserted by an ADC
when a data word is available on the ECL data bus.
The data is stable on the output for a minimum of
15 ns before the Write Strobe occurs and is
asserted for a minimum of 15 ns after the Write
Acknowledge (WAK) signal occurs. The WST
signal is used to strobe the data into a fast FIFO
buffer in the HM413.
WAK The Write Acknowledge signal is asserted by
the readout controller when the data on the ECL
bus has been accepted. WAK should be removed
after WST has been released. WST is not
reasserted after WAK has been released until 50 ns
have elapsed. The HM413 generates this signal
only in the Readout Control mode.
Fig. 2. ECL Port Readout Timing Diagram.
4.3. MONITOR MODE
4.4. READOUT CONTROL MODE
When used in the Monitor mode, multiple HM413s
may be connected in a data collection system that
has another FERA driver (such as the LeCroy
4301) operating as the readout controller. The
control functions of the HM413s should be disabled
by setting all switches on the Control Signals
Switch to the OFF position. In this mode, the only
connections to the HM413 are the ECL Control and
Data busses. There should not be a need for any
other signal connections to the HM413. See
Sections 3.1, 3.2, 3.5, 3.6, and 4.1.
If the HM413 is to be used as the Readout
Controller, all switches of the Control Signals
Switch on the HM413 will have to be placed in the
ON position (see Sections 3.1, 3.2, 3.5, 3.7, and
4.1). In addition to the ECL Data bus and the ECL
Control bus connections, there will be some added
connections, to the HM413 depending on the type
of data collection mode. If the HM413 and only one
ADC module are connected as a simple
multichannel analyzer and operated in the Singles
mode, the REO signal from the HM413 must be
connected to the REN input on the ADC module.
Typically the ADCs will be operating in the
coincidence mode, and the HM413 should also be
set to the coincidence mode by issuing command
F(26)&A(2). See section 4.5 for avoiding lock-up. If
the ADCs are operated in the singles mode, set up
the HM413 with the F(24)&A(2) command.
The automatic CLR function is not needed when
the ORTEC ADCs are operating in the singles
mode. For the singles mode, issue the F(24)&A(2)
command to the HM413.
If the system is operated in the Coincidence mode,
an appropriate Gate signal must be applied to the
13
HM413 for distribution to the ADCs through the
ECL control bus. Also, the REO output from the
HM413 must be connected to the REN input on the
first ADC in the system. The Pass output from the
last ADC module to be read must be connected to
the CLI differential input on the HM413 to generate
a Clear. In the Coincidence mode, another
conversion cycle cannot occur until the Clear signal
is generated (see section 4.5). See Section 3.7 for
more information on system interconnections.
4.5. AVOIDING LOCK-UP AFTER THE
MASTER GATE
In the coincidence mode, if none of the ADC inputs
receive an input during the Master Gate signal, it is
possible for the system to hang up, since no REQ
signal will be generated by the ADCs. To prevent
this from happening, set up the "automatic CLR"
function by issuing the F(26)&A(2) command to the
HM413. With the automatic CLR function enabled,
a timer is started in the HM413 when the GATE
signal is generated. If a REQ signal is not
generated before the timer period expires, a REQ
signal is automatically generated by the HM413.
The resulting REO signal will ripple through the
REN/PASS chain on the ADC modules and cause
a Clear signal to be generated to reset the system.
The period of the timer (10 µs) is long enough to
accommodate the longest conversion time of the
ADCs connected in the system.
4.6. STARTING AND STOPPING DATA
COLLECTION
It is good practice to always select memory
segment zero and send the Clear Memory
command N&F(9)&A(0) before enabling the Analyze
Mode. This prevents the corruption of data by
information already stored in the data memory. The
Analyze mode of the HM413 is enabled by the N
&F(26)&A(1) command (see Section 4.1 for more
detail). The collection of data in the HM413 will
continue until the Analyze mode is disabled. If the
contents of any channel in the memory exceeds the
storage capacity of the memory (16,777,215) and
the LAM is enabled, a LAM will be generated to
notify the controller of the overflow condition. When
the data collection cycle is complete, the Analyze
Mode must be disabled before data can be
transferred to the CAMAC Controller.
Data collection in the HM413 may be stopped by
one of two methods. (1) By asserting the CAMAC
Inhibit signal (I). This allows all data collection to be
stopped synchronously. (2) By sending the
N&F(24)&A(1) Disable Analyze command. This
stops the histogramming function but does not stop
the ADCs from converting input signals.
4.7. CAMAC READOUT
The Analyze Mode must be disabled by the
N&F(24)&A(1) command, even when data collection
was stopped by the Inhibit (I) signal, before the
HM413 will allow data to be read from the data
memory. After a data collection cycle has been
completed, the histogram of the data is present in
the data memory. This information may be
transferred to the CAMAC controller one segment
at a time. As a block of data containing the memory
contents of the selected segment, where each
segment represents the data from one ADC. The
number of segments, controlled by bits 3, 4, and 5
of the Configuration Register, was set before the
data acquisition began.
To transfer the contents of a selected segment,
load the Segment Register with the value of the
segment to be transferred using the CAMAC
function N&F(17)&A(3)&(VALUE = Segment
number). Then use the Q-Stop block transfer with
the function N&F(0)&A(0) to read the segment
contents. A Q = 0 response will be generated when
the end of the segment is reached. The first data
word replaces the contents of channel 0 with the
following information, bits R1 through bit R8 will be
the Virtual Station Number of the ADC from which
the data was taken, bits R9 through bits R16 will
contain the number of the segment being read. The
most significant 8 bits R17 through R24 of the first
data word are undefined. The number of channels
transferred in this mode will depend on the number
of segments selected before data collection began.
If only 2 segments were selected, the length of
each segment will be 16,384 channels. If 32
segments were selected, the length of each
segment is only 1024 channels.
If the Q-Stop block transfer is not used, the data
may be read one channel at a time by first loading
the segment number using the CAMAC function
N&F(17)&A(3)&(VALUE = segment number), then
use the CAMAC command N&F(0)&A(0) to read the
channel contents. This function transfers the
contents of the channel to the CAMAC interface
and increments the memory pointer to the next
channel. The readout is the same as in the
previous two paragraphs, except that the
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N&F(0)&A(0) command must be repeated for each
channel in the segment. A Q = 1 response will be
generated for each valid channel in the segment. A
Q = 0 response occurs when the channel number
exceeds the limits of the segment.
The contents of any individual channel may be read
by first setting the segment register to zero. Then
issue the N&F(0)&A(0) command. This reads VSN1
in bits R1 through R8 and the segment number in
bits R9 through R16 (bits R17 through R24 are
undefined). Next, load the address of the desired
channel using the N & F(16) & A(0) & (VALUE)
command. VALUE is the absolute address of the
channel with respect to the total memory, not a
segment.
Channels are numbered from 0 to 32,767. The
contents are then read using the N&F(0)&A(0)
command. The channel contents are contained in
bits R1 through R24. Subsequent N&F(0)&A(0)
commands will read the contents of sequential
memory locations. Using this method, the true
contents of the first channel in each segment can
be read.
APPENDIX A. RECOMMENDED CABLE COMPONENTS
Since each experimental system is unique, no attempt is made to supply custom cables to form an ECL bus
readout chain, but a kit is available: the C-ECLBUS Cable Kit. Each kit contains:
Quantity
1
Description
16-conductor ribbon cable with 23 headers installed at 7.6-cm intervals for the ECL Control
Bus.
1
34-conductor ribbon cable with 23 headers installed at 7.6-cm intervals for the ECL Data Bus.
1
51-cm long twisted pair cable with 2-pin sockets on each end for the PASS to CLI connection.
23
15-cm long twisted pair cables with 2-pin sockets on each end for the REO to REN, and the
PASS to REN connections.
The ribbon cables will serve an entire crate full of FERAbus modules, and can be cut to handle smaller groups
of modules. The cut ends must be trimmed carefully to prevent shorting to the front-panel metal.
Alternatively, custom cables can be built from the following components:
Control Bus Cable
Parts
16-conductor ribbon cable with 0.050 inches between conductors. 3M part number = 3365/16
16-position header configured, two rows of 8 sockets.
3M part number = 3452-6006
AMP part number = 499497-3
Construction
Using a ribbon cable construction tool (3M 3698-08), place one header on the cable for each
ADC and HM413 in the readout chain and one header for the Readout Controller on the end.
Headers should be positioned such that a minimum of cable separates the module
connections.
15
Data Bus Cable
Parts
34-conductor ribbon cable with 0.050 inch spacing between conductors. 3M part number =
3365/34
34 position header configured, two rows of 17 sockets. 3M part number = 3414-6006 AMP
part number = 499498-9
Construction
Using ribbon cable tool (3M 3698-08) place one header on the cable for each ADC and
HM413 in the readout chain and one header for the FERA driver on the end. Headers should
be positioned such that a minimum of cable separates the module connections.
Patch Cables (Used for the REN/PASS readout chain)
Parts
2-position header for twisted pair cable.
AMP part number = 5-87456-3
Sockets for header.
AMP part number = 1-87756-8
Construction
Using a crimping tool (AMP 90202-2-N), crimp sockets on both ends of the individual stranded
wire. Take two such wires and twist tightly to form a twisted pair cable. Plug the sockets into
the header to form the cable.
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