FDS8024RNv1-1 (823184 байта)
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
May 2004
ADVANTAGES
DESCRIPTION
•
The TDK 73S8024RN is a single smart card (ICC) interface
IC that can be controlled by a dedicated control bus. The
TDK 73S8024RN has been designed to provide full electrical
compliance with ISO-7816-3, EMV 4.0 (EMV2000) and NDS*
specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to a clock signal.
TDK
73S8024RN
incorporates
an
ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the selected
card voltage (3V or 5V), coming from an internal Low DropOut (LDO) voltage regulator. This LDO regulator is powered
by a dedicated power supply input VPC. Digital circuitry is
separately powered by a digital power supply VDD.
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
•
•
•
•
•
Card Interface:
Complies with ISO-7816-3, EMV 4.0 and NDS*
A LDO voltage regulator provides 3V / 5V to the card
from an external power supply input
Provides at least 90mA to the card
ISO-7816-3 Activation / Deactivation sequencer with
emergency automated deactivation on card removal
or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that detect
voltage drops on VCC (card), VDD (digital), and VPC
(regulator) power supplies
The VDD voltage supervisor threshold value can be
externally adjusted
Over-current detection 150mA max.
Card clock stop high or low
2 card detection inputs, 1 for each possible user polarity
Auxiliary I/O lines, for C4 / C8 contact signals
Card CLK clock frequency up to 20MHz
•
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock (division rate and
card clock stop modes)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults.
Crystal oscillator or host clock, up to 27MHz
•
Regulator Power Supply:
4.75V to 5.5V (EMV 4.0)
4.85V to 5.5V (NDS)
•
Digital Interfacing: 2.7V to 5.5V
•
•
6kV ESD Protection on the card interface
Package: SO28 or 32QFN
Emergency card deactivation is initiated upon card extraction
or upon any fault generated by the protection circuitry. The
fault can be a card over-current, a VDD (digital power supply),
a VPC (regulator power supply), a VCC (card power supply) or
an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to VCC voltage drop detection, as usually
implemented in ICC interface ICs.
APPLICATIONS
•
•
•
Set-Top-Box Conditional Access and Pay-per-View
Point of Sales & Transaction Terminals
Control Access & Identification
* Pending final approval
Page 1
Pin-to-pin compatible with industry-standards
TDA8004 and TDA8024
Card clock STOP (high and low) mode
Small format (5x5x0.8mm) 32QFN package option
True card over-current detection
FEATURES
With its embedded LDO regulator, the TDK 73S8024RN is a
cost-effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts, is
provided.
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It allows
automated card deactivation at a customized VDD voltage
threshold value. It can be used, for instance, to match the
system controller operating voltage range.
Traditional step-up converter is replaced by a LDO
regulator:
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
FUNCTIONAL DIAGRAM
VDD
VDDF_ADJ
21 [20]
VPC
NC
18 [17]
5 [9,16,25,32]
6
6 [3]
VPC FAULT
DIGITAL POWER SUPPLY
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
[21] 22
GND
VDD FAULT
VCC FAULT
ICC FAULT
[18] 19
Int_Clk
CMDVCC
[19] 20
RSTIN
[31] 3
5V/3V
[22] 23
OFF
DIGITAL
CIRCUITRY
&
FAULT LOGIC
[29] 1
CLKDIV1
[30] 2
CLKDIV2
[23] 24
XTALIN
[24] 25
XTALOUT
[4] 7
CLKSTOP
[5] 8
CLKLEV
[26] 26
I/OUC
[27] 27
AUX1UC
[28] 28
AUX2UC
R-C
OSC.
ISO-7816
SEQUENCER
XTAL
OSC
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
4 [1]
GND
14 [12]
GND
17 [15]
VCC
ICC RESET
BUFFER
16 [14]
RST
ICC CLOCK
BUFFER
15 [13]
CLK
10 [7]
PRES
CLOCK
GENERATION
9 [6]
PRES
OVER
TEMP
TEMP FAULT
11 [8]
I/O
ICC I/O BUFFERS
13 [11]
AUX1
12 [10]
AUX2
Pin numbers reference to the SO28 package
[Pin numbers] reference to the QFN32 package
Figure 1: 73S8024RN Block Diagram
Page 2
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
PIN DESCRIPTION
CARD INTERFACE
PIN
(SO)
PIN
(QFN)
I/O
11
8
Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1
13
11
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2
12
10
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
RST
16
14
Card reset: provides reset (RST) signal to card.
CLK
15
13
Card clock: provides clock signal (CLK) to card. The rate of this clock is determined by the
external crystal frequency or frequency of the external clock signal applied on XTALIN and
CLKDIV selections.
PRES
10
7
Card Presence switch: active high indicates card is present. Should be tied to GND when not
used, but it Includes a high-impedance pull-down current source.
9
6
Card Presence switch: active low indicates card is present. Should be tied to VDD when not
used, but it Includes a high-impedance pull-up current source.
VCC
17
15
Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an
external filter capacitor to the card GND
GND
14
12
Card ground
NAME
PRES
DESCRIPTION
MISCELLANEOUS INPUTS AND OUTPUTS
NAME
PIN
(SO)
PIN
(QFN)
XTALIN
24
23
Crystal oscillator input: can either be connected to crystal or driven as a source for the card
clock.
XTALOUT
25
24
Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external
clock input.
VDDF_ADJ
18
17
VDD fault threshold adjustment input: this pin can be used to adjust the VDDF values (that
controls deactivation of the card). Must be left open if unused.
NC
5
9, 16,
25, 32
DESCRIPTION
Non-connected pin.
POWER SUPPLY AND GROUND
PIN
(SO)
PIN
(QFN)
VDD
21
20
System interface supply voltage and supply voltage for internal circuitry.
VPC
6
3
LDO regulator power supply source.
GND
4
1
LDO Regulator ground.
GND
22
21
Digital ground.
NAME
Page 3
DESCRIPTION
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
MICROCONTROLLER INTERFACE
PIN
(SO)
PIN
(QFN)
CMDVCC
19
18
Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp
the VCC supply to the card and initiates a card activation sequence, if a card is present.
5V/#V
3
31
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low
selects 3 volt operation. When the part is to be used with a single card voltage, this pin should
be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default
this pin high (selection of 5V card) when not connected.
7
4
Stops the card clock signal during a card session when set high (card clock STOP mode).
Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is
not used.
8
5
Sets the logic level of the card clock STOP mode when the clock is de-activated by setting pin 7
high. Logic low selects card STOP low. Logic high selects card STOP high. Internal pull-down
resistor allows this pin to be left as an open circuit if the clock STOP mode is not used.
NAME
CLKSTOP
CLKLVL
CLKDIV1
CLKDIV2
1
2
29
30
DESCRIPTION
Sets the divide ratio from the XTAL oscillator (or external clock input) to the card clock. These
pins include pull-down resistors.
CLKDIV1
CLKDIV2
0
0
CLOCK RATE
XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
OFF
23
22
Interrupt signal to the processor. Active Low - Multi-function indicating fault conditions and card
presence. Open drain output configuration – It includes an internal 22kΩ pull-up to VDD.
RSTIN
20
19
Reset Input: This signal is the reset command to the card.
I/OUC
26
26
System controller data I/O to/from the card. Includes a pull-up resistor to VDD.
AUX1UC
27
27
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD.
AUX2UC
28
28
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD.
SYSTEM CONTROLLER INTERFACE
3 separated digital inputs allow direct control of the card interface from the host as follows:
Pin CMDVCC: When low, starts an activation sequence
Pin RSTIN: controls the card Reset signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card voltage
Card clock is controlled by 4 digital inputs:
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input
clock frequency (crystal or external clock)
CLKSTOP (active high) allows card power down mode by stopping the card clock
CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC is set low (Card activation sequence requested
from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or
voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence.
Page 4
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
POWER SUPPLY AND VOLTAGE SUPERVISON
The TDK 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is
controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power
supply applied on the VPC pin.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller.
Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation
sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for VPC and VCC
are linked so that a fault is generated to activate a deactivation sequence when the voltage VPC becomes lower
than VCC. It allows the 73S8024RN to operate at lower VPC voltage when using 3V cards only. The voltage
regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 and NDS specifications.
The VPC voltage supervisor threshold values are defined from applicable standards (EMV and NDS). A third
voltage supervisor monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to
deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set
by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value.
The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external
resistor REXT to ground to raise the VDD fault voltage to another value VDDF. The resistor value is defined as
follows:
REXT= 56kΩ /(VDDF - 2.33)
An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from
the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives:
R3 = 24000 / 0.42046 = 57080.
Solving for R1 gives:
R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.3V default threshold is used, this pin must be left unconnected.
Page 5
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
CARD POWER SUPPLY
The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO-7816-3
sequencer. Card voltage selection is carried out by the digital input 5V/#V.
Choice of the VCC capacitor:
Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that
the interface must be able to provide to the card are different. An external capacitor must be connected between
the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the
transient requirements. The type and value of this capacitor can be optimized to meet the desired specification.
The table below shows the recommended capacitors for each VPC power supply configuration and applicable
specification.
Specification Requirements
Specification
EMV 4.0
ISO-7816-3
NDS
System Requirements
Min VCC Voltage
allowed during
transient current
Max
transient
current
charge
Min VPC
Power
Supply
required
Capacitor
Type
Capacitor Value
4.6V
4.5V
4.6V
30nA.s
20nA.s
40nA.s
4.75V
4.75V
4.85V
X5R/X7R
w/
ESR < 100mΩ
3.3 µF
1 µF
1 µF
Table 1: Choice of VCC pin capacitor
Note: Capacitor value for NDS implementation is also defined by the deactivation time requirement.
OVER-TEMPERATURE MONITOR
A built-in detector monitors die temperature. Upon an over-temperature condition, a card deactivation sequence is
initiated, and an error or fault condition is reported to the system controller.
ON-CHIP OSCILLATOR AND CARD CLOCK
The TDK 73S8024RN device has an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock
signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be
left unconnected.
The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1
and CLKDIV 2, as per the following table:
CLKDIV1
0
0
1
1
CLKDIV2
0
1
0
1
CLK
1/8 XTALIN
¼ XTALIN
XTALIN
½ XTALIN
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs
CLKSTOP and CLKLEV.
Page 6
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
ACTIVATION SEQUENCE
The TDK 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the application
of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be set low to
activate the card. In order to initiate activation, the card must be present; there can be no over-temperature fault
or no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC low while the RSTIN is low:
-
CMDVCC is set low.
Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low
to report a fault to the system controller, and the power VCC to the card is shut off.
Turn I/O (AUX1, AUX2) to reception mode at the end of (t2).
CLK is applied to the card at the end of (t3).
RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = >0.5µs, CLK starts
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 2: Activation Sequence – RSTIN low when CMDVCC goes low
Page 7
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
-
CMDVCC is set low.
Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC to the card is shut down.
Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode.
CLK is applied to the card at the end of (t3), after I/O is in reception mode.
RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 3: Activation Sequence – RSTIN high when CMDVCCB goes low
Page 8
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
DEACTIVATION SEQUENCE
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event
of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card
extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated
when VPC goes lower than VCC.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
-
RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
CMDVCC
-- OR --
OFF
RST
CLK
I/O
VCC
t1
t1 =
t2 =
t3 =
t4 =
t5 =
t2
t3
t4
t5
> 0.5µs, timing by 1.5MHZ internal Oscillator
> 7.5µs
> 0.5µs
> 0.5µs
depends on VCC filter capacitor.
For NDS application, CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs
Figure 4: Deactivation Sequence
Page 9
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
OFF AND FAULT DETECTION
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card
presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present, and high
if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.
During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault detection
is detected. At the same time that OFF is set low, the sequencer starts the deactivation process.
The Figure 5 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and
outside the card session:
OFF is low by
card extracted
OFF is low by
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 5: Timing Diagram - Management of the Interrupt Line OFF
I/O CIRCUITRY AND TIMING
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation
sequencer turns on the I/O reception state. See Activation Sequence timing section for more details on when the
I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turn on, the first I/O line on which a falling edge is
detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge
is detected then both I/O lines return to their neutral state.
The Figure 6 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 7.
Page 10
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
No
I/OUC
&
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 6: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tI/O_LH
tI/O_HL = 100ns
tI/OUC_HL = 100ns
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 25ns
tI/OUC_LH = 25ns
Figure 7: I/O – I/OUC Delays - Timing Diagram
Page 11
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
TYPICAL APPLICATION SCHEMATIC
AUX2UC_to/from_uC
AUX1UC_to.from_uC
See NOTE 5
I/OUC_to/from_uC
VDD
See NOTE 6
CLKDIV1_from_uC
See NOTE 3
CLKDIV2_from_uC
5V/3V_select_from_uC
External_clock_from uC
VDD
C4
VPC
100nF
C5
10uF
See NOTE 2
CLKSTOP_from_uC
CLKLVL_from_uC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
See NOTE 5
CLKDIV1
CLKDIV2
5V3V_
GND
NC
VPC
CLKSTOP
CLKLVL
PRESB
PRES
I/O
AUX2
AUX1
GND
73S8024RN
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
OFF_
GND
VDD
RSTIN
CMDVCC_
VDDF_ADJ
VCC
RST
CLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SO28
- OR R3
Rext2
C2
VDD
See NOTE 1
C6
R1
Rext1
100nF
Y1
22pF
C3
CRYSTAL
22pF
See NOTE 4
See note 7
OFF_interrupt_to_uC
RSTIN_from_uC
CMDVCC_from_uC
8
7
6
5
4
3
2
1
NDS & ISO7816=1uF, EMV=3.3uF
Low ESR (<100mohms) C1
C1 should be placed near the SC
connecter contact
C8
I/O
VPP
GND
C4
CLK
RST
VCC
SW-2
SW-1
R2
NOTES:
Card detection
1) VDD = 2.7V to 5.5V DC.
20K
switch is
normally closed
2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6)Internal pull-up allows it to be left open if unused.
7) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
10
9
VDD
CLK track should be routed
far from RST, I/O, C4 and
C8.
Smart Card Connector
Figure 8: 73S8024RN – Typical Application Schematic
Page 12
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
ELECTRICAL SPECIFICATION
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins
are protected against short circuits to VCC, ground, and each other.
PARAMETER
RATING
Supply Voltage VDD
-0.5 to 6.0 VDC
Supply Voltage VPC
-0.5 to 6.0 VDC
Input Voltage for Digital Inputs
-0.3 to (VDD +0.5) VDC
Storage Temperature
-60 to 150°C
Pin Voltage (except card interface)
-0.3 to (VDD +0.5) VDC
Pin Voltage (card interface)
-0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins
+/- 6kV
ESD Tolerance – Other pins
+/- 2kV
*Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.
RECOMMENDED OPERATING CONDITIONS
Page 13
PARAMETER
RATING
Supply Voltage VDD
2.7 to 5.5 VDC
Supply Voltage VPC
4.75 to 5.5 VDC
NDS Supply Voltage VPC
4.85 to 5.5 VDC
Ambient Operating Temperature
-40°C to +85°C
Input Voltage for Digital Inputs
0V to VDD + 0.3V
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
SMART CARD INTERFACE REQUIREMENTS
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
Card Power Supply (VCC) Regulator
General conditions, -40°C < T < 85°C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v
NDS conditions, 4.85v < VPC < 5.5v
VCC
VCCrip
ICCmax
ICCF
VSR - VSF
VSRN VSFN
Card supply voltage
including ripple and
noise
VCC Ripple
Card supply output
current
ICC fault current
VCC slew rate VCC slew rate
Inactive mode
Inactive mode
ICC = 1mA
Active mode; ICC <65mA; 5v
Active mode; ICC <65mA; 5v,
NDS condition
Active mode; ICC <90mA; 5v
Active mode; ICC <90mA; 3v
Active mode; single pulse of
100mA for 2µs; 5 volt, fixed load
= 25mA
Active mode; single pulse of
100mA for 2µs; 3v, fixed load =
25mA
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 5v
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 5v,
NDS condition
Active mode; current pulses of
40nAs with peak |ICC | <200mA,
t <400ns; 3v
fRIPPLE = 20K – 200MHz
Static load current, VCC>4.6
Static load current, VCC>4.55 or
2.7 volts as selected
CF = 3.3µF on VCC
CF = 1.0µF on VCC
NDS applications
CF
External filter capacitor
(VCC to GND)
CF should be ceramic with low
ESR (<100mΩ).
CFNDS
External filter capacitor
(VCC to GND)
CF should be ceramic with low ESR
(<100mΩ).
Page 14
NDS applications
© 2004 TDK Semiconductor Corporation
-0.1
0.1
V
-0.1
0.4
V
4.60
5.25
V
4.75
5.25
V
4.55
2.80
5.25
3.2
V
V
4.6
5.25
V
2.76
3.2
V
4.6
5.25
V
4.65
5.25
V
2.76
3.2
V
350
65
mV
mA
90
mA
90
0.02
0.050
150
0.08
V/µs
mA
0.06
0.160
0.26
V/µs
1
3.3
5
µF
0.5
1.0
1.5
µF
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
VOH
Output level, high (I/O, AUX1,
AUX2)
ILEAK
IIL
Output level, high (I/OUC,
AUX1UC, AUX2UC)
Output level, low
Input level, high (I/O, AUX1,
AUX2)
Input level, high (I/OUC,
AUX1UC, AUX2UC)
Input level, low
Output voltage when outside
of session
Input leakage
Input current, low
ISHORTL
Short circuit output current
ISHORTH
Short circuit output current
tR, tF
Output rise time, fall times
tIR, tIF
Input rise, fall times
VOH
VOL
VIH
VIH
VIL
VINACT
RPU
Internal pull-up resistor
FDMAX
TFDIO
Maximum data rate
Delay, I/O to I/OUC, AUX1 to
AUX1UC, AUX2 to AUX2UC,
I/OUC to I/O, AUX1UC to
AUX1, AUX2UC to AUX2
(respectively falling edge to
falling edge and rising edge
to rising edge)
Input capacitance
TRDIO
CIN
Page 15
IOH =0
IOH = -40µA
IOH =0
IOH = -40µA
IOL=1mA
0.9 VCC
0.75 VCC
0.9 VDD
0.75 VDD
VCC+0.1
VCC+0.1
VDD+0.1
VDD+0.1
0.3
V
V
V
V
V
1.8
VCC+0.30
V
1.8
VDD +0.30
V
-0.3
0.8
0.1
0.3
10
0.65
V
V
V
µA
mA
15
mA
15
mA
100
ns
1
µs
11
14
kΩ
MHz
100
1
200
25
90
ns
10
pF
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
For output low,
shorted to VCC
through 33 ohms
For output high,
shorted to ground
through 33 ohms
For I/O, AUX1,
AUX2, CL = 80pF,
10% to 90%.
For I/OUC,
AUX1UC, AUX2UC,
CL=50Pf, 10% to
90%.
Output stable for
>200ns
8
60
Edge from master to
slave, measured at
50%
© 2004 TDK Semiconductor Corporation
ns
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
SYMBOL
PARAMETER
Condition
MIN
IOH =-200µA
IOL=200µA
IOL = 0
IOL = 1mA
0.9 VCC
0
Vcc = 3V
Vcc = 5V
CL = 35pF for CLK,
10% to 90%
CL = 200pF for RST,
10% to 90%
CL =35Pf,
FCLK ≤ 20MHz
0.3
0.5
Condition
MIN
Typ.
MAX
UNIT
VCC
0.3
0.1
0.3
30
70
V
V
V
V
mA
mA
V/ns
V/ns
8
ns
100
ns
55
%
MAX
UNIT
0.8
VDD + 0.3
0.45
V
V
V
V
Reset and Clock for card interface, RST, CLK
VOH
VOL
IRST_LIM
ICLK_LIM
CLKSR3V
CLKSR5V
Output level, high
Output level, low
Output voltage when outside
of session
Output current limit, RST
Output current limit, CLK
CLK slew rate
CLK slew rate
tR, tF
Output rise time, fall time
VINACT
δ
Duty cycle for CLK
45
CHARACTERISTICS: DIGITAL SIGNALS
SYMBOL
PARAMETER
Typ.
Digital I/O except for OSC I/O
VIL
VIH
VOL
VOH
ROUT
|IIL1|
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Pull-up resistor, OFF
Input Leakage Current
-0.3
0.7 VDD
IOL = 2mA
IOH = -1mA
VDD - 0.45
20
GND < VIN < VDD
-5
5
kΩ
µA
-0.3
0.7 VDD
0.3 VDD
VDD+0.3
V
V
-30
30
µA
27
MHz
52
%
Oscillator (XTALIN) I/O Parameters
VILXTAL
VIHXTAL
IILXTAL
fMAX
δin
Page 16
Input Low Voltage - XTALIN
Input High Voltage - XTALIN
Input Current XTALIN
Max freq. Osc or external clock
External input duty cycle limit
GND < VIN < VDD
tR/F < 10% fIN,
45% < δCLK < 55%
© 2004 TDK Semiconductor Corporation
48
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
DC CHARACTERISTICS
SYMBOL
IDD
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
2.7
7.0
mA
VCC on, ICC=0
I/O, AUX1,
AUX2=high,
Clock not toggling
450
650
µA
CMDVCC High
345
550
µA
Typ.
MAX
UNIT
2.4
V
Supply Current
IPC
Supply Current
IPCOFF
VPC supply current when
VCC = 0
VOLTAGE / TEMPERATURE FAULT DETECTION CIRCUITS
SYMBOL
VDDF
VPCF
VCCF
TF
Page 17
PARAMETER
VDD fault
(VDD Voltage supervisor
threshold)
VPC fault
(VPC Voltage supervisor
threshold)
VCC fault
(VCC Voltage supervisor
threshold)
Die over temperature fault
Condition
MIN
No external resistor
on VDDF_ADJ pin
2.15
VPC<VCC, a transient
event
VCC - 0.2
V
VCC = 5v
4.20
4.55
V
VCC= 3v
2.5
2.7
V
115
145
°C
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
MECHANICAL DRAWING (QFN)
0 .8 5 N O M . / 0 .9 M A X .
5
0 .0 0 / 0 .0 0 5
4.75
2.5
0 .2 0 R E F .
2.375
1
2.5
2.375
2
3
5
4.75
12º M A X
S E A T IN G
PLANE
TOP VIEW
S ID E V IE W
0.24 / 0.6
2.95 / 3.25
0.18 / 0.3
1.475 / 1.625
0.24 / 0.6
1
0.45
2
3
1.475 / 1.625
2.95 / 3.25
0.25 MIN.
0.3 / 0.5
0.25 MIN.
0.5
BOTTOM VIEW
Figure 9: 32QFN
Page 18
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
PACKAGE PIN DESIGNATION (QFN)
NC
5V/#V
CLKDIV2
CLKDIV1
AUX2UC
AUX1UC
I/OUC
NC
32
31
30
29
28
27
26
25
CAUTION: Use handling procedures necessary
for a static sensitive component
GND
1
24
XTALOUT
NC
2
23
XTALIN
VPC
3
22
OFF
CLKSTOP
4
21
GND
CLKLVL
5
20
VDD
PRES
6
19
RSTIN
PRES
7
18
CMDVCC
I/O
8
17
VDDF_ADJ
10
11
12
13
14
15
16
AUX2
AUX1
GND
CLK
RST
VCC
NC
NC
9
TDK 73S8024RN
Figure 10: 32QFN 73S8024RN Pin Out
Page 19
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
MECHANICAL DRAWING
.050 TYP. (1.270)
.305 (7.747)
.285 (7.239)
PIN NO.1
BEVEL
.715 (18.161)
.695 (17.653)
.420 (10.668)
.390 (9.906)
.010 (0.254)
.003 (0.076)
.110 (2.790)
.092 (2.336)
.335 (8.509)
.320 (8.128)
.016 nom (0.40)
Figure 11: 28 Lead SO
PACKAGE PIN DESIGNATION (SO)
CAUTION: Use handling procedures necessary
for a static sensitive component
(Top View)
CLKDIV1
1
28
AUX2UC
CLKDIV2
2
27
AUX1UC
5V3V
3
26
I/OUC
GND
4
25
XTALOUT
NC
5
24
XTALIN
VPC
6
23
OFF
CLKSTOP
7
22
GND
CLKLVL
8
21
VDD
PRES
9
20
RSTIN
PRES
10
19
CMDVCC
I/O
11
18
VDDF_ADJ
AUX2
12
17
VCC
AUX1
13
16
RST
GND
14
15
CLK
Figure 12: 28SO 73S8024RN pin out
Page 20
© 2004 TDK Semiconductor Corporation
Rev 1.1
73S8024RN
Low Cost Smart Card Interface
DATA-SHEET
ORDERING INFORMATION
PART DESCRIPTION
73S8024RN-SOL
28-pin SO
73S8024RN-SOL
28-pin SO Tape / Reel
73S8024RN-SOL
28-pin Lead-Free SO
73S8024RN-SOL
28-pin Lead-Free SO Tape / Reel
73S8024RN-QFN
32-pin QFN
73S8024RN-QFN
32-pin QFN Tape / Reel
73S8024RN-QFN
32-pin Lead-Free QFN
73S8024RN-QFN
32-pin Lead-Free QFN Tape / Reel
ORDER NO.
PACKAGING MARK
73S8024RN-IL
73S8024RN-IL
73S8024RN-ILR
73S8024RN-IL
73S8024RN-IL/F
73S8024RN-IL
73S8024RN-ILR/F
73S8024RN-IL
73S8024RN-IM
73S8024RN
73S8024RN-IMR
73S8024RN
73S8024RN-IM/F
73S8024RN
73S8024RN-IMR/F
73S8024RN
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any
infringements of patents and trademarks or other rights of third parties resulting from its use. No license is
granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation. TDK semiconductor
Corporation reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheet is current before placing orders.
TDK Semiconductor Corp. • 6440 Oak Canyon Rd. • Irvine, CA • 92618-5201
TEL (714) 508-8800 • FAX (714) 508-8877
http://www.tdksemiconductor.com
5/18/04 Rev 1.1
Page 21
© 2004 TDK Semiconductor Corporation
Rev 1.1
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