EFM32G840 Errata History

EFM32G840 Errata History
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EFM32G840 Errata History
F128/F64/F32
This document describes known errata for all revisions of EFM32G840 devices.
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1 Errata History
1.1 Errata Overview
Table 1.1 (p. 2) shows which erratum is applicable for each revision. The device datasheet explains how to identify chip revision, either from package
marking or electronically.
In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p0 (www.arm.com) also applies to all revisions of this device.
Table 1.1. Errata Overview
Erratum ID
Rev. Rev.
D
C
ACMP_E101
Rev. Rev.
B
A
X
ADC_E101
X
ADC_E102
X
ADC_E104
X
ADC_E105
X
X
ADC_E106
X
ADC_E108
X
ADC_E110
X
ADC_E111
X
X
ADC_E112
X
X
ADC_E113
X
X
ADC_E114
X
X
X
X
X
X
X
X
ADC_E115
AES_E101
X
X
BOD_E101
X
CMU_E101
X
CMU_E102
X
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Erratum ID
Rev. Rev.
D
C
Rev. Rev.
B
A
CMU_E103
X
CMU_E104
X
CMU_E105
CMU_E106
X
X
X
X
CMU_E107
X
X
X
X
CMU_E108
X
X
X
CMU_E109
X
X
X
DAC_E101
X
X
DAC_E102
X
X
DAC_E103
X
X
DAC_E104
X
X
DAC_E105
X
X
DAC_E107
X
X
DAC_E108
X
X
X
X
X
X
DMA_E101
X
X
EMU_E101
EMU_E102
X
EMU_E103
X
X
X
EMU_E104
X
X
X
X
EMU_E105
X
X
X
EMU_E106
X
X
X
HFRCO_E101
X
I2C_E101
X
I2C_E102
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X
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Erratum ID
Rev. Rev.
D
C
Rev. Rev.
B
A
LCD_E101
X
LCD_E102
X
X
LETIMER_E101
X
X
LEUART_E101
X
LEUART_E102
X
X
LEUART_E103
X
X
LFRCO_E101
X
X
LFXO_E102
X
X
PCNT_E101
X
X
X
X
X
X
RTC_E101
X
X
TIMER_E101
TIMER_E102
X
X
X
X
USART_E101
X
X
X
X
USART_E102
X
X
USART_E103
X
X
USART_E104
X
X
USART_E105
X
X
USART_E106
X
X
USART_E107
X
X
USART_E108
X
X
USART_E109
X
X
USART_E110
X
X
USART_E111
X
X
VCMP_E101
X
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Erratum ID
Rev. Rev.
D
C
VCMP_E102
Rev. Rev.
B
A
X
WDOG_E101
X
WDOG_E102
WDOG_E103
X
X
X
X
X
X
X
X
1.2 EFM32G840 Errata Descriptions
Table 1.2. EFM32G840 Errata Descriptions
ID
Title/Problem
Effect
Fix/Workaround
ACMP_E101
ACMP Mode
The ACMP only works in the low power reference mode.
When the low power reference mode is disabled (by not setting the LPREF bit in ACMPn_INPUTSEL), the ACMP does
not work and its output is always 1.
When using the ACMP, put it in its low power reference
mode by setting the LPREF bit in ACMPn_INPUTSEL (which
is the default setting). In this mode, the power consumption
in the reference buffer (VDD and bandgap) is lowered at the
cost of accuracy.
The temperature values read when sampling the temperature
sensor in the ADC are not correct.
Do not use the ADC temperature sensor.
When SCANGAIN and SINGLEGAIN in ADCn_CAL have
different values, single conversions will be affected by the
SCANGAIN value.
Configure SCANGAIN and SINGLEGAIN in ADCn_CAL to
the same value. This requires the same reference to be used
for both single and scan conversions.
At default ADC bias settings the ADC conversion results are
wrong when running the ADC_CLK at 13 MHz, which is required to reach the 1 Msample/s performance. Under typical conditions wrong conversions have been observed for
ADC_CLK speeds of 8 MHz and higher.
Increase the ADC performance by programming increased
ADC bias, for example by using value 0xF0F for register
ADCn_BIASPROG.
When the ADC is sampling voltages at (or close to) the middle of its range, the ADC output code can be off by a large
value (e.g. returning value 1023 or 3072 instead of the expected value of 2048). This effect happens for all ADC reference selections.
Perform multiple (e.g. 3) ADC measurements for each ADC
sample required and use the median value. Do not average
the ADC results, throw away the 1023 or 3072 sample instead.
The ACMP only works in the low power reference mode.
ADC_E101
ADC Temperature Sensor
The temperature sensor in the ADC
does not work.
ADC_E102
ADC SCANGAIN
SCANGAIN in ADCn_CAL affects the
gain setting for single conversions.
ADC_E104
ADC 1 Msample/s
1 Msample/s is not achived for default
ADC bias settings.
ADC_E105
ADC Output
The ADC does not always sample a
voltage at (or close to) the middle of
its range correctly (e.g. when sampling
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ID
Title/Problem
Effect
Fix/Workaround
Measurements done using one of the internal references will
not be correct before the reference has settled. This effect
appears when switching between references and when the
references have been off between samples.
When using the internal references, set WARMUPMODE=3
in ADCn_CTRL and wait until the references have settled before taking the first sample.
Temperature measurements done using the temperature
sensor in the ADC will be wrong without the fix described below.
To enable the temperature sensor, set *0x400C6018 = 0x6.
This fix can not be used at the same time as the fix for CMU4
Measurements done with the VDD reference will appear to
have been divided by 2.
Double each measurement to give the measurements the
correct amplitude, sacrificing one bit of resolution. This
workaround will not be compatible with devices of later revisions where this erratum is corrected.
The reference doubling results in a decrease of the ADC resolution by one bit. As an example, when using an external
reference of 1 V in single ended mode, a signal with values
from 0 V to 1 V will result in adc codes from 0 to 2047 instead
of the full 0 to 4095.
A temporary fix for the external references is to halve the reference voltage. This will give full resolution, but will not be
compatible with devices of later revisions where this erratum
has been corrected.
The ADC accuracy may vary depending on the ADC configuration and may in some cases be down to 10 effective bits.
The DNL/INL anomalies will cause low level spurs in the output spectra. The gain error for the 2XVDD reference is over
20 LSBs and gain for this reference cannot be calibrated.
ADC accuracy can be increased by using hardware oversampling to increase resolution and/or by increasing the
ADC bias current. The ADC oversampling rate can be
programmed in the OVSRSEL field of the ADCn_CTRL
register; the oversampling can be enabled by using the
OVS value in the RES field of the ADCn_SINGLECTRL or
ADCn_SCANCTRL register. The ADC bias current can be
programmed via the ADCn_BIASPROG register.
With a DC input voltage, the ADC output will vary depending on changes in VDD level, input common mode level, and
temperature. The temperature related variation particularly
applies to the 5VDIFF reference. For a DC level input, variability of the ADC output code over VDD is 2, 32, 7 LSBs for
the VDD, 5VDIFF, and external references respectively. With
With external references, adjust the common mode level of
the differential external reference to a lower level. For the external differential references, performance is better with the
lower external reference negative input level at 0V.
1.25V when using the 2.5V internal
reference).
ADC_E106
ADC Reference Settling
The ADC internal references, i.e.
1V25, 2V5 and VDD have a settling
time of about 500 us.
ADC_E108
ADC Temperature Sensor does not
work out of reset.
The temperature sensor in the ADC
does not work out of reset.
ADC_E110
ADC VDD Reference Gives Half
Resolution
When using the internal VDD reference, the ADC resolution is reduced to
11 bits.
ADC_E111
ADC References Doubled
In single-ended mode, external and
differential references are doubled internally.
ADC_E112
ADC Accuracy
The ADC does not meet the specified
accuracy of 11.7 effective bits. The
ADC is monotonic and although within specification, the hit frequency for
some codes such as 3071 and 3072
is such that DNL is distinctly different
from the average DNL (but there are
no missing codes). The gain of the
2XVDD reference is larger than 1.0.
ADC_E113
ADC Variability
The PSRR, CMRR and variability over
temperature for the ADC do not meet
the specification.
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ID
Title/Problem
Effect
Fix/Workaround
external references, there is about 8 LSBs variation in ADC
output code depending on the input common mode level.
ADC_E114
Incorrect ADC Calibration Register
Reset Value
The ADC will be uncalibrated out of reset and can show offset and gain error outside of specification.
Copy the gain and offset values for the selected ADC reference from the Device Information (DI) page in flash to the
corresponding ADCn_CAL register fields before starting a
conversion.
Devices with PROD_REV values of 9 or 10 does not have
correct ADC temperature sensor reading stored in the
ADC0_TEMP_0_READ_1V25 register of the Device Information Page, and using this value for calculating the temperature will yield wrong results.
Instead of using the value stored in the Device Information table, use ADC0_TEMP_0_READ_1V25 = 0x906 and
CAL_TEMP_0 = 0x19 when calculating the temperature.
These values are gathered from production data, and will
give an accuracy where 3x the standard deviation correspond to 5.2 degrees celsius.
If BYTEORDER is used in combination with DATASTART
or XORSTART, the AES data and key are interpreted in the
wrong order.
Do not use BYTEORDER in combination with DATASTART
or XORSTART.
The high BOD threshold voltage may create sporadic BOD
resets while the EFM32 is running in Energy Mode 2. Also,
the BOD may cause a reset at higher voltages than specified
as the threshold voltage in the Electrical Characterisitics.
Download Development Kit Board Support Library and Example Code (rev 1.1.1 or later) and include efm32_chip.h
in your project. In the start of the application code, call void
CHIP_Init(void);. This procedure will re-program the device to a safe BOD threshold.
The device cannot enter EM2/3 if a debug session has been
entered since the last reset. When attempting to go to either
EM2 or EM3, the system goes to EM1, and the peripheral
clocks, which should have been turned off in EM2/EM3 keep
going. This is only an issue when debugging a system.
If the debugger is running, clear HFPERCLKEN in
CMU_HFPERCLKDIV before going to EM2/EM3 and set it
when going back to EM0.
When switching between EM0 and EM2/3, the following
events can happen occasionally:
Make this line of code part of your startup code, typically
in the start of main(): *(volatile unsigned int*)
0x400C600CUL = 0x00020100; As a result of this
workaround, the current consumption in EM2/3 will go up by
The ADC calibration register
(ADCn_CAL) are not updated with calibration values from production test
during reset.
ADC_E115
Incorrect ADC Temperature Sensor
Calibration Data
The ADC temperature sensor calibration value stored in the DI page is not
correct.
AES_E101
BYTEORDER does not work
in combination with DATASTART/XORSTART
When the BYTEORDER bit in
AES_CTRL is set, an encryption or decryption should not be started through
DATASTART or XORSTART.
BOD_E101
BOD Threshold
The Brown-Out Detector (BOD)
threshold voltage is calibrated to a too
high value.
CMU_E101
Peripheral Clocks Active In EM2/
EM3 During Debug
When a debug session has been active since the last reset, EM1 is entered when trying to enter EM2 or
EM3.
CMU_E102
LFRCO/HFRCO Frequency Change
during EM2/3
• The frequency of LFRCO becomes off by up to 14%
• The frequency of HFRCO becomes off by up to 6%
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ID
CMU_E103
Title/Problem
450 nA. This fix is not compatible with devices of later revisions where this erratum has been corrected.
Wrong RCO Frequency
The oscillator frequency has not been programmed with correct calibration values, and the frequencies are not within the
expected frequency ranges.
The oscillator frequency can be calibrated in the Clock Management Unit, which is described in the CMU chapter of the
EFM32G Reference Manual.
When switching between energy modes, there is a slight
chance that HFRCO will temporarily overshoot its configured
frequency and in some cases cause a BOD reset. This overshoot may be up to 50%, and may take the system out of its
allowed opereating conditions by having a system clock higher than 32 MHz. Note that when the MSC is configured to
use zero waitstates when accessing flash, the maximum core
frequency is 16 MHz.
To fix issue, set *0x400C6018 = 0xC201. This gives better HFRCO stability at the cost of an increased current consumption in EM0 and EM1 of 10 uA. This fix is not compatible with the fix for ADC8. This fix is not compatible with devices of later revisions where this erratum has been corrected.
If AUXHFRCO is running while in EM2/EM3, and the
EMVREG bit in EMU_CTRL is cleared. This may result in an
unstable system.
Disable AUXHFRCO by writing a 1 to AUXHFRCODIS in
CMU_OSCENCMD, before going to EM2/EM3. When waking
up, enable the AUXHFRCO again if needed by writing a 1 to
AUXHFRCOEN in CMU_OSCENCMD.
When LFXOMODE in CMU_CTRL is set to DIGEXTCLK
the LFXORDY flag in CMU_STATUS and CMU_IF will not
be set when the number of cycles set in LFXOTIMEOUT in
CMU_CTRL has elapsed. Thus polling of this flag will not
work. However, the clock propagates as normal. It is only the
flag that is not set.
To detect that the clock has propagated through the ripple
counter, write to any Asynchronous Register in any Low
Energy peripheral and wait for SYNCBUSY for that register field to go low. Remember to enable the LE core clock
and the clock for the LE peripheral you choose. For example, write 0xA5 to RTC_COMP0 and wait for COMP0 in
RTC_SYNCBUSY to go low.
The LFA and LFB clocks tick with a frequency equal to
the source clock divided by 32768 when the corresponding enable bit in CMU_LFACLKEN0/CMU_LFBCLKEN0 is
not set. So, for example, if the RTC is enabled and RTC in
CMU_LFACLKEN0 is 0, the RTC will tick once every second.
Notice that it is not possible to write to a Low Energy Peripheral when the clock to the peripheral is not enabled. Thus,
the effects of this issue is only seen when the clock to an active Low Energy Peripheral is turned off.
Disable the Low Energy Peripheral before disabling the clock
to the Low Energy Peripheral to avoid unexpected behaviour.
For devices with PROD_REV < 15, enabling the clock for
LFA/LFB after reset and then immediately writing LFACLKEN/LFBCLKEN, may cause the write to miss its effect.
For devices with PROD_REV < 15, make sure
CMU_SYNCBUSY is not set before writing LFACLKEN/LFB-
Energy Mode Transitions Cause
HFRCO Overshoot
Transitions between energy modes
may cause an overshoot in the HFRCO frequency
CMU_E105
AUXHFRCO Active in EM2/EM3
AUXHFRCO is not disabled automatically when entering EM2/EM3.
CMU_E106
LFXO Digital External Mode
LFXO ready flags are never set when
LFXO is configured in Digital External
Clock mode.
CMU_E107
Disabled Low Frequency Clocks
Disabled Low Frequency Clocks tick
once every second.
CMU_E108
Fix/Workaround
RCO oscillator frequency can become The frequency will be off for a shorter or longer period.
unstable on transitions between EM2/3
and EM0.
The HFRCO, AUCHFRCO and LFRCO oscillators has wrong frequency
when running with default settings.
CMU_E104
Effect
LFxCLKEN write
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ID
Title/Problem
Effect
Fix/Workaround
First write to LFxCLKEN can be
missed.
CMU_E109
LFXO configuration incorrect
CLKEN. Can temporarily switch to HFCORECLKLEDIV2 to
speed up clearing synchbusy.
For devices with PROD_REV < 15, the default value for
LFXOBOOST in CMU_CTRL are wrong.
On devices with PROD_REV < 15, change LFXOBOOST to
0.
The DAC output starts drifting in the order of 10 mV/us after
two DAC clock cycles.
Put the DAC in continuous mode by setting the CONVMODE
field in the DACn_CTRL register to CONTINUOUS. The DAC
channels will then drive their outputs continuously with the
data in the DACn_CHxDATA registers. This mode will maintain the output voltage and refresh is therefore not needed.
As the DAC cores are not turned off between samples in
continuous mode, the power consumption is somewhat increased compared to sample/hold mode.
LFXO configuration incorrect.
DAC_E101
DAC Sample-Hold
When the DAC is in sample/hold
mode, the DAC output is not correctly
held, but drifts faster than specified.
DAC_E102
DAC Enabling
DAC conversions done closely after
enabling the DAC channel are incorrect.
DAC_E103
DAC Ringing
Ringing effects can also be observed
on the DAC output.
DAC_E104
DAC Sample-Hold/Sample-Off
The DAC output takes about 600 us (under typical conAfter enabling a DAC channel, wait 600 us before proditions) to settle after a DAC channel has been enabled
gramming the channel data (via DACn_CH0DATA,
via setting field CH0EN in DACn_CH0CTRL (or CH1EN in
DACn_CH1DATA, or DACn_COMBDATA).
DACn_CH1CTRL for channel 1). The effect is most visible for
the 1.25V and 2.5V internal references.
When applying large steps to the DAC, ringing can be observed on the output (up to 100 mV peak-to-peak depending
on load). The oscillations will last no longer than 1 us
Filter on output or don't apply large steps.
The voltage-dip causes noise
Use the DAC in continuous mode by setting the CONVMODE
field in the DACn_CTRL register to CONTINUOUS.
The DAC output is incorrect a short while after enabling the
DAC channel.
To prevent the transient on the DAC output, make sure
the DAC output is disabled by clearing OUTMODE in
DACn_CTRL when enabling a DAC channel.
The DAC accuracy may vary depending on the DAC configuration and may in some cases be down to 9 effective bits
(which is primarily caused by the SFDR without external filtering being limited to about 55 dB in case of the 1V25 ref-
No workaround.
When a sample/refresh is done while
in the sample-hold and sample-off
modes, a dip in the DAC output voltage occurs.
DAC_E105
DAC startup
When enabling a DAC channel, there
may be a transient on the channel output. This transient may be up to 800
mV and last about 1us on an unloaded
DAC.
DAC_E107
DAC Accuracy
The DAC does not meet the specified
accuracy of 11.5 effective bits. The
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ID
DAC_E108
Title/Problem
Effect
Fix/Workaround
DAC linearity does not meet the specification for all input codes.
erence). For some input codes, e.g. 1024, 2048, 3072, an
increase/decrease of one input code will result in an output
change equal to up to 3 input codes.
Incorrect DAC Calibration Register
Reset Value
The DAC will be uncalibrated out of reset and can show offset and gain error outside of specification.
Copy the gain and offset values for the selected DAC reference from the Device Information (DI) page in flash to the
corresponding DACn_CAL register fields before starting a
conversion.
In EM2, when sleeping with WFE (Wait for Event), an interrupt from the DMA will not wake up the system.
Use WFI (Wait for Interrupt) or EM1 instead.
When switching between energy modes, there is a chance
that the system will experience a BO. In that case, the system will be reset and the error condition can be detected by
reading the RMU_RSTCAUSE register, which will then show
that an internal BO was the reason for the reset.
To fix issue, set *0x400C6020 |= 0x6000. This prevents the
BO, but results in an increase of current consumption in EM0
and EM1 by about 4%. This fix is not compatible with devices
of later revisions where this erratum has been corrected.
The DMA will prevent the system to go to EM2/EM3 as long
as the DMA clock is disabled.
Make sure the DMA clock is enabled when going to EM2/
EM3. The DMA clock can be enabled in the CMU.
If EM4 is issued within a 10µs-12µs window after the 1kHz
RC oscillator rising edge transition the device will permanently consume 700nA.
There two possible workarounds for this issue.
The DAC calibration register
(DACn_CAL) are not updated with calibration values from production test
during reset.
DMA_E101
EM2 with WFE and DMA
WFE does not work for the DMA in
EM2.
EMU_E101
EM Transition Brown Out
In rare situations, transitioning between energy modes may cause a
Brown Out (BO)
EMU_E102
DMA Clock EM2/EM3
When the DMA clock is disabled, the
EFM32 is not able to go to Energy
Modes 2 or 3.
EMU_E103
EM4 current
In EM4 the device may consume
700nA instead of 20nA.
The first workaround is using the WDOG to identify the rising edge transition and add a delay before going into EM4.
Write on the WDOG_CTRL register (for instance WDOG>CTRL|=WDOG_CTRL_CLKSEL_ULFRCO) and wait for the
SYNCBUSY to be released. The release of the SYNCBUSY
happens on a rising edge transition of the 1Khz clock. After
that insert a number of __NOP(); to cause a delay of 20µs
(12µs plus margin). The number of __NOP(); will depend on
the processor frequency. After the delay EM4 can be entered
safely. Note: to implement this workaround the WDOG can
not be locked, otherwise the registers will not be written.
The second workaround is by outputting the ULFRCO on a
pin (CMU_CLK0) using CMU_CTRL and CMU_ROUTE registers. That pin should then be configured as push pull with
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ID
Title/Problem
Effect
Fix/Workaround
interrupt enable on rising edge, so the device can go to EM2
while it waits for the ULFRCO rising edge transition. When
the interrupt occurs clear it and add a number of __NOP();
before entering EM4, as described in the first workaround.
Note: the pin used to output the ULFRCO should be driven
by an external source.
EMU_E104
Sequencing of Analog and Digital
Power
Power-on Reset might fail if power is
applied to IOVDD_x or VDD_DREG
before AVDD_x
EMU_E105
Debug unavailable during DMA processing from EM2
The debugger cannot access the system processing DMA request from
EM2.
EMU_E106
SWO line pulled low in EM2
The device might lock up if power is applied to IOVDD_x or
VDD_DREG pins before AVDD_x pins during power up. This
lock-up state can be exited by removing power to the device
followed by a power up sequence according to what is described in the workaround.
Make sure that the power on the AVDD_x pins ramp earlier or at the same time as the power on IOVDD_x and
VDD_DREG during power up. Practical schematic recommendations for this workaround are given in the EFM32 Application Note "AN0002 Hardware Design Considerations".
DMA requests from the LEUART can trigger a DMA operation from EM2. While waiting for the DMA to fetch data from
the respective peripheral, the debugger cannot access the
system. If such a DMA request is not handled by the DMA
controller, the system will keep waiting for it while denying
debug access.
Make sure DMA requests triggered from EM2 are handled.
The SWO line is pulled low in EM2. This can be interpreted
as garbage by an outside observer.
Before entering EM2, disable pin-enable by clearing
SWOPEN in GPIO_ROUTE, and set SWO pin output high.
After exiting EM2, the SWO pin should be re-enabled.
The HFRCO frequency will be outside the expected frequency range when applying the calibration value from the device
information page.
The oscillator frequency can be calibrated in the Clock Management Unit, which is described in the CMU chapter of the
EFM32G Reference Manual.
If a received byte is acknowledged before it is read out of the
RXDATA, all new bytes received before the read operation
are discarded. A new byte is not discarded if the read operation is performed before the new byte is fully received.
Make sure to read the RX buffer before the reception of the
next byte completes. One way to ensure this is to always
read a received byte before acknowledging it.
When waking up from EM2/EM3 with the USART0 clock disabled, the I2C module will be in a disabled state until the USART0 clock has been enabled again.
Make sure the USART0 clock is enabled when using the I2C.
Alternatively, enable the USART0 clock for a short while after
exiting EM2/EM3.
SWO pulled low in EM2.
HFRCO_E101
HFRCO Calibration
The Device Information page does
not contain calibration values for the 1
MHz, 7 MHz, 11 MHz and 21 MHz frequency band.
I2C_E101
2
I C RX Overflow
If reception of a byte by the RX shift
register is completed while there is still
a byte in the RX buffer, the byte in the
shift register is silently discarded.
I2C_E102
2
I C Disabled After EM2/EM3
If the USART0 clock is disabled, the
I2C will not work when waking up from
EM2/EM3
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ID
Title/Problem
Effect
Fix/Workaround
LCD_E101
LCD Com Line
The LCD com lines (LCD_COM0-LCD_COM3) show intermediate voltage levels before settling to their correct values.
The artifact depends on the LCD contrast settings.
Always adjust the LCD contrast relative to VDD (VLCD) by
setting CONCONF field to 0 in LCD_DISPCTRL. This is its
default value. Use any contrast level other than the maximum
value, so keep CONLEV in LCD_DISPCTRL in the range
0-30. The default value of CONLEV is okay.
If voltage boost is enabled when the boost target voltage, given by VBLEV in LCD_DISPCTRL is lower than or close to
VDD, the current consumption of the LCD driver increases by
about 500 uA.
Make sure the voltage boost is not enabled before VDD is
below the boost target voltage. This can be done by using
the VCMP module to monitor VDD and enable/disable voltage boost when VDD goes below/above a given voltage, or
by using the ADC to regularly sample VDD.
In Buffered Mode, both CNT and LETIMERn_COMP0
shall be updated with new LETIMERn_COMP1 value
when REP0 goes to zero. Instead, CNT gets the previous
LETIMERn_COMP0 value, while LETIMERn_COMP0 is correctly updated. Thus, the first period in the next repeat-sequence is the previous top value (LETIMERn_COMP0) and
not the new top value (LETIMERn_COMP1) as one would
expect.
No workaround.
Artifacts are seen on the LCD com
lines (LCD_COM0-LCD_COM3).
LCD_E102
LCD Voltage Boost Current
When the LCD boost target voltage is
close to or lower than VDD, the voltage boost function draws an excessive
amount of current
LETIMER_E101
Buffered Top Value
CNT is updated with
LETIMERn_COMP0 instead of
LETIMERn_COMP1 when REP0 goes
to zero.
LEUART_E101
LEUART + DMA
When using the LEUART with DMA in EM2, TXDMAWU in
LEUARTn_CTRL must be cleared when the DMA has no
EM2 cannot be entered when transmit- more data to transmit. Otherwise the LEUART will keep the
ting the last byte using LEUART and
system awake waiting for data from the DMA. The way to do
DMA.
this is to clear TXDMAWU in the DMA DONE interrupt for the
channel feeding the LEUART with data. In this device revision, the DMA DONE interrupt will not trigger a wakeup from
EM2, and software will thus not be able to clear TXDMAWU
immediately when a transmission has been completed, causing the system to be awake more than necessary.
Use the TX complete interrupt (TXC) in the leuart to clear
TXDMAWU, or clear TXDMAWU in the DMA DONE interrupt
and make sure the TXC interrupt is triggered. The system will
then be awake with a higher power consumption while the
last byte is transmitted by the LEUART, but will be allowed to
go back to EM2 once TXDMAWU has been cleared.
LEUART_E102
LEUART Baudrate
For some baudrate settings, the jitter will be higher than +0.5 clock cycles, and the average baudrate value will also
not be as expected. For ~9600 b/s @ 32.768 kHz oscillator
frequency, CLKDIV=0x268 and CLKDIV=0x270 for instance
gives significantly different baudrates. For lower baudrates
there should be no problem when using a 32 kHz oscillator.
For 9600 b/s @ 32.768 kHz, use CLKDIV=0x270, which
gives a baudrate of ~9534 b/s. This workaround will not be
compatible with devices of later revisions where this erratum
has been corrected.
RXOF is set one cycle too early with the consequence that if
RX buffer is read in the same internal clock cycle as RXOF is
set, the frame causing RX data is actually loaded into the RX
Consider RXOF as an indication that an overflow might have
occurred
The LEUART baudrate generator
should have an integral baudrate error no larger than +- 0.5 clock cycles.
However, the error may be up to 1
clock cycle.
LEUART_E103
LEUART RXOF
In rare situations RX overflow interrupt
can be set despite RX data is not lost.
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ID
Title/Problem
Effect
Fix/Workaround
buffer. Thus, the overflow interrupt does not guarantee that
data has been lost.
LFRCO_E101
LFRCO Frequency
Calibrating the LFRCO for a given frequency in EM0/EM1 will
not guarantee the same frequency in EM2/EM3.
Use LFXO if an accurate clock frequency is important.
The frequency of the LFRCO changes
with up to 30% between EM0/EM1 and
EM2/EM3.
LFXO_E102
LFXO Temperature Sensitivity
LFXO may not start.
PCNT_E101
PCNT0 TOP Register
The reset value of the TOP register of
PCNT0 is incorrect.
RTC_E101
RTC PRS output
On some devices the LFXO may not start, on others the
Place a resistor in parallel with the LFXO crystal. The resistor
LFXO may stop when temperature approaches -40C. In the
should be approximately 50 MOhm.
latter case the LFXO will start up again when the temperature
rises.
When counting downwards, the pulse counter underflows to
an incorrect value. When counting upwards, no interrupt flag
is set when counting beyond the maximum value of 0xFF.
Before enabling PCNT0, write the desired top value to the
TOPB register. Then load this value into the TOP register by
setting LTOPBM in the CMD register.
If the RTC is selected as a PRS producer there might occur
glitches which will accidentally cause false triggers.
Do not use the RTC as a PRS producer, instead use one of
the other timer sources (e.g. TIMER0).
Up/down mode may generate pulses that are not centered
around the TIMERn_TOP value.
Correct PWM operation can be ensured by updating TIMERn_CCx_CCVB after the timer overflow flag
(TIMERn_IF_OF) is set. When using the DMA overflow/underflow trigger to update TIMERn_CCx_CCVB, the CCV
samples in the source buffer must duplicated once. For example, if the CCV sequence is {0x24, 0x100, 0x99}, the
buffer the DMA reads from must be {0x24, 0x24, 0x100,
0x100, 0x99, 0x99}. The first sample is written on the underflow event and the second (duplicate) is written on the overflow event. The DMA work-around is not compatible with rev
C fix.
When DEBUGRUN is disabled, and the capture input is
HIGH it is possible to wrongly trigger a capture event by halting the MCU and starting it again (for instance by setting a
breakpoint).
Enable DEBUGRUN when using a debugger.
When a frame is loaded into the transmission shift register,
transmission control bits are always taken from outer buffer
element. If only one frame is in the U(S)ART buffer, the content of the buffer elements is equivalent, and transmission
control bits work as specified. If two frames are in the buffer
If using transmission control bits in registers TXDATAX
or TXDOUBLEX make sure there are not more than one
frame in the U(S)ART buffer at a time, or that the control
bits are equal. When TXBL in U(S)ARTn_CTRL is cleared,
the TXBL status and interrupt flags in U(S)ARTn_STATUS
The RTC PRS output might cause
false triggers
TIMER_E101
TIMER Up/down Mode
In up/down mode TIMERn_CCV and
TIMER_TOP are updated on both
overflow and underflow.
TIMER_E102
Timer capture and debugger
Timer capture triggered when timer is
halted by debugger.
USART_E101
U(S)ART Double Buffer
Transmission control through TXDATAX and TXDOUBLEX does not
work with data double buffering.
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ID
USART_E102
Title/Problem
U(S)ART RXOF
In rare situations RX overflow interrupt
can be set despite RX data is not lost.
USART_E103
U(S)ART Slave TXUF Causes Shift
Slave TXUF may take TX out of sync
with master.
USART_E104
U(S)ART Autotri One Cycle Late
The AUTOTRI feature enables output
one cycle late.
USART_E105
U(S)ART Fractional Baudrate
Fractional baudrate is wrong for divisors 1.25, 1.50 and 1.75.
USART_E106
U(S)ART Slave TX Tristate
TXTRIEN/TXTRIDIS do not work in
half-duplex synchronous slave mode.
Effect
Fix/Workaround
however, the control bits for the frame in the outer buffer are
used for transmitting the frame in inner buffer. This is not
a problem for frames consisting of more than 9 bits, since
these large frames occupy both the inner and outer buffer elements.
and U(S)ARTn_IF respectively tell when the buffer is empty. When using transmission control bits, a single frame can
then be loaded into the USART for transmission.
RXOF is set one cycle too early with the consequence that if On RX overflow, the last frame received may contain a bit erRX buffer is read in the same internal clock cycle as RXOF
ror. Disregard this frame.
is set, the frame causing RX data is actually loaded into the
RX buffer. Thus, the overflow interrupt does not guarantee
that data has been lost. In addition, this frame will have its lsb
cleared when transmitting lsb first, and its msb cleared if msb
is transmitted first
When in sync slave mode, an underflow may take the slave
TX out of sync with the master clock, and data received at
the master will be shifted.
Make sure the TX does not underflow when in slave mode.
When output enable is controlled by AUTOTRI, the output
will be enabled one clock cycle after the first data is output.
The larges effect of this will occur when the U(S)ART clock is
close to the U(S)ART baudrate.
If the timing of AUTOTRI is not sufficient, use the TXTRIEN/TXTRIDIS commands to enable and disable the USART output.
The fractional baudrate generated by the U(S)ART is wrong
for the divisors 1.25, 1.50 and 1.75. This corresponds to the
CLKDIV values 0x40, 0x80 and 0xC0.
Avoid using the erroneous divisors.
In slave mode, the TXTRIEN and TXTRIDIS commands have
no effect on the enabled state of the MISO output. The MISO
output is controlled solely by whether the slave is selected
by the master or not. This affects half-duplex communication
when using the USART in synchronous slave mode.
To explicitly control output-enable in slave mode, use GPIO
to control the mode of the MISO pin.
USART_E107
U(S)ART TXC
If data is written to the U(S)ART at the same time as the previous transmission completes, the TXC status flag may be
TXC may be set even though data is in set even though new data has been written to the USART
the TX buffer.
and the USART starts transmission of this data.
Qualify the TXC status with the status of TXBL to know
whether the U(S)ART is idle and empty.
USART_E108
U(S)ART Slave TX Data Required
Early
Make sure the slave TX has data in time or use CLKPHA=1
in synchronous slave mode.
For CLKPHA=0, slave TX data is required too early.
2013-08-21 - EFM32G840FXX - d0020_Rev1.80
When operating with CLKPHA=0, and the slave TX is empty
when CS is asserted or on the last edge of a frame, the slave
underflows. In this case, no data will be clocked out on the
next frame.
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ID
Title/Problem
Effect
Fix/Workaround
USART_E109
U(S)ART Slave TXUF artifacts
When underflowing, a U(S)ART slave may give a pulse on
MISO on every setup-edge of the SPI clock. The underflow
interrupt flag may also be set multiple times during a frame
where the slave underflows.
Make sure the slave TX has data in time.
When operating as a slave with CLKPHA=0, a frame is
cleared from the TX buffer when CS is asserted by the SPI
master.
Use CLKPHA=1, or make sure to not write more data to the
slave TX than what is intended to transmit during a transmission.
MISO toggling and TXUF set multiple
times on slave TX underflow.
USART_E110
U(S)ART Slave TX Data Lost
For CLKPHA=0 a frame is cleared
from TX buffer on CS deassert.
USART_E111
U(S)ART RX DMA Request After TX
For CLKDIV less than 0x100 RX DMA
double requests come after the TX
DMA double request.
VCMP_E101
VCMP Mode
The VCMP only works in the low power reference mode.
VCMP_E102
VCMP Current
The current consumption of the VCMP
is too high in low power reference
mode.
WDOG_E101
WDOG in EM2/EM3
When operating with LOOPBK=1 writing and reading 16-bits Keep the system load under control and handle the U(S)ART
at a time to the USART using DMA on a loaded system, this
overflows
will result in TX requests being handled before RX requests,
which may result in TX transmitting frames too fast for RX too
handle, leading to RX overflows
The VCMP only works in the low power reference mode.
When the low power reference mode is disabled (by not setting the LPREF bit in VCMP_INPUTSEL), the VCMP does
not work and its output is always 1.
When using the VCMP, put it in its low power reference
mode by setting the LPREF bit in VCMP_INPUTSEL (which
is the default setting). In this mode, the power consumption
in the reference buffer (VDD and bandgap) is lowered at the
cost of accuracy.
When the VCMP is enabled in low power reference mode,
the current consumption is higher than specified. The current
is the same independent of whether the low power reference
mode is enabled or not.
No workaround.
After a watchdog reset from EM2/EM3, the EFM32 may go
directly to hard fault or may not start at all.
Do not use the watchdog in EM2/EM3 by disabling WDOG
before entering EM2/EM3. Note that EM2RUN and EM3RUN
bits cannot be used (see WDOG2 Erratum description).
If the WDOG is enabled when entering EM2 or EM3, a
WDOG reset will occur unless the system wakes up from
EM2/EM3 (by interrupt) and clears the WDOG timer before
the WDOG times out.
Disable WDOG before entering EM2/EM3 by writing EN bit
in WDOG_CTRL to 0. This requires that the WDOG configuration is unlocked (LOCK bit in WDOG_CTRL = 0). If WDOG
configuration is locked, the WDOG will remain enabled in
EM2/EM3 and the system must wake up the device from
EM2/EM3 and clear WDOG before WDOG times out.
When the watchdog (WDOG) triggers
a reset while the EFM32 is in EM2 or
EM3, the resulting behaviour is undefined.
WDOG_E102
WDOG does not freeze in EM2/EM3
The WDOG keeps running in EM2
and EM3 even though EM2RUN and
EM3RUN bits in WDOG_CTRL are
programmed to 0.
WDOG_E103
WDOG EM2 detection with LFXO
digital/sine input
2013-08-21 - EFM32G840FXX - d0020_Rev1.80
When the WDOG is using LFXO with digital or sine input as a When using LFXO with digital/sine input, EM3RUN must be
clock source, it will mistake EM2 for EM3. The EM2RUN and set to keep the WDOG running in EM2.
EM3RUN bits of WDOG_CTRL will behave accordingly.
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ID
Title/Problem
Effect
Fix/Workaround
The WDOG will mistake EM2 for EM3
if using LFXO with digital or sine input.
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2 Revision History
2.1 Revision 1.80
August 21st, 2013
Updated disclaimer, trademark and contact information.
2.2 Revision 1.70
July 30th, 2013
Added DMA_E101.
Updated errata naming convention.
2.3 Revision 1.60
December 11th, 2012
Added AES1.
Added TIMER2.
Updated with chip revision D.
2.4 Revision 1.50
January 12th, 2012
Added ADC15.
Added CMU6.
Added CMU8.
Added CMU9.
Added EMU5.
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Added WDOG3.
2.5 Revision 1.40
November 17th, 2010
Added EMU4.
Added ADC14.
Added DAC8.
Updated BOD1 description to new CMSIS naming.
Updated CMU2 description.
Updated CMU4 description.
Updated CMU5 description.
Updated EMU1 description.
Updated EMU2 description.
Updated ADC10 description.
Updated LEUART2 description.
2.6 Revision 1.30
October 26th, 2010
Added EMU3 and RTC1.
2.7 Revision 1.20
August 31st, 2010
Updated with chip revision C information.
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Added WDOG2.
2.8 Revision 1.00
April 23rd, 2010
Initial Version.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system
and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples
described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon
Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications.
Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or
chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, the Silicon Labs logo, Energy Micro, EFM, EFM32, EFR, logo and combinations thereof, and others are the
registered trademarks or trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM
Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Errata History ............................................................................................................................................................................................................................. 2
1.1. Errata Overview ................................................................................................................................................................................................................ 2
1.2. EFM32G840 Errata Descriptions .......................................................................................................................................................................................... 5
2. Revision History ........................................................................................................................................................................................................................ 17
2.1. Revision 1.80 ................................................................................................................................................................................................................. 17
2.2. Revision 1.70 ................................................................................................................................................................................................................. 17
2.3. Revision 1.60 ................................................................................................................................................................................................................. 17
2.4. Revision 1.50 ................................................................................................................................................................................................................. 17
2.5. Revision 1.40 ................................................................................................................................................................................................................. 18
2.6. Revision 1.30 ................................................................................................................................................................................................................. 18
2.7. Revision 1.20 ................................................................................................................................................................................................................. 18
2.8. Revision 1.00 ................................................................................................................................................................................................................. 19
A. Disclaimer and Trademarks ......................................................................................................................................................................................................... 20
A.1. Disclaimer ..................................................................................................................................................................................................................... 20
A.2. Trademark Information ..................................................................................................................................................................................................... 20
B. Contact Information ................................................................................................................................................................................................................... 21
B.1. ................................................................................................................................................................................................................................... 21
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List of Tables
1.1. Errata Overview ........................................................................................................................................................................................................................ 2
1.2. EFM32G840 Errata Descriptions .................................................................................................................................................................................................. 5
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