DM00041883
STGIPS30C60
SLLIMM™ small low-loss intelligent molded module
IPM, 3-phase inverter - 30 A, 600 V short-circuit rugged IGBT
Datasheet - production data
Applications
• 3-phase inverters for motor drives
• Air conditioners
Description
This intelligent power module provides a
compact, high performance AC motor drive in a
simple, rugged design. Combining ST proprietary
control ICs with the most advanced short-circuitrugged IGBT system technology, this device is
ideal for 3-phase inverters in applications such as
motor drives and air conditioners. SLLIMM™ is a
trademark of STMicroelectronics.
SDIP-25L
Features
• IPM 30 A, 600 V 3-phase IGBT inverter bridge
including control ICs for gate driving and freewheeling diodes
• Short-circuit rugged IGBTs
• 3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull down /
pull up resistors
• Undervoltage lockout
• Internal bootstrap diode
• Interlocking function
• Smart shutdown function
• Comparator for fault protection against over
temperature and overcurrent
• DBC leading to low thermal resistance
• Isolation rating of 2500 Vrms/min
• UL recognized: UL1557 file E81734
Table 1. Device summary
Order code
Marking
Package
Packing
STGIPS30C60
GIPS30C60
SDIP-25L
Tube
March 2015
This is information on a product in full production.
DocID022471 Rev 8
1/20
www.st.com
Contents
STGIPS30C60
Contents
1
Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
6
7
2/20
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
SDIP-25L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID022471 Rev 8
STGIPS30C60
1
Internal block diagram and pin configuration
Internal block diagram and pin configuration
Figure 1. Internal block diagram
Pin 1
Pin 25
OUT U
P
VBOOT U
LIN
Vboot
LIN-U
SD/OD HVG
HIN-U
HIN
VCC
OUT
U
VCC
DT
LVG
CP+
NU
GND
OUT V
VBOOT V
P
LIN
GND
Vboot
SD/OD HVG
LIN-V
HIN
HIN-V
VCC
OUT
V
DT
LVG
CP+
NV
GND
OUT W
VBOOT W
P
LIN
Vboot
LIN-W
SD/OD HVG
HIN-W
HIN
SD/OD
VCC
CIN
OUT
W
DT
LVG
Pin 16
CP+
NW
GND
Pin 17
AM05002v1
DocID022471 Rev 8
3/20
20
Internal block diagram and pin configuration
STGIPS30C60
Table 2. Pin description
Pin n°
Symbol
Description
1
OUTU
High-side reference output for U phase
2
VbootU
Bootstrap voltage for U phase
3
LINU
Low-side logic input for U phase
4
HINU
High-side logic input for U phase
5
VCC
Low voltage power supply
6
OUTV
High-side reference output for V phase
7
Vboot V
Bootstrap voltage for V phase
8
GND
Ground
9
LINV
Low-side logic input for V phase
10
HINV
High-side logic input for V phase
11
OUTW
High-side reference output for W phase
12
Vboot W
Bootstrap voltage for W phase
13
LINW
Low-side logic input for W phase
14
HINW
High-side logic input for W phase
15
SD / OD
16
CIN
Comparator input
17
NW
Negative DC input for W phase
18
W
W phase output
19
P
Positive DC input
20
NV
21
V
V phase output
22
P
Positive DC input
23
NU
Negative DC input for U phase
24
U
U phase output
25
P
Positive DC input
Shutdown logic input (active low) / open-drain (comparator output)
Negative DC input for V phase
Figure 2. Pin layout (bottom view)
0$5.,1*$5($
4/20
DocID022471 Rev 8
STGIPS30C60
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Table 3. Inverter part
Symbol
Parameter
Value
Unit
VPN
Supply voltage applied between P - NU, NV, NW
450
V
VPN(surge)
Supply voltage (surge) applied between P - NU,
NV, NW
500
V
VCES
Each IGBT collector emitter voltage (VIN(1) = 0)
600
V
Each IGBT continuous collector current
at TC = 25°C
30
A
Each IGBT pulsed collector current
60
A
Each IGBT total dissipation at TC = 25°C
52
W
Short circuit withstand time, VCE = 0.5 V(BR)CES
TJ = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0 - 5 V
5
µs
Value
Unit
Vboot - 21 to Vboot + 0.3
V
± IC
± ICP (2)
PTOT
tscw
1. Applied between HINi, LINi and GND for i = U, V, W
2. Pulse width limited by max junction temperature
Table 4. Control part
Symbol
Parameter
VOUT
Output voltage applied between
OUTU, OUTV, OUTW - GND
VCC
Low voltage power supply
-0.3 to +21
V
VCIN
Comparator input voltage
-0.3 to VCC +0.3
V
Vboot
Bootstrap voltage applied between
Vboot i - OUTi for i = U, V, W
-0.3 to 620
V
Logic input voltage applied between HIN, LIN and
GND
-0.3 to 15
V
Open drain voltage
-0.3 to 15
V
50
V/ns
Value
Unit
2500
V
VIN
VSD/OD
dVOUT/dt
Allowed output slew rate
Table 5. Total system
Symbol
VISO
Parameter
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.)
Tj
Power chips operating junction temperature
-40 to 150
°C
TC
Module case operation temperature
-40 to 125
°C
DocID022471 Rev 8
5/20
20
Electrical ratings
2.2
STGIPS30C60
Thermal data
Table 6. Thermal data
Symbol
RthJC
Parameter
Value
Unit
Thermal resistance junction-case single IGBT
2.4
°C/W
Thermal resistance junction-case single diode
5
°C/W
Figure 3. Maximum IC(RMS) current vs. switching
frequency (1)
Ic(RMS)
(A)
AM17110v1
3-phase sinusoidal PWM
VPN = 300 V, Modulation Index = 0.8,
PF = 0.6, Tj = 150 °C, fsine = 60 Hz
32
30
28
Figure 4. Maximum IC(RMS) current vs. fsine(1)
AM17111v1
Ic(RMS)
(A)
3 -phase sinusoidal PWM
VPN = 300 V, Modulation Index = 0.8,
PF = 0.6, T j = 150 °C,Tc = 100 °C
20
18
26
fsw = 16 kHz
fsw = 12 kHz
Tc = 80 °C
16
24
22
14
20
fsw = 20 kHz
12
18
Tc = 100 °C
16
10
14
12
4
8
12
16
f sw (kHz)
8
1
1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c.
6/20
DocID022471 Rev 8
10
100
f sine (Hz)
STGIPS30C60
3
Electrical characteristics
Electrical characteristics
TJ = 25 °C unless otherwise specified.
Table 7. Inverter part
Value
Symbol
VCE(sat)
ICES
VF
Parameter
Test conditions
Unit
Min.
Typ.
Max.
VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V,
IC = 30 A
-
1.9
2.4
VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V,
IC = 30 A, TJ = 125 °C
-
Collector-cut off current
(VIN(1)= 0 “logic state”)
VCE = 550 V, VCC = VBoot = 15 V
-
100
µA
Diode forward voltage
VIN(1) = 0 “logic state”, IC = 30 A
-
2.35
V
Collector-emitter
saturation voltage
V
2.2
Inductive load switching time and energy
ton
tc(on)
toff
tc(off)
trr
Turn-on time
Crossover time (on)
Turn-off time
Crossover time (off)
Reverse recovery time
Eon
Turn-on switching losses
Eoff
Turn-off switching losses
VPN = 300 V,
VCC = Vboot = 15 V,
VIN(1) = 0 ÷ 5 V,
IC = 30 A
(see Figure 5)
-
440
-
-
190
-
-
780
-
-
135
-
-
505
-
-
870
-
-
740
-
ns
µJ
1. Applied between HINi, LINi and GND for i = U, V, W. (LIN inputs are active-low).
Note:
tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are
the switching time of IGBT itself under the internally given gate driving condition.
DocID022471 Rev 8
7/20
20
Electrical characteristics
STGIPS30C60
Figure 5. Switching time test circuit
AM06019v2
Figure 6. Switching time definition
100% IC 100% IC
t rr
IC
VCE
VCE
IC
VIN
VIN
t ON
t OFF
t C(OFF)
t C(ON)
VIN(ON)
10% IC 90% IC 10% VCE
(a) turn-on
VIN(OFF)
10% VCE
(b) turn-off
10% IC
AM09223V1
Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity
must be inverted for turn-on and turn-off.
8/20
DocID022471 Rev 8
STGIPS30C60
3.1
Electrical characteristics
Control part
Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vcc UV hysteresis
1.2
1.5
1.8
V
VCC_thON
Vcc UV turn ON threshold
11.5
12
12.5
V
VCC_thOFF
Vcc UV turn OFF threshold
10
10.5
11
V
VCC_hys
Parameter
Test conditions
Iqccu
Undervoltage quiescent
supply current
VCC = 10 V
SD/OD = 5 V; LIN = 5 V;
HIN = 0, CIN = 0
450
µA
Iqcc
Quiescent current
VCC = 15 V
SD/OD = 5 V; LIN = 5 V
HIN = 0, CIN = 0
3.5
mA
Vref
Internal comparator (CIN)
reference voltage
0.58
V
0.5
0.54
Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
VBS UV hysteresis
1.2
1.5
1.8
V
VBS_thON
VBS UV turn ON threshold
11.1
11.5
12.1
V
VBS_thOFF
VBS UV turn OFF threshold
9.8
10
10.6
V
IQBSU
Undervoltage VBS quiescent
current
VBS < 9 V
SD/OD = 5 V; LIN and
HIN = 5 V; CIN = 0
70
110
µA
IQBS
VBS quiescent current
VBS = 15 V
SD/OD = 5 V; LIN and
HIN = 5 V; CIN = 0
200
300
µA
Bootstrap driver on resistance
LIN= 5 V; HIN= 0 V
120
VBS_hys
RDS(on)
Parameter
Test conditions
Ω
Table 10. Logic inputs (VCC = 15 V unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vil
Low logic level voltage
0.8
1.1
V
Vih
High logic level voltage
1.9
2.25
V
260
µA
1
µA
20
µA
1
µA
300
µA
3
µA
IHINh
HIN logic “1” input bias current
HIN = 15 V
IHINl
HIN logic “0” input bias current
HIN = 0 V
ILINl
LIN logic “1” input bias current
LIN = 0 V
ILINh
LIN logic “0” input bias current
LIN = 15 V
ISDh
SD logic “0” input bias current
SD = 15 V
ISDl
SD logic “1” input bias current
SD = 0 V
Dt
Dead time
see Figure 7 and Table 13
DocID022471 Rev 8
110
3
30
175
6
120
1.2
µs
9/20
20
Electrical characteristics
STGIPS30C60
Table 11. Sense comparator characteristics (VCC = 15 V unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Iib
Input bias current
VCIN(i) = 1 V
Vol
Open-drain low-level output
voltage
Iod = 3 mA
Comparator delay
SD/OD pulled to 5 V through
100 kΩ resistor
90
SR
Slew rate
CL = 180 pF; Rpu = 5 kΩ
60
tsd
Shut down to high / low side
driver propagation delay
VOUT = 0, Vboot = VCC,
VIN = 0 to 3.3 V
tisd
Comparator triggering to high /
low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN
td_comp
50
Max.
Unit
3
µA
0.5
V
130
ns
V/µsec
125
200
ns
50
200
250
Table 12. Truth table
Logic input (VI)
Output
Condition
SD/OD
LIN
HIN
LVG
HVG
Shutdown enable
half-bridge tri-state
L
X
X
L
L
Interlocking
half-bridge tri-state
H
L
H
L
L
0 ‘’logic state”
half-bridge tri-state
H
H
L
L
L
1 “logic state”
low side direct driving
H
L
L
H
L
1 “logic state”
high side direct driving
H
H
H
L
H
Note:
10/20
X: don’t care
DocID022471 Rev 8
STGIPS30C60
Waveforms definitions
Figure 7. Dead time and interlocking waveforms definitions
HIN
INTE
RLO
CK
ING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
ING
LIN
INTE
RLO
CK
3.2
Electrical characteristics
LVG
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DocID022471 Rev 8
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
11/20
20
Smart shutdown function
4
STGIPS30C60
Smart shutdown function
The STGIPS30C60 integrates a comparator for fault sensing purposes. The comparator has
an internal voltage reference Vref connected to the inverting input, while the non-inverting
input, available on pin (CIN), can be connected to an external shunt resistor in order to
implement a simple over-current protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the
halfbridge in tri-state. In the common overcurrent protection architectures the comparator
output is usually connected to the shutdown input through a RC network, in order to provide
a mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic
which holds it on until the shutdown voltage is lower than the logic input lower threshold
(Vil). Finally the smart shutdown function provides the possibility to increase the real disable
time without increasing the constant time of the external RC network.
12/20
DocID022471 Rev 8
STGIPS30C60
Smart shutdown function
Figure 8. Smart shutdown timing waveforms
comp Vref
CP+
HIN/LIN
PROTECTION
HVG/LVG
SD/OD
open drain gate
(internal)
disable time
Fast shut down:
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal has not yet reach the lower input threshold
An approximation of the disable time is given by:
SHUT DOWN CIRCUIT
VBIAS
where:
RSD
SD/OD
FROM/TO
CONTROLLER
CSD
RON_OD
SMART
SD
LOGIC
RPD_SD
AM12947v1
Pls refer to Table 11 for internal propagation delay time details.
DocID022471 Rev 8
13/20
20
14/20
3.3V/5V Line
DocID022471 Rev 8
Csd
Rsd
Cbw
Cbv
CIN
SD/OD
HIN-W
LIN-W
VBOOT W
OUT W
HIN-V
LIN-V
GND
VBOOT V
OUT V
VCC
HIN-U
LIN-U
VBOOT U
OUT U
Rdt
Cvcc
Rdt
Cvcc
Rdt
Cvcc
Cdt
Cdt
Cdt
OUT
HIN
OUT
HIN
OUT
HIN
GND
DT
CP+
LVG
HVG
VCC
Vboot
SD/OD
CP+
LIN
GND
DT
LVG
HVG
VCC
Vboot
SD/OD
CP+
LIN
GND
DT
LVG
HVG
SD/OD
VCC
Vboot
LIN
Rg
Rg
Rg
Rg
Rg
Rg
T6
T5
T4
T3
T2
T1
D6
D5
D4
D3
D2
D1
C
R
Nw
W
Nv
V
Nu
U
P
Rshunt
M
+
VDC
5
VCC
Cbu
Applications information
STGIPS30C60
Applications information
Figure 9. Typical application circuit
CONTROLLER
AM05001v2
STGIPS30C60
5.1
Applications information
Recommendations
•
Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each
high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.
•
Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an
internal 5 V regulator through a diode, is built-in for each low side input.
•
To prevent the input signals oscillation, the wiring of each input should be as short as
possible.
•
By integrating an application specific type HVIC inside the module, direct coupling to
MCU terminals without any opto-coupler is possible.
•
Each capacitor should be located as nearby the pins of IPM as possible.
•
Low inductance shunt resistors should be used for phase leg current sensing.
•
Electrolytic bus capacitors should be mounted as close to the module bus terminals as
possible. Additional high frequency ceramic capacitor mounted close to the module
pins will further improve performance.
•
The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: Smart shutdown function for detailed info).
Table 13. Recommended operating conditions
Value
Symbol
Parameter
Conditions
Unit
Min.
VPN
Note:
Supply Voltage
Applied between P-Nu,Nv,Nw
VCC
Control supply voltage Applied between VCC-GND
VBS
High side bias voltage
tdead
13.5
Applied between VBOOTi-OUTi for
i=U,V,W
13
Blanking time to
prevent Arm-short
For each input signal
1.5
fPWM
PWM input signal
-40°C < Tc < 100°C
-40°C < Tj < 125°C
TC
Case operation
temperature
Typ.
Max.
300
400
V
15
18
V
18
V
µs
20
kHz
100
°C
For further details refer to AN3338.
DocID022471 Rev 8
15/20
20
Package information
6
STGIPS30C60
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Please refer to dedicated technical note TN0107 for mounting instructions.
6.1
SDIP-25L package information
Figure 10. SDIP-25L package outline
B
16/20
DocID022471 Rev 8
STGIPS30C60
Package information
Table 14. SDIP-25L mechanical data
mm
Dim.
Min.
Typ.
Max.
A
43.90
44.40
44.90
A1
1.15
1.35
1.55
A2
1.40
1.60
1.80
A3
38.90
39.40
39.90
B
21.50
22.00
22.50
B1
11.25
11.85
12.45
B2
24.83
25.23
25.63
C
5.00
5.40
6.00
C1
6.50
7.00
7.50
C2
11.20
11.70
12.20
C3
2.90
3.00
3.10
e
2.15
2.35
2.55
e1
3.40
3.60
3.80
e2
4.50
4.70
4.90
e3
6.30
6.50
6.70
D
33.30
D1
5.55
E
11.20
E1
1.40
F
0.85
1.00
1.15
F1
0.35
0.50
0.65
R
1.55
1.75
1.95
T
0.45
0.55
0.65
V
0°
6°
DocID022471 Rev 8
17/20
20
Package information
6.2
STGIPS30C60
Packing information
Base quantity: 11 pcs
Bulk quantity: 132 pcs
8123127_E
AM10488v1
Figure 11. SDIP-25L packing specification
18/20
DocID022471 Rev 8
STGIPS30C60
7
Revision history
Revision history
Table 15. Document revision history
Date
Revision
07-Dec-2011
1
Initial release
04-Dec-2012
2
Added: PTOT value Table 3 on page 5, RthJC values Table 6 on
page 6, typical values Table 7 on page 7
Removed: note 2 Table 3 on page 5.
02-Apr-2013
3
Added Figure 3 and Figure 4 on page 6.
Updated: Figure 8 on page 13.
17-Jun-2013
4
Updated Dt value in Table 10: Logic inputs (VCC = 15 V unless
otherwise specified), Figure 7: Dead time and interlocking
waveforms definitions and tdead in Table 13: Recommended
operating conditions.
09-Jul-2013
5
Updated Dt value in Table 10: Logic inputs (VCC = 15 V unless
otherwise specified)
12-Jul-2013
6
Document status promoted from preliminary to production data.
14-May-2014
7
Updated Table 3: Inverter part, Table 6: Thermal data, Table 7:
Inverter part and Section 7: Packaging mechanical data.
Minor text changes.
8
Minor text and formating changes.
Updated Figure 2
Section 6: Package information:
- Renamed (was Package mechanical data)
- Updated with revised package outline and mechanical data.
- Added Section 6.2: Packing information (was Section 7:
Packaging mechanical data)
20-Mar-2015
Changes
DocID022471 Rev 8
19/20
20
STGIPS30C60
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
20/20
DocID022471 Rev 8
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement