Fujitsu MB15F74UV Datasheet

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Fujitsu MB15F74UV Datasheet | Manualzz

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual S erial Input

PLL Frequency

Synthesizer

MB15F76UL

DS04-21373-1E

DESCRIPTION

The Fujitsu MB15F76UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 6.0 GHz and a

1.5 GHz prescalers. Both prescalers for RF and IF have a 1/4 divider. A 16/17 or a 32/33 for the 6.0 GHz prescaler, and a 4/5 or a 8/9 for the 1.5 GHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 8.5 mA at 3.0 V. The supply voltage range is from 2.5 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The pin assignments are is the same as the MB15F78UL. Fast locking is achieved for adopting the new circuit.

The new package (BCC20) decreases a mount area of MB15F76UL more than 30

%

comparing with the former

BCC16 (for dual PLL) .

PACKAGE

20-pad plastic BCC

(LCC-20P-M05)

2

MB15F76UL

FEATURES

• High frequency operation : RF synthesizer : 6.0 GHz Max

: IF synthesizer : 1.5 GHz Max

• Low power supply voltage : V

CC

=

2.5 V to 3.6 V

• Ultra low power supply current : I

CC

=

8.5 mA Typ

(V

CC

=

Vp

=

3.0 V, Ta

= +

25

°

C, SW

IF

=

SW

RF

=

0 in IF/RF locking state)

• Direct power saving function : Power supply current in power saving mode

Typ. 0.1

µ

A (V

10

µ

A (V

CC

=

Vp

=

3.0 V, Ta

= +

25

°

C)

CC

=

Vp

=

3.0 V)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 6.0 GHz prescaler (1/4 divider and 16/17 or 32/33) /

1.5 GHz prescaler (1/4 divider and 4/5 or 8/9)

• 23-bit shift register

• Serial input binary 14-bit programmable reference divider : R

=

3 to 16,383

• Serial input programmable divider consisting of:

- Binary 5-bit swallow counter : 0 to 31

- Binary 13-bit programmable counter : 3 to 8,191

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta

= −

40

°

C to

+

85

°

C

PIN ASSIGNMENT

(BCC-20)

TOP VIEW fin

IF

Xfin

IF

GND

IF

V

CCIF

PS

IF

Vp

IF

OSC

IN

Data

GND Clock

1

4

5

2

3

6

20 19 18 17

16

15

14

13

12

7 8 9 10 11

Do

IF

Do

RF

LD/fout Vp

RF

LE fin

RF

Xfin

RF

GND

RF

V

CCRF

PS

RF

(LCC-20P-M05)

MB15F76UL

PIN DESCRIPTION

Pin no.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Pin name

I/O Descriptions

fin

IF

I

Prescaler input pin for the IF-PLL.

Connection to an external VCO should be AC coupling.

Xfin

IF

I

Prescaler complimentary input for the IF-PLL section.

This pin should be grounded via a capacitor.

GND

IF

Ground pin for the IF-PLL section.

V

CCIF

Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit), the shift register and the oscillator input buffer.

PS

Vp

Do

IF

IF

IF

I

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.)

PS

IF

=

“H” ; Normal mode/PS

IF

=

“L” ; Power saving mode

Power supply voltage input pin for the IF-PLL charge pump.

O Charge pump output for the IF-PLL section.

LD/fout O

PS

RF

I

Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data.

LDS bit

=

“H” ; outputs fout signal/LDS bit

=

“L” ; outputs LD signal

Do

RF

O Charge pump output for the RF-PLL section.

Vp

RF

Power supply voltage input pin for the RF-PLL charge pump.

Power saving mode control for the RF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited. )

PS

RF

=

“H” ; Normal mode/PS

RF

=

“L” ; Power saving mode

V

CCRF

Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit)

GND

RF

Ground pin for the RF-PLL section

Xfin

RF

I

Prescaler complimentary input pin for the RF-PLL section.

This pin should be grounded via a capacitor.

fin

RF

I

Prescaler input pin for the RF-PLL.

Connection to an external VCO should be via AC coupling.

LE

Data I

I

Load enable signal input pin (with the schmitt trigger circuit)

When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.

Serial data input pin (with the schmitt trigger circuit)

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.

Clock I

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)

One bit data is shifted into the shift register on a rising edge of the clock.

OSC

IN

I

The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor.

GND

Ground pin for OSC input buffer and the shift register circuit.

3

4

MB15F76UL

BLOCK DIAGRAM

V

CCIF

GND

IF

4 3

Vp

IF

6

PS

IF

5 fin

IF

1

Xfin

IF

2

OSC

IN

19

Intermittent mode control

(IF-PLL)

Prescaler

(IF-PLL)

Modulus

(4/5, 8/9)

1/4 divider

OR fin

RF

15

Xfin

RF

14

PS

RF

11

1/4 divider

Modulus

(16/17, 32/33)

Prescaler

(RF-PLL)

Intermittent mode control

(RF-PLL)

3 bit latch

5 bit latch 13 bit latch

Binary 5-bit swallow counter

(IF-PLL)

Binary 13-bit programmable counter (IF-PLL) fp

IF

Phase comp.

(IF-PLL)

Fast lock

Tuning

Charge pump

(IF-PLL)

Current

Switch

7

Do

IF

Lock Det.

(IF-PLL)

LD

IF

2 bit latch

T1 T2

14 bit latch

Binary 14-bit programmable ref.

counter(IF-PLL)

1 bit latch

C/P setting counter fr

IF

T1 T2

2 bit latch fr

RF

Binary 14-bit programmable ref.

counter (RF-PLL))

14 bit latch

C/P setting counter

1 bit latch

AND

Fast lock

Tuning

Selector

LD fr

IF fr

RF fp

IF fp

RF

8

LD

/ fout fp

RF

LD

RF

Lock Det.

(RF-PLL)

3 bit latch

Binary 5-bit swallow counter

(RF-PLL)

Binary 13-bit programmable counter (RF-PLL) fp

RF

Phase comp.

(RF-PLL)

5 bit latch 13 bit latch

Charge pump

(RF-PLL)

Current

Switch

9

Do

RF

LE 16

Schmitt circuit

Latch selector

Data 17

Clock 18

Schmitt circuit

Schmitt circuit

C

N

1

C

N

2

23-bit shift register

20

GND

12 13

V

CCRF

GND

RF

10

Vp

RF

MB15F76UL

ABSOLUTE MAXIMUM RATINGS

V

O

V

DO

Tstg

Rating

Input voltage

Parameter

Power supply voltage

Output voltage

Storage temperature

LD/fout

Do

IF

, Do

RF

Symbol

V

CC

Vp

V

I

Min.

0.5

V

CC

0.5

GND

GND

55

Max.

4.0

4.0

V

CC

+

0.5

V

CC

Vp

+

125

Unit

V

V

V

V

V

°

C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

Value

Parameter Symbol Unit Remarks

Min.

Typ.

Max.

V

CC

2.5

V

CC

3.0

3.6

3.6

V

V

V

CCRF

=

V

CCIF

Power supply voltage

Input voltage

Operating temperature

Vp

V

Ta

I

GND

40

3.0

V

+

CC

85

°

V

C

Note :

V

CCRF

, Vp

RF

, V

CCIF

and Vp

IF

must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF

, Vp

RF

, V

CCIF

and Vp

IF

to keep them equal.

It is recommended that the non-use PLL is controlled by power saving function.

Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry

has been improved in electrostatic protection, observe the following precautions when handling the device.

When storing and transporting the device, put it in a conductive case.

Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench.

Before fitting the device into or removing it from the socket, turn the power supply off.

When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

5

6

MB15F76UL

*

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition

(V

CC

=

2.5 V to 3.6 V, Ta

= −

40

°

C to

+

85

°

C)

Value

Unit

Min.

Typ.

Max.

Power supply current

Power saving current

I

I

CCIF

CCRF

*1

*1 fin

IF

=

570 MHz,

V

CCIF

=

Vp

IF

=

3.0 V fin

RF

=

4750 MHz,

V

CCRF

=

Vp

RF

=

3.0 V

I

PSIF

PS

IF

=

PS

RF

=

“L”

I

PSRF

PS

IF

=

PS

RF

=

“L” fin

IF

IF PLL fin

IF

*3

Operating frequency fin

RF

*3 fin

RF

RF PLL

Input sensitivity

OSC fin

IF fin

RF

Input available voltage OSC

IN

IN f

OSC

Pfin

IF

IF PLL, 50

system

Pfin

RF

RF PLL, 50

system

V

OSC

V

IH

Schmitt trigger input “H” level input voltage

“L” level input voltage

Data

LE

Clock

V

IL

“H” level input voltage

“L” level input voltage

PS

PS

IF

RF

“H” level input current

“L” level input current

Data

LE

Clock

PS

“H” level input current

“L” level input current

OSC

“H” level output voltage LD/

“L” level output voltage fout

“H” level output voltage Do

IF

“L” level output voltage

Do

RF

High impedance cutoff current

Do

IF

Do

RF

“H” level output current LD/

“L” level output current fout

IN

I

I

V

V

IH

IL

IH

IL

*4

*4

Schmitt trigger input

1.8

0.7 V

1.0

1.0

CC

I

I

IH

IL

V

*4

OH

0

100

V

CC

=

Vp

=

3.0 V, I

OH

= −

1 mA V

CC

0.4

V

OL

V

CC

=

Vp

=

3.0 V, I

OL

=

1 mA

V

DOH

V

CC

=

Vp

=

3.0 V, I

DOH

= −

0.5 mA Vp

0.4

I

V

DOL

V

CC

=

Vp

=

3.0 V, I

DOL

=

0.5 mA

I

OFF

V

CC

=

Vp

=

3.0 V

V

OFF

=

0.5 V to Vp

0.5 V

OH

I

*4

OL

V

CC

=

Vp

=

3.0 V

V

CC

=

Vp

=

3.0 V

1.0

5.2

100

2000

3

15

10

0.5

0.7 V

CC

+

0.4

2.3

6.2

0.1

*2

0.1

*2

10

1500

6000

0.3 V

CC

0.4

0.3 V

+

+

2.9

7.5

10

40

+

2

+

2

V

CC

1.0

1.0

+

100

0

0.4

0.4

2.5

CC mA mA

µ

A

µ

A

MHz

MHz

MHz dBm dBm

V

P

P

V

V

V

V

µ

A

µ

A

µ

A

µ

A

V

V

V

V nA

1.0

 mA mA

(Continued)

MB15F76UL

(Continued)

Parameter

“H” level output current

Do

Do

IF

*8

RF

Symbol

I

DOH

*4

Ta

= +

25

°

C

Condition

V

CC

=

Vp

=

3.0 V,

V

DOH

=

Vp

/

2,

(V

CC

=

2.5 V to 3.6 V, Ta

= −

40

°

C to

+

85

°

C)

Value

Unit

Min.

Typ.

Max.

CS bit

=

“H”

CS bit

=

“L”

8.2

2.2

6.0

1.5

4.1

0.8

mA mA

“L” level output current

Charge pump current rate

I

Do

Do

IF

DOL

/I

*8

RF

vs V

DOH vs Ta

DO

I

I

I

I

DOL

DOMT

DOVD

DOTA

*5

*6

*7

V

CC

=

Vp

=

3.0 V,

V

DOL

=

Vp

/

2,

Ta

= +

25

°

C

CS bit

CS bit

V

DO

=

Vp

/

2

0.5 V

V

DO

Vp

0.5 V

40

°

C

Ta

≤ +

85

°

C,

V

DO

=

Vp

/

2

=

=

“H”

“L”

4.1

0.8

6.0

1.5

3

10

5

*1 : Conditions ; fosc

=

10.0 MHz, Ta

= +

25

°

C, SW

=

“L” in locking state.

*2 : V

CCIF

=

Vp

IF

=

V

CCRF

=

Vp

RF

=

3.0 V, fosc

=

10.0 MHz, Ta

= +

25

°

C, in power saving mode.

PS

IF

=

PS

RF

=

GND

V

IH

=

V

CC

, V

IL

=

GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency.

8.2

2.2

10

15

10 mA mA

%

%

%

*4 : The symbol “–” (minus) means the direction of current flow.

*5 : V

CC

=

Vp

=

3.0 V, Ta

= +

25

°

C (||I

3

|

|I

4

||)

/

[ (|I

3

|

+

|I

4

|)

/

2]

×

100 (

%

)

*6 : V

CC

=

Vp

=

3.0 V, Ta

= +

25

°

C [ (||I

2

|

|I

1

||)

/

2]

/

[ (|I

1

|

+

|I

2

|)

/

2]

×

100 (

%

) (Applied to both l

DOL

and l

DOH

)

*7 : V

CC

=

Vp

=

3.0 V, [||I

DO

(

+

85

°

C

) |

|I

DO

(

–40

°

C

) ||

/

2]

/

[|I

DO

(

+

85

°

C

) |

+

|I

DO

(

–40

°

C

) |

/

2]

×

100 (

%

) (Applied to both I

DOL

and I

DOH

)

*8 : When Charge pump current is measured, set LDS

=

“L” , T1

=

“L” and T2

=

“H”.

I

DOL

I

1

I

3

I

2

I

DOH

I

2

I

4

I

1

0.5

Vp/2 Vp

0.5 Vp

Charge pump output voltage (V)

7

8

MB15F76UL

FUNCTIONAL DESCRIPTION

1.

Pulse swallow function

f

VCO

=

[ (P

×

N)

+

A]

×

4

×

f

OSC

÷

R f

VCO

: Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (4 or 8 for IF-PLL, 16 or 32 for RF-PLL)

N : Preset divide ratio of binary 13-bit programmable counter (3 to 8,191)

A : Preset divide ratio of binary 5-bit swallow counter (0

A

31, A < N) f

OSC

: Reference oscillation frequency (OSC

IN

input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2.

Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-

PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.

The serial data of binary data is entered through Data pin.

On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting.

CN1

CN2

The programmable reference counter for the IF-PLL

0

The programmable reference counter for the RF-PLL

1

0 0

The programmable counter and the swallow counter for the IF-PLL

0

1

The programmable counter and the swallow counter for the RF-PLL

1

1

(1)

Shift Register Configuration

Programmable Reference Counter

(LSB) Data Flow (MSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit

R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)

T1, 2

CN1, 2

X

: LD/fout output setting bit

: Control bit

: Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

MB15F76UL

• Programmable Counter

(LSB) Data Flow (MSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 LDS SW

IF

/

RF

FC

IF

/

RF

A1 A2 A3 A4 A5 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

A1 to A5 : Divide ratio setting bits for the swallow counter (0 to 31)

N1 to N13 : Divide ratio setting bits for the programmable counter (3 to 8,191)

LDS

SW

IF

/

RF

: LD/fout signal select bit

: Divide ratio setting bit for the prescaler (IF : SW

IF

, RF : SW

RF

)

FC

IF

/

RF

CN1, 2

: Phase control bit for the phase detector (IF : FC

IF

, RF : FC

RF

)

: Control bit

Note : Data input with MSB first.

(2) Data setting

Binary 14

bit Programmable Reference Counter Data Setting

Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1

3

4

16383

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

1

1

1

0

1

1

0

1

Note : Divide ratio less than 3 is prohibited.

Binary 13

bit Programmable Counter Data Setting

Divide ratio N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1

3 0 0 0 0 0 0 0 0 0 0 0 1 1

4

8191

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

1

0

1

Note : Divide ratio less than 3 is prohibited

Binary 5

bit Swallow Counter Data Setting

Divide ratio A5 A4 A3 A2 A1

0 0 0 0 0 0

1

31

0

1

0

1

0

1

0

1

1

1

9

MB15F76UL

Prescaler Data Setting

Divide ratio

Prescaler divide ratio IF-PLL

Prescaler divide ratio RF-PLL

• Charge Pump Current Setting

Current value

±

6.0 mA

±

1.5 mA

CS

1

0

SW

====

“H”

4/5

16/17

LD

/ fout output Selectable Bit Setting

LD/fout pin state LDS

0 fout output

LD output fr

IF fr

RF fp

IF fp

RF

1

1

0

0

1

1

SW

====

“L”

8/9

32/33

0

1

0

1

T1

0

1

1

Phase Comparator Phase Switching Data Setting

FC

IF

,

RF

====

“H”

Phase comparator input

Do

IF

,

RF

fr

>

fp fr

<

fp fr

=

fp

Z

:

High-impedance

H

L

Z

FC

IF

,

RF

====

“L”

Depending upon the VCO and LPF polarity, FC bit should be set.

Do

IF

,

RF

L

H

Z

1

1

0

0

T2

0

0

1

High

(1) VCO polarity FC

=

“H”

(2) VCO polarity FC

=

“L”

VCO Output

Frequency

LPF Output voltage

10

Note : Give attention to the polarity for using active type LPF.

(1)

(2)

Max.

MB15F76UL

3.

Power Saving Mode (Intermittent Mode Control Circuit)

Status PS pin

Normal mode

Power saving mode

H

L

The intermittent mode control circuit reduces the PLL power consumption.

By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value.

The phase detector output, Do, becomes high impedance.

For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.

Setting the PS pin high, releases the power saving mode, and the device works normally.

The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time.

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation.

Notes :

When power (VCC) is first applied, the device must be in standby mode.

PS pin must be set “L” at Power-ON.

V

CC

Clock

Data

LE

PS

OFF t

V

1

µ s

ON t

PS

100 ns

(1) (2) (3)

(1) PS

=

L (power saving mode) at Power-ON

(2) Set serial data at least 1

µ s after the power supply becomes stable (V

CC

2.2 V) .

(3) Release power saving mode (PS

IF

, PS

RF

: “L”

“H”) at least 100 ns later after setting serial data.

11

12

MB15F76UL

4.

Serial Data Input Timing

Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.

Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.

1st data 2nd data

Control bit

Invalid data

Data

MSB LSB

Clock

LE t

7 t

1 t

2 t

3 t

6 t

4 t

5

Parameter Min

t

1 t

2

20

20 t

3 t

4

30

30

Typ

Max

Unit

ns ns ns ns

Parameter

t t

5 t

6

7

Note : LE should be “L” when the data is transferred into the shift register.

Min Typ Max

100

20

100

Unit

ns ns ns

MB15F76UL

PHASE COMPARATOR OUTPUT WAVEFORM

fr

IF

/

RF fp

IF

/

RF t

WU t

WL

LD

(FC bit

=

High)

D o

IF

/

RF

Z

(

FC bit

=

Low

)

D o

IF

/

RF

Z

H

L

H

L

• LD Output Logic

IF-PLL section

Locking state/Power saving state

Locking state/Power saving state

Unlocking state

Unlocking state

RF-PLL section

Locking state/Power saving state

Unlocking state

Locking state/Power saving state

Unlocking state

LD output

H

L

L

L

Notes :

Phase error detection range

= −

2

π

to

+

2

π

Pulses on Do

IF/RF

signals during locking state are output to prevent dead zone.

LD output becomes low when phase error is t

WU

or more.

LD output becomes high when phase error is t

WL

or less and continues to be so for three cycles or more.

t

WU

and t

WL

depend on OSC

IN

input frequency as follows.

t

WU

2/fosc : e.g. t

WU

200 ns when fosc

=

10.0 MHz t

WU

4/fosc : e.g. t

WL

400 ns when fosc

=

10.0 MHz

13

14

MB15F76UL

TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC

IN

)

S.G

Controller

(Divide ratio setting)

1000 pF

S.G

50

W

1000 pF

50

W

1000 pF

V

CCIF

0.1 m

F

Oscilloscope finIF

Xfin

IF

GND

IF

V

CCIF

PS

IF

Vp

IF

Vp

IF

0.1 m

F

GND OSC

IN

Clock Data

1

20 19 18 17

16

2

15

3

14

MB15F76UL

4

13

5

12

6

7 8 9 10 11

LE fin

RF

Xfin

RF

GND

RF

V

CCRF

PS

RF

Do

IF

LD/fout D

ORF

VpRF

VpRF

0.1 m

F

1000 pF

S.G

50

W

V

CCRF

0.1 m

F

1000 pF

MB15F76UL

TYPICAL CHARACTERISTICS

1.

fin input sensitivity

RF-PLL input sensitivity vs. Input frequency

10

0

-10

-20

-30

-40

-50

0

SPEC

1000 2000 3000 4000 fin

RF

[MHz]

5000 6000 7000

V

CC

= 2.5 V

V

CC

= 2.7 V

V

CC

= 3.0 V

V

CC

= 3.6 V

SPEC

IF-PLL input sensitivity vs. Input frequency

10

0

-10

-20

-30

-40

-50

0

SPEC

500

1000 1500

2000 fin

IF

[MHz]

2500 3000 3500 4000

V

CC

= 2.5 V

V

CC

= 2.7 V

V

CC

= 3.0 V

V

CC

= 3.6 V

SPEC

15

16

MB15F76UL

2.

OSC

IN

input sensitivity

Input sensitivity vs. Input frequency

10

0

-10

SPEC

-20

-30

-40

-50

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300

Input

frequency f

OSC

(MHz)

V

CC

= 2.5 V

V

CC

= 2.7 V

V

CC

= 3.0 V

V

CC

= 3.6 V

SPEC

3.

RF-PLL Do output current

• 1.5 mA mode

I

DO

V

DO

10.0

V

CC

=

Vp

=

3.0 V

0

• 6.0 mA mode

10.0

0.0 1.0

2.0

3.0

Charge pump output voltage V

DO

(V)

I

DO

V

DO

10.0

V

CC

=

Vp

=

3.0 V

0

10.0

0.0 1.0

2.0

3.0

Charge pump output voltage V

DO

(V)

MB15F76UL

17

18

MB15F76UL

4.

IF-PLL Do output current

• 1.5 mA mode

I

DO

V

DO

10.0

V

CC

=

Vp

=

3.0 V

0

• 6.0 mA mode

10.0

0.0 1.0

2.0

3.0

Charge pump

output voltage V

DO

(V)

I

DO

V

DO

10.0

V

CC

=

Vp

=

3.0 V

0

10.0

0.0

1.0

2.0

3.0

Charge pump

output voltage V

DO

(V)

MB15F76UL

5.

fin input impedance

fin

IF input impedance

4 : 20.141

-92.027

1.153 pF

1 500. 000 000 MHz

1 : 714.75

-1.2319 k

100 MHz

2 : 64.484

-318.44

500 MHz

3 : 30.18

-155.06

1 GHz

4

3

2

1

START 100. 000 000 MHz STOP 1 500. 000 000 MHz

3 fin

RF input impedance

4

4 : 22.418

67.184

6 000. 000 000 MHz

1 : 19.186

-63.068

2 GHz

2 : 18.665

-14.222

3 GHz

3 : 21.018

29.733

5 GHz

2

START 2 000. 000 000 MHz

1

STOP 6 000. 000 000 MHz

19

20

MB15F76UL

6.

OSC

IN

input impedance

OSC

IN input impedance

4 : 064.94

-1.0402 k

1.5301 pF

100. 000 000 MHz

1 : 19.527 k

-13.395 k

3 MHz

2 : 4.5245 k

-8.9645

10 MHz

3 : 305.63

-2.6423 k

40 MHz

4

3

1

2

START 3. 000 000 MHz STOP 100. 000 000 MHz

MB15F76UL

REFERENCE INFORMATION

( for Phase Noise and Reference Leakage

)

S.G.

Spectrum

Analyzer

Test Circuit

OSC

IN

Do fin

VCO

LPF

• PLL Reference Leakage

ATTEN 10dB

RL 0 dBm

VAVG 16

10 dB/

MKR -74.00 dB

1.000 MHz

D

S

MKR

1.000 MHz

-74.00 dB f

VCO

=

4750 MHz V

CC

=

3.0 V Ta

= +

25

°

C fr

=

250 kHz (channel spacing = 1 MHz) f

OSC

=

13 MHz CP : 1.5 mA mode

LPF

820 pF

910

3.9 k

8200 pF

To VCO

470 pF

• PLL Phase Noise

D

S

ATTEN 10 dB

RL 0 dBm

MKR

1.00 kHz

-72.17 dB/Hz

VAVG 16

10 dB/

CENTER 4.750000 GHz

*RBW 30 kHz VBW 30 kHz

SPAN 5.000 MHz

*SWP 2.00 s

Reference Leak : -74.00 dBc

MKR -72.17 dB/Hz

1.00 kHz

D

S

ATTEN 10 dB

RL 0 dBm

VAVG 16

10 dB/

MKR 17.5 kHz

-69.62 dB/Hz

MKR -69.62 dB/Hz

17.5 kHz

CENTER 4.75000000 GHz

*RBW 30 Hz VBW 30 Hz

SPAN 10.00 kHz

SWP 1.92 s

C/N

1 kHz : -72.17 dBc/Hz

CENTER 4.7500000 GHz

*RBW 300 Hz VBW 300Hz

SPAN 100.0kHz

*SWP 3.00 s

C/N Peak : -69.62 dBc/Hz

BW : 33.5 kHz

21

22

MB15F76UL

APPLICATION EXAMPLE

TCXO

1000 pF

From controller

1000 pF

1000 pF

3.0 V

0.1

µ

F

GND OSC

IN

Clock Data fin

IF

Xfin

IF

GND

IF

V

CCIF

PS

IF

Vp

IF

3.0 V

0.1

µ

F

1 20 19 18 17 16

2

15

3

14

MB15F76UL

4

13

5

12

6 7

8

9

10

11

Do

IF

LD/fout Do

RF

Vp

RF

3.0 V

0.1

µ

F

LE fin

RF

Xfin

RF

GND

RF

V

CCRF

PS

RF

1000 pF

3.0 V

0.1

µ

F

1000 pF

Lock Det.

LPF

LPF

VCO

VCO

Output

Output

Notes : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) .

MB15F76UL

USAGE PRECAUTIONS

(1) V

CCRF

, Vp

RF

, V

CCIF

and Vp

IF

must be equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF

, Vp

RF

, V

CCIF

and Vp

IF

to keep them equal. It is recommended that the non-use PLL is controlled by power saving function.

(2) To protect against damage by electrostatic discharge, note the following handling precautions :

Store and transport devices in conductive containers.

Use properly grounded workstations, tools, and equipment.

Turn off power before inserting or removing this device into or from a socket.

Protect leads with conductive sheet, when transporting a board mounted device

ORDERING INFORMATION

Part number Remarks

MB15F76ULPVA

Package

20-pad plastic BCC

(LCC-20P-M05)

23

24

MB15F76UL

PACKAGE DIMENSIONS

20-pad plastic BCC

(LCC-20P-M05)

3.60±0.10(.142±.004)

16

1

11

INDEX AREA

3.40±0.10

(.134±.004)

6

0.55±0.05

(.022±.002)

(Mounting height)

0.25±0.10

(.010±.004)

2.70(.106)

TYP

11

3.00(.118)TYP

0.25±0.10

(.010±.004)

"D"

"A" "B" "C"

16

0.50(.020)

TYP

6 1

0.075±0.025

(.003±.001)

(Stand off)

0.50(.020)

TYP

2.80(.110)REF

0.05(.002)

Details of "A" part

0.50±0.10

(.020±.004)

0.60±0.10

(.024±.004)

Details of "B" part

0.50±0.10

(.020±.004)

0.30±0.10

(.012±.004)

Details of "C" part

0.50±0.10

(.020±.004)

C0.20(.008)

0.60±0.10

(.024±.004)

Details of "D" part

0.30±0.10

(.012±.004)

0.40±0.10

(.016±.004)

C

2001 FUJITSU LIMITED C20056S-c-2-1

Dimensions in mm (inches)

MB15F76UL

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F0209

FUJITSU LIMITED Printed in Japan

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