datasheet for VL33B2863F

datasheet for VL33B2863F
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
General Information
1GB 128M x 72 DDR3 SDRAM ULP ECC 240-PIN RDIMM
Description
The VL33B2863F is a 128M x 72 DDR3 SDRAM high density RDIMM. This memory module consists of nine CMOS
128M x 8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages, a 28-bit registered buffer/PLL clock in BGA
package, and a 2K EEPROM with thermal sensor in an 8-pin MLF package. This module is a 240-pin registered dual inline memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the
printed circuit board for each DDR3 SDRAM.
Features
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Pin Description
240-pin, registered dual in-line memory module (RDIMM)
Support ECC error detection and correction
Fast data transfer rates: PC3-10600, PC3-8500, PC3-6400
VDD = VDDQ = 1.5V +/-0.075V
JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 )
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency: 9 (DDR3-1333), 7 (DDR3-1066),
6 (DDR3-800)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD) with thermal sensor,
referenced to JEDEC SPD4_01_04
( www.JEDEC.org/download/search/4_01_04r18.pdf )
o
o
o
Thermal sensor range: -20 C to +125 C (+/- 1 C accuracy)
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 17.78mm (0.700”), double sided components
Order Information:
VL33B2863F-K9 S X
DRAM DIE (Option)
DRAM MANUFACTURER
S - SAMSUNG
Pin Name
Function
A0~A13
Address Inputs
A10/AP
Address Input/ Autoprecharge
A12/BC#
Address Input/ Burst Chop
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
ODT0
On-die Termination Control
PAR_IN
Parity Input
ERR_OUT#
Parity Error Output
CK0, CK0#
Clock Input
CKE0
Clock Enables
CS0#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
VDD
Voltage Supply 1.5V +/- 0.075V
VSS
Ground
SA0~SA2
SPD Address
SDA
SPD Data Input/Output
SCL
SPD Clock Input
DM0~DM8/
DQS9~DQS17
Data Masks/
Data Strobes (Read)
DQS9#~DQS17#
Data Strobes Complement (Read)
CB0~CB7
Data Check Bits I/O
VREFCA
Reference Voltage for CA
VREFDQ
Reference Voltage for DQ
VDDSPD
SPD Voltage Supply 3.0V to 3.6V
MODULE SPEED
K9: PC3-10600 @ CL9
F8: PC3-8500 @ CL7
E7: PC3-6400 @ CL6
VTT
Termination Voltage
RESET#
Register and SDRAM Control
EVENT#
Reserved for Temp Sensing
VL: Lead-free/RoHS
NC
No Connect
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1
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Pin Configuration
240-PIN DDR3 RDIMM FRONT SIDE
240-PIN DDR3 RDIMM BACK SIDE
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
1
VREFDQ
31
DQ25
61
A2
91
DQ41
121
VSS
Name
151
VSS
181
A1
211
VSS
182
VDD
212
DM5/
DQS14
2
VSS
32
VSS
62
VDD
92
VSS
122
DQ4
152
DM3/
DQS12
3
DQ0
33
DQS3#
63
CK1 *
93
DQS5#
123
DQ5
153
NC/DQS12#
183
VDD
213
NC/DQS14#
4
DQ1
34
DQS3
64
CK1# *
94
DQS5
124
VSS
154
VSS
184
CK0
214
VSS
155
DQ30
185
CK0#
215
DQ46
5
VSS
35
VSS
65
VDD
95
VSS
125
DM0/
DQS9
6
DQS0#
36
DQ26
66
VDD
96
DQ42
126
NC/DQS9#
156
DQ31
186
VDD
216
DQ47
7
DQS0
37
DQ27
67
VREFCA
97
DQ43
127
VSS
157
VSS
187
EVENT#
217
VSS
8
VSS
38
VSS
68
PAR_IN
98
VSS
128
DQ6
158
CB4
188
A0
218
DQ52
9
DQ2
39
CB0
69
VDD
99
DQ48
129
DQ7
159
CB5
189
VDD
219
DQ53
10
DQ3
40
CB1
70
A10/AP
100
DQ49
130
VSS
160
VSS
190
BA1
220
VSS
191
VDD
221
DM6/
DQS15
11
VSS
41
VSS
71
BA0
101
VSS
131
DQ12
161
DM8/
DQS17
12
DQ8
42
DQS8#
72
VDD
102
DQS6#
132
DQ13
162
NC/DQS17#
192
RAS#
222
NC/DQS15#
13
DQ9
43
DQS8
73
WE#
103
DQS6
133
VSS
163
VSS
193
CS0#
223
VSS
164
CB6
194
VDD
224
DQ54
14
VSS
44
VSS
74
CAS#
104
VSS
134
DM1/
DQS10
15
DQS1#
45
CB2
75
VDD
105
DQ50
135
NC/DQS10#
165
CB7
195
ODT0
225
DQ55
16
DQS1
46
CB3
76
CS1# *
106
DQ51
136
VSS
166
VSS
196
A13
226
VSS
17
VSS
47
VSS
77
ODT1 *
107
VSS
137
DQ14
167
TEST *
197
VDD
227
DQ60
18
DQ10
48
VTT
78
VDD
108
DQ56
138
DQ15
168
RESET#
198
CS3# *
228
DQ61
19
DQ11
49
VTT
79
CS2# *
109
DQ57
139
VSS
169
CKE1 *
199
VSS
229
VSS
20
VSS
50
CKE0
80
VSS
110
VSS
140
DQ20
170
VDD
200
DQ36
230
DM7/
DQS16
21
DQ16
51
VDD
81
DQ32
111
DQS7#
141
DQ21
171
A15 *
201
DQ37
231
NC/DQS16#
22
DQ17
52
BA2
82
DQ33
112
DQS7
142
VSS
172
A14 *
202
VSS
232
VSS
173
VDD
203
DM4/
DQS13
233
DQ62
204 NC/DQS13#
234
DQ63
23
VSS
53
ERR_OUT#
83
VSS
113
VSS
143
DM2/
DQS11
24
DQS2#
54
VDD
84
DQS4#
114
DQ58
144
NC/DQS11#
174
A12/ BC#
25
DQS2
55
A11
85
DQS4
115
DQ59
145
VSS
175
A9
205
VSS
235
VSS
26
VSS
56
A7
86
VSS
116
VSS
146
DQ22
176
VDD
206
DQ38
236
VDDSPD
27
DQ18
57
VDD
87
DQ34
117
SA0
147
DQ23
177
A8
207
DQ39
237
SA1
28
DQ19
58
A5
88
DQ35
118
SCL
148
VSS
178
A6
208
VSS
238
SDA
29
VSS
59
A4
89
VSS
119
SA2
149
DQ28
179
VDD
209
DQ44
239
VSS
30
DQ24
60
VDD
90
DQ40
120
VTT
150
DQ29
180
A3
210
DQ45
240
VTT
*: These pins are not used in this module.
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2
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Function Block Diagram
RCS0#
DQS0#
DQS0
DM0/DQS9
NC/DQS9#
DQS4#
DQS4
DM4/DQS13
NC/DQS13#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D0
DQ
DQ
DQ
DQ
ZQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vss
DQS1#
DQS1
DM1/DQS10
NC/DQS10#
DQS5#
DQS5
DM5/DQS14
NC/DQS14#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D1
DQ
DQ
DQ
DQ
ZQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vss
DQS2#
DQS2
DM2/DQS11
NC/DQS11#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D2
DQ
DQ
DQ
DQ
ZQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D6
DQ
DQ
DQ
DQ
ZQ
DQS7#
DQS7
DM7/DQS16
NC/DQS16#
DQS3#
DQS3
DM3/DQS12
NC/DQS12#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D3
DQ
DQ
DQ
DQ
ZQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
DQS8#
DQS8
DM8/DQS17
NC/DQS17#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D7
DQ
DQ
DQ
DQ
ZQ
Command, address, control, and clock line terminations
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D8
DQ
DQ
DQ
DQ
ZQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Vss
RA0-RA13, RBA0-RBA2
RRAS#, RCAS#, RWE#,
RCS0#, RCKE0, RODT0
DDR3
SDRAM
DDR3
SDRAM
VDDS PD
1:2
R
E
G
I
S
T
E
R
/
P
L
L
120 omh
+/-1%
RCS0# -> CS0#: SDRAMs D0-D8
RA0-RA13 -> A0-A13: SDRAMs D0-D8
RB A0-RA2 -> BA0-B A2: SDRAMs D0-D8
RRAS# -> RAS#: SDRAMs D0-D8
RCAS# -> CAS#: SDRAMs D0-D8
RWE# -> WE#: SDRAMs D0-D8
RCKE0 -> CKE0: SDRAMs D0-D8
RODT0 -> ODT0: SDRAMs D0-D8
39 ohm +/-5%
39 ohm+/-5%
PCK0
PCK0#
22 ohm +/-5%
CS0#
A0-A13
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT0
CK0
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D5
DQ
DQ
DQ
DQ
ZQ
DQS6#
DQS6
DM6/DQS15
NC/DQS15#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
CK0#
DM/ TDQS# CS# DQS DQS#
TDQS
DQ
DQ
DQ
DQ
D4
DQ
DQ
DQ
DQ
ZQ
VDD
Integrated Thermal Sensor in S PD
SCL
EV ENT#
E VENT#
A0
A1
A2
SA0 SA1 SA2
Serial PD with Integrated thermal sensor
0.1uF
Thermal sensor/
Serial PD
D0-D8
VTT
D0-D8
VREFCA
D0-D8
VREFDQ
D0-D8
VSS
D0-D8
SDA
PCK0
PCK0#
22 ohm +/-5%
Q ER R #
PAR_IN
RESET#
Err_Out#
R ST #
RST#: SDRAMs D0-D8
Notes:
1. Unless otherwise noted, resistor values are 15 ohms +/-5%
2. ZQ resistors are 240 ohms +/-1%
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3
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-0.4
1.975
V
Voltage on VDDQ pin relative to VSS
-0.4
1.975
V
Voltage on any pin relative to VSS
-0.4
1.975
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, BA,
RAS#, CAS#,WE#,
CS#, CKE, ODT
-5
5
uA
CK, CK#
-5
150
uA
DM
-2
2
uA
-5
5
uA
-9
9
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
VDD
VDDQ
Parameter
Min
Typical
Max
Unit
Notes
Supply Voltage
1.425
1.5
1.575
V
1,2
I/O Supply Voltage
1.425
1.5
1.575
V
1,2
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VREFDQ (DC)
I/O reference voltage DQ bus
VREFCA (DC)
Input reference voltage CMD/ADD bus
VTT
Termination Reference Voltage
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
-0.483 x VDDQ
0.5 x VDDQ
+0.517 x VDDQ
V
5
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
TOPER
Parameter
Operating temperature
Rating
Units
0 - 95
0
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At 0 – 85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
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4
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(DC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.100
VDD
V
VILCA(DC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
VSS
VREF - 0.100
V
VIHDQ(DC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.100
VDD
V
VILDQ(DC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
VSS
VREF - 0.100
V
Min
Max
Unit
DQ and DM
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Command and Address
VIHCA(AC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.175
-
V
VILCA(AC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
-
VREF - 0.175
V
DQ and DM
VIHDQ(AC)
Input High (Logic 1) Voltage DDR3-800/1066
VREF + 0.175
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage DDR3-800/1066
-
VREF - 0.175
V
VIHDQ(AC)
Input High (Logic 1) Voltage DDR3-1333
VREF + 0.150
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage DDR3-1333
-
VREF - 0.150
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
DDR3-1333
DDR3-1066
DDR3-800
Min
Max
Min
Max
Min
Max
Symbol
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
5.5
6.5
5.5
6.5
5.5
6.5
pF
Input capacitance (CKE0, ODT0, CS0#)
CIN2
5.5
6.5
5.5
6.5
5.5
6.5
pF
Input capacitance (CK0, CK0#)
CIN3
5.5
6.5
5.5
6.5
5.5
6.5
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
CIO
5.5
6.5
5.5
6.7
5.5
7
pF
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5
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
IDD Specification
Condition
DDR3-1333
DDR3-1066
DDR3-800
K9
F8
E7
IDD0*
685
640
595
mA
IDD1*
820
775
730
mA
IDD2P-F**
325
325
325
mA
IDD2P-S**
190
190
190
mA
IDD2N**
415
370
370
mA
IDD2Q**
415
370
325
mA
IDD3P**
325
325
325
mA
IDD3N**
550
505
460
mA
IDD4R*
1225
1090
955
mA
IDD4W*
1315
1135
865
mA
IDD5**
1540
1450
1450
mA
IDD6**
90
90
90
mA
IDD7*
2170
1765
1630
mA
Symbol
Unit
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC=
tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
Precharge power-down current;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS
MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL
= CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP=
tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD);
AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is
HIGH; CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL =
tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD =
tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R.
Note: IDD specification is based on Samsung E-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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6
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
tCK(DLL_OFF)
8
-
8
-
8
-
ns
tCK(avg)
1.5
<1.875
1.875
<2.5
2.5
3.3
ns
ns
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
tCK(abs)
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)ma
x+
tJIT(per)ma
x
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-80
80
-90
90
-100
100
ps
tJIT(per, lck)
-70
70
-80
80
-90
90
ps
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(cc)
160
180
200
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
140
160
180
ps
Cumulative error across 2 cycles
tERR(2per)
-118
118
-132
132
-147
147
ps
Cumulative error across 3 cycles
tERR(3per)
-140
140
-157
157
-175
175
ps
Cumulative error across 4 cycles
tERR(4per)
-155
155
-175
175
-194
194
ps
Cumulative error across 5 cycles
tERR(5per)
-168
168
-188
188
-209
209
ps
Cumulative error across 6 cycles
tERR(6per)
-177
177
-200
200
-222
222
ps
Cumulative error across 7 cycles
tERR(7per)
-186
186
-209
209
-232
232
ps
Cumulative error across 8 cycles
tERR(8per)
-193
193
-217
217
-241
241
ps
Cumulative error across 9 cycles
tERR(9per)
-200
200
-224
224
-249
249
ps
Cumulative error across 10 cycles
tERR(10per)
-205
205
-231
231
-257
257
ps
Cumulative error across 11 cycles
tERR(11per)
-210
210
-237
237
-263
263
ps
Cumulative error across 12 cycles
tERR(12per)
-215
215
-242
242
-269
269
ps
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min
tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max
tERR(nper)
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
tDQSQ
-
125
-
150
-
200
ps
tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-500
250
-600
300
-800
400
ps
DQ high-impedance time from CK, CK#
tHZ(DQ)
-
250
-
300
-
400
ps
tDS(base)
30
-
25
-
75
-
ps
tDH(base)
65
-
100
-
150
-
ps
tDIPW
400
-
490
-
600
-
ps
Data Timing
DQS,DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
Data setup time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
Data hold time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
DQ and DM Input pulse width for each input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
7
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS# READ Preamble
tRPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# differential READ Postamble
tRPST
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS# output high time
tQSH
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# output low time
tQSL
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK
tDQSCK
-255
255
-300
300
-400
400
ps
tLZ(DQS)
-500
250
-600
300
-800
400
ps
DQS, DQS# rising edge output access time from rising
CK, CK#
DQS, DQS# low-impedance time (Referenced from
RL-1)
DQS, DQS# high-impedance time (Referenced from
RL+BL/ 2)
tHZ(DQS)
-
250
-
300
-
400
ps
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,DQS# failing edge setup time to CK, CK# rising
edge
tDSS
0.2
-
0.2
-
0.2
-
tCK(avg)
DQS,DQS# failing edge hold time to CK, CK# rising edge
tDSH
0.2
-
0.2
-
0.2
-
tCK(avg)
tDLLK
512
-
512
-
512
-
nCK
tRTP
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
tWTR
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
tWR
15
-
15
-
15
-
ns
tMRD
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
Command and Address Timing
DLL locking time
Internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time
Mode Register Set command cycle time
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
nCK
1
-
1
-
1
-
nCK
tRAS
36
9*tREFI
37.5
9*tREFI
37.5
9*tREFI
ns
tRRD
max
(4tCK,6ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
ACTIVE to ACTIVE command period for 2KB page size
tRRD
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
max
(4tCK,10ns)
-
Four activate window for 1KB page size
tFAW
30
-
37.5
-
40
-
ns
Four activate window for 2KB page size
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
tMPRR
nCK
tFAW
45
-
50
-
50
-
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
65
-
125
-
200
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIH(base)
140
-
200
-
275
-
ps
tIPW
620
-
780
-
900
-
ps
Control & Address Input pulse width for each input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
8
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
-
110
-
110
-
Refresh Timing
1Gb REFRESH to REFRESH OR REFRESH to
ACTIVE command interval
tRFC
110
Average periodic refresh interval
(0°C<= TCASE <= 85 °C)
tREFI
7.8
7.8
7.8
us
Average periodic refresh interval
(85°C<= TCASE <= 95 °C)
tREFI
3.9
3.9
3.9
us
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
tCK
Normal operation Short calibration time
tZQCS
64
-
64
-
64
-
tCK
tXPR
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
Exit Self Refresh to commands not requiring a locked
DLL
tXS
max(5tCK,
tRFC +10ns)
-
max(5tCK,
tRFC +10ns)
-
max(5tCK,
tRFC +10ns)
-
Exit Self Refresh to commands requiring a locked DLL
ns
Calibration Timing
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry (SRE)
tCKSRE
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
tCKSRX
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
tXP
max
(3tCK,6ns)
-
max
(3tCK,7.5ns)
-
max
(3tCK,7.5ns)
-
tXPDLL
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
tCKE
max (3tCK,
5.625ns)
-
max (3tCK,
5.625ns)
-
max (3tCK,
7.5ns)
-
tCPDED
1
-
1
-
1
-
nCK
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
Timing of ACT command to Power Down entry
tACTPDEN
1
-
1
-
1
-
nCK
Timing of PRE command to Power Down entry
tPRPDEN
1
-
1
-
1
-
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
tWRPDEN
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
nCK
tWRAPDEN
WL+4+WR+
1
-
WL+4+WR+1
-
WL+4+WR+1
-
nCK
tWRPDEN
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
nCK
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN
WL+2+WR+
1
-
WL+2+WR+1
-
WL+2+WR+1
-
nCK
Timing of REF command to Power Down entry
tREFPDEN
1
-
1
-
1
-
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
Valid Clock Requirement before Self Refresh Exit
(SRX)
nCK
Power Down Timing
Exit Power Down with DLL to any valid command; Exit
Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of WR command to Power Down entry BL8
(OTF, MRS), BL4OTF
Timing of WRA command to Power Down entry BL8
(OTF, MRS), BL4OTF
Timing of WR command to Power Down entry
(BL4MRS)
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
9
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
ODT Timing
ODT high time without write command or with write
command and BC4
ODTH4
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
nCK
Asynchronous RTT turn-on delay (Power-Down with DLL
frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down with DLL
frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
tAON
-250
250
-300
300
-400
400
ps
ODT turn-on
RTT_NOM and RTT_WR turn-off time from ODTL off
reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(av
g)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(av
g)
tWLMRD
40
-
40
-
40
-
tCK
tWLDQSEN
25
-
25
-
25
-
tCK
Setup time for tDQSS latch
tWLS
195
-
245
-
325
-
ps
Hold time for tDQSS latch
tWLH
195
-
245
-
325
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode
is programmed
DQS/DQS delay after tDQS margining mode is
programmed
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
10
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Package Dimensions
FRONT VIEW
133.35
3.67 MAX
0.70 R MAX (8X)
2.50 D (2X)
17.78
9.50
2.30 TYP
1.50 +/- 0.10
PIN 1
2.20 TYP
1.45 TYP
0.75 R
1.27 +/- 0.10
1.00 TYP
0.80 TYP
PIN 120
54.68 TYP
123 .00 TYP
BACK VIEW
3.00 TYP (4X)
3.05 TYP
PIN 121
PIN 240
71.00 TYP
47.00 TYP
5.00 TYP
Note: 1. All dimension are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
11
Product Specifications
PART NO.:
VL33B2863F-K9S/F8S/E7S
REV: 1.0
Revision History:VN-110909
Date
09/11/09
Rev.
1.0
Page
All
Changes
Spec release
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
12
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