SSD1303

SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD1303

Advance Information

132 x 64 Dot Matrix

OLED/PLED Segment/Common Driver with Controller

This document contains information on a new product. Specifications and information herein are subject to change without notice.

http://www.solomon-systech.com

SSD1303

Rev 1.7 P 1/56 May 2005 Copyright

 2005 Solomon Systech Limited

TABLE OF CONTENTS

1 GENERAL INFORMATION ............................................................................................................................5

2 FEATURES .........................................................................................................................................................5

3 ORDERING INFORMATION ..........................................................................................................................6

4 BLOCK DIAGRAM ...........................................................................................................................................7

5 DIE PAD FLOOR PLAN....................................................................................................................................8

6 PIN DESCRIPTION .........................................................................................................................................12

7 FUNCTIONAL BLOCK DESCRIPTIONS ....................................................................................................15

7.1

O

SCILLATOR

C

IRCUIT AND

D

ISPLAY

T

IME

G

ENERATOR

..................................................................................15

7.2

R

ESET

C

IRCUIT

................................................................................................................................................15

7.3

C

OMMAND

D

ECODER AND

C

OMMAND

I

NTERFACE

..........................................................................................15

7.4

MPU P

ARALLEL

6800-

SERIES

I

NTERFACE

.......................................................................................................16

7.5

MPU P

ARALLEL

8080-

SERIES

I

NTERFACE

.......................................................................................................16

7.6

MPU S

ERIAL

I

NTERFACE

.................................................................................................................................17

7.7

G

RAPHIC

D

ISPLAY

D

ATA

RAM (GDDRAM) ..................................................................................................17

7.8

C

URRENT

C

ONTROL AND

V

OLTAGE

C

ONTROL

.................................................................................................17

7.9

S

EGMENT

D

RIVERS

/ C

OMMON

D

RIVERS

.........................................................................................................18

7.10

A

REA

C

OLOUR

D

ECODER

.................................................................................................................................18

7.11

DC-DC V

OLTAGE

C

ONVERTER

.......................................................................................................................19

8 COMMAND TABLE ........................................................................................................................................21

8.1

D

ATA

R

EAD

/ W

RITE

........................................................................................................................................24

9 COMMAND DESCRIPTIONS........................................................................................................................25

10 MAXIMUM RATINGS ....................................................................................................................................32

11 DC CHARACTERISTICS ...............................................................................................................................33

12 AC CHARACTERISTICS ...............................................................................................................................34

13 APPLICATION EXAMPLE ............................................................................................................................38

14 SSD1303T3R1 PACKAGE DETAILS.............................................................................................................39

SSD1303T3R1 P

IN

A

SSIGNMENT

................................................................................................................................39

15 SSD1303T6R1 PACKAGE DETAILS.............................................................................................................43

SSD1303T6R1 P

IN

A

SSIGNMENT

................................................................................................................................43

SSD1303T6R1 TAB P

ACKAGE

D

IMENSIONS

..............................................................................................................45

16 SSD1303T8R1 PACKAGE DETAILS.............................................................................................................47

SSD1303T8R1 P

IN

A

SSIGNMENT

................................................................................................................................47

SSD1303T8R1 TAB P

ACKAGE

D

IMENSIONS

..............................................................................................................49

17 SSD1303T9R1 PACKAGE DETAILS.............................................................................................................51

SSD1303T9R1 P

IN

A

SSIGNMENT

................................................................................................................................51

SSD1303T9R1 TAB P

ACKAGE

D

IMENSIONS

..............................................................................................................53

Solomon Systech

May 2005 P 2/56 Rev 1.7

SSD1303

18 SSD1303Z PACKAGE DETAILS ...................................................................................................................55

SSD1303

Rev 1.7 P 3/56 May 2005

Solomon Systech

TABLE OF FIGURES

Figure 1 - Block Diagram.................................................................................................................................. 7

Figure 2 - SSD1303Z Pin Assignment ............................................................................................................. 8

Figure 3 - SSD1303Z Alignment mark dimensions ........................................................................................ 11

Figure 4 - Oscillator Circuit ............................................................................................................................. 15

Figure 5 - Display data read back procedure - insertion of dummy read ....................................................... 16

Figure 6 – Display data write procedure in SPI mode.................................................................................... 17

Figure 7 - DC-DC voltage converter circuit .................................................................................................... 19

Figure 8 - Horizontal scroll direction............................................................................................................... 25

Figure 9 - Segment current vs Contrast setting ............................................................................................. 26

Figure 10 - 6800-series MPU parallel interface characteristics ..................................................................... 35

Figure 11 - 8080-series MPU parallel interface characteristics ..................................................................... 36

Figure 12 - Serial interface characteristics ..................................................................................................... 37

Figure 13 - Application Example (Block Diagram of SSD1303T3)................................................................. 38

Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design) .......................................... 39

Figure 15 - SSD1303T6R1 pin assignment (Copper view) ............................................................................ 43

Figure 16 - SSD1303T9R1 pin assignment (Copper view) ............................................................................ 51

LIST OF TABLES

Table 1 - Ordering Information ......................................................................................................................... 6

Table 2 - SSD1303Z Die Pad Coordinates ...................................................................................................... 9

Table 3 - Passive component selection: ........................................................................................................ 20

Table 4 - Command table ............................................................................................................................... 21

Table 5 - Read command table ...................................................................................................................... 23

Table 6 - Address increment table (Automatic).............................................................................................. 24

Table 7 - Maximum Ratings ........................................................................................................................... 32

Table 8 - DC Characteristics .......................................................................................................................... 33

Table 9 - AC Characteristics .......................................................................................................................... 34

Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics......................................................... 35

Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics......................................................... 36

Table 12 - Serial Interface Timing Characteristics ......................................................................................... 37

Table 13 - SSD1303T3R1 pin assignment..................................................................................................... 40

Table 14 - SSD1303T6R1 pin assignment..................................................................................................... 44

Table 15 - SSD1303T8R1 pin assignment..................................................................................................... 48

Table 16 - SSD1303T9R1 pin assignment..................................................................................................... 52

Solomon Systech

May 2005 P 4/56 Rev 1.7

SSD1303

The SSD1303 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. It consists of 132 segments, 64 commons that can support a maximum display resolution of 132x64. Besides, there are 4-colour selections to support monochrome or area colour OLED/PLED. This IC is designed for Common Cathode type OLED panel.

The SSD1303 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It is suitable for many compact portable applications, such as mobile phone sub-display, calculator and MP3 player, etc.

2 FEATURES

- Support maximum 132 x 64 dot matrix panel

- Area colour support with 4 Colour Selection and 64 steps per colour

- Logic voltage supply: V

DD

= 2.4V - 3.5V

- High voltage supply: V

CC

= 7.0V - 16.0V

- Maximum segment output current: 320uA

- Maximum common sink current: 45mA

- Embedded 132 x 64 bit SRAM display buffer

- 256-step Contrast Control on monochrome passive OLED panel

- Programmable Frame Frequency and Multiplexing Ratio

- 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface

- Row Re-mapping and Column Re-mapping

- Automatic horizontal scrolling function

- Low power consumption

- Wide range of operating temperatures: -40 to 90

°

C

SSD1303

Rev 1.7 P 5/56 May 2005

Solomon Systech

Table 1 - Ordering Information

Ordering Part Number SEG COM Package Form Reference Remark

SSD1303Z 132 64 Gold Bump Die Page 8

Die size: 9.22mm x 1.55mm

Pad pitch: COM 51.8µm SEG 52.2µm

35mm film

4 sprocket hole

SSD1303T3R1 96 Page

Folding TAB

80 / 68 / SPI interface

Output lead pitch 0.12974mm

35mm film

4 sprocket hole

SSD1303T6R1 132 TAB

Folding TAB

80 / 68 / SPI interface

Output lead pitch 0.11976

35mm film

4 sprocket hole

SSD1303T8R1 96 Page

Folding TAB

80 / 68 / SPI interface

Output lead pitch 0.12974mm

35mm film

4 sprocket hole

SSD1303T9R1 96 Page

Folding TAB

80 / 68 / SPI interface

Output lead pitch 0.12974mm

Solomon Systech

May 2005 P 6/56 Rev 1.7

SSD1303

RES#

CS#

D/C

E (RD#)

R/W (WR#)

BS2

BS1

BS0

D3

D2

D1

D0

D7

D6

D5

D4

VDD

VSS

SSD1303

Figure 1 - Block Diagram

Rev 1.7 P 7/56 May 2005

Solomon Systech

.

.

.

.

.

.

.

.

.

.

.

COM63

COM61

.

.

.

COM3

COM1

.

.

.

.

.

.

.

.

.

.

.

SEG131

SEG130

.

.

.

SEG1

SEG0

.

.

.

.

.

.

.

.

.

.

.

COM0

COM2

.

.

.

COM60

COM62

5 DIE PAD FLOOR PLAN

Figure 2 - SSD1303Z Pin Assignment

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

.

.

SEG117

.

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

DUMMY

DUMMY

COM30

COM28

COM26

COM24

COM6

COM4

.

.

.

COM2

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG128

SEG129

SEG130

SEG131

COM1

COM3

COM5

COM7

.

.

COM25

COM27

.

COM29

COM31

DUMMY

DUMMY

SSD1303

Y

RES#

CS#

VSS

DOF#

CL

M

VSS

BS2

VDD

BS1

VSS

BS0

VDD

GPIO1

GPIO0

VCC

D5

D4

D3

D2

D1

D0

VDD

E/RD

R/W

VSS

D/C

VSS

BGGND

SENSE

VBREF

RESE

FB

VDD (x2)

VDDB (x2)

GDR (x2)

VSSB (x2)

IREF

ICAS

VDD

CLS

M/S

VSS

D7

D6

DUMMY (x2)

COM32

COM34

.

.

COM60

COM62

VSS (x3)

VCL (x3)

VSS (x2)

VSL (x3)

VDD

VCC (x2)

VREF

VCOMH (x2)

VSS

TR0

TR1

TR2

TR3

TR4

TR5

TR6

TR7

TR8

VCOMH (x2)

VCC (x2)

VDD

VSL (x3)

VSSB (x2)

VSS (x2)

VCL (x3)

VSS (x3)

COM63

COM61

.

.

COM35

COM33

DUMMY (x2)

X

Pad 1,2,3,? >130

Gold Bumps face up

Die size

Die height

Bump height

Bump size

Pad 1-18, 113-298

Pad 19-112

Alignment mark

T shape

+ shape

Circle

Circle

(-3132.9, 79.5)

(3148.9, 79.5)

(3433.9, -274.6)

(-3433.9, -274.6)

PAD 1

Solomon Systech

May 2005 P 8/56 Rev 1.7

9.22mm x 1.55mm

475 +/- 25um

Nominal 18um

34um x 84um

54um x 84um

75um x 75um

75um x 75um

R37.5um, inner 18um

R37.5um, inner 18um

SSD1303

Table 2 - SSD1303Z Die Pad Coordinates

38

39

40

41

32

33

34

35

36

37

42

43

44

45

46

25

26

27

28

29

30

31

19

20

21

22

23

24

51

52

53

54

55

56

57

58

47

48

49

50

59

60

12

13

14

15

16

17

18

Pad no. Pad Name X-pos

1 NC -4535.4

Y-pos

-679.6

2

3

NC

COM33

-4483.2

-4431.0

-679.6

-679.6

4

5

6

7

COM35

COM37

COM39

COM41

-4379.2

-4327.4

-4275.6

-4223.8

-679.6

-679.6

-679.6

-679.6

8

9

10

11

COM43

COM45

COM47

COM49

-4172.0

-679.6

-4120.2

-679.6

-4068.4

-679.6

-4016.6

-679.6

COM51

COM53

COM55

COM57

COM59

COM61

COM63

-3964.8

-3913.0

-3861.2

-679.6

-679.6

-679.6

-3809.4

-679.6

-3757.6

-679.6

-3705.8

-679.6

-3654.0

-679.6

VSS

VSS

VSS

VCL

VCL

VCL

VSS

VSS

VSSB

VSSB

VSL

VSL

VSL

VDD

VCC

VCC

VCOMH

VCOMH

TR8

TR7

TR6

TR5

TR4

TR3

TR2

TR1

TR0

VSS

VSSB

VSSB

GDR

GDR

VDDB

VDDB

VDD

VDD

FB

RESE

VBREF

SENSE

BGGND

VSS

-3543.3

-679.6

-3467.1

-679.6

-3390.9

-679.6

-3314.7

-679.6

-3238.5

-679.6

-3162.3

-679.6

-3086.1

-679.6

-3009.9

-679.6

-2933.7

-679.6

-2857.5

-679.6

-2781.3

-679.6

-2705.1

-679.6

-2628.9

-679.6

-2552.7

-679.6

-2476.5

-679.6

-2400.3

-679.6

-2324.1

-679.6

-2247.9

-679.6

-2171.7

-679.6

-2095.5

-679.6

-2019.3

-679.6

-1943.1

-679.6

-1866.9

-679.6

-1790.7

-679.6

-1714.5

-679.6

-1638.3

-679.6

-1562.1

-679.6

-1485.9

-679.6

-1409.7

-679.6

-1333.5

-679.6

-1257.3

-679.6

-1181.1

-679.6

-1104.9

-679.6

-1028.7

-679.6

-952.5

-876.3

-679.6

-679.6

-800.1

-723.9

-647.7

-571.5

-679.6

-679.6

-679.6

-679.6

-495.3

-419.1

-679.6

-679.6

98

99

100

101

92

93

94

95

96

97

102

103

104

105

106

85

86

87

88

89

90

91

79

80

81

82

83

84

107

108

109

110

111

112

113

114

115

116

117

118

119

120

72

73

74

75

76

77

78

Pad no. Pad Name X-pos

61 VCC -342.9

62

63

GPIO0

GPIO1

-267.2

-190.5

64

65

66

67

VDD

BS0

VSS

BS1

-114.3

-38.1

38.1

114.3

68

69

70

71

VDD

BS2

VSS

M

190.5

266.7

342.9

419.1

CL

DOF#

VSS

CS#

RES#

D/C

VSS

495.3

571.5

647.7

723.9

800.1

876.3

952.5

R/W

E/RD

VDD

D0

D1

D2

D3

D4

D5

D6

D7

VSS

M/S

CLS

VDD

ICAS

IREF

VCOMH

VCOMH

VREF

VCC

VCC

VDD

VSL

VSL

VSL

VSS

VSS

VCL

VCL

VCL

VSS

VSS

VSS

COM62

COM60

COM58

COM56

COM54

COM52

COM50

COM48

1028.7

-679.6

1104.9

-679.6

1181.1

-679.6

1257.3

-679.6

1333.5

-679.6

1409.7

-679.6

1485.9

-679.6

1562.1

-679.6

1638.3

-679.6

1714.5

-679.6

1790.7

-679.6

1866.9

-679.6

1943.1

-679.6

2019.3

-679.6

2095.5

-679.6

2171.7

-679.6

2247.9

-679.6

2324.1

-679.6

2400.3

-679.6

2476.5

-679.6

2552.7

-679.6

2628.9

-679.6

2705.1

-679.6

2781.3

-679.6

2857.5

-679.6

2933.7

-679.6

3009.9

-679.6

3086.1

-679.6

3162.3

-679.6

3238.5

-679.6

3314.7

-679.6

3390.9

-679.6

3467.1

-679.6

3543.3

-679.6

3654.0

-679.6

3705.8

-679.6

3757.6

-679.6

3809.4

-679.6

3861.2

-679.6

3913.0

-679.6

3964.8

-679.6

4016.6

-679.6

Y-pos

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

-679.6

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

145

146

147

148

149

150

151

139

140

141

142

143

144

167

168

169

170

171

172

173

174

175

176

177

178

179

180

132

133

134

135

136

137

138

Pad no. Pad Name X-pos

121 COM46 4068.4

Y-pos

-679.6

122

123

COM44

COM42

4120.2

4172.0

-679.6

-679.6

124

125

126

127

COM40

COM38

COM36

COM34

4223.8

4275.6

4327.4

4379.2

-679.6

-679.6

-679.6

-679.6

128

129

130

131

COM32

NC

NC

NC

4431.0

-679.6

4483.2

-679.6

4535.4

-679.6

4535.4

679.6

NC

COM30

COM28

COM26

COM24

COM22

COM20

4483.2

4431.0

4379.2

4327.4

4275.6

4223.8

4172.0

679.6

679.6

679.6

679.6

679.6

679.6

679.6

COM18

COM16

COM14

COM12

COM10

COM8

COM6

COM4

COM2

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

4120.2

4068.4

4016.6

3964.8

3913.0

3861.2

3809.4

3757.6

3705.8

3654.0

3445.2

3393.0

3340.8

3288.6

3236.4

3184.2

3132.0

3079.8

3027.6

2975.4

2923.2

2871.0

2818.8

2766.6

2714.4

2662.2

2610.0

2557.8

2505.6

2453.4

2401.2

2349.0

2296.8

2244.6

2192.4

2140.2

2088.0

2035.8

1983.6

1931.4

1879.2

1827.0

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

SSD1303

Rev 1.7 P 9/56 May 2005

Solomon Systech

222

223

224

225

226

227

228

229

230

231

214

215

216

217

218

219

220

221

232

233

234

235

236

237

238

239

240

205

206

207

208

209

210

211

212

213

200

201

202

203

204

192

193

194

195

196

197

198

199

Pad no. Pad Name X-pos

181 SEG32 1774.8

182

183

SEG33

SEG34

1722.6

1670.4

184

185

186

187

188

189

190

191

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

1618.2

1566.0

1513.8

1461.6

1409.4

1357.2

1305.0

1252.8

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

783.0

730.8

678.6

626.4

574.2

-417.6

-469.8

-522.0

-574.2

-626.4

-678.6

-730.8

-783.0

-835.2

-887.4

52.2

0.0

-52.2

-104.4

-156.6

-208.8

-261.0

-365.4

-939.6

-991.8

-1044.0

-1096.2

-1148.4

-1200.6

-1252.8

-1305.0

-1357.2

522.0

469.8

417.6

365.4

313.2

261.0

208.8

156.6

104.4

1200.6

1148.4

1096.2

1044.0

991.8

939.6

887.4

835.2

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

Y-pos

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

679.6

282

283

284

285

286

287

288

289

290

291

274

275

276

277

278

279

280

281

292

293

294

295

296

297

298

265

266

267

268

269

270

271

272

273

260

261

262

263

264

252

253

254

255

256

257

258

259

Pad no. Pad Name X-pos

241 SEG92 -1409.4

Y-pos

679.6

242

243

SEG93

SEG94

-1461.6

-1513.8

679.6

679.6

244

245

246

247

248

249

250

251

SEG95

SEG96

SEG97

SEG98

SEG99

SEG100

SEG101

SEG102

-1566.0

-1618.2

-1670.4

679.6

679.6

679.6

-1722.6

679.6

-1774.8

679.6

-1827.0

-1879.2

-1931.4

679.6

679.6

679.6

SEG103

SEG104

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

-1983.6

-2035.8

-2296.8

-2349.0

679.6

679.6

-2088.0

679.6

-2140.2

679.6

-2192.4

679.6

-2244.6

679.6

679.6

679.6

SEG111

SEG112

SEG113

SEG114

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

COM1

COM3

COM5

COM7

COM9

COM11

COM13

COM15

COM17

COM19

COM21

COM23

COM25

COM27

COM29

COM31

NC

NC

-2401.2

679.6

-2453.4

679.6

-2505.6

679.6

-2557.8

679.6

-2610.0

679.6

-2662.2

679.6

-2714.4

679.6

-2766.6

679.6

-2818.8

679.6

-2871.0

679.6

-2923.2

679.6

-2975.4

679.6

-3027.6

679.6

-3079.8

679.6

-3132.0

679.6

-3184.2

679.6

-3236.4

679.6

-3288.6

679.6

-3340.8

679.6

-3393.0

679.6

-3445.2

679.6

-3654.0

679.6

-3705.8

679.6

-3757.6

679.6

-3809.4

679.6

-3861.2

679.6

-3913.0

679.6

-3964.8

679.6

-4016.6

679.6

-4068.4

679.6

-4120.2

679.6

-4172.0

679.6

-4223.8

679.6

-4275.6

679.6

-4327.4

679.6

-4379.2

679.6

-4431.0

679.6

-4483.2

679.6

-4535.4

679.6

Solomon Systech

May 2005 P 10/56 Rev 1.7

SSD1303

Figure 3 - SSD1303Z Alignment mark dimensions

SSD1303

Rev 1.7 P 11/56 May 2005

+ shape

T shape

Circle

Unit in um

Solomon Systech

6 PIN DESCRIPTION

CL

This pin is the system clock input. When internal clock is enabled, this pin should be left open. The internal clock is output from this pin. When internal oscillator is disabled, this pin receives display clock signal from external clock source.

CLS

This is the internal clock enable pin. When it is pulled HIGH, internal clock is enabled. When it is pulled

LOW, the internal clock is disabled, an external clock source must be connected to the CL pin for normal operation

.

BS0, BS1, BS2

These are MCU interface input selection pins. See the following table for selecting different interfaces: interface

BS0 0 interface

0

Serial interface

0

BS1 0

BS2 1

1

1

0

0

CS#

This pin is the chip select input. The chip is enabled for MCU communication only when CS# had been pulled low.

RES#

This is a reset signal input pin. When it is pulled LOW, initialization of the chip is executed.

D/C

This is the Data/Command control pin. When it is pulled HIGH, the input at D

7

-D

0

is treated as display data.

When it is pulled LOW, the input at D

7

-D

0

is transferred to the command registers. For detail relationship to

MCU interface signals, please refer to the Timing Characteristics Diagrams.

R/W (WR#)

This is a MCU interface input pin. When 6800-series Parallel Interface mode is selected, this pin is used as

Read/Write (R/W) selection input. Pull this pin to HIGH for read mode and pull it to LOW for write mode.

When 8080-series Parallel Interface mode is selected, this pin is used as Write (WR#) selection input. Pull this pin to LOW for write mode. Data write operation is initiated when this pin is pulled LOW and the CS# is pulled LOW.

E (RD#)

This is a MCU interface input pin. When 6800-series Parallel Interface is selected, this pin is used as

Enable (E) signal. Read/Write operation is initiated when this pin is pulled HIGH and the CS# pin is pulled

LOW. When 8080-series Parallel Interface is selected, this pin is used to receive the Read Data (RD#) signal. Data read operation is initiated when this pin is pulled LOW and CS# pin is pulled LOW.

D

7

-D

0

These are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial interface mode is selected, D

1

will be the serial data input, SDIN, D

0

will be the serial clock input, SCLK, and

D

2

should be left opened.

Solomon Systech

May 2005 P 12/56 Rev 1.7

SSD1303

VDD

This is a voltage supply pin. It must be connected to external source.

VSS

This is a ground pin. It also acts as a reference for the logic pins and the OLED driving voltages. It must be connected to external ground.

BGGND

This is a ground pin for analog circuits. It must be connected to external ground

VCC

This is the most positive voltage supply pin of the chip. It should be supplied externally.

VREF

This is a voltage reference pin for pre-charge voltage in driving OLED device. Voltage should be set to match with the OLED driving voltage in current drive phase. It can either be supplied externally or by connecting to VCC.

IREF

This is a segment current reference pin. A resistor should be connected between this pin and V

SS

. Set the current at 10uA.

VCOMH

This is an input pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS.

VDDB This is a power supply pin for the internal buffer of the DC-DC voltage converter. It must be connected to V

DD

when the converter is used.

VSSB

This is a ground pin for the internal buffer of the DC-DC voltage converter. It must be connected to V

SS when the converter is used.

GDR

This is an output pin drives the gate of the external NMOS of the booster circuit.

RESE

This is a source current pin of the external NMOS of the booster circuit.

VB

REF

This is an internal voltage reference pin for booster circuit. A stabilization capacitor, typ. 1uF, should be connected to Vss.

FB

This is a feedback resistor input pin for the booster circuit. It is used to adjust the booster output voltage level, Vcc.

COM0-COM63

These are pins provided the Common switch signals to the OLED panel. They are in high impedance state when display is OFF.

SSD1303

Rev 1.7 P 13/56 May 2005

Solomon Systech

SEG0-SEG131

These are pins provided the Segment switch signals to the OLED panal. They are in high impedance stage when display is OFF.

TR0-TR8, GPIO0, GPIO1, ICAS, M and DOF#

These are reserved pins. No connection necessary and should be left open individually.

VSL

This is a segment voltage reference pin. This pin should be connected to VSS externally.

VCL

This is a common voltage reference pin. This pin should be connected to VSS externally.

M/S

This pin must be connected to VDD to enable the chip.

NC

Dummy pad. Do not group or short NC pins together.

Solomon Systech

May 2005 P 14/56 Rev 1.7

SSD1303

7 FUNCTIONAL BLOCK DESCRIPTIONS

7.1 Oscillator Circuit and Display Time Generator

Internal

Oscillator

CL

M

U

X

CLK

Divider

DCLK

Internal

Display

Clock

Figure 4 - Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the Display Timing Generator.

7.2 Reset Circuit

When RES# pin is pulled LOW, the chip is initialized with the following status:

1. Display is OFF

2. 132 x 64 Display Mode

3. Normal segment and display data column address and row address mapping (SEG0 is mapped to column address 00H and COM0 is mapped to row address 00H)

4. Shift register data clear in serial interface

5. Display start line is set at display RAM address 0

6. Column address counter is set at 0

7. Normal scan direction of the COM outputs

8. Contrast control register is set at 80H

7.3 Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. When the D/C# pin is pulled HIGH, the inputs at D

7

-D

0

are interpreted as data and be written to Graphic Display Data RAM

(GDDRAM). When it is pulled LOW, the inputs at D

7

-D

0

are interpreted as command, they will be decoded and be written to the corresponding command registers.

SSD1303

Rev 1.7 P 15/56 May 2005

Solomon Systech

7.4 MPU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D

7

-D

0

), R/W (WR#), E (RD#), D/C, CS#. When the R/W (WR#) pin is pulled HIGH, Read operation from the Graphic Display Data RAM (GDDRAM) or the status register occurs. When the R/W (WR#) pin is pulled LOW, Write operation to Display Data RAM or

Internal Command Registers occurs, depending on the status of D/C input. The E (RD#) input serves as data latch signal (clock) when HIGH provided that CS# is LOW. Refer to Parallel Interface Timing Diagram of 6800-series microprocessors.

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed, which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 5 below.

R/W#

(W/R#)

E (RD#)

Data bus

N

Write column address Dummy read n

Data read1 n+1

Data read2 n+2

Data read3

Figure 5 - Display data read back procedure - insertion of dummy read

7.5 MPU Parallel 8080-series Interface

The parallel interface consists of 8 bi-directional data pins (D

7

-D

0

), R/W (WR#), E (RD#), D/C, CS#. The E

(RD#) input serves as data read latch signal (clock) when it is LOW provided that CS# is LOW. Display data or status register read is controlled by D/C signal.

R/W (WR#) input serves as data write latch signal (clock) when it is HIGH and provided that CS# is LOW.

Display data or command register write is controlled by D/C. Refer to Parallel Interface Timing Diagram of

8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.

Solomon Systech

May 2005 P 16/56 Rev 1.7

SSD1303

7.6 MPU Serial Interface

The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as

SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins can be connected to external ground.

SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D

7

, D

6

, ... D

0

. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock.

During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to

Figure 6.

Figure 6 – Display data write procedure in SPI mode

CS#

D/C

SDIN/

SCLK

DB1 DB2 DBn NOP COMMAND

SCLK(D0)

SDIN(D1) D7 D6 D5 D4 D3 D2 D1 D0

7.7 Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is

132 x 64 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software.

For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display.

7.8 Current Control and Voltage Control

This block is used to derive the incoming power sources into different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive the driving voltage for segments and commons. IREF is a reference current source for segment current drivers.

SSD1303

Rev 1.7 P 17/56 May 2005

Solomon Systech

7.9 Segment Drivers / Common Drivers

Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted from

0 to 300uA with 256 steps. Common drivers generate voltage scanning pulses.

7.10 Area Colour Decoder

Page 0 and Page 1 of the display are divided into 32 banks. Bank16 and Bank32 comprise of a display area of 12 x 8 pixels. Other banks (0~15 & 17~31) have matrices of 8 x 8 pixels. Each bank can be programmed to any one of the four colours (colour A, B, C, D). Detailed operation can be referred to the Command

Table.

Page 0, bank

1 Page 0, bank 16

Page 1, bank

17

Page 1, bank 32

Bank 0 (background)

Page 2 – Page 7

Solomon Systech

May 2005 P 18/56 Rev 1.7

SSD1303

7.11 DC-DC Voltage Converter

It is a switching voltage generator circuit, designed for handheld applications. In SSD1303, internal DC-DC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply V

CC

from a low voltage supply input V

DD

. V

CC

is the voltage supply to the OLED driver block. Below application circuit is an example for the input voltage of 3V VDD to generate V

CC

of 12V

@0mA ~ 20mA application.

Figure 7 - DC-DC voltage converter circuit

L1

VDD

+

D1

VCC

C5

AGND

Q1

VDDB GDR

R1

+

C6

VBREF RESE

+

C7

+

C2

+

C3

+

C1

R3

VSSB FB

AGND

+

C4

R2

AGND

Remark:

1.

2.

3.

4.

DGND

VSSB is tied to VSS on SSD1303T3 package.

L1, D1, Q1, C5 should be grouped closed together on PCB layout.

R1, R2, C1, C4 should be grouped closed together on PCB layout.

The VCC output voltage level can be adjusted by R1and R2, the reference formula is:

VCC = 1.2 x (R1+R2) / R2

The value of (R1+R2) should be between 500k to 1M Ohm.

SSD1303

Rev 1.7 P 19/56 May 2005

Solomon Systech

Table 3 - Passive component selection:

D1

Q1

R1, R2

R3

C2

Schottky diode

MOSFET

Resistor

Resistor, 1.2

Capacitor, 6.8µF

Remark

1A, 25V e.g. 1N5822, BAT54 [Philips

Semiconductors]

N-FET with low R

DS

(on) and low Vth voltage. e.g. MGSF1N02LT1 [ON SEMI]

1%,1/10W

1%, 1/2W

Low ESR, 25V

C5

C6

Capacitor, 1 ~ 10 µF

Capacitor, 0.1 ~ 1µF

16V

16V

Solomon Systech

May 2005 P 20/56 Rev 1.7

SSD1303

Table 4 - Command table

(D/C =0, R/W (WR#)=0, E (RD#)=1)

Note: commands marked with “**” are compatible to SSD1301

D/C Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

0 00~0F 0 0 0 0 X

3

X

2

X

1

X

0

Set Lower Column

Address **

Description

Set the lower nibble of the column address register using X

3

X

2

X

1

X

0

as data bits. The initial display line register is reset to 0000b after POR.

0 10~1F 0 0 0 1 X

3

X

2

X

1

X

0

Set Higher Column

Address **

Set the higher nibble of the column address register using X

3

X

2

X

1

X

0

as data bits. The initial display line register is reset to 0000b after POR.

0 26 0 0 1 0 0 1 1 0 Horizontal scroll setup A[2:0] Set the number of column scroll per step

0 A[2:0] * * * * * A

2

A

1

A

0

0 B[2:0] * * * * * B

2

B

1

B

0

0 C[1:0] * * * * * * C

1

C

0

Valid value: 001b, 010b, 011b, 100b

B[2:0] Define start page address

C[1:0] Set time interval between each scroll step in terms of frame frequency

0 D[2:0] * * * * * D

2

D

1

D

0

0 2F

0 2E

00b – 12 frame

01b – 64 frames

10b – 128 frames

11b – 256 frames

D[2:0] Define end page address

Set the value of D[2:0] larger or equal to B[2:0]

0 0 1 0 1 1 1 1 Activate horizontal scroll Start horizontal scrolling

0 0 1 0 1 1 1 0 Deactivate horizontal scroll

Stop horizontal scrolling

X

5

X

4

X

3

X

2

X

1

X

0

Set Display Start Line Set display TAM display start line register from 0-63

using X

5

X

3

X

2

X

1

X

0

.

Display start line register is reset to 000000 during

POR

0 81 1 0 0 0 0 0 0 1

0 A[7:0] A

0 91

7

1

A

6

0

A

0 X[5:0] * * X

0 A[5:0] * * A

5

0

5

5

A

0 A[7:0] A

7

A

6

A

5

A

1

X

A

4

4

4

A

X

A

3

0

3

3

A

0

X

A

2

2

2

A

X

A

1

0

1

1

A

X

A

0

4

A

3

A

2

A

1

A

0

1

0

0

0 B[5:0] * * B

5

B

4

B

3

B

2

B

1

B

0

0 C[5:0] * * C

5

C

4

C

3

C

2

C

1

C

0

Set Contrast Control

Register **

0 82 1 0 0 0 0 0 1 0 Brightness for color banks

Set Look Up Table

(LUT) for area colour

Double byte command to select 1 out of 256 contrast steps. Contrast increases as the value increases.

(POR = 80h)

Double byte command to select 1 out of 256 brightness steps. Brightness increases as the value increases. (POR = 80h)

Set current drive pulse width of Bank 0, Colour A, B and C.

Bank 0: X[5:0] = 0… 63; for pulse width set to 1 ~

64 clocks (POR = 110001b)

Colour A: A[5:0] same as above (POR = 111111b)

Colour B: B[5:0] same as above (POR = 111111b)

Colour C: C[5:0] same as above (POR = 111111b)

Note: colour D pulse width is fixed at 64 clocks pulse .

SSD1303

Rev 1.7 P 21/56 May 2005

Solomon Systech

D/C Hex D7 D6 D5 D4 D3 D2 D1 D0

0 92 1 0 0 1 0 0 1 0

Command

Set bank colour of for bank 1-16 (Page 0)

Description

A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 1

0 A[7:0] A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 2

0 B[7:0] B

7

B

6

B

5

B

4

B

3

B

2

B

1

B

0

:

0 C[7:0] C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

:

0 D[7:0] D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of bank 16

0 93 1 0 0 1 0 0 1 1

0 A[7:0] A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Set bank colour of for bank 17-32 (Page 1)

A[1:0] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 17

A[3:2] : 00, 01, 10, or 11 for Colour = A, B, C or D of bank 18

0 B[7:0] B

7

B

6

B

5

B

4

B

3

B

2

B

1

B

0

:

0 C[7:0] C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

:

0 D[7:0] D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D[7:6]: 00, 01, 10, or 11 for Colour = A, B, C or D of bank 32

A1 1 0 1 0 0 0 0 Set Segment Re-map ** X

0

=0: column address 0 is mapped to SEG0 (POR)

0 A4~A5 1 0 1 0 0 1 0 X

0

Set Entire Display

ON/OFF **

X

0

=1: column address 131 is mapped to SEG0

X

0

=0: normal display (POR)

X

0

=1: entire display ON

0 A6~A7 1 0 1 0 0 1 1 X

0

Set

Display **

X

0

=0: normal display (POR)

X

0

=1: inverse display

0 A8 1 0 1 0 1 0 0 0 Set Multiplex Ratio ** The next command, A[5:0] determines multiplex ratio

0 A[5:0] * * A

5

A

4

A

3

A

2

A

1

A

0

N from 16MUX-64MUX, POR= 64MUX

0

0

0

AB

AD

1

1

1

0 1 0

0

0

1

0

0

0

1

1

1

0

1

0

1 1

0

1

1

X

0

NOP

Set DC-DC on/off

0 AE~AF 1 0 1 0 1 1 1 X

0

Set Display ON/OFF **

0 B0~BF 1 0 1 1 X

3

X

2

X

1

X

0

Set Page Address **

Reserved, do not use

X

0

: 1 DC-DC will be turned on when display on

(POR)

0 DC-DC is disable

X

0

=0: turns OFF OLED panel (POR)

X

0

=1: turns ON OLED panel

Set GDDRAM Page Address (0~7) for read/write using X

3

X

2

X

1

X

0

0 C0/C8 1 1 0 0 X

3

* * * Set COM Output Scan

Direction **

0 D0-D1 1 1 0 1 0 0 0 X

0

Reserved

X

3

=0: normal mode (POR) Scan from COM 0 to COM

[N –1]

X

3

=1: remapped mode. Scan from COM [N-1] to

COM0

Where N is the Multiplex ratio.

Reserved, do not use

Solomon Systech

May 2005 P 22/56 Rev 1.7

SSD1303

D/C Hex D7 D6 D5 D4 D3 D2 D1 D0 Command

0 D3 1 1 0 1 0 0 1 1 Set Display Offset **

0 A[5:0] * * A

5

A

4

A

3

A

2

A

1

A

0

Description

scroll COM

The value is reset to 00H after POR.

A[3:0] Define the divide ratio of the display clocks

(DCLK): Divide Ratio/Oscillator

Frequency

0 A[7:0] A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Divide ratio= A[3:0] + 1, POR is 0000b (divide ratio =

1)

A[7:4] Set the Oscillator Frequency. Oscillator

Frequency increases with the value of A[7:4] and vice versa. POR is 0111b

0 D8 1 1 0 1 1 0 0 0 Set area colour mode

0 D9

X

5

X

4

0 X

2

0 X

0 on/off & low power display mode

X

5

X

4

= 00 (POR) : mono mode

X

5

X

4

= 11 Area Colour enable

X

2

=0 and X

0

=0: Normal (POR) power mode

X

2

=1 and X

0

=1: Set low power save mode

1 1 0 1 1 0 0 1 Set Pre-charge period** A[3:0] Phase 1 period of up to 15 dclk clocks

[POR=2h]; 0 is invalid entry

0 A[7:0] A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

0 DA 1 1 0 1 1 0 1 0 Set COM pins hardware

0 0 0 1 0 configuration

A[7:4] Phase 2 period of up to 15 dclk clocks

[POR=2h]; 0 is invalid entry

X

4

=0, Sequential COM pin configuration

(i.e. COM31, 30, 29….0 ; SEG0-132;

COM31,32….62,63)

X

4

=1(POR), Alternative COM pin configuration

(i.e. COM62,60,58,…2,0; SEG0-132;

COM1,3,5…61,63)

0 A[6:0] * A

6

A

5

A

4

A

3

A

2

A

1

A

0

Level

0 E2 1 1 1 0 0 0 1 0 Reserved

A[6:0] 0000000 low VCOM deselect level (~ 0.43

Vref)

0110101 normal VCOM deselect level (~ 0.77*Vref

(POR))

1111111 high VCOM deselect level (equal Vref)

Reserved

Reserved, do not use Reserved

0 F* 1 1 1 1 * * * *

Note: Remark “*” stands for “Don’t Care”

Table 5 - Read command table

SSD1303

Rev 1.7 P 23/56 May 2005

Solomon Systech

(D/C=0, R/W (WR#)=1, E (RD#)=1 for 6800 or E (RD#)=0 for 8080)

Bit Pattern Command Description

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Status Register Read *

D

7

: Reserve

D

6

: “1” for display OFF / “0” for display ON

D

5 :

Reserve

D

4 :

Reserve

D

3 :

Reserve

D

2 :

Reserve

D

1 :

Reserve

D

0 :

Reserve

Note: Patterns other than that given in Command Table are prohibited to enter to the chip as a command; otherwise, unexpected result will occur.

8.1 Data Read / Write

To read data from the GDDRAM, input HIGH to R/W (WR#) pin and D/C pin for 6800-series parallel mode,

LOW to E (RD#) pin and HIGH to D/C# pin for 8080-series parallel mode. No data read is provided in serial mode operation.

In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read.

Also, a dummy read is required before the first data read. See Figure 5 in Functional Block Description.

To write data to the GDDRAM, input LOW to R/W (WR#) pin and HIGH to D/C pin for 6800-series parallel mode AND 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write.

Table 6 - Address increment table (Automatic)

D/C R/W (WR#) Comment

Address Increment

*1. If read-data command is issued in read-modify-write mode, address increase is not applied.

Solomon Systech

May 2005 P 24/56 Rev 1.7

SSD1303

Set Lower Column Address

This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU.

Set Higher Column Address

This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU.

Activate Horizontal Scroll

Start motion of horizontal scrolling. This command should only be issued after Horizontal scroll setup parameters are defined.

The following actions are prohibited after the horizontal scroll is activated

1. RAM access (Data write or read)

2. Changing horizontal scroll setup parameters

The SSD1303 horizontal scroll is designed for 128 columns scrolling only. 4 remaining columns are reserved for computation and should be left open.

With column address 0 mapped to SEG0 (Segment remap setting = A0h), the 4 unused columns will be

SEG128, SEG129, SEG130, SEG131.

With column address 0 mapped to SEG131 (Segment remap setting = A1h), the 4 unused columns will be

SEG0, SEG1, SEG2, SEG3.

Figure 8 - Horizontal scroll direction

REMAP

SETTING

A0

A1

A B C D E

Invalid data Z

F

! ! !

Y

Y

" " "

F

Z

E

Invalid data

D C B A

Scroll direction

SSD1303

Rev 1.7 P 25/56 May 2005

Solomon Systech

Deactivate Horizontal Scroll

Stop motion of horizontal scrolling.

Horizontal Scroll Setup

This command consists of 5 consecutive bytes to set up the horizontal scroll parameters. It determined the scrolling start page, end page and the scrolling speed.

Before issuing this command, the horizontal scroll must be deactivated (2Eh). Otherwise, ram content may be corrupted.

Set Display Start Line

This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D

0

of Page 0 is mapped to COM0. With value equals to 1, D

1

of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to

Page 0 to 7.

Set Contrast Control Register

This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current increases as the contrast step value increases. See Figure 9.

Figure 9 - Segment current vs Contrast setting

Segm ent current vs Contrast setting

350

300

Current (uA)

250

200

150

100

Segment output current setting:

Iseg = Cr/256 * Iref * scale factor

Where:

Cr is contrast step

Iref is reference current equals 10uA

Scale factor =32

50

0

00 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF

Contrast setting

Set Brightness for Color Banks

This command is to set Brightness Setting of the display for area colors banks (except bank 0). The chip has 256 brightness steps from 00 to FF. The segment output current increases as the brightness step value increases

Solomon Systech

May 2005 P 26/56 Rev 1.7

SSD1303

Set Look Up Table (LUT) for area colour

SSD1303 provides 4 colour (pulse width) settings - Colour A, B, C and D. The colour intensity (or grey scale) is defined by the current drive pulse width. The pulse width of colour A, B, C can be programmable from 1 to 64 DCLK* duration. The colour D is fixed at 64 DCLK pulse width. This colour setting has to be stored in the Look Up Table (LUT).

For the background colour, the colour intensity is defined by a variable X[5:0].

Set LUT command: 10010001

X[5:0]

A[5:0]

B[5:0]

C[5:0]

Bank 0

Colour A

Colour B

Colour C

Set background colour

Set Pulse Width A

Set Pulse Width B

Set Pulse Width C

DCLKs

X[5:0]

A[5:0]

B[5:0]

Colour D Pulse width D is fixed to 64

DCLK

DCLK: Internal Display Clock

C[5:0]

64 (fixed)

Set bank colour of bank 1-16 (Page 0) and bank colour of bank 17-32 (Page 1)

Next step is to define the colour of each display area. The 132x64 display matrix is divided into 8 pages of 8 commons per pages. The first two pages, page 0 and page 1, are divided into 32 banks: Bank16 and

Bank32 comprise of a display area of 12x8 pixels. Other banks (0~15 & 17~31) have matrices of 8x8 pixels.

Each bank can be programmable to any 1 of the 4 colour (A, B, C, D). User can use 92h and 93h command for the bank colour setting. Note: Only applicable in area colour mode.

Set Segment Re-map

This command changes the mapping between the display data column address and segment driver. It allows flexibility in OLED module design. Refer to Command Table.

Set Entire Display ON/OFF

This command forces the entire display to be “ON” regardless of the contents of the display data RAM. This command has priority over normal/reverse display. This command will be used with “Set Display ON/OFF” command to form a compound command for entering power save mode.

Set Normal/Inverse Display

This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an

“ON” pixel while in inverse display; a RAM data of 0 indicates an “ON” pixel.

Set Multiplex Ratio

This command switches default 63 multiplex mode to any multiplex ratio from 2 to 63. The output pads

COM0-COM63 will be switched to corresponding COM signal.

Set DC-DC on/off

This command is to control the DC-DC voltage converter. The converter will be turned on by issuing this command then DISPLAY ON command. The panel display must be off while issuing this command.

POR the DC-DC will be turned on.

SSD1303

Rev 1.7 P 27/56 May 2005

Solomon Systech

Set Display ON/OFF

This command turns the display ON or OFF. When the display is OFF, the segment and common output are in high impedance state.

Set Page Address

This command positions the page address from 0 to 7 in GDDRAM. Refer to Command Table.

Set COM Output Scan Direction

This command sets the scan direction of the COM output allowing layout flexibility in OLED module design.

In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will be vertically flipped.

Set Display Offset

This is a double byte command. The next command specifies the mapping of display start line to one of

COM0-63 (it is assumed that COM0 is the display start line, display start line register equals to 0).

For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second byte should be given by 010000. To move in the opposite direction by 16 lines, the 6-bit data should be given by

(64 – 16) and so the second byte should be 100000.

Solomon Systech

May 2005 P 28/56 Rev 1.7

SSD1303

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

Hardware pin name

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row50

Row51

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row40

Row41

Row52

Row53

Row54

Row55

Row56

Row57

Row58

Row59

Row60

Row61

Row62

Row63

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row30

Row31

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

Row21

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row8

Row9

Row10

Row11

Row12

64

Normal

0

0

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

RAM8

RAM9

RAM10

RAM11

RAM12

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM30

RAM31

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

RAM21

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

RAM50

RAM51

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM40

RAM41

RAM52

RAM53

RAM54

RAM55

RAM56

RAM57

RAM58

RAM59

RAM60

RAM61

RAM62

RAM63

Row50

Row51

Row52

Row53

Row54

Row55

Row56

Row57

Row58

Row59

Row40

Row41

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row60

Row61

Row62

Row63

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row30

Row31

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row21

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row8

Row9

Row10

Row11

Row12

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

64

Normal

8

0

RAM8

RAM9

RAM10

RAM11

RAM12

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

RAM30

RAM31

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM21

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM50

RAM51

RAM52

RAM53

RAM54

RAM55

RAM56

RAM57

RAM58

RAM59

RAM40

RAM41

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

RAM60

RAM61

RAM62

RAM63

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row50

Row51

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row40

Row41

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row30

Row31

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

Row21

Row52

Row53

Row54

Row55

Row56

Row57

Row58

Row59

Row60

Row61

Row62

Row63

Output

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row8

Row9

Row10

Row11

Row12

64

Normal

0

8

RAM8

RAM9

RAM10

RAM11

RAM12

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row8

Row9

Row10

Row11

Row12

56

Normal

0

0

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

RAM8

RAM9

RAM10

RAM11

RAM12

RAM50

RAM51

RAM52

RAM53

RAM54

RAM55

RAM56

RAM57

RAM58

RAM59

RAM40

RAM41

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

RAM30

RAM31

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM21

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM60

RAM61

RAM62

RAM63

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row50

Row51

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row40

Row41

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row30

Row31

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

Row21

Row52

Row53

Row54

Row55

-

-

-

-

-

-

-

-

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

RAM50

RAM51

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM40

RAM41

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM30

RAM31

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

RAM21

RAM52

RAM53

RAM54

RAM55

-

-

-

-

-

-

-

-

Row50

Row51

Row52

Row53

Row54

Row55

-

-

-

-

Row40

Row41

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row0

Row1

Row2

Row3

Row4

-

-

-

-

Row5

Row6

Row7

Row30

Row31

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row21

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row8

Row9

Row10

Row11

Row12

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

56

Normal

8

0

RAM8

RAM9

RAM10

RAM11

RAM12

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

RAM30

RAM31

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM21

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM50

RAM51

RAM52

RAM53

RAM54

RAM55

-

-

-

-

RAM40

RAM41

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

-

-

-

-

RAM0

RAM1

RAM2

RAM3

RAM4

RAM5

RAM6

RAM7

Row42

Row43

Row44

Row45

Row46

Row47

Row48

Row49

Row50

Row51

Row32

Row33

Row34

Row35

Row36

Row37

Row38

Row39

Row40

Row41

Row52

Row53

Row54

Row55

-

-

-

-

-

-

-

-

Row22

Row23

Row24

Row25

Row26

Row27

Row28

Row29

Row30

Row31

Row13

Row14

Row15

Row16

Row17

Row18

Row19

Row20

Row21

Row0

Row1

Row2

Row3

Row4

Row5

Row6

Row7

Row8

Row9

Row10

Row11

Row12

56

Normal

0

8

RAM8

RAM9

RAM10

RAM11

RAM12

RAM13

RAM14

RAM15

RAM16

RAM17

RAM18

RAM19

RAM20

RAM30

RAM31

RAM32

RAM33

RAM34

RAM35

RAM36

RAM37

RAM38

RAM39

RAM21

RAM22

RAM23

RAM24

RAM25

RAM26

RAM27

RAM28

RAM29

RAM50

RAM51

RAM52

RAM53

RAM54

RAM55

RAM56

RAM57

RAM58

RAM59

RAM40

RAM41

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM48

RAM49

RAM60

RAM61

RAM62

RAM63

-

-

-

-

-

-

-

-

Set MUX ratio(A8)

COM Normal / Remapped (C0 / C8)

Display offset (D3)

Display start line (40 - 7F)

SSD1303

Rev 1.7 P 29/56 May 2005

Solomon Systech

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

Row23

Row22

Row21

Row20

Row19

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row47

Row46

Row45

Row44

Row43

Row42

Row41

Row40

Row18

Row17

Row16

Row15

Row14

Row13

Row12

Row11

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row57

Row56

Row55

Row54

Row53

Row52

Row51

Row50

Row49

Row48

Row63

Row62

Row61

Row60

Row59

Row58

64

Remap

0

0

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

Row23

Row22

Row21

Row20

Row19

Row18

Row17

Row16

Row15

Row14

Row13

Row12

Row11

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row2

Row1

Row0

-

-

-

-

-

-

-

Row47

Row46

Row45

Row44

-

-

-

-

-

-

Row43

Row42

Row41

Row40

48

Remap

8

16

-

-

RAM63

RAM62

RAM61

RAM60

-

-

-

-

-

-

RAM59

RAM58

RAM57

RAM56

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

-

-

-

-

-

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

Row15

Row14

Row13

Row12

Row11

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row23

Row22

Row21

Row20

Row19

Row18

Row17

Row16

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

-

-

-

-

-

-

-

-

Row2

Row1

Row0

-

-

-

-

-

Row41

Row40

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row47

Row46

Row45

Row44

Row43

Row42

48

Remap

0

8

RAM41

RAM40

RAM41

RAM42

RAM43

RAM44

RAM45

RAM46

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

-

-

-

-

-

-

-

-

RAM10

RAM9

RAM8

-

-

-

-

-

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

Row23

Row22

Row21

Row20

Row19

Row18

Row17

Row16

Row15

Row14

Row13

Row12

Row11

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row2

Row1

Row0

-

-

-

-

-

-

-

Row47

Row46

Row45

Row44

-

-

-

-

-

-

Row43

Row42

Row41

Row40

48

Remap

8

0

-

-

RAM47

RAM46

RAM45

RAM44

-

-

-

-

-

-

RAM43

RAM42

RAM41

RAM40

RAM10

RAM9

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

-

-

-

-

-

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

Row15

Row14

Row13

Row12

Row11

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row23

Row22

Row21

Row20

Row19

Row18

Row17

Row16

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

-

-

-

-

-

-

-

-

Row2

Row1

Row0

-

-

-

-

-

Row47

Row46

Row45

Row44

Row43

Row42

Row41

Row40

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Output

48

Remap

0

0

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

-

-

-

-

-

-

-

-

RAM2

RAM1

RAM0

-

-

-

-

-

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM9

RAM8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM31

RAM30

RAM29

RAM28

RAM27

RAM26

RAM25

RAM24

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row31

Row30

Row29

Row28

Row27

Row47

Row46

Row45

Row44

Row43

Row42

Row41

Row40

Row55

Row54

Row53

Row52

Row51

Row50

Row49

Row48

Row26

Row25

Row24

Row23

Row22

Row21

Row20

Row19

Row18

Row17

Row16

Row15

Row14

Row13

Row12

Row11

Row1

Row0

Row63

Row62

Row61

Row60

Row59

Row58

Row57

Row56

Row7

Row6

Row5

Row4

Row3

Row2

64

Remap

8

0

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

Hardware pin name

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

Row31

Row30

Row29

Row28

Row27

Row26

Row25

Row24

Row23

Row22

Row21

Row20

Row19

Row39

Row38

Row37

Row36

Row35

Row34

Row33

Row32

Row47

Row46

Row45

Row44

Row43

Row42

Row41

Row40

Row18

Row17

Row16

Row15

Row14

Row13

Row12

Row11

Row10

Row9

Row8

Row7

Row6

Row5

Row4

Row3

Row57

Row56

Row55

Row54

Row53

Row52

Row51

Row50

Row49

Row48

Row63

Row62

Row61

Row60

Row59

Row58

64

Remap

0

8

RAM7

RAM6

RAM5

RAM4

RAM3

RAM2

RAM1

RAM0

RAM63

RAM62

RAM61

RAM60

RAM59

RAM58

RAM57

RAM56

RAM26

RAM25

RAM24

RAM23

RAM22

RAM21

RAM20

RAM19

RAM18

RAM17

RAM16

RAM15

RAM14

RAM13

RAM12

RAM11

RAM39

RAM38

RAM37

RAM36

RAM35

RAM34

RAM33

RAM32

RAM31

RAM30

RAM29

RAM28

RAM27

RAM47

RAM46

RAM45

RAM44

RAM43

RAM42

RAM41

RAM40

RAM55

RAM54

RAM53

RAM52

RAM51

RAM50

RAM49

RAM48

Set MUX ratio(A8)

COM Normal / Remapped (C0 / C8)

Display offset (D3)

Display start line (40 - 7F)

COM61

COM62

COM63

Row2

Row1

Row0

RAM2

RAM1

RAM0

Row10

Row9

Row8

RAM10

RAM9

RAM8

Row2

Row1

Row0

RAM10

RAM9

RAM8

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Set Display Clock Divide Ratio/ Oscillator Frequency

This command is used to set the frequency of the internal display clocks, DCLKs. It is defined as the divide ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency.

Set Area Colour Mode ON/OFF

This command is used to enable area colour mode. POR is mono mode.

Solomon Systech

May 2005 P 30/56 Rev 1.7

SSD1303

Set Low Power Display Mode

This is a double byte command. This command is set to reduce power consumption during IC operation.

Set Pre-charge period

This command is used to set the duration of the pre-charge period. The interval is counted in number of

DCLK. POR is 2 DCLK.

Set COM pins hardware configuration

This command is to set the COM signals pin configuration (sequential or alternative) to match the OLED panel hardware layout

Sequential COM pin configuration:

COM31, 30, 29…0 SEG0, 1, 2… 131 COM32, 33, 34…63

Alternative COM pin configuration (POR):

COM62, 60, 58…0 SEG0, 1, 2… 131 COM1, 3, 5…63

Set VCOM deselect level

This command is to set the COM pin output voltage level at deselect stage.

NOP

No Operation Command

Status register Read

This command is issued by setting D/C# LOW during a data read (refer to Figure 10 and Figure 11 for parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.

SSD1303

Rev 1.7 P 31/56 May 2005

Solomon Systech

10 MAXIMUM RATINGS

Table 7 - Maximum Ratings

(Voltage Reference to V

SS

)

Symbol Parameter Value Unit

V

DD

V

CC

V

REF

V

COMH

-

Supply Voltage

Supply Voltage/Output voltage

SEG/COM output voltage

-0.3 to +4.0

0.0 to 18.0

0.0 to 18.0

0.0 to 18.0

0.0 to 18.0

V

V

V

V

V

V in

T

A

T stg

Input voltage

Operating Temperature

Storage Temperature Range

Vss-0.3 to Vdd+0.3

-40 to +90

-65 to +150

V

ºC

ºC

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description.

Solomon Systech

May 2005 P 32/56 Rev 1.7

SSD1303

11 DC CHARACTERISTICS

Table 8 - DC Characteristics

(Unless otherwise specified, Voltage Referenced to V

SS

, V

DD

= 2.4 to 3.5V, T

A

= 25

°

C)

Symbol Parameter Test

V

CC

Operating -

V

DD

- 2.4 -

V

DD

V

OH

V

OL

V

IH

V

IL

I

CC, SLEEP

I

DD, SLEEP

Logic Supply Voltage

Logic Supply Voltage (internal

DC/DC enable)

High Logic Output Level

Low Logic Output Level

High Logic Input Level

Low Logic Input Level

Sleep mode Current

Sleep mode Current

-

3.5

V

IOUT = 100uA, 3.3MHz 0.9*V

DD

- V

DD

V

IOUT = 100uA, 3.3MHz 0 - 0.1*V

DD

V

IOUT = 100uA, 3.3MHz 0.8*V

DD

- V

DD

V

IOUT = 100uA, 3.3MHz 0 - 0.2*V

DD

V

VDD=2.7V, display

OFF, No panel attached

VDD=2.7V, display

OFF, No panel attached

I

CC

V

CC

Supply Current

V

DD

= 2.7V, V

CC

= 12V, I

REF

= 10uA

No loading, Display ON, All ON

Contrast = FF

I

DD

I

SEG

Dev

Adj. Dev

Vcc

Pwr

V

DD

Supply Current

V

DD

= 2.7V, V

CC

= 12V, I

REF

= 10uA

No loading, Display ON, All ON

Segment Output Current

VDD=2.7V, VCC=12V,

IREF=10uA, Display ON, Segment pin under test is connected with a

20K resistive load to VSS

Contrast = FF

Segment output current uniformity

Adjacent pin output current uniformity (contrast = FF)

DC-DC converter output voltage

DC-DC converter output power

Dev = (I

SEG

– I

MID

)/I

MID

I

MID

= (I

MAX

+ I

MIN

)/2

I

SEG

[0:131] = Segment current at contrast = FF

Adj Dev = (I[n]-I[n+1]) /

(I[n]+I[n+1])

VDD input=3V, L=22uH;

R1=450Kohm;

R2=50Kohm;

Icc = 20mA(loading)

-

VDD input=3V, L=22uH;

Vcc = 12V

-

-

-

-

550

190

-

±

2.0

-

-

±

3 uA uA uA

%

- %

11.0 12.0 13.0

V

7 - 16

- mW

SSD1303

Rev 1.7 P 33/56 May 2005

Solomon Systech

12 AC CHARACTERISTICS

Table 9 - AC Characteristics

(Unless otherwise specified, Voltage Referenced to V

SS

, V

DD

= 2.4 to 3.5V, T

A

= 25°C.)

Symbol

F

OSC

F

FRM

RES#

Oscillation Frequency of

Display Timing

Generator

Frame Frequency for 64

MUX Mode

Reset low pulse width

Vdd = 2.7V

132x64 Graphic Display Mode,

Display ON, Internal Oscillator

Enabled

-

-

3

F

OSC

X

1/(D*K*64)

Reset complete time -

D: divide ratio (default value = 1)

K: number of display clocks (default value = 54)

Refer to command table (set display clock divide ratio/oscillator freq) for detail description

-

2

Hz us us

Solomon Systech

May 2005 P 34/56 Rev 1.7

SSD1303

Table 10 - 6800-Series MPU Parallel Interface Timing Characteristics

(V

DD

- V

SS

= 2.4 to 3.5V, T

A

= 25°C)

Symbol Parameter

t cycle t

AS

Address Time t t t

AH

Time

DSW

DHW

Write Data Setup Time

Write Data Hold Time t

DHR

Read Data Hold Time t

OH

Output Time t

ACC

PW

PW t

R

CSL

CSH

Chip Select Low Pulse Width (read)

Chip Select Low Pulse Width (write)

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write) t

F

Fall

D/C t

AS t

AH

R/W

Min Typ Max Unit

300 - - ns

0 - - ns

0 - - ns

40

7

-

-

-

- ns ns

20 - - ns

- - 70 ns

- - 140 ns

120

60

60

60

- - ns

- - ns

- - 15 ns

- - 15 ns

E

CS#

D

0

~D

7

(WRITE)

D

0

~D

7

(READ) t cycle

PW

CSH t

F

PW

CSL t

R t

DSW

Valid Data t

DHW t

ACC t

DHR

Valid Data t

OH

Figure 10 - 6800-series MPU parallel interface characteristics

SSD1303

Rev 1.7 P 35/56 May 2005

Solomon Systech

Table 11 - 8080-Series MPU Parallel Interface Timing Characteristics

(V

DD

- V

SS

= 2.4 to 3.5V, T

A

= 25°C)

Symbol Parameter

t cycle

Clock t

AS

Address t t

AH

Address

DSW

Write Data Setup Time t t

DHW

DHR

Write Data Hold Time

Read Data Hold Time t

OH

Output t

ACC

Access

PW

CSL

Chip Select Low Pulse Width (read)

Chip Select Low Pulse Width (write)

PW

CSH

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write) t

R

Time t

F

Time

D/C

CS#

RD#

WR# t

F t

AS

D

0

-D

7

(Write data to driver)

D

0

-D

7

(Read data from driver) t

ACC

PW

CSL t

DSW t cycle

Valid Data

Valid Data t

AH t

DHW t

R t

DHR

Min Typ Max Unit

40

7

20

120

60

60

60

- - ns

- - ns

- - 15 ns

- - 15 ns t

PW

CSH

Figure 11 - 8080-series MPU parallel interface characteristics

-

-

-

-

-

- ns ns ns

Solomon Systech

May 2005 P 36/56 Rev 1.7

SSD1303

Table 12 - Serial Interface Timing Characteristics

(V

DD

- V

SS

= 2.4 to 3.5V, T

A

= 25°C)

Symbol

t

CSH t

DSW t

DHW t

CLKL t

CLKH t cycle t

AS t

AH t

CSS t

R t

F

Clock Cycle Time

Address Setup Time

Address Hold Time

Chip Select Setup Time

Chip Select Hold Time

Write Data Setup Time

Write Data Hold Time

Clock Low Time

Clock High Time

Rise Time

Fall Time

Parameter Min Typ Max Unit

250

- - ns

150 - - ns

150 - - ns

120 - - ns

60 - - ns

100 - - ns

100 - - ns

100 - - ns

100 - - ns

- - 15 ns

- - 15 ns

D/C

CS# t

CSS t

AS t

AH t

CSH t cycle t

CLKL t

CLKH

SCLK(D

0

) t

F t

R t

DHW

SDIN(D

1

) t

DSW

Valid Data

CS#

SCLK(D

0

)

SDIN(D

1

)

SSD1303

D7 D6 D5

Figure 12 - Serial interface characteristics

Rev 1.7 P 37/56 May 2005

D4 D3 D2 D1 D0

Solomon Systech

13 APPLICATION EXAMPLE

Figure 13 - Application Example (Block Diagram of SSD1303T3)

The configuration for 6800-parallel interface mode, externally V

CC

is shown in the following diagram:

(V

DD

=2.7V, V

CC

=V

REF

=12V, I

REF

=10uA)

DISPLAY PANEL SIZE

96 x 64

SSD1303T3

V

CC

V

COMH

I

REF

D

7

~D

0

E (RD#) R/W# (W/R#) D/C# RES# CS# BS

1

BS

2

V

DD

VDDB GDR RESE FB VB

REF

V

SS

C

3

C

2

Vcc

R

1

V

SS

[GND]

C

1

D

0

~D

7

E (RD#) R/W# (W/R#) D/C# RES# CS# BS

1

BS

2

V

DD

V

SS

Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, CS#, RES#

Pin externally connected to VSS: BS0, VSSB

Pin internally connected to VCC: VREF

GDR, RESE, VB

REF

, FB should be left open individually;

C

1

~ C

3

: 4.7uF

R1: 910k

, R

1

=(Voltage at IREF pin-VSS)/I

REF

Voltage at IREF pin = VCC-3V

Solomon Systech

May 2005 P 38/56 Rev 1.7

SSD1303

14 SSD1303T3R1 PACKAGE DETAILS

SSD1303T3R1 Pin Assignment

Figure 14 - SSD1303T3R1 pin assignment (Copper view, Normal TAB design)

Remark:

Use internal clock

VREF is connected to VCC

Support MCU interface: 8-bit 6800/8080 parallel interface and SPI

VSSB, BGGND are connected to VSS

BS0 is connected to VSS

SSD1303

Rev 1.7 P 39/56 May 2005

Solomon Systech

Table 13 - SSD1303T3R1 pin assignment

Pin no.

Pin name

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

NC

NC

128

129

130

131

132

133

134

135

136

121

122

123

124

125

126

127

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

159

160

161

162

163

164

165

166

167

152

153

154

155

156

157

158

168

169

170

171

172

173

174

175

176

177

178

179

180

NC

NC

NC

NC

NC

NC

COM1

COM3

COM5

Pin no.

Pin name

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

NC

NC

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

COM8

COM6

COM4

COM2

COM0

NC

NC

NC

NC

NC

NC

99

100

101

102

103

104

105

106

107

92

93

94

95

96

97

98

108

109

110

111

112

113

114

115

116

117

118

119

120

72

73

74

75

76

68

69

70

71

61

62

63

64

65

66

67

81

82

83

84

77

78

79

80

85

86

87

88

89

90

91

Pin no.

Pin name

43

44

45

46

47

39

40

41

42

32

33

34

35

36

37

38

52

53

54

55

48

49

50

51

56

57

58

59

60

12

13

14

15

16

8

9

10

11

6

7

4

5

1

2

3

21

22

23

24

17

18

19

20

25

26

27

28

29

30

31

NC

NC

COM62

COM60

COM58

COM56

COM54

COM52

COM50

COM48

COM46

COM44

COM42

COM40

COM38

COM36

COM34

COM32

COM30

COM28

COM26

COM24

COM22

COM20

COM18

COM16

COM14

COM12

COM10

NC

VSS

GDR

VDDB

FB

RESE

VBREF

GP0

GP1

NC

VDD1

BS1

BS2

NC

CS#

RES#

D/C

R/W

E/RD

D0

D1

D2

D3

D4

D5

D6

D7

IREF

VCOMH

VCC

NC

Pin no.

Pin name

188

189

190

191

192

193

194

195

196

181

182

183

184

185

186

187

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

COM7

COM9

COM11

COM13

COM15

COM17

COM19

COM21

COM23

COM25

COM27

COM29

COM31

COM33

COM35

COM37

COM39

COM41

COM43

COM45

COM47

COM49

COM51

COM53

COM55

COM57

COM59

COM61

COM63

NC

NC

Solomon Systech

May 2005 P 40/56 Rev 1.7

SSD1303

SSD1303T3R1 TAB PACKAGE DIMENSIONS

SSD1303

Rev 1.7 P 41/56 May 2005

Solomon Systech

Solomon Systech

May 2005 P 42/56 Rev 1.7

SSD1303

15 SSD1303T6R1 PACKAGE DETAILS

SSD1303T6R1 Pin Assignment

Figure 15 - SSD1303T6R1 pin assignment (Copper view)

Remark:

Use internal clock

VREF is connected to VCC

Support MCU interface: 8-bit 6800/8080 parallel interface and SPI

VSSB, BGGND are connected to VSS

BS0 is connected to VSS

SSD1303

Rev 1.7 P 43/56 May 2005

Solomon Systech

Pin no.

Pin name

43

44

45

46

47

48

37

38

39

40

41

42

29

30

31

32

33

34

35

36

23

24

25

26

27

28

55

56

57

58

59

60

49

50

51

52

53

54

17

18

19

20

21

22

10

11

12

13

14

15

16

8

9

6

7

3

4

1

2

5

COM57

COM55

COM53

COM51

COM49

COM47

COM45

COM43

COM41

COM39

COM37

COM35

NC

NC

VBREF

RESE

FB

VDDB

GDR

VSS

NC

NC

NC

COM63

COM61

COM59

COM33

COM31

COM29

COM27

COM25

COM23

COM21

COM19

COM17

COM15

COM13

COM11

D2

D1

D0

E/RD

R/W

D/C

RES#

CS#

NC

BS2

BS1

VDD

NC

NC

VCC

VCOMH

IREF

D7

D6

D5

D4

D3

Solomon Systech

Table 14 - SSD1303T6R1 pin assignment

Pin no.

Pin name

103

104

105

106

107

108

97

98

99

100

101

102

89

90

91

92

93

94

95

96

83

84

85

86

87

88

115

116

117

118

119

120

109

110

111

112

113

114

77

78

79

80

81

82

70

71

72

73

74

75

76

66

67

68

69

61

62

63

64

65

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG99

SEG98

SEG97

SEG96

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG95

SEG94

SEG93

SEG92

SEG91

SEG90

SEG89

SEG88

SEG87

SEG86

SEG85

SEG84

NC

NC

NC

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

SEG123

SEG122

COM9

COM7

COM5

COM3

COM1

NC

NC

NC

NC

Pin no.

Pin name

163

164

165

166

167

168

157

158

159

160

161

162

149

150

151

152

153

154

155

156

143

144

145

146

147

148

175

176

177

178

179

180

169

170

171

172

173

174

137

138

139

140

141

142

130

131

132

133

134

135

136

121

122

123

124

125

126

127

128

129

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG61

SEG60

SEG59

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG74

SEG73

SEG72

SEG71

SEG70

SEG69

SEG68

SEG67

SEG66

SEG65

SEG64

SEG63

SEG62

SEG83

SEG82

SEG81

SEG80

SEG79

SEG78

SEG77

SEG76

SEG75

Pin no.

Pin name

223

224

225

226

227

228

217

218

219

220

221

222

209

210

211

212

213

214

215

216

203

204

205

206

207

208

235

236

237

238

239

240

229

230

231

232

233

234

197

198

199

200

201

202

190

191

192

193

194

195

196

181

182

183

184

185

186

187

188

189

COM2

COM4

COM6

COM8

COM10

COM12

COM14

COM16

COM18

COM20

COM22

COM24

SEG1

SEG0

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

COM0

COM26

COM28

COM30

COM32

COM34

COM36

COM38

COM40

COM42

COM44

COM46

COM48

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

Pin no.

Pin name

241

242

243

244

245

246

247

248

249

COM50

COM52

COM54

COM56

COM58

COM60

COM62

NC

NC

May 2005 P 44/56 Rev 1.7

SSD1303

SSD1303T6R1 TAB Package Dimensions

SS

D1

30

3T

6

SSD1303

Rev 1.7 P 45/56 May 2005

Solomon Systech

Solomon Systech

May 2005 P 46/56 Rev 1.7

SSD1303

16 SSD1303T8R1 PACKAGE DETAILS

SSD1303T8R1 Pin Assignment

Remark:

Use internal clock

VREF is connected to VCC

Support MCU interface: 8-bit 6800/8080 parallel interface and SPI

VSSB, BGGND are connected to VSS

BS0 is connected to VSS

SSD1303

Rev 1.7 P 47/56 May 2005

Solomon Systech

Table 15 - SSD1303T8R1 pin assignment

170

171

172

173

174

175

176

177

178

179

180

162

163

164

165

166

167

168

169

152

153

154

155

156

157

158

159

160

161

Pin no.

Pin name

121

SEG47

122

123

124

125

SEG48

SEG49

SEG50

SEG51

126

127

128

129

130

131

132

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

NC

NC

NC

NC

NC

NC

NC

NC

COM1

COM3

COM5

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

Pin no.

Pin name

COM8

COM6

COM4

COM2

COM0

NC

NC

NC

NC

NC

NC

NC

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

NC

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

68

69

70

71

72

73

74

75

76

61

62

63

64

65

66

67

86

87

88

89

90

91

82

83

84

85

77

78

79

80

81

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

110

111

112

113

114

115

116

117

118

119

120

102

103

104

105

106

107

108

109

92

93

94

95

96

97

98

99

100

101

Pin no.

Pin name

8

9

10

11

12

13

14

15

16

6

7

4

5

1

2

3

26

27

28

29

30

31

22

23

24

25

17

18

19

20

21

NC

VSS

GDR

VDDB

FB

RESE

VBREF

GP0

GP1

NC

VDD1

BS1

BS2

NC

CS#

RES#

D/C

R/W

E/RD

D0

D1

D2

D3

D4

D5

D6

D7

IREF

VCOMH

VCC

NC

50

51

52

53

54

55

56

57

58

59

60

46

47

48

49

42

43

44

45

32

33

34

35

36

37

38

39

40

41

COM30

COM28

COM26

COM24

COM22

COM20

COM18

COM16

COM14

COM12

COM10

NC

NC

COM62

COM60

COM58

COM56

COM54

COM52

COM50

COM48

COM46

COM44

COM42

COM40

COM38

COM36

COM34

COM32

Solomon Systech

Pin no.

Pin name

188

189

190

191

192

193

194

195

196

181

182

183

184

185

186

187

202

203

204

205

206

207

208

209

210

211

197

198

199

200

201

COM7

COM9

COM11

COM13

COM15

COM17

COM19

COM21

COM23

COM25

COM27

COM29

COM31

COM33

COM35

COM37

COM39

COM41

COM43

COM45

COM47

COM49

COM51

COM53

COM55

COM57

COM59

COM61

COM63

NC

NC

May 2005 P 48/56 Rev 1.7

SSD1303

SSD1303T8R1 TAB Package Dimensions

SSD1303

Rev 1.7 P 49/56 May 2005

Solomon Systech

Solomon Systech

May 2005 P 50/56 Rev 1.7

SSD1303

17 SSD1303T9R1 PACKAGE DETAILS

SSD1303T9R1 Pin Assignment

Figure 16 - SSD1303T9R1 pin assignment (Copper view)

Remark:

Use internal clock

VREF is connected to VCC

Support MCU interface: 8-bit 6800/8080 parallel interface and SPI

VSSB, BGGND are connected to VSS

BS0 is connected to VSS

SSD1303

Rev 1.7 P 51/56 May 2005

Solomon Systech

Table 16 - SSD1303T9R1 pin assignment

Pin

No.

Pin name

1 NC

2 VCC

Pin

No.

Pin name

4 IREF

5 D7

6 D6

7 D5

8 D4

9 D3

10 D2

11 D1

12 D0

13 E

14 R/W

15 D/C

16 RES

17 CS#

18 NC

19 BS2

20 BS1

21 VDD1

22 NC

66 NC

67 NC

68 NC

69 NC

70 NC

71 NC

72 NC

73 NC

Pin

No.

Pin name

Pin

No.

Pin name

26 RESE

27 FB

30 VSS

31 NC

32 NC

33 NC

90 NC

211 NC

42 COM47 102 SEG99 162 SEG39

43 COM45 103 SEG98 163 SEG38

44 COM43 104 SEG97 164 SEG37

45 COM41 105 SEG96 165 SEG36

46 COM39 106 SEG95 166 SEG35

47 COM37 107 SEG94 167 SEG34

48 COM35 108 SEG93 168 SEG33

49 COM33 109 SEG92 169 SEG32

50 COM31 110 SEG91 170 NC

51 COM29 111 SEG90 171 NC

52 COM27 112 SEG89 172 NC

53 COM25 113 SEG88 173 NC

54 COM23 114 SEG87 174 NC

55 COM21 115 SEG86 175 NC

56 COM19 116 SEG85 176 NC

57 COM17 117 SEG84 177 NC

58 COM15 118 SEG83 178 COM0

59 COM13 119 SEG82 179 COM2

60 COM11 120 SEG81 180 COM4

Solomon Systech

May 2005 P 52/56 Rev 1.7

SSD1303

SSD1303T9R1 TAB Package Dimensions

SS

D1

30

3T

9

SSD1303

Rev 1.7 P 53/56 May 2005

Solomon Systech

Solomon Systech

May 2005 P 54/56 Rev 1.7

SSD1303

18 SSD1303Z PACKAGE DETAILS

DIE TRAY DIMENSIONS

SSD1303

Rev 1.7 P 55/56 May 2005

Solomon Systech

Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.

http://www.solomon-systech.com

Solomon Systech

May 2005 P 56/56 Rev 1.7

SSD1303

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