XMC4500 Errata Sheet for Steps ES

XMC4500 Errata Sheet for Steps ES
Errata Sheet
Rel. 1.1, 2014-04
Device
XMC4500
Marking/Step
ES-AC, AC
Package
PG-LQFP-100/144, PG-LFBGA-144
Overview
Document ID is 02916AERRA.
This “Errata Sheet” describes product deviations with respect to the user
documentation listed below.
Table 1
Current User Documentation
Document
Version Date
XMC4500 Reference Manual
V1.4
April 2014
XMC4500 Data Sheet
V1.3
March 2014
Make sure that you always use the latest documentation for this device listed in
category “Documents” at http://www.infineon.com/xmc4000.
Notes
1. The errata described in this sheet apply to all temperature and frequency
versions and to all memory size and configuration variants of affected
devices, unless explicitly noted otherwise.
2. Devices marked with EES or ES are engineering samples which may not be
completely tested in all functional and electrical characteristics, therefore
they must be used for evaluation only. Specific test conditions for EES and
ES are documented in a separate “Status Sheet”, delivered with the device.
3. XMC4000 devices are equipped with an ARM® Cortex™-M4 core. Some of
the errata have a workaround which may be supported by some compiler
tools. In order to make use of the workaround the corresponding compiler
switches may need to be set.
XMC4500, ES-AC, AC
1/66
Subject to Agreement on the Use of Product Information
Rel. 1.1, 2014-04
Errata Sheet
Conventions used in this Document
Each erratum is identified by Module_Marker.TypeNumber:
•
•
•
•
Module: Subsystem, peripheral, or function affected by the erratum.
Marker: Used only by Infineon internal.
Type: type of deviation
– (none): Functional Deviation
– P: Parametric Deviation
– H: Application Hint
– D: Documentation Update
Number: Ascending sequential number. As this sequence is used over
several derivatives, including already solved deviations, gaps inside this
enumeration can occur.
XMC4500, ES-AC, AC
2/66
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Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
1
History List / Change Summary
Table 2
History List
Version
Date
Remark
1.0
2013-08
Initial AC step version. Previous step is AB.
Changes wrt. XMC4500 AB Errata Sheet v1.2:
Added ADC_AI.008, CCU8_AI.004,
CPU_CM.004, DAC_CM.P001, ADC_AI.H003
1.1
2014-04
This Document. For changes see column "Chg"
in the tables below.
Table 3
Errata fixed in this step
Errata
Short Description
ADC_AI.002
Result of Injected Conversion may be wrong Fixed
CCU8_AI.002
CC82 Timer of the CCU8x module cannot
use the external shadow transfer trigger
connected to the POSIFx module
Fixed
PMU_CM.001
Branch from non-cacheable to cacheable
address space instruction may corrupt the
program execution
Fixed
PORTS_CM.002
P0.9 Pull-up permanently active
Fixed
STARTUP_CM.001
CAN Bootstrap Loader
Fixed
Table 4
Change
Functional Deviations
Functional
Deviation
Short Description
Chg Pg
ADC_AI.008
Wait-for-Read condition for register
GLOBRES not detected in continuous
auto-scan sequence
Upd
ate
ADC_TC.064
Effect of conversions in 10-bit fast
compare mode on post-calibration
New 10
XMC4500, ES-AC, AC
3/66
Subject to Agreement on the Use of Product Information
9
Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
Table 4
Functional Deviations (cont’d)
Functional
Deviation
Short Description
CCU4_AI.001
CCU4 period interrupt is not generated in
capture mode
10
CCU8_AI.001
CCU8 Floating Prescaler function does not
work with Capture Trigger 1
12
CCU8_AI.003
CCU8 Parity Checker Interrupt Status is
cleared automatically by hardware
13
CCU8_AI.004
CCU8 output PWM glitch when using low
side modulation via the Multi Channel
Mode
15
CCU_AI.001
CCU4 and CCU8 capture full flags do not
work when module clock is faster than
peripheral bus clock
18
CCU_AI.002
CCU4 and CCU8 Prescaler
synchronization clear does not work when
Module Clock is faster than Peripheral Bus
Clock
20
CCU_AI.003
CCU4 and CCU8 capture full flag is not
cleared if a capture event occurs during a
bus read phase
21
CCU_AI.004
CCU4 and CCU8 Extended Read Back loss
of data
24
CCU_AI.005
CCU4 and CCU8 External IP clock Usage
26
CPU_CM.001
Interrupted loads to SP can cause
erroneous behavior
27
CPU_CM.004
VDIV or VSQRT instructions might not
complete correctly when very short ISRs
are used
29
DAC_CM.001
DAC immediate register read following a
write issue
30
XMC4500, ES-AC, AC
4/66
Subject to Agreement on the Use of Product Information
Chg Pg
Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
Table 4
Functional Deviations (cont’d)
Functional
Deviation
Short Description
DAC_CM.002
No error response for write access to read
only DAC ID register
30
DEBUG_CM.001
OCDS logic in peripherals affected by
TRST
31
DEBUG_CM.002
CoreSight logic only reset after power-on
reset
31
DSD_AI.001
Possible Result Overflow with Certain
Decimation Factors
ETH_AI.001
Incorrect IP Payload Checksum at
incorrect location for IPv6 packets with
Authentication extension header
32
ETH_AI.002
Incorrect IP Payload Checksum Error
status when IPv6 packet with
Authentication extension header is
received
33
ETH_AI.003
Overflow Status bits of Missed Frame and
Buffer Overflow counters get cleared
without a Read operation
34
GPDMA_CM.001
Unexpected Block Complete Interrupt
During Multi-Block Transfers
35
GPDMA_CM.002
GPDMA doesn't Accept Transfer During/In
2nd Cycle of 2-Cycle ERROR Response
37
LEDTS_AI.001
Delay in the update of FNCTL.PADT bit
field
37
PORTS_CM.001
P15_PDISC.[4,5] register bits cannot be
written
42
PORTS_CM.005
Different PORT register reset values after
module reset
43
XMC4500, ES-AC, AC
5/66
Subject to Agreement on the Use of Product Information
Chg Pg
New 32
Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
Table 4
Functional Deviations (cont’d)
Functional
Deviation
Short Description
POSIF_AI.001
Input Index signal from Rotary Encoder is
not decoded when the length is 1/4 of the
tick period
44
RTC_CM.001
RTC event might get lost
46
SCU_CM.002
Missed wake-up event during entering
external hibernate mode
46
SCU_CM.003
The state of HDCR.HIB bit of HCU gets
updated only once in the register mirror
after reset release
47
SCU_CM.006
Deep sleep entry with PLL power-down
option generates SOSCWDGT and
SVCOLCKT trap
47
SCU_CM.015
Parity Memory Test function not usable
New 48
SDMMC_CM.001
Unexpected interrupts after execution of
CMD13 during bus test
48
SDMMC_CM.002
Unexpected Tx complete interrupt during
R1b response
48
USB_CM.002
GAHBCFG.GlblIntrMsk not cleared with a
software reset
49
USB_CM.003
Endpoint NAK not sent in Device Class
applications with multiple endpoints
enabled
USIC_AI.005
Only 7 data bits are generated in IIC mode
when TBUF is loaded in SDA hold time
51
USIC_AI.006
Dual SPI format not supported
51
USIC_AI.007
Protocol-related argument and error bits in
register RBUFSR contain incorrect values
following a received data word
51
USIC_AI.008
SSC delay compensation feature cannot
be used
XMC4500, ES-AC, AC
6/66
Subject to Agreement on the Use of Product Information
Chg Pg
New 50
Upd
ate
53
Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
Table 4
Functional Deviations (cont’d)
Functional
Deviation
Short Description
USIC_AI.009
Baud rate generator interrupt cannot be
used
54
USIC_AI.010
Minimum and maximum supported word
and frame length in multi-IO SSC modes
54
USIC_AI.011
Write to TBUF01 has no effect
55
USIC_AI.013
SCTR register bit fields DSM and HPCDIR
are not shadowed with start of data word
transfer
55
USIC_AI.014
No serial transfer possible while running
capture mode timer
55
USIC_AI.015
Wrong generation of FIFO standard
transmit/receive buffer events when
TBCTR.STBTEN/RBCTR.SRBTEN = 1
56
USIC_AI.016
Transmit parameters are updated during
FIFO buffer bypass
56
USIC_AI.018
Clearing PSR.MSLS bit immediately
deasserts the SELOx output signal
57
USIC_AI.020
Handling unused DOUT lines in multi-IO
SSC mode
Table 5
Chg Pg
New 58
Deviations from Electrical- and Timing Specification
AC/DC Deviation
Short Description
DAC_CM.P001
INL parameter limits violated by some
devices
XMC4500, ES-AC, AC
7/66
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Chg Pg
59
Rel. 1.1, 2014-04
Errata Sheet
History List / Change Summary
Table 6
Application Hints
Hint
Short Description
ADC_AI.H003
Injected conversion may be performed
with sample time of aborted conversion
60
ADC_AI.H004
Completion of Startup Calibration
61
ADC_AI.H008
Injected conversion with broken wire
detection
New 61
ADC_TC.H011
Bit DCMSB in register GLOBCFG
New 62
MultiCAN_AI.H005
TxD Pulse upon short disable request
63
MultiCAN_AI.H006
Time stamp influenced by
resynchronization
63
MultiCAN_AI.H007
Alert Interrupt Behavior in case of BusOff
63
MultiCAN_AI.H008
Effect of CANDIS on SUSACK
64
MultiCAN_TC.H003
Message may be discarded before
transmission in STT mode
64
MultiCAN_TC.H004
Double remote request
65
RESET_CM.H001
Power-On Reset Release
XMC4500, ES-AC, AC
8/66
Subject to Agreement on the Use of Product Information
Chg Pg
Upd
ate
65
Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
2
Functional Deviations
The errata in this section describe deviations from the documented functional
behavior.
ADC_AI.008 Wait-for-Read condition for register GLOBRES not detected
in continuous auto-scan sequence
In the following scenario:
•
•
A continuous auto-scan is performed over several ADC groups and
channels by the Background Scan Source, using the global result register
(GLOBRES) as result target (GxCHCTRy.RESTBS=1B), and
The Wait-for-Read mode for GLOBRES is enabled (GLOBRCR.WFR=1B),
each conversion of the auto-scan sequence has to wait for its start until the
result of the previous conversion has been read out of GLOBRES.
When the last channel of the auto-scan is converted and its result written to
GLOBRES, the auto-scan re-starts with the highest channel number of the
highest ADC group number. But the start of this channel does not wait until the
result of the lowest channel of the previous sequence has been read from
register GLOBRES, i.e. the result of the lowest channel may be lost.
Workaround
If either the last or the first channel in the auto-scan sequence does not write its
result into GLOBRES, but instead into its group result register (selected via bit
GxCHCTRy.RESTBS=0B), then the Wait-for-Read feature for GLOBRES works
correctly for all other channels of the auto-scan sequence.
For this purpose, the auto-scan sequence may be extended by a “dummy”
conversion of group x/ channel y, where the Wait-for-Read mode must not be
selected (GxRCRy.WFR=0B) if the result of this “dummy” conversion is not
read.
XMC4500, ES-AC, AC
9/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
ADC_TC.064 Effect of conversions in 10-bit fast compare mode on postcalibration
The calibrated converters Gx (x = 0..3) support post-calibration. Unless
disabled by software (via bits GLOBCFG.DPCALx = 0), a calibration step is
performed after each conversion, incrementally increasing/decreasing internal
calibration values to compensate process, temperature, and voltage variations.
If a conversion in 10-bit fast-compare mode (bit field CMS/E = 101B in
corresponding Input Class register) is performed between two conversions in
other (non-fast-compare) modes on a converter Gx, the information gained from
the last post-calibration step is disturbed. This will lead to a slightly less
accurate result of the next conversion in a non-fast-compare mode.
Depending on the ratio of conversions in fast-compare mode versus
conversions in other modes, this effect will be more or less obvious.
In a worst case scenario (fast-compare with a constant result injected between
each two normal conversions), all calibration values can drift to their maxima /
minima, causing the converter Gx to deliver considerably inaccurate results.
Workaround
Do not perform conversions using 10-bit fast-compare mode on the calibrated
converters Gx (x = 0..3). Instead, use the uncalibrated converters Gy (y = 4..7)
to perform conversions in fast-compare mode.
CCU4_AI.001 CCU4 period interrupt is not generated in capture mode
The Capture/Compare Unit 4 (CCU4) has several capture modes. These
capture modes are shown in Figure 1.
The depth-2 x2 capture mode enables the usage of two different capture
triggers (Capture Trigger 0 and Capture Trigger 1). Each capture trigger is
linked to two capture registers that work in FIFO mode.
The depth-4 capture mode only has one capture trigger (capture trigger 1). This
capture trigger is then linked with the 4 available capture registers that build the
FIFO structure.
XMC4500, ES-AC, AC
10/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
The period interrupt is not generated when the timer slice is programmed in the
depth-4 capture mode or when is programmed in depth-2 capture mode and the
capture trigger 1 is used.
These situations occur whenever capture trigger 1 is being used (when the
CC4yCMC.CAP1S field is programmed with a value different from 00B).
Note that the period interrupt is only necessary if the capture trigger periodicity
is bigger than the timer period itself.
08.03.2012 - 15.03.2012
Depth-2 FIFO x 2
Capture register 3
Capture register 2
Capture trigger 1
CC4yTIMER
Capture trigger 0
Capture register 1
Capture register 0
a)
08.03.2012 - 15.03.2012
Depth-4 FIFO
CC4yTIMER
Capture register 3
Capture register 2
Capture register 1
Capture register 0
Capture trigger 1
b)
Figure 1
CCU4 capture modes - a) Depth-2 x2 Capture; b) Depth-4
Capture
XMC4500, ES-AC, AC
11/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
Workaround 1
A straightforward workaround is to use only 2 capture registers (instead of a
maximum of 4). This is done by setting the CC4yCMC.CAP1S to 00B and
program the CC4yCMC.CAP0S with a value different from 00B.
Workaround 2
By using the floating prescaler function present in each timer slice, the capture
routine can ignore the missing period interrupt, for a capture trigger frequency
as low as 0.25 Hz (for fCCU equal to 120 MHz).
The floating prescaler function can be enabled by setting the CC4yTC.FPE =
1B.
CCU8_AI.001 CCU8 Floating Prescaler function does not work with Capture Trigger 1
Each CCU8 Timer Slice contains a Floating Prescaler function that allows
capturing the elapsed time between two triggers (with unknown or very high
dynamics), with minimum software interaction Figure 2.
Referring to Figure 2, the time elapsed between the two capture triggers can
be calculated as a dependency between the actual Timer Value plus the
distance between the two capture triggers dictated by the Current Prescaler
Value.
Each CCU8 Timer also has four capture registers: Capture Register 0, Capture
Register 1, Capture Register 2 and Capture Register 3. All these registers can
be used to capture the Timer Value and the Current Prescaler Value.
The usage of Capture Register 2 and Capture Register 3 is not possible when
the Floating Prescaler function is enabled, CC8yTC.FPE = 1B. This only
happens when the Capture Trigger 1 is being used, CC8yCMD.CAP1S != 00B.
Therefore is not possible to use the Floating Prescaler feature with the capture
trigger 1. The usage of the capture trigger 0 is not affected, which means that
capture register 0 and capture register 1 can be used with the floating prescaler
feature.
XMC4500, ES-AC, AC
12/66
Subject to Agreement on the Use of Product Information
Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
Timer clock
Capture Trigger
Capture Trigger
Timer
Period
Match
Increments
prescaler
Prescaler
Value
Initial
Initial + 1
Increments
prescaler
Increments
prescaler
Initial
Initial + 2
Capture
register X
Figure 2
Increments
prescaler
Initial + 1
Initial + 2
Initial
Prescaler Value + Timer Value
Floating Prescaler for Capturing
Workaround
None.
CCU8_AI.003 CCU8 Parity Checker Interrupt Status is cleared automatically by hardware
Each CCU8 Module Timer has an associated interrupt status register. This
Status register, CC8yINTS, keeps the information about which interrupt source
triggered an interrupt. The status of this interrupt source can only be cleared by
software. This is an advantage because the user can configure multiple
interrupt sources to the same interrupt line and in each triggered interrupt
routine, it reads back the status register to know which was the origin of the
interrupt.
Each CCU8 module also contains a function called Parity Checker. This Parity
Checker function, crosschecks the output of a XOR structure versus an input
signal, as seen in Figure 1.
When using the parity checker function, the associated status bitfield, is cleared
automatically by hardware in the next PWM cycle whenever an error is not
present.
This means that if in the previous PWM cycle an error was detected and one
interrupt was triggered, the software needs to read back the status register
before the end of the immediately next PWM cycle.
XMC4500, ES-AC, AC
13/66
Subject to Agreement on the Use of Product Information
Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
This is indeed only necessary if multiple interrupt sources are ORed together in
the same interrupt line. If this is not the case and the parity checker error source
is the only one associated with an interrupt line, then there is no need to read
back the status information. This is due to the fact, that only one action can be
triggered in the software routine, the one linked with the parity checker error.
Selection
GPCHK.PCTS
CCU8x.OUT00
XOR
CCU8x.OUT01
CC80
XOR
CCU8x.OUT02
XOR
CCU8x.OUT03
XOR
CCU8x.OUT10
XOR
CCU8x.OUT11
CC81
XOR
CCU8x.OUT12
XOR
CCU8x.OUT13
XOR
CCU8x.OUT20
XOR
CCU8x.OUT21
CC82
XOR
CCU8x.OUT22
XOR
CCU8x.OUT23
XOR
CCU8x.OUT30
XOR
CCU8x.OUT31
CC83
XOR
CCU8x.OUT32
XOR
CCU8x.OUT33
XOR
Input Signal
Error detection
Logic
Set
Interrupt
Status
Interrupt
GPCHK.PISEL
Figure 3
Parity Checker diagram
Workaround
Not ORing the Parity Checker error interrupt with any other interrupt source.
With this approach, the software does not need to read back the status
information to understand what was the origin of the interrupt - because there
is only one source.
XMC4500, ES-AC, AC
14/66
Subject to Agreement on the Use of Product Information
Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
CCU8_AI.004 CCU8 output PWM glitch when using low side modulation
via the Multi Channel Mode
Each CCU8 Timer Slice can be configured to use the Multi Channel Mode - this
is done by setting the CC8yTC.MCME1 and/or CC8yTC.MCME2 bit fields to 1B.
Each bit field enables the multi channel mode for the associated compare
channel of the CCU8 Timer Slice (each CCU8 Timer Slice has two compare
channels that are able to generate each a complementary pair of PWM
outputs).
After enabled, the Multi Channel mode is then controlled by several input
signals, one signal per output. Whenever an input is active, the specific PWM
output is set to passive level - Figure 1.
The Multi Channel mode is normally used to modulate in parallel several PWM
outputs (a complete CCU8 - up to 16 PWM signals can be modulated in
parallel).
A normal use case is the parallel control of the PWM output for BLDC motor
control. In Figure 2, we can see the Multi Channel Pattern being updated
synchronously to the PWM signals. Whenever a multi channel input is active (in
this case 0), the specific output is set into passive level (the level in which the
external switch is OFF).
XMC4500, ES-AC, AC
15/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
CC8y – Timer Slice y
(output view only)
Compare Channel 1 Path
CCU8x.MCIy[0]
0
CC8yTC.MCME1
CCU8x.MCIy[1]
Multi Channel
mode inputs
for a specific
Timer Slice
CCU8x.OUTy0
Other
sources
1
1
A
N
D
0
CCU8x.OUTy1
Compare Channel 2 Path
CCU8x.MCIy[2]
A
N
D
1
1
0
CC8yTC.MCME2
CCU8x.MCIy[3]
CCU8x.OUTy2
The specific
outputs is set
to passive
whenever
associated
multi channel
input is active
Other
sources
1
1
Figure 4
A
N
D
1
1
0
A
N
D
CCU8x.OUTy3
Multi Channel Mode diagram
CCU8x.OUT00
CCU8x.OUT01
CCU8x.OUT02
CCU8x.OUT03
CCU8x.OUT10
CCU8x.OUT11
Multi channel pattern
Figure 5
011101 b
110101 b
110101b
Multi Channel Mode applied to several CCU8 outputs
XMC4500, ES-AC, AC
16/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
A glitch is present at the PWM outputs whenever the dead time of the specific
compare channel is enabled - CC8yDTC.DTE1 and/or CC8yDTC.DTE2 set to
1B (each compare channel has a separate dead time function) - and the specific
multi channel pattern for the channel is 01B or 10B.
This glitch is not present if the specific timer slice is configure in symmetric edge
aligned mode - CC8yTC.TCM = 0B and CC8yCHC.ASE = 0B.
This glitch only affects the PWM output that is linked to the inverting ST path of
each compare channel (non inverting outputs are not affected).
The effect of this glitch can be seen in Figure 3. The duration of the PWM glitch
has the same length has the dead time value programmed into the
CC8yDC1R.DT1F field (for compare channel 1) or into the CC8yDC1R.DT2F.
CCU8x.OUT00
CCU8x.OUT01
CCU8x.OUT02
CCU8x.OUT03
CCU8x.OUT10
CCU8x.OUT11
Multi channel pattern
Figure 6
011101 b
110101 b
110101b
PWM output glitch
Workaround
To avoid the glitch on the inverting path of the PWM output, one can disable the
dead time function before the Multi Channel Pattern is set to 01B or 10B.
Disabling the dead time of the inverting PWM output can be done by setting:
CC8yDTC.DCEN2 = 0 //if compare channel 1 is being used
XMC4500, ES-AC, AC
17/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
CC8yDTC.DCEN4 = 0 //if compare channel 2 is being used
The dead time needs to be re enabled, before the complementary outputs
become modulated at the same time:
CC8yDTC.DCEN2 = 1 //if compare channel 1 is being used
CC8yDTC.DCEN4 = 1 //if compare channel 2 is being used
CCU_AI.001 CCU4 and CCU8 capture full flags do not work when module
clock is faster than peripheral bus clock
Each CCU4/CCU8 timer slice contains a “Full Flag” field in every capture
register. The structure of the different capture modes for each timer slice can be
seen in Figure 7.
The full flag field serves as an indication to the software (when it is reading back
the specific capture register), for checking whether a new value has been
captured or not into this register, since the previous read back.
When the peripheral bus clock frequency is smaller than the CCU4/CCU8
module clock frequency, fperiph < fccu, the read back of the full flag is inconsistent.
Sometimes it returns the information that a new value has been captured and
sometimes it does not.
Note: The capture interrupt is generated correctly.
XMC4500, ES-AC, AC
18/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
Full Flag
0 – No new value
1 – New value
08.03.2012 - 15.03.2012
Depth-2 FIFO x 2
CCU4/CCU8 is
operating at fCCU
Full Flag
Full Flag
Capture register 3
Capture register 2
SW read at fPERIPH
Capture trigger 1
CC4yTIMER
Capture trigger 0
Capture register 1
Capture register 0
Full Flag
Full Flag
a)
08.03.2012 - 15.03.2012
Depth-4 FIFO
CCU4/CCU8 is
operating at fCCU
SW read at fPERIPH
CC4yTIMER
Capture register 3
Capture register 2
Capture register 1
Capture register 0
Full Flag
Full Flag
Full Flag
Full Flag
Capture trigger 1
b)
Figure 7
Capture Modes Structure - a) Depth-2 x2 Capture; b) Depth-4
Capture
Workaround
When the usage of the FFL field is needed, the module clock of the
CCU4/CCU8 module should be equal to the peripheral bus clock frequency:
fperiph = fccu.
To do this, the following SCU (System Control Unit) registers should be set with
values that force this condition: CCUCLKCR.CCUDIV, CPUCLKCR.CPUDIV
and PBCLKCR.PBDIV.
XMC4500, ES-AC, AC
19/66
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Rel. 1.1, 2014-04
Errata Sheet
Functional Deviations
CCU_AI.002 CCU4 and CCU8 Prescaler synchronization clear does not
work when Module Clock is faster than Peripheral Bus Clock
Each CCU4/CCU8 module contains a feature that allows to clear the prescaler
division counter synchronized with the clear of a run bit of a Timer Slice. This is
configure via the GCTRL.PRBC field. The default value of 000B dictates that
only the software can clear the prescaler internal division counter. Programming
a value different from 000B into the PRBC will impose that the prescaler division
counter is cleared to 0D whenever the selected Timer Slice (selected via the
PRBC field) run bit is cleared (TRB bit field).
In normal operating conditions, clearing the internal prescaler division counter
is not needed. The only situation were a clear of the division may be needed is
when several Timer Slices inside one unit (CCU4/CCU8) are using different
prescaling factors and a realignment of all the timer clocks is needed. This
normally only has a benefit if there is a big difference between the prescaling
values, e.g. Timer Slice 0 using a module clock divided by 2D and Timer Slice 1
using a module clock divided by 1024D.
When the peripheral bus clock frequency is smaller than the CCU4/CCU8
module clock frequency, fperiph < fccu, it is not possible to clear the prescaler
division counter, synchronized with the clear of the run bit of one specific Timer
Slice.
Workaround 1
The clearing of the prescaler internal division counter needs to be done via
software: GCTRL.PRBC programmed with 000B and whenever a clear is
needed, writing 1B into the GIDLS.CPRB bit field.
Workaround 2
When the usage of the Prescaler internal division clear needs to be
synchronized with a timer run bit clear, the module clock of the CCU4/CCU8
should be equal to the peripheral bus clock frequency: fperiph = fccu.
To do this, the following SCU (System Control Unit) registers should be set with
values that force this condition: CCUCLKCR.CCUDIV, CPUCLKCR.CPUDIV
and PBCLKCR.PBDIV.
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Functional Deviations
CCU_AI.003 CCU4 and CCU8 capture full flag is not cleared if a capture
event occurs during a bus read phase
Each CCU4/CCU8 Timer Slice contains a Full Flag field in every capture
register. The structure of the different capture modes for each Timer Slice can
be seen in Figure 8.
The full flag field serves as an indication to the software (when it is reading back
the specific capture register), if a new value has been captured or not into this
register, since the previous read back. (Note that the capture interrupt can still
be generated).
When a capture event collides with a read back on the data bus, the proper data
is read by the software, but this data is shifted to the immediately capture
register and the associated full flag is set, Figure 9 - for simplification purposes
a 2 depth capture scheme is shown.
Referring to Figure 9, it can be understood that the proper data is sent to the
software when it reads back the capture register 1, nevertheless this same data
is shifted to the next capture register (capture register 0) and the full flag of this
register is set.
After this if the software reads back capture register 0, a value is going to be
returned with a full flag set (indicating that this is a new value - that has not yet
been read, which is not true).
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Functional Deviations
Full Flag
0 – No new value
1 – New value
08.03.2012 - 15.03.2012
Depth-2 FIFO x 2
CCU4/CCU8 is
operating at fCCU
Full Flag
Full Flag
Capture register 3
Capture register 2
SW read at fPERIPH
Capture trigger 1
CC4yTIMER
Capture trigger 0
Capture register 1
Capture register 0
Full Flag
Full Flag
a)
08.03.2012 - 15.03.2012
Depth-4 FIFO
CCU4/CCU8 is
operating at fCCU
SW read at fPERIPH
CC4yTIMER
Capture register 3
Capture register 2
Capture register 1
Capture register 0
Full Flag
Full Flag
Full Flag
Full Flag
Capture trigger 1
b)
Figure 8
Capture Modes Structure - a) Depth-2 x2 Capture; b) Depth-4
Capture
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Functional Deviations
Full Flag
Timeframe 0
0 – No new value
1 – New value
24.07.2012 - 31.07.2012
Depth-2 FIFO x 2
Capture register 1
Capture register 0
Full Flag = 1
Full Flag = 0
056FH
Empty
Capture trigger
056FH
Timer
a)
Timeframe 1
24.07.2012 - 31.07.2012
Depth-2 FIFO x 2
Capture register 1
Capture register 0
Full Flag = 1
Full Flag = 1
F960H
056FH
Capture trigger
SW read at fPERIPH from
Capture Register 1
HW returns:
Full Flag = 1 and F960H
F960H
Timer
b)
Figure 9
Capture shift during read back phase - a) Capture trigger
without collision with read back; b) Capture trigger collision
with read back
Workaround 1
If the dynamics of the capture trigger(s) cannot guarantee a safe read back of
the captured data without collision, then the software can monitor if the timer
has rollover or not between two reads.
This can be done by enabling per example by setting the timer mode in Edge
Aligned, TCM = 0B and enabling the Period Interrupt PME = 1B. This interrupt
should then be routed to one of the service request outputs by setting the POSR
field accordingly (e.g. setting POSR = 00B will output the Period Interrupt at the
Service Request Output 0 of CCU4/CCU8).
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Functional Deviations
In every read back where the software finds a value equal to the previous one,
it should then poll the interrupt status to understand if the timer has rollover or
not. If the timer has not rollover, then this is the same value that was previously
read.
Workaround 2
The software reads back in every capture event. This can be done by enabling
the capture interrupt, and in each capture interrupt it reads back a capture
register.
Enabling the capture interrupt is done in the following way: if the capture trigger
is linked to input Event 0, then E0AE needs to be set to 1B; if the capture trigger
is linked to input Event 1, then E1AE needs to be set to 1B; if the capture trigger
is linked to input Event 2, then E2AE needs to be set to 1B.
Routing the interrupt to one of the four available service request outputs: if
Event 0 is being used and the Service Request Output 0 should be used, then
E0SR needs to be set with the value 00B (for Event 1 the field is E1SR and for
Event 2 E2SR).
CCU_AI.004 CCU4 and CCU8 Extended Read Back loss of data
Each CCU4/CCU8 Timer Slice contains a bit field that allows the enabling of the
Extended Read Back feature. This is done by setting the
CC8yTC.ECM/CC4yTC.ECM = 1B. Setting this bit field to 1B only has an impact
if the specific Timer Slice is working in Capture Mode (CC8yCMC.CAP1S or
CC8yCMC.CAP0S different from 00B - same fields for CCU4).
By setting the bit field to ECM = 1B, is then possible to read back the capture
data of the specific Timer Slice (or multiple Timer Slices, if this bit field is set in
more than one Timer Slice) trough a single address. This address is linked to
the ECRD register.
Referring to Figure 10, the hardware every time that the software reads back
from the ECRD address, will return the immediately next capture register that
contains new data. This is done in a circular access, that contains all the capture
registers from the Timer Slices that are working in capture mode.
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Functional Deviations
When using this feature, there is the possibility of losing captured data within a
Timer Slice. The data that is lost is always the last captured data within a timer
slice, e.g (with CCU4 nomenclature - same applies to CCU8):
•
•
•
Timer X has 4 capture registers and is the only Timer set with ECM = 1B. At
the moment that the software starts reading the capture registers via the
ECRD address, we have already capture four values. The ECRD read back
will output CC4xC0V -> CC4xC1V -> CC4xC2V -> CC4xC2V (CC4xC3V
value is lost)
Timer X has 4 capture registers and is the only Timer set with ECM = 1B. At
the moment that the software starts reading the capture registers via the
ECRD address, we have already capture two values. The ECRD read back
will output CC4xC2V -> CC4xC2V (CC4xC3V value is lost)
Timer X and Timer Y have 4 capture registers each and they are both
configured with ECM = 1B. At the moment that the software starts reading
the capture registers via the ECRD address, we have already capture two
values on Timer X and 4 on Timer Y. The ECRD read back will output
CC4xC0V -> CC4xC1V -> CC4xC2V -> CC4xC3V -> CC4yC2V ->
CC4yC2V (CC4yC3V value is lost)
Timer Slice 0
CC40C0V
ptr stays if
full
ptr
CC40C1V
ptr stays if
full
ptr
CC41C1V
ptr stays if
full
ptr
CC42C1V
ptr stays if
full
ptr
CC43C1V
ptr stays if
full
ptr
CC40C2V
ptr stays if
full
ptr
CC41C2V
ptr stays if
full
ptr
CC42C2V
ptr stays if
full
ptr
CC43C2V
ptr stays if
full
ptr
CC40C3V
ptr stays if
full
ptr
CC41C3V
ptr stays if
full
ptr
CC42C3V
ptr stays if
full
ptr
CC43C3V
ptr stays if
full
ptr
Timer Slice 1
CC41C0V
ptr stays if
full
Timer Slice 2
CC42C0V
ptr stays if
full
Timer Slice 3
CC43C0V
ptr stays if
full
ptr
SW reads from ECRD address
and HW goes through all capture
registers (in a circular way) and
returns the capture register that
contains new data
ptr
ptr
Figure 10
Extended Read Back access - example for CCU4 (CCU8
structure is the same)
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Functional Deviations
Workaround
None.
CCU_AI.005 CCU4 and CCU8 External IP clock Usage
Each CCU4/CCU8 module offers the possibility of selecting an external signal
to be used as the master clock for every timer inside the module Figure 1.
External signal in this context is understood as a signal connected to other
module/IP or connected to the device ports.
The user has the possibility after selecting what is the clock for the module
(external signal or the clock provided by the system), to also select if this clock
needs to be divided. The division ratios start from 1 (no frequency division) up
to 32768 (where the selected timer uses a frequency of the selected clock
divided by 32768).
This division is selected by the PSIV field inside of the CC4yPSC/CC8yPSC
register. Notice that each Timer Slice (CC4y/CC8y) have a specific PSIV field,
which means that each timer can operate in a different frequency.
Currently is only possible to use an external signal as Timer Clock when a
division ratio of 2 or higher is selected. When no division is selected (divided by
1), the external signal cannot be used.
The user must program the PSIV field of each Timer Slice with a value different
from 0000B - minimum division value is /2.
This is only applicable if the Module Clock provided by the system (the normal
default configuration and use case scenario) is not being used. In the case that
the normal clock configured and programmed at system level is being used,
there is not any type of constraints.
One should not also confuse the usage of an external signal as clock for the
module with the usage of an external signal for counting. These two features
are completely unrelated and there are not any dependencies between both.
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Functional Deviations
CCU4/CCU8
Module clock
from the system
Module External
Signals
/1
/2
Prescaler
CC40/CC80
...
...
Timer clock
CC4/80PSC.PSIV
/16384
/32768
CC41/CC81
...
Timer clock
CC4/81PSC.PSIV
CC42/CC82
...
Timer clock
CC4/82PSC.PSIV
CC43/CC83
...
Timer clock
CC4/83PSC.PSIV
Figure 11
Clock Selection Diagram for CCU4/CCU8
Workaround
None.
CPU_CM.001 Interrupted loads to SP can cause erroneous behavior
If an interrupt occurs during the data-phase of a single word load to the stackpointer (SP/R13), erroneous behavior can occur. In all cases, returning from the
interrupt will result in the load instruction being executed an additional time. For
all instructions performing an update to the base register, the base register will
be erroneously updated on each execution, resulting in the stack-pointer being
loaded from an incorrect memory location.The affected instructions that can
result in the load transaction being repeated are:
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Functional Deviations
1.
2.
3.
4.
5.
LDR SP,[Rn],#imm
LDR SP,[Rn,#imm]!
LDR SP,[Rn,#imm]
LDR SP,[Rn]
LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from
an incorrect memory address are:
1. LDR SP,[Rn],#imm
2. LDR SP,[Rn,#imm]!
Conditions
1. An LDR is executed, with SP/R13 as the destination
2. The address for the LDR is successfully issued to the memory system
3. An interrupt is taken before the data has been returned and written to the
stack-pointer.
Implications
Unless the load is being performed to Device or Strongly-Ordered memory,
there should be no implications from the repetition of the load. In the unlikely
event that the load is being performed to Device or Strongly-Ordered memory,
the repeated read can result in the final stack-pointer value being different than
had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the
base register value and final stack-pointer value being incorrect. This can result
in apparent stack corruption and subsequent unintended modification of
memory.
Workaround
Both issues may be worked around by replacing the direct load to the stackpointer, with an intermediate load to a general-purpose register followed by a
move to the stack-pointer.
If repeated reads are acceptable, then the base-update issue may be worked
around by performing the stack pointer load without the base increment
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Functional Deviations
followed by a subsequent ADD or SUB instruction to perform the appropriate
update to the base register.
CPU_CM.004 VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used
The VDIV and VSQRT instructions take 14 cycles to execute. When an interrupt
is taken a VDIV or VSQRT instruction is not terminated, and completes its
execution while the interrupt stacking occurs. If lazy context save of floating
point state is enabled then the automatic stacking of the floating point context
does not occur until a floating point instruction is executed inside the interrupt
service routine.
Lazy context save is enabled by default. When it is enabled, the minimum time
for the first instruction in the interrupt service routine to start executing is 12
cycles. In certain timing conditions, and if there is only one or two instructions
inside the interrupt service routine, then the VDIV or VSQRT instruction might
not write its result to the register bank or to the FPSCR.
Conditions
1.
2.
3.
4.
5.
6.
The floating point unit is present and enabled
Lazy context saving is not disabled
A VDIV or VSQRT is executed
The destination register for the VDIV or VSQRT is one of s0 - s15
An interrupt occurs and is taken
The interrupt service routine being executed does not contain a floating
point instruction
7. 14 cycles after the VDIV or VSQRT is executed, an interrupt return is
executed
A minimum of 12 of these 14 cycles are utilized for the context state stacking,
which leaves 2 cycles for instructions inside the interrupt service routine, or 2
wait states applied to the entire stacking sequence (which means that it is not a
constant wait state for every access).In general this means that if the memory
system inserts wait states for stack transactions then this erratum cannot be
observed.
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Functional Deviations
Implications
The VDIV or VQSRT instruction does not complete correctly and the register
bank and FPSCR are not updated, meaning that these registers hold incorrect,
out of date, data.
Workaround
A workaround is only required if the floating point unit is present and enabled.
A workaround is not required if the memory system inserts one or more wait
states to every stack transaction.
There are two workarounds:
1. Disable lazy context save of floating point state by clearing LSPEN to 0 (bit
30 of the FPCCR at address 0xE000EF34).
2. Ensure that every interrupt service routine contains more than 2 instructions
in addition to the exception return instruction.
DAC_CM.001 DAC immediate register read following a write issue
In case a read access to a DAC register is done immediately after a write
access to the same register, the `old` data value is returned, which was stored
before the write access, and not the newly written one.
Workaround
In case of a series of write accesses to DAC registers, repeat the last write
access. In case of a single write access, repeat this one. Then no read access
can fail.
DAC_CM.002 No error response for write access to read only DAC ID register
The DAC ID register is a read only register. But in case a write access is done
to it, no bus error response is returned. The DAC ID register value is kept, as
intended.
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Functional Deviations
Workaround
None.
DEBUG_CM.001 OCDS logic in peripherals affected by TRST
The OCDS logic in peripherals is erroneously reset if TRST is activated.
In the device the OCDS logic in the peripherals is kept in reset and therefore not
available by default (after reset) because P0.8 is configured as TRST and the
internal pull-down is active.
Workaround 1
Connect an external pull-up resistor to P0.8 to drive TRST high (inactive), if
P0.8 is not used by the application.
Workaround 2
During software configuration program P0.8 as GPIO input, This configuration
drives TRST internally to the inactive state.
Note: With this solution the debug functionality remains unavailable right after
reset.
DEBUG_CM.002 CoreSight logic only reset after power-on reset
The CoreSight logic should also be reset with a debug reset (DBGRESET).
Opposed to this specification the debug reset does not have an effect on the
CoreSight logic. Therefore CoreSight logic can only be reset by a power-on
reset (PORESET).
Workaround
If the user quits the debug session and likes to leave the system clean, without
a PORESET, the following steps have to be performed:
•
Disable debug functions by disable of DHCSR.C_DEBUGEN bit in debug
halting and status register.
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Functional Deviations
•
•
Disable HW breakpoints in FPB unit of each comparator by disable of
FP_CTRL.ENABLE bit in flashpatch control register.
Disable trace functions by disable of DEMCR.TRCENA bit in debug
exception and monitor control register. This disables DWT, ITM, ETM and
TPIU functions.
DSD_AI.001 Possible Result Overflow with Certain Decimation Factors
Certain combinations of CIC filter grade and oversampling rate (see below) can
lead to an overflow within the CIC filter. These combinations must be avoided
to ensure proper operation of the digital filter.
Critical combinations:
•
•
•
CIC2 (CFMC/CFAC = 01B) with oversampling rate of 182
CIC3 (CFMC/CFAC = 10B) with oversampling rate of 33, 41, 51, 65, 81, 102,
129, 162…182, 204
CICF (CFMC/CFAC = 11B) with oversampling rate of 129, 182
Note: Filter grade and oversampling rate are defined in register
FCFGCx/FCFGAx. The shown oversampling rates are defined as
CFMDF+1/CFADF+1.
Workaround
None.
ETH_AI.001 Incorrect IP Payload Checksum at incorrect location for IPv6
packets with Authentication extension header
When enabled, the Ethernet MAC computes and inserts the IP header
checksum (IPv4) or TCP, UDP, or ICMP payload checksum in the transmitted
IP datagram (IPv4 or IPv6) on per-packet basis. The Ethernet MAC processes
the IPv6 header and the optional extension headers (if present) to identify the
start of actual TCP, UDP, or ICMP payload for correct computation and
insertion of payload checksum at appropriate location in the packet. The IPv6
header length is fixed (40 bytes) whereas the extension header length is
specified in units of N bytes:
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Functional Deviations
Extension Header Length Field Value x N bytes + 8 bytes
where N = 4 for authentication extension header and N = 8 for all other
extension headers supported by the Ethernet MAC. If the actual payload bytes
are less than the bytes indicated in the Payload Length field of the IP header,
the Ethernet MAC indicates the IP Payload Checksum error.
If the payload checksum is enabled for an IPv6 packet containing the
authentication extension header, then instead of bypassing the payload
checksum insertion, the Ethernet MAC incorrectly processes the packet and
inserts a payload checksum at an incorrect location. As a result, the packet gets
corrupted, and it is dropped at the destination. The software should not enable
the payload checksum insertion for such packets because the Integrity Check
Value (ICV) in the authentication extension header is calculated and inserted
considering that the payload data is immutable (not modified) in transit.
Therefore, even if the payload checksum is correctly calculated and inserted, it
results into a failure of the ICV check at the final destination and the packet is
eventually dropped.
Workaround
The software should not enable the IP payload checksum insertion by the
Ethernet MAC for Tx IPv6 packets with authentication extension headers. The
software can compute and insert the IP payload checksum for such packets.
ETH_AI.002 Incorrect IP Payload Checksum Error status when IPv6 packet with Authentication extension header is received
The Ethernet MAC processes a TCP, UDP, or ICMP payload in the received IP
datagrams (IPv4 or IPv6) and checks whether the received checksum field
matches the computed value. The result of this operation is given as an IP
Payload Checksum Error in the receive status word. This status bit is also set if
the length of the TCP, UDP, or ICMP payload does not match the expected
payload length given in the IP header.
In IPv6 packets, there can be optional extension headers before actual TCP,
UDP, or ICMP payload. To compute and compare the payload checksum for
such packets, the Ethernet MAC sequentially parses the extension headers,
determines the extension header length, and identifies the start of actual TCP,
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Functional Deviations
UDP, or ICMP payload. The header length of all extension headers supported
by the Ethernet MAC is specified in units of 8 bytes (Extension Header Length
Field Value x 8 bytes + 8 bytes) except in the case of authentication extension
header. For authentication extension header, the header length is specified in
units of 4 bytes (Extension Header Length Field Value x 4 bytes + 8 bytes).
However, because of this defect, the Ethernet MAC incorrectly interprets the
size of the authentication extension header in units of 8 bytes, because of which
the following happens:
•
•
•
•
Incorrect identification of the start of actual TCP, UDP, or ICMP payload
Computing of incorrect payload checksum
Comparison with incorrect payload checksum field in the received IPv6
frame that contains the authentication extension header
Incorrect IP Payload Checksum Error status
As a result, the IP Payload checksum error status is generated for proper IPv6
packets with authentication extension header. If the Ethernet MAC core is
programmed to drop such `error` packets, such packets are not forwarded to
the host software stack.
Workaround
Disable dropping of TCP/IP Checksum Error Frames by setting Bit 26 (DT) in
the Operation Mode Register (OPERATION_MODE). This enables the Ethernet
MAC core to forward all packets with IP checksum error to the software driver.
The software driver must process all such IPv6 packets that have payload
checksum error status and check whether they contain the authentication
extension header. If authentication extension header is present, the software
driver should either check the payload checksum or inform the upper software
stack to check the packet for payload checksum.
ETH_AI.003 Overflow Status bits of Missed Frame and Buffer Overflow
counters get cleared without a Read operation
The DMA maintains two counters to track the number of frames missed
because of the following:
•
Rx Descriptor not being available
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Functional Deviations
•
Rx FIFO overflow during reception
The Missed Frame and Buffer Overflow Counter register indicates the current
value of the missed frames and FIFO overflow frame counters. This register
also has the Overflow status bits (Bit 16 and Bit 28) which indicate whether the
rollover occurred for respective counter. These bits are set when respective
counter rolls over. These bits should remain high until this register is read.
However, erroneously, when the counter rollover occurs second time after the
status bit is set, the respective status bit is reset to zero.
Effects
The application may incorrectly detect that the rollover did not occur since the
last read operation.
Workaround
The application should read the Missed Frame and Buffer Overflow Counter
register periodically (or after the Overflow or Rollover status bits are set) such
that the counter rollover does not occur twice between read operations.
GPDMA_CM.001
Block Transfers
Unexpected Block Complete Interrupt During Multi-
The GPMDA allows an interrupt to be generated on completion of a DMA block
transfer to the destination. This interrupt is generated if the INT_EN (CTLx[0])
bit is set. On a channel enabled for multi-block transfers, the CTLx register is
reprogrammed using either of the following methods:
•
•
Block chaining using linked lists
Auto-reloading
When CTLx is re-programmed using block-chaining of linked lists, interrupts
can be enabled or disabled seperately for each block in the transfer. The block
interrupt is generated from a combinational logic, which is coded such that, for
a particular channel, if the 'RawBlock' register bit is set and the rawblock
interrupt is unmasked, an interrupt is triggered soon as the INT_EN (CTLx[0])
bit is written as `1`, as shown in the equation below:
block_int = rawblock & (!maskblock) & int_en ;
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Functional Deviations
This can cause a false block interrupt to be generated in multi-block transfers.
Conditions
1. Consider a multi-block transfer of three blocks(LLI0, LLI1, LLI2) on
channelX, where SARx, DARx, CTLx are all re-programmed using linked
lists.
2. For the first block, interrupts are not enabled; that is, LLI0.CTLx[0] = 0. For
the second and third blocks, interrupts are enabled; that is, LLI1.CTLx[0] =
1, LLI2.CTLx[0] = 1.
3. Block interrupt for channel x is unmasked by writing to MaskBlock register.
4. After the first block transfer completes, the rawblock bit is set to 1; that is,
RawBlock[0] = 1. At this point, no interrupt is generated because, for this
block, int_en = 0; that is, LLI0.CTLx[0] = 0 ).
5. An LLI update occurs for the next block transfer, and SARx, DARx, and
CTLx are re-programmed with the contents of LLI1.SARx, LL1.DARx, and
LLI1.CTLx, respectively.
6. Since the RawBlock register has not been cleared by software after the first
block completion, RawBlock[0] is still set to 1.
7. Because LLI1.CTLx[0] = 1, the int_en bit is set to `1` as soon as CTLx is
updated with the contents of LLI1.CTLx[0]. This triggers a false Block
Complete Interrupt at this point.
Implications
Unexpected Block Complete Interrupt can occur during Multi-Block Transfers.
Workaround
The software knows which blocks of the multi-block transfer are interruptenabled. Based on this, code the Interrupt Service Routine such that it keeps a
count of the interrupts. It can then ignore the unwanted interrupts and service
only the expected interrupts.In the example above, the software expects block
interrupts only for LLI1 and LLI2, but not for LLI0. So the ISR can be coded to
ignore the first interrupt and service the next two interrupts, as shown in the
psuedo code below:
ISR :
blk_flag++
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Functional Deviations
If(blk_flag==1)
{
clear_block_interrupt
exit
} else {
// do normal operation;
}
GPDMA_CM.002 GPDMA doesn't Accept Transfer During/In 2nd Cycle of
2-Cycle ERROR Response
In the GPDMA, the slave bus interface unit is coded such that, after the second
cycle of a two-cycle error response, the logic transitions the state machine to
the IDLE state and hence does not accept any transfer issued during the
second cycle of the two-cycle error response.
Workaround
•
•
Write software to not perform any actions that cause GPDMA to generate
an error response.
Ensure that any master that communicates to the GPDMA does not issue a
transfer in the second cycle of a two-cycle error response.
LEDTS_AI.001 Delay in the update of FNCTL.PADT bit field
The touch-sense pad turn (PADT) value is updated, not at the end of the touchsense time slice (ColA), but one time slice later (Figure 12).
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Functional Deviations
Time Frame
Active Column
ColA
Current PADT update behavior
Expected PADT update behavior
Figure 12
LED slice
LED slice
Touch‐sense slice
Col1
Col0
ColA
0
0
Col1
Col0
ColA
1
1
Col1
Col0
2
2
3
3
PADT update behavior
If the number of LED columns enabled is smaller than 2, the delay will affect the
activation period of the current active pad. At the beginning of every new Col A,
the value of the current PADT’s compare register is updated to the internal
compare register. However, the delay causes the value of the previous PADT’s
compare register is updated to the internal compare register instead. This
means that the current active pad would be activated with the duration of the
previous pad’s oscillation window (Figure 13). In addition to this, when no LEDs
are enabled, pad turn 0 will prevail for one time slice longer before it gets
updated (Figure 14).
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Functional Deviations
Time Frame
Active Column
Current PADT update behavior
Internal Compare Register
Figure 13
LED slice
Touch‐sense slice
Col0
ColA
0
Col0
ColA
1
Col0
ColA
2
Col0
ColA
3
Col0
4
CMP_LD0 CMP_TS0 CMP_LD0 CMP_TS1 CMP_LD0 CMP_TS2 CMP_LD0 CMP_TS3 CMP_LD0
Effect of delay on the update of Internal Compare Register
with 1 LED column enabled
Touch‐sense slice = Time frame
Active Column
Current PADT update behavior
Internal Compare Register
Figure 14
ColA
ColA
0
ColA
ColA
ColA
ColA
ColA
ColA
ColA
1
2
3
4
5
6
7
CMP_TS0 CMP_TS1 CMP_TS2 CMP_TS3 CMP_TS4 CMP_TS5 CMP_TS6 CMP_TS7 CMP_TS0
Pad turn 0 prevails for one time slice longer when no LEDs are
enabled
If the number of LED columns enabled is 2 or more, the additional LED columns
would provide some buffer time for the delay. So, at the start of a new touchsense time slice, the update of PADT value would have taken place. Hence, the
current active PADT compare register value is updated to the internal compare
register (Figure 15).
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Functional Deviations
Time Frame
Active Column
ColA
Current PADT update behavior
Internal Compare Register
Figure 15
LED slice
LED slice
Touch‐sense slice
Col1
Col0
ColA
0
Col1
Col0
1
ColA
2
Col1
Col0
3
CMP_TS0 CMP_LD1 CMP_LD0 CMP_TS1 CMP_LD1 CMP_LD0 CMP_TS2 CMP_LD1 CMP_LD0
Internal Compare Register updated with correct compare
register value with 2 LED columns enabled
Conditions
This delay in PADT update can be seen in cases where hardware pad turn
control mode (FNCTL.PADTSW = 0) is selected and the touch-sense function
is enabled (GLOBCTL.TS_EN = 1).
Workaround
This section is divided to two parts. The first part will provide a guide on reading
the value of the bit field FNCTL.PADT via software. The second part will provide
some workarounds for ensuring that the CMP_TS[x] values are aligned to the
current active pad turn.
Workaround for reading PADT
Due to the delay in the PADT update, the user would get the current active pad
turn when PADT is read in the time frame interrupt. However, this PADT value
read differs when read in a time slice interrupt. This depends on the number of
LED columns enabled and the active function or LED column in the previous
time slice (Table 7). The bit field FNCTL.FNCOL provides a way of interpreting
the active function or LED column in the previous time slice.
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Functional Deviations
Table 7
PADT value as read in the time slice interrupt
No. of LED
Columns
Enabled
Previous active
function / LED
column
FNCTL.FNCOL
PADT value
0-1
Touch-sense or
LED Col0
110B or 111B
Previous active pad
turn
2-7
Touch-sense or 110B or 111B
first LED column
after touch-sense
Previous active pad
turn
101B to 000B
Second LED
column after
touch-sense
onwards
Current or next
active pad turn
Workaround for aligning CMP_TSx
One workaround is to use the software pad turn control. Then this issue can be
avoided entirely because the pad turn update will have to be handled by
software.
However, it is still possible to work around this issue when using the hardware
pad turn control. In the previous section, it is known that when the number of
LED columns enabled is smaller than 2, the current active pad is activated with
the oscillation window of the previous active pad. This means that the current
active pad is activated with the value programmed in the bit field CMP_TS[x-1]
instead of CMP_TS[x]. There are two possible software workarounds for this
issue:
1. At the end of the time frame interrupt service routine, software can prepare
for the next active pad turn by programming the CMP_TS[x-1] bit field with
the intended compare value for TSIN[x]. As an example, if the next active
pad is TSIN[2], program CMP_TS[1] with the compare value intended for
TSIN[2] (Figure 16).
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Functional Deviations
Time Frame
Active Column
Col0
PADT value read
Figure 16
0
ColA
Col0
ColA
Col0
ColA
Col0
ColA
Col0
1
2
3
4
Time Frame Interrupt
Next active pad = TSIN[2]
Program CMP_TS1 with value intended for TSIN[2]
Time Frame Interrupt
Next active pad = TSIN[3]
Program CMP_TS2 with value intended for TSIN[3]
Time Frame Interrupt
Next active pad = TSIN[4]
Program CMP_TS3 with value intended for TSIN[4]
Time Frame Interrupt
Next active pad = TSIN[5]
Program CMP_TS4 with value intended for TSIN[5]
Software workaround demonstration
1. During the initialization phase, program the CMP_TS[x] bit fields with the
left-shift factored in. Example: CMP_TS[0] for TSIN[1], CMP_TS[1] for
TSIN[2], ... CMP[7] for TSIN[0].
PORTS_CM.001 P15_PDISC.[4,5] register bits cannot be written
The bits 4 and 5 of the register P15_PDISC cannot be modified by software and
always retain their reset value 0B. As a result of this, the digital input path of the
related shared analog and digital input pins cannot be disabled.
Implications
Software that sets one or both of these bits and later reads P15_PDISC will not
see the expected read value, but always reads 0B for P15_PDISC.[4,5].
Software that reads P15_IN will read undefined values for P15_IN[4,5]. The
read values depend on the analog input level of the respective pin.
Workaround
None.
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Functional Deviations
PORTS_CM.005 Different PORT register reset values after module reset
The PORTS registers can be reset independent of the reset of the system with
SCU_PRSET1.PPORTSRS. After such a module reset, some PORTS registers
have a reset value different to the reset value that is documented in the
Reference Manual.
Table 8
PORTS registers reset values
Register
Sytem reset value
Module reset value
Pn_IOCR8
0000 0000H
2020 2020H1)
2)
Pn_PDISC
XXXX XXXXH
0000 0000H
Pn_PDR0
2222 2222H
0000 0000H
Pn_PDR1
2222 2222H
0000 0000H
1) Only in XMC4500 devices.
2) Device and package dependent
Implications
The different value in Pn_IOCR8 configures the respective port pins Pn.[11:8]
as inverted inputs instead of direct inputs. User software in Priviledged Mode
can reconfigure them as needed by the application.
With the different value in Pn_PDISC of the digital ports the availability of digital
pins in a device can no longer be verified via this register. Note that Pn_PDISC
of pure digital ports is read-only; user software can’t write to them.
The Pn_PDISC of the shared analog/digital port pins (P14 and P15)
enables/disables the digital input path. After a system reset this path is
disabled, after a module reset enabled. User software in Priviledged Mode can
reconfigure them as needed by the application.
The different value in the Pn_PDR registers configures output port pins with a
“Strong-Sharp” output driver mode, as opposed to “Strong-Soft” driver mode
after a system reset. This may result in a higher current consumption and more
noise induced to the external system. User software in Priviledged Mode can
reconfigure them as needed by the application.
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Functional Deviations
Workaround
None.
POSIF_AI.001 Input Index signal from Rotary Encoder is not decoded
when the length is 1/4 of the tick period
Each POSIF module can be used as an input interface for a Rotary Encoder. It
is possible to configure the POSIF module to decode 3 different signals: Phase
A, Phase B (these two signals are 90° out of phase) and Index. The index signal
is normally understood as the marker for the zero position of the motor Figure 1.
phase A
phase A
phase B
phase B
Index/
marker
Index/
marker
Figure 17
Rotary Encoder outputs - Phase A, Phase B and Index
There are several types of Rotary Encoder when it comes to length of the index
signal:
•
•
•
length equal or bigger than 1 tick period
length equal or bigger than 1/2 tick period
length equal or bigger than 1/4 tick period
When the index signal is smaller than 1/2 of the tick period, the POSIF module
is not able to decode this signal properly, Figure 2 - notice that the reference
edge of the index generation in this figure is the falling of Phase B, nevertheless
this is an example and depending on the encoder type, this edge may be one
of the other three.
Due to this fact it is not possible to use the POSIF to decode these type of
signals (index with duration below 1/2 of the tick period).
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Functional Deviations
Tick period (Tp)
Phase A
Phase B
Index
T i < ½ Tp
Figure 18
Different index signal types
Workaround
To make usage of the Index signal, when the length of this signal is less than
1/2 of the tick period, one should connect it directly to the specific counter/timer.
This connection should be done at port level of the device (e.g. connecting the
device port to the specific Timer/Counter(s)), Figure 3.
Phase A
Up or dow count
Phase B
POSIF
Index
CCU4
Timer/
counter
Index
a)
Phase A
Up or dow count
Phase B
POSIF
CCU4
Timer/
counter
Index
b)
Figure 19
Index usage workaround - a) Non working solution; b)
Working solution
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Functional Deviations
RTC_CM.001 RTC event might get lost
RTC interrupt may get cleared in the RTC module before propagated to the
CPU interrupt controller.
Single-shot RTC alarm may be missed. Periodic alarm events may be missed
at the rate of once in 15 seconds.
Implications
RTC alarm interrupt alone cannot be reliably used for critical control functions.
Note: Wake-up from hibernate mode is not affected and RTC timer value is
always correct.
Workaround
While in active mode use alternate timer for periodic event trigger and/or read
the RTC timer value periodically.
SCU_CM.002 Missed wake-up event during entering external hibernate
mode
Single-shot wake-up event and/or the first occurrence of a periodic wake-up
event from hibernate mode may be missed if it occurs within 200 microseconds
after hibernate mode request issued in software.
A wake-up event may be missed if it gets triggered during the process of
entering hibernate mode i.e. between software access to the hibernate control
register and the moment hibernate mode is effectively entered.
Implications
While entering hibernate mode it is required that expected wake-up event will
not occur in the next 200 microseconds which not always may be guaranteed if
external wake-up source is considered.
Workaround
Use of a backup wake-up event source generated internally with RTC may be
applied in order to compensate for the missing trigger after a defined time-out.
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Functional Deviations
SCU_CM.003 The state of HDCR.HIB bit of HCU gets updated only once
in the register mirror after reset release
The state of HDCR.HIB bit of HCU gets updated only once in the register mirror
in SCU after system reset. Any write access to this register gets propagated to
hibernate domain but it will be not propagated back to the register mirror when
altered by the hardware inside of the hibernate domain.
Implications
The state of HDCR.HIB cannot be effectively used for the purpose debugging
of hibernate mode control software.
Workaround
For debugging of the hibernate mode control software observe the electrical
states on the hibernate control pins in order to verify hibernate control circuit
behavior.
SCU_CM.006 Deep sleep entry with PLL power-down option generates
SOSCWDGT and SVCOLCKT trap
Entering the deep sleep mode with PLL power-down option (selected in
DSLEEPCR register of SCU module) may result with system traps triggered by
PLL watchdog (the SOSCWDGT trap) and/or loss-of-lock (the SVCOLCKT
trap).
Implications
Occurrence of one of the enabled traps will result in an immediate wake-up from
the deep sleep state, i.e. the deep sleep is effectively not entered.
Workaround
Disable SOSCWDGT and SVCOLCKT trap generation in TRAPDIS register of
SCU before entering deep sleep mode with PLL power-down option selected.
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Functional Deviations
SCU_CM.015 Parity Memory Test function not usable
The device provides an interface to access the parity bits of the contained
memories. The interface is based on using SCU registers PMTPR and PMTSR.
Due to synchronization issues wrong results will be produced.
Implications
The Parity Memory Test function is not usable.
Workaround
None.
SDMMC_CM.001 Unexpected interrupts after execution of CMD13 during
bus test
This issue affects eMMC cards only.
The conditions for this behavior are as follows (all 2 conditions must be
true):
•
•
The host sends CMD19 (bus test pattern to a card), and driver issues
CMD13 (SEND_STATUS command) to read the card status
The transmit FSM is in Tx data state during bus testing procedure
The
host
controller
may
assert
data
timeout
error
SDMMC_INT_STATUS_ERR.DATA_TIMEOUT_ERR. As a consequence,
unexpected interrupts may be generated.
Workaround
User should avoid sending CMD13 when bus testing is in progress.
SDMMC_CM.002 Unexpected Tx complete interrupt during R1b response
This issue affects both SD and eMMC cards.
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Functional Deviations
R1b is a response type with an optional busy indication on the data line DAT[0].
SD and eMMC cards may send a busy response for the following commands:
Table 9
SD Commands with R1b response
CMD INDEX
Response Type Abbreviation
CMD12
R1b
STOP_TRANSMISSION
CMD28
R1b
SET_WRITE_PROT
CMD29
R1b
CLR_WRITE_PROT
CMD38
R1b
ERASE
Table 10
eMMC Commands with R1b response
CMD INDEX
Response Type Abbreviation
CMD5
R1b
SLEEP_AWAKE
CMD6
R1b
SWITCH
CMD12
R1b
STOP_TRANSMISSION
CMD28
R1b
SET_WRITE_PROT
CMD29
R1b
CLR_WRITE_PROT
CMD38
R1b
ERASE
When the card is in busy state for R1b, and driver sends the SEND_STATUS
command (CMD13) to read the card status. Due to this CMD13, unexpected
transfer complete interrupt SDMMC_INT_STATUS_NORM.TX_COMPLETE
may be asserted by the host controller even before the busy signal gets
released by the card.
Workaround
User should avoid sending CMD13 while the card is in busy state for R1b.
USB_CM.002 GAHBCFG.GlblIntrMsk not cleared with a software reset
When the application issues a software reset to the core through the
GRSTCTL.CSftRst bit, the GAHBCFG.GlblIntrMsk bit is not reset to 0.
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Functional Deviations
Therefore, an interrupt will be generated in case any of the individual interrupt
mask bit (in GINTMSK) is unmasked after the software reset by the application.
Workaround
The workaround is to clear GAHBCFG.GlblIntrMsk to 0 immediately after
GRSTCTL.CSftRst is programmed for software reset.
USB_CM.003 Endpoint NAK not sent in Device Class applications with
multiple endpoints enabled
In device descriptor DMA mode, the USB 2.0 OTG core does not send NAK
handshake for all OUT endpoints once the transfer is complete.
This can be a problem for an application with high latency if it cannot re-enable
the endpoint after the transfer is completed on the OUT endpoint.
If the host sends further OUT tokens when the endpoint is disabled, this packet
blocks the RxFIFO till the application re-enables the endpoint to read out the
packet. Blocking the RxFIFO results in all the other OUT endpoints not
receiving any further data. Eventually, the RxFIFO becomes full.
Implications
The bug affects Communication Device Class (AMC) applications (e.g.
Ethernet over USB) where multiple endpoints are enabled. When using the
recommended Infineon USB device software stacks, the issue will be handled
and no further workaround is needed.
Workaround
The application needs to set MTRF=1 for the OUT endpoints. This ensures that
the OUT endpoints do not get disabled and hence the RxFIFO blocking
limitation is not seen.
When MTRF=1, in order to ensure that there is no BNA (Buffer Not Available)
scenario, the application needs to set a long descriptor chain for the OUT
endpoints. When MTRF=1, the OUT EP is not disabled and the application and
the core share the same descriptor chain simultaneously.
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Functional Deviations
USIC_AI.005 Only 7 data bits are generated in IIC mode when TBUF is
loaded in SDA hold time
When the delay time counter is used to delay the data line SDA (HDEL > 0), and
the empty transmit buffer TBUF was loaded between the end of the
acknowledge bit and the expiration of programmed delay time HDEL, only 7 data
bits are transmitted.
With setting HDEL=0 the delay time will be tHDEL = 4 x 1/fSYS + delay
(approximately 60ns @ 80MHz).
Workaround
•
•
Do not use the delay time counter, i.e use only HDEL=0 (default),
or
write TBUF before the end of the last transmission (end of the acknowledge
bit) is reached.
USIC_AI.006 Dual SPI format not supported
Dual SPI format is not supported in SSC mode. Therefore, user should always
configure either the standard SPI or Quad SPI format in this mode.
Workaround
None.
USIC_AI.007 Protocol-related argument and error bits in register RBUFSR contain incorrect values following a received data word
The protocol-related argument and error bits (PAR and PERR respectively) in
register RBUFSR contain incorrect values following a received data word. This
leads to the following errors:
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Functional Deviations
Table 11
Protocol Error due to incorrect PAR and PERR values
ASC
•
•
SSC
•
•
Received parity bit (RBUFSR.PAR) and result of the parity
check (RBUFSR.PERR) are incorrect.
When a data word is received, an alternate receive event
(PSR.AIF) may be indicated instead of a receive event
(PSR.RIF) even though parity mode is disabled.
Received parity bit (RBUFSR.PAR) and result of parity check
(PSR.PAERR) are incorrect.
The first data word of a frame may be indicated by a receive
event (PSR.RIF) instead of an alternate receive event
(PSR.AIF). Similarly, a data word that is not the first word of a
frame may be indicated by PSR.AIF instead of PSR.RIF.
IIC
•
•
Received acknowledge bit in RBUFSR.PAR is incorrect.
The first data word of a frame may be indicated by a receive
event (PSR.RIF) instead of an alternate receive event
(PSR.AIF). Similarly, a data word that is not the first word of a
frame may be indicated by PSR.AIF instead of PSR.RIF.
IIS
•
Sampling of condition WA = 1 may be indicated by a receive
event (PSR.RIF) instead of an alternate receive event
(PSR.AIF). Similarly, sampling of condition WA = 0 may be
indicated by PSR.AIF instead of PSR.RIF.
Workaround
The workarounds are summarized below:
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Functional Deviations
Table 12
Protocol Workaround
ASC
•
•
Parity mode cannot be used.
To check if a data word is received, both PSR.RIF and PSR.AIF
flags need to be monitored. If interrupts are used, interrupt
service handlers need to be set up for both interrupt sources.
SSC
•
•
Parity mode cannot be used.
To check if a data word is received, both PSR.RIF and PSR.AIF
flags need to be monitored. If interrupts are used, interrupt
service handlers need to be set up for both interrupt sources.
To check if a data word is the first data word of a frame, the bit
RBUFSR.SOF can be used.
•
IIC
•
•
•
IIS
•
•
To check for the acknowledge bit, bit 8 of the receive buffer
RBUF can be used.
To check if a data word is received, both PSR.RIF and PSR.AIF
flags need to be monitored. If interrupts are used, interrupt
service handlers need to be set up for both interrupt sources.
To check if a data word is the first data word of a frame, bit 9 of
RBUF can be used.
To check if a data word is received, both PSR.RIF and PSR.AIF
flags need to be monitored. If interrupts are used, interrupt
service handlers need to be set up for both interrupt sources.
To check the sampled value of WA, the bit PSR.WA can be
used.
USIC_AI.008 SSC delay compensation feature cannot be used
SSC master mode and complete closed loop delay compensation cannot be
used. The bit DX1CR.DCEN should always be written with zero to disable the
delay compensation.
Workaround
None.
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Functional Deviations
USIC_AI.009 Baud rate generator interrupt cannot be used
The baud rate generator interrupt cannot be used. The bit CCR.BRGIEN must
always be written with zero to disable baud rate generator interrupt generation.
Workaround
None.
USIC_AI.010 Minimum and maximum supported word and frame length in
multi-IO SSC modes
The minimum and maximum supported word and frame length in multi-IO SSC
modes are shown in the table below:
Table 13
Multi-IO SSC Modes Word Length (bits)
Minimum
Frame Length (bits)
Maximum
Minimum
Maximum
Dual-SSC
4
16
4
64
Quad-SSC
8
16
8
64
Workaround
If a frame length greater than 64 data bits is required, the generation of the
master slave select signal by SSC should be disabled by PCR.MSLSEN.
To generate the master slave select signal:
•
•
Configure the same pin (containing the SELOx function) to general purpose
output function instead by writing 10000B to the pin’s input/output control
register (Pn_IOCRx.PCy); and
Use software to control the output level to emulate the master slave select
signal
This way, multiple frames of 64 data bits can be made to appear as a single
much larger frame.
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Functional Deviations
USIC_AI.011 Write to TBUF01 has no effect
Writing data to Transmit Buffer Input Location 01 (register TBUF01 at offset
address 084H) does not load the data to the transmit buffer (TBUF).
Workaround
Use registers TBUF00 or TBUFx (x = 02 to 31) to load data to the transmit
buffer.
If the Transmit Control Information (TCI) value of 00001B needs to be generated
together with the load to TBUF, use a FIFO setup and Transmit FIFO Buffer
Input location 01 (register IN01 at offset address 184H) instead.
USIC_AI.013 SCTR register bit fields DSM and HPCDIR are not shadowed
with start of data word transfer
The bit fields DSM and HPCDIR in register SCTR are not shadowed with the
start of a data word transfer.
Workaround
If the transfer parameters controlled by these bit fields need to be changed for
the next data word, they should be updated only after the current data word
transfer is completed, as indicated by the transmit shift interrupt PSR.TSIF.
USIC_AI.014 No serial transfer possible while running capture mode timer
When the capture mode timer of the baud rate generator is enabled
(BRG.TMEN = 1) to perform timing measurements, no serial transmission or
reception can take place.
Workaround
None.
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Functional Deviations
USIC_AI.015 Wrong generation of FIFO standard transmit/receive buffer
events when TBCTR.STBTEN/RBCTR.SRBTEN = 1
Transmit FIFO buffer modes selected by TBCTR.STBTEN = 1 generates a
standard transmit buffer event whenever TBUF is loaded with the FIFO data or
there is a write to INxx register, except when TRBSR.TBFLVL = TBCTR.LIMIT.
This is independent of TBCTR.LOF setting.
Similarly, receive FIFO buffer modes selected by RBCTR.SRBTEN = 1
generates a standard receive buffer event whenever data is read out from FIFO
or received into the FIFO, except when TRBSR.RBFLVL = RBCTR.LIMIT. This
is independent of RBCTR.LOF setting.
Both cases result in the wrong generation of the standard transmit and receive
buffer events and interrupts, if interrupts are enabled.
Workaround
Use only the modes with TBCTR.STBTEN and RBCTR.SRBTEN = 0.
USIC_AI.016 Transmit parameters are updated during FIFO buffer bypass
Transmit Control Information (TCI) can be transferred from the bypass structure
to the USIC channel when a bypass data is loaded into TBUF. Depending on
the setting of TCSR register bit fields, different transmit parameters are updated
by TCI:
•
•
•
•
•
When SELMD = 1, PCR.CTR[20:16] is updated by BYPCR.SELO
(applicable only in SSC mode)
When WLEMD = 1, SCTR.WLE and TCSR.EOF are updated by
BYPCR.BWLE
When FLEMD = 1, SCTR.FLE[4:0] is updated by BYPCR.BWLE
When HPCMD = 1, SCTR.HPCDIR and SCTR.DSM are updated by BHPC
When all of the xxMD bits are 0, no transmit parameters will be updated
However in the current device, independent of the xxMD bits setting, the
following are always updated by the TCI generated by the bypass structure,
when TBUF is loaded with a bypass data:
•
WLE, HPCDIR and DSM bits in SCTR register
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Errata Sheet
Functional Deviations
•
•
EOF and SOF bits in TCSR register
PCR.CTR[20:16] (applicable only in SSC mode)
Workaround
The application must take into consideration the above behaviour when using
FIFO buffer bypass.
USIC_AI.018 Clearing PSR.MSLS bit immediately deasserts the SELOx
output signal
In SSC master mode, the transmission of a data frame can be stopped explicitly
by clearing bit PSR.MSLS, which is achieved by writing a 1 to the related bit
position in register PSCR.
This write action immediately clears bit PSR.MSLS and will deassert the slave
select output signal SELOx after finishing a currently running word transfer and
respecting the slave select trailing delay (Ttd) and next-frame delay (Tnf).
However in the current implementation, the running word transfer will also be
immediately stopped and the SELOx deasserted following the slave select
delays.
If the write to register PSCR occurs during the duration of the slave select
leading delay (Tld) before the start of a new word transmission, no data will be
transmitted and the SELOx gets deasserted following Ttd and Tnf.
Workaround
There are two possible workarounds:
•
•
Use alternative end-of-frame control mechanisms, for example, end-offrame indication with TSCR.EOF bit.
Check that any running word transfer is completed (PSR.TSIF flag = 1)
before clearing bit PSR.MSLS.
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Functional Deviations
USIC_AI.020 Handling unused DOUT lines in multi-IO SSC mode
In multi-IO SSC mode, when the number of DOUT lines enabled through the bit
field CCR.HPCEN is greater than the number of DOUT lines used as defined in
the bit field SCTR.DSM, the unused DOUT lines output incorrect values instead
of the passive data level defined by SCTR.PDL.
Implications
Unintended edges on the unused DOUT lines.
Workaround
To avoid unintended edges on the unused DOUT lines, it is recommended to
use the exact number of DOUT lines as enabled by the hardware controlled
interface during a multi-IO data transfer.
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Errata Sheet
Deviations from Electrical- and Timing Specification
3
Deviations from Electrical- and Timing
Specification
The errata in this section describe deviations from the documented electricaland timing specifications.
DAC_CM.P001 INL parameter limits violated by some devices
At some devices the DAC module violates the Integral Nonlinearity (INL)
parameter limits of ±4 LSB, especially for very cold temperatures. These
devices can show INL values up to ±5.5 LSB, measured with best straight line
method.
Note: Integral Nonlinearity (INL) is defined as the max. deviation of the output
characteristic against a straight line. Selecting the straight line which
gives best INL number, is called best straight line method.
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Errata Sheet
Application Hints
4
Application Hints
The errata in this section describe application hints which must be regarded to
ensure correct operation under specific application conditions.
ADC_AI.H003 Injected conversion may be performed with sample time of
aborted conversion
For specific timing conditions and configuration parameters, a higher prioritized
conversion ci (including a synchronized request from another ADC kernel) in
cancel-inject-repeat mode may erroneously be performed with the sample time
parameters of the lower prioritized cancelled conversion cc. This can lead to
wrong sample results (depending on the source impedance), and may also shift
the starting point of following conversions.
The conditions for this behavior are as follows (all 3 conditions must be met):
1. Sample Time setting: injected conversion ci and cancelled conversion cc
use different sample time settings, i.e. bit fields STC* in the corresponding
Input Class Registers for cc and for ci (GxICLASS0/1, GLOBICLASS0/1)
are programmed to different values.
2. Timing condition: conversion ci starts during the first fADCI clock cycle of the
sample phase of cc.
3. Configuration parameters: the ratio between the analog clock fADCI and
the arbiter speed is as follows:
NA > ND*(NAR+3),
with
a) NA = ratio fADC/fADCI (NA = 2 .. 32, as defined in bit field DIVA),
b) ND = ratio fADC/fADCD = number of fADC clock cycles per arbitration slot
(ND = 1 .. 4, as defined in bit field DIVD),
c) NAR = number of arbitration slots per arbitration round (NAR = 4, 8, 16, or
20, as defined in bit field GxARBCFG.ARBRND).
Bit fields DIVA and DIVD mentioned above are located in register GLOBCFG.
As can be seen from the formula above, a problem typically only occurs when
the arbiter is running at maximum speed, and a divider NA > 7 is selected to
obtain fADCI.
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Errata Sheet
Application Hints
Recommendation 1
Select the same sample time for injected conversions ci and potentially
cancelled conversions cc, i.e. program all bit fields STC* in the corresponding
Input Class Registers for cc and for ci (GxICLASS0/1, GLOBICLASS0/1) to
the same value.
Recommendation 2
Select the parameters in register GLOBCFG and GxARBCFG according to the
following relation:
NA ≤ ND*(NAR+3).
ADC_AI.H004 Completion of Startup Calibration
Before using the VADC the startup calibration must be completed.
The calibration is started by setting GLOBCFG.SUCAL. The active phase of the
calibration is indicated by GxARBCFG.CAL = 1. Completion of the calibration is
indicated by GxARBCFG.CAL = 0.
When checking for bit CAL = 1 immediately after setting bit SUCAL, bit CAL
might not yet be set by hardware. As a consequence the active calibration
phase may not be detected by software.The software may use the following
sequence for startup calibration:
1. GLOBCFG.SUCAL = 1
2. Wait for GxARBCFG.CAL = 1
3. Check for GxARBCFG.CAL = 0 before starting a conversion
Make sure that steps 1 and 2 of this sequence are not interrupted to avoid a
deadlock situation with waiting for GxARBCFG.CAL = 1.
ADC_AI.H008 Injected conversion with broken wire detection
If a higher prioritized injected conversion ci (in cancel-inject-repeat mode) using
the broken wire detection feature (GxCHCTRy.BWDEN = 1B) interrupts a lower
prioritized conversion cc before start of the conversion phase of cc, the following
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Errata Sheet
Application Hints
effects will occur for the injected conversion ci (independent of the
recommendations in ADC_AI.H003):
1. The effective sample time is either doubled, or it is equal to the sample time
of the lower prioritized cancelled conversion cc. This will shift the starting
point of following conversions, and may lead to wrong sample results if the
sample time for cc is considerably shorter than the programmed sample time
for ci (depending on the source impedance).
2. The preparation phase for ci may be skipped, i.e. during the effective sample
phase (as described above), the selected channel is sampled without
precharging the capacitor network to the level selected for the broken wire
detection. Depending on the synchronization between ci and cc, this may
increase the time until a broken connection is detected.
The interrupted conversion cc will be correctly restarted after completion of the
injected conversion ci.
Recommendation
Perform injected conversions without enabling the broken wire detection
feature, and follow the recommendations given in ADC_AI.H003.
Alternatively, configure the trigger source that includes channels using the
broken wire detection feature such that it will not cancel other conversions. This
can be achieved by setting the priority of the request source s to the lowest
priority (GxARBPR.PRIOs = 00B), or by setting the conversion start mode to
“wait-for-start mode” (GxARBPR.CSMs = 0B).
ADC_TC.H011 Bit DCMSB in register GLOBCFG
The default setting for bit DCMSB (Double Clock for the MSB Conversion) in
register GLOBCFG is 0B, i.e. one clock cycle for the MSB conversion step is
selected.
DCMSB = 1B is reserved in future documentation and must not be used.
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Errata Sheet
Application Hints
MultiCAN_AI.H005 TxD Pulse upon short disable request
If a CAN disable request is set and then canceled in a very short time (one bit
time or less) then a dominant transmit pulse may be generated by MultiCAN
module, even if the CAN bus is in the idle state.
Example for setup of the CAN disable request:
Workaround
Set all INIT bits to 1 before requesting module disable.
MultiCAN_AI.H006 Time stamp influenced by resynchronization
The time stamp measurement feature is not based on an absolute time
measurement, but on actual CAN bit times which are subject to the CAN
resynchronization during CAN bus operation.The time stamp value merely
indicates the number of elapsed actual bit times. Those actual bit times can be
shorter or longer than nominal bit time length due to the CAN resynchronization
events.
Workaround
None.
MultiCAN_AI.H007 Alert Interrupt Behavior in case of Bus-Off
The MultiCAN module shows the following behavior in case of a bus-off status:
TEC=0x60 or
REC=0x60
EWRN
Figure 20
REC=0x1,
TEC=0x1
BOFF
INIT
REC=0x60,
TEC=0x1
EWRN+BOFF
INIT
REC=0x0,
TEC=0x0
ALERT
INIT
Alert Interrupt Behavior in case of Bus-Off
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Errata Sheet
Application Hints
When the threshold for error warning (EWRN) is reached (default value of Error
Warning Level EWRN = 0x60), then the EWRN interrupt is issued. The bus-off
(BOFF) status is reached if TEC > 255 according to CAN specification,
changing the MultiCAN module with REC and TEC to the same value 0x1,
setting the INIT bit to 1B, and issuing the BOFF interrupt. The bus-off recovery
phase starts automatically. Every time an idle time is seen, REC is incremented.
If REC = 0x60, a combined status EWRN+BOFF is reached. The corresponding
interrupt can also be seen as a pre-warning interrupt, that the bus-off recovery
phase will be finished soon. When the bus-off recovery phase has finished (128
times idle time have been seen on the bus), EWRN and BOFF are cleared, the
ALERT interrupt bit is set and the INIT bit is still set.
MultiCAN_AI.H008 Effect of CANDIS on SUSACK
When a CAN node is disabled by setting bit NCR.CANDIS = 1B, the node waits
for the bus idle state and then sets bit NSR.SUSACK = 1B.
However, SUSACK has no effect on applications, as its original intention is to
have an indication that the suspend mode of the node is reached during
debugging.
MultiCAN_TC.H003 Message may be discarded before transmission in
STT mode
If MOFCRn.STT=1 (Single Transmit Trial enabled), bit TXRQ is cleared
(TXRQ=0) as soon as the message object has been selected for transmission
and, in case of error, no retransmission takes places.
Therefore, if the error occurs between the selection for transmission and the
real start of frame transmission, the message is actually never sent.
Workaround
In case the transmission shall be guaranteed, it is not suitable to use the STT
mode. In this case, MOFCRn.STT shall be 0.
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Errata Sheet
Application Hints
MultiCAN_TC.H004 Double remote request
Assume the following scenario: A first remote frame (dedicated to a message
object) has been received. It performs a transmit setup (TXRQ is set) with
clearing NEWDAT. MultiCAN starts to send the receiver message object (data
frame), but loses arbitration against a second remote request received by the
same message object as the first one (NEWDAT will be set).
When the appropriate message object (data frame) triggered by the first remote
frame wins the arbitration, it will be sent out and NEWDAT is not reset. This leads
to an additional data frame, that will be sent by this message object (clearing
NEWDAT).
There will, however, not be more data frames than there are corresponding
remote requests.
C AN Bus
r e m o te
re q u e s t
r e m o te
re q u e s t
d a ta
d a ta
lo s s o f
a rb itra tio n
s e tu p
M u ltiC A N
d a ta
o b je c t
c le a r
NEW DAT
by H W
Figure 21
s e tu p
c le a r s e t
NEW DAT
by H W
d a ta
o b je c t
d a ta
s e tu p
o b je c t
c le a r
NEW DAT
by H W
Loss of Arbitration
RESET_CM.H001 Power-On Reset Release
The on-chip EVR implements a power validation circuitry which supervises
VDDP and VDDC. This circuit releases or asserts the system reset to ensure
safe operation. This reset is visible on bidirectional PORST pin.
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Errata Sheet
Application Hints
Implications
Potential effects if the PORST release requirement is not met (please refer to
the Data Sheet for details) is presence of spikes or toggling on the PORST pin
which may have an effect on the rest of the system if the reset signal is shared
with other electronic components on the PCB. A repeated PORST may also
result in loss of information about hibernation status after an interrupted wakeup has been performed. Potential presence of the spikes on PORST, however,
will not lead to a fatal system startup failure or deadlock.
Recommendation
It is required to ensure fast PORST release, as specified in Data Sheet. The
recommended approach is to apply a pull-up resistor on the PORST pin.
Typically a 10 - 90 kΩ resistor is sufficient in application cases where the device
is in control of the reset generation performed by its internal power validation
circuit and no additional load is applied to the PORST pin. The required pull-up
resistor value may vary depending on the electrical parameters of the system,
like parasitic wire resistance and capacitance of the PCB, driving strength of
other electronic components connected to the PORST pin and other side
conditions. The pull-up resistance may need to be adapted accordingly.
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