SCA8X0/21X0/3100

SCA8X0/21X0/3100
SCA8X0/21X0/3100 Series
Product Family Specification
Murata Automotive Digital Accelerometer
Platform
SCA8X0 / 21X0 / 31X0 Accelerometers
SCA8X0/21X0/3100 Serie
TABLE OF CONTENTS
Table of Contents .....................................................................................................................2
General Description ..................................................................................................................5
1.1
Introduction ............................................................................................................................. 5
1.2
Features ................................................................................................................................... 5
1.3
Typical applications ................................................................................................................ 6
1.4
Functional Description ........................................................................................................... 6
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
1.4.10
1.4.11
Sensing element ................................................................................................................................... 6
Interface IC............................................................................................................................................ 6
Capacitance to voltage conversion ....................................................................................................... 6
Analog to digital conversion .................................................................................................................. 7
Signal conditioning and filtering ............................................................................................................ 7
Temperature measurement .................................................................................................................. 7
Memory ................................................................................................................................................. 7
SPI ........................................................................................................................................................ 7
Self diagnostics ..................................................................................................................................... 7
Power supply interface .......................................................................................................................... 7
Factory calibration ................................................................................................................................. 7
2 Operation Modes .................................................................................................................8
2.1
Measurement mode ................................................................................................................ 8
2.2
Temperature output ................................................................................................................ 8
2.3
Self-diagnostic functions ....................................................................................................... 8
2.3.1
Memory self-diagnostic ......................................................................................................................... 8
2.3.2
Signal path self-diagnostic .................................................................................................................... 8
2.3.2.1
SCA8X0 – single axis accelerometers .......................................................................................... 8
2.3.2.2
SCA21X0 and SCA31X0 – multi axis accelerometers .................................................................. 8
2.4
Power Down mode .................................................................................................................. 9
2.5
Recommended start-up sequence ......................................................................................... 9
2.6
Recommended operation sequence .................................................................................... 10
2.7
Recommended procedures or optional features ................................................................ 11
2.7.1
SCA8x0/SCA21x0/SCA31x0 .............................................................................................................. 11
2.7.1.1
Read back procedure .................................................................................................................. 11
2.7.1.2
Checksum during operation ......................................................................................................... 11
2.7.1.3
Saturated data ............................................................................................................................. 11
2.7.1.4
Noiseless output .......................................................................................................................... 11
2.7.1.5
Component ID .............................................................................................................................. 11
2.7.2
SCA8x0 ............................................................................................................................................... 11
2.7.2.1
Mass deflection during operation ................................................................................................. 11
2.7.2.2
Monitor acceleration data during mass deflection ....................................................................... 12
3 Addressing Space .............................................................................................................12
3.1
Output registers .................................................................................................................... 12
3.1.1
X axis acceleration output ................................................................................................................... 12
3.1.1.1
X_LSB .......................................................................................................................................... 12
3.1.1.2
X_MSB ......................................................................................................................................... 13
3.1.2
Y axis acceleration output ................................................................................................................... 13
3.1.2.1
Y_LSB .......................................................................................................................................... 13
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3.1.2.2
Y_MSB ......................................................................................................................................... 13
3.1.3
Z axis acceleration output ................................................................................................................... 13
3.1.3.1
Z_LSB .......................................................................................................................................... 13
3.1.3.2
Z_MSB ......................................................................................................................................... 13
3.1.4
Output data conversion ....................................................................................................................... 14
3.1.4.1
2g products .................................................................................................................................. 14
3.1.4.2
6 g products ................................................................................................................................. 15
3.1.4.3
1 g products ................................................................................................................................. 15
3.1.5
Temperature output ............................................................................................................................ 15
3.1.5.1
Temperature Register Low (TEMP_LSB) .................................................................................... 15
3.1.5.2
Temperature Register High (TEMP_MSB) .................................................................................. 16
3.1.6
Status Register (STATUS) .................................................................................................................. 17
3.1.7
Interrupt Status Register (INT_STATUS) ........................................................................................... 17
3.2
Operation control registers .................................................................................................. 18
3.2.1
3.2.2
3.3
Control Register (CTRL) ..................................................................................................................... 18
Reset Register (RESET) ..................................................................................................................... 19
Identification registers .......................................................................................................... 19
3.3.1
3.3.2
Revision ID (REVID) ........................................................................................................................... 19
Component ID (ID) .............................................................................................................................. 19
4 SPI Interface ......................................................................................................................20
4.1
Output of Acceleration Data ................................................................................................. 21
4.1.1
4.1.2
4.1.3
4.2
Register read operation ...................................................................................................................... 22
Decremented register read operation ................................................................................................. 22
MOSI data of SPI commands ............................................................................................................. 23
Error Conditioning ................................................................................................................ 23
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
FRME-bit ............................................................................................................................................. 23
PORST-bit ........................................................................................................................................... 23
ST-bit (SCA21X0 / 3100) .................................................................................................................... 24
SAT-bit (SCA21X0 / 3100) .................................................................................................................. 24
aPAR-bit (SCA21X0 / 3100) ............................................................................................................... 24
dPAR-bit .............................................................................................................................................. 25
Fixed bits ............................................................................................................................................. 25
Output data ......................................................................................................................................... 25
5 Electrical Characteristics .................................................................................................26
5.1
Absolute maximum ratings .................................................................................................. 26
5.2
Power Supply ........................................................................................................................ 26
5.3
Digital I/O Specification ........................................................................................................ 26
5.3.1
5.3.2
DC Characteristics .............................................................................................................................. 26
AC Characteristics .............................................................................................................................. 26
6 Application information ....................................................................................................28
6.1
Package dimensions ............................................................................................................. 28
6.2
Output to Angle Conversion................................................................................................. 29
6.3
Measuring Directions ............................................................................................................ 30
6.4
Pin Description ...................................................................................................................... 31
6.5
Recommended circuit diagram ............................................................................................ 31
6.6
Recommended PWB layout .................................................................................................. 32
6.7
Assembly instructions .......................................................................................................... 34
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6.8
Tape and reel specifications ................................................................................................ 34
7 Document Change Control ..................................................... Error! Bookmark not defined.
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General Description
1.1
Introduction
Murata Automotive Digital Accelerometer Platform is an accelerometer product concept based on
Murata capacitive 3D-MEMS technology. The Murata ADP platform integrates high accuracy
micromechanical acceleration sensing together with a flexible SPI digital interface. The products
within the platform range from single axis accelerometers into two or three axis accelerometers.
Dual Flat Lead (DFL) housing of the component guarantees robust operation over the product
lifetime.
The products are designed, manufactured and tested for high stability, reliability and quality
requirements of automotive applications. The accelerometers have extremely stable output over
wide range of temperature, humidity and mechanical noise. The components are qualified against
AEC-Q100 standard and have several advanced self diagnostics features. The DFL housing is
suitable for SMD mounting and the component is compatible with RoHS and ELV directives.
This Product Family Specification describes the Murata Automotive Digital Accelerometer Platform
common characteristics and how to operate with the products. Detail product specification is
described in individual data sheets of each product.
1.2
Features
Standard features of the Murata Automotive Digital Accelerometer Platform
 Single, dual or three axis acceleration measurement
 SPI digital interface
 3.3V supply voltage
 Enhanced self diagnostics features
 Internal temperature sensor
 Size 7.6 x 3.3 x 8.6 mm (w x h x l)
 RoHS compliant Dual Flat Lead (DFL) plastic package suitable for lead free soldering
process and SMD mounting
 Package, pin-out and SPI protocol compatible within the product family
 Proven capacitive 3D-MEMS technology
 Qualified according to AEC-Q100 standard
Main characteristics of each product within the product family are listed in Table 1 below.
Table 1: Digital platform summary
Type
SCA810-D01
SCA820-D03
SCA830-D05
SCA2100-D01
SCA2110-D03
SCA2120-D05
SCA3100-D01
X
Z
Y
X, Y
X, Z
Y, Z
X, Y, Z
Measuring directions
Single axis Accelerometer
Single axis Accelerometer
Single axis Accelerometer
Dual axis Accelerometer
Dual axis Accelerometer
Dual axis Accelerometer
Three axis Accelerometer
Figure 1: Measurement directions
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1.3
Typical applications
Murata Automotive Digital Accelerometer Platform is targeted to automotive applications with high
stability requirements. Typical applications include but are not limited to
 Electronic Stability Control (ESC)
 Hill Start Assist (HSA)
 Electronic Parking Brake (EPB)
 Roll Over
 Active Suspension
 Inclination
 Industrial applications
1.4
Functional Description
Basic product concept of the Murata Automotive Digital Accelerometer Platform is a two chip
solution consisting of a single sensing element and one ASIC inside a pre-molded 12-pin housing.
The interface to the application is a four wire digital SPI interface. In single axis products there is
also Pulse Width Modulation output available. In addition to the supply voltage filtering the
component does not require any other components to be connected to the device.
Block diagram of SCA8X0/SCA21X0/31X0
1.4.1
Sensing element
The sensing element of the product is manufactured by using Murata proprietary bulk 3D-mems
process enabling a robust, stable and low noise capacitive sensor. Depending on the product type
and measurement direction the sensing element type and orientation inside the housing can vary.
Single axis products are equipped with single axis sensing elements and multi axis products are
equipped with multi axis sensing elements.
1.4.2
Interface IC
The main functional blocks of the interface ASIC are the following:
1.4.3
Capacitance to voltage conversion
The acceleration is causing a capacitance change inside the sensing element. The capacitance
change can be detected by the ASIC analog interface. The capacitance information is converted
into an analog voltage that can be further processed easily inside the ASIC.
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1.4.4
Analog to digital conversion
Analog voltage information is amplified and filtered and converted into digital information for signal
processing inside the ASIC.
1.4.5
Signal conditioning and filtering
The block filters and conditions the measurement information needed for the application
1.4.6
Temperature measurement
The accelerometers contain a temperature sensor for temperature compensation purposes and for
use in the application.
1.4.7
Memory
Factory programmed calibration values are stored in a non-volatile memory
1.4.8
SPI
SPI interface is a simple four wire interface for communication between the component and the
application micro controller.
1.4.9
Self diagnostics
The Murata Automotive Digital Platform contains several enhanced diagnostics features to allow
timely and robust failure detection.
1.4.10 Power supply interface
The products are equipped with separate power and ground pins for analog and digital functionality
to allow high accuracy measurement.
1.4.11 Factory calibration
Murata Automotive Digital Platform accelerometers are factory calibrated. No separate calibration
is required in the application. Trimmed parameters during production include sensitivity, offset and
frequency response. Calibration parameters are stored during the manufacturing of the part inside
a non-volatile memory. The parameters are read automatically from the internal non-volatile
memory during the startup of the sensor after power on.
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2
Operation Modes
2.1
Measurement mode
After the startup the acceleration data is immediately available through the SPI registers. There is
no need to initialize the accelerometer before starting to use of it. If the application is requiring
monitoring of the correctness of the operation there are several options available to monitor the
operation status.
2.2
Temperature output
The devices include a temperature measurement function. Temperature data can be read through
the SPI interface. Temperature measurement is not calibrated for absolute accuracy. If absolute
accuracy is needed, it can be achieved through measuring the temperature value in two
temperature points in final application and storing them as a calibration value and calculating the
absolute temperature value by using the two points.
2.3
Self-diagnostic functions
Murata Automotive Digital Accelerometer Platform has a set of built-in self-diagnostic functions to
support the application fail safety. The diagnostic functions cover the accelerometer sensing
element functionality, accelerometer internal operation and signal path functionality
2.3.1
Memory self-diagnostic
Factory calibrated values of the accelerometer are stored in a non-volatile memory. The calibrated
values are read during the device power on into volatile registers that control the operation of the
device. During the startup of the device the calculated sum of non-volatile registers is compared to
the factory calibrated value. The test is done automatically after supplies are set on, after any reset
state of component and after return from power-down mode. Test can also be started by a CTRLregister command.
2.3.2
Signal path self-diagnostic
2.3.2.1
SCA8X0 – single axis accelerometers
Sensor element and signal path is tested by deflecting the proof mass of the sensing element to
both directions over a predefined dynamic range. The test is done automatically during start-up and
it can be repeated by a CTRL-register command. The result of the test is a momentary mass
deflection seen in the output of the device. During the test the accelerometer performs a
comparison of the deflection result to a pre-defined threshold value. When the needed dynamics
have been detected the device will return the result of a passed test in a register. By following the
output of the device on SPI interface it is possible to detect failures through the signal path.
2.3.2.2
SCA21X0 and SCA31X0 – multi axis accelerometers
2.3.2.2.1
Start-up Self Test (STS)
During the application start up or when the accelerometer is affected by the gravity force only it is
possible to detect possible sensing element anomalies by applying a start up self test. The test is
done in a following way: a digitally calculated resultant acceleration of x, y and z-axis is compared
to predefined threshold value. Test is started by CTRL-register command and it is done once when
requested.
2.3.2.2.2
Continuous Self Test (STC)
During device operation the continuous self test is monitoring the sensing element performance.
Digitally calculated self-diagnostic function is compared to predefined threshold value. Test is
started by CTRL-register command and it is calculated continuously on background until disabled.
Possible errors are indicated in an error status register and in SPI frame.
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2.4
Power Down mode
For low power applications it is possible to set the accelerometer into power down mode. During
the power down mode the power consumption is minimized inside the device. This is achieved by
stopping the internal clocks and resetting the control registers of the device. Please refer to the
individual device data sheets for detail power consumption figures.
2.5
Recommended start-up sequence
For correct device operation there are no specific configuration needed for the device before
starting of measuring the acceleration. However if the device detail features are being used the
following operations could be made after the powering on the device.
Table 2: SCA8X0 start up sequence
Item
1
Procedure
Set Vdd=3.0...3.6V
2
Wait 95ms
3
Read CTRL-register
4
Read STATUS-register
5
Write CTRL=0000 0000
6
Read X_MSB, X_LSB –
registers
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Functions
 Set the power
on to release
part from
reset and to
start the
operation
 During the
first 95ms the
part is
performing
the memory
read and selfdiagnostics.
 Possible
signal path
selfdiagnostic
test is carried
out.
 Settling of
signal path
 Check the
self-test pass
status
 Check the
memory
checksum
pass status
 After device
power on set
PORST=0 to
be able to
detect any
future
occurring
power
failures
 Start reading
the
acceleration
data
Check
-
-









CTRL.ST=0
SPI fixed bits
dPAR, data parity
STATUS.CSMERR=0
SPI fixed bits
SPI FRME=0
dPAR, data parity
SPI fixed bits
SPI FRME=0




SPI fixed bits
SPI FRME=0
SPI PORST=0
dPAR, data parity
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Table 3: SCA21X0 and SCA31X0 start up sequence
Item
1
Procedure
Set Vdd=3.0...3.6V
2
Wait 35ms
3
Read INT_STATUS
4
Write
CTRL=00001010 (a)
or
CTRL=00001000 (b)
or
CTRL=00000000 (c)
Wait 10ms
Read CTRL
5
6
7
2.6
Read Z_MSB, Z_LSB,
Y_MSB, Y_LSB,
X_MSB, X_LSB
Functions
 Release part from
reset
 Memory reading and
self-diagnostic
 Settling of signal
path
 Acknowledge for
possible saturation
(SAT-bit)
 Checksum pass
detected from SPI
frame

Set PORST=0 (abc)

Start STC (ab)
 Start STS (a)
STS calculation
 Check that STC is
on, if enabled
 Check that STS is
over if enabled
Read acceleration data
Check
-


SPI fixed bits
SPI ST=0




SPI fixed bits
SPI FRME=0
SPI ST=0
SPI SAT=0














CTRL.ST=1
CTRL.ST_CFG=0
SPI fixed bits
SPI FRME=0
SPI PORST=0
SPI ST=0
SPI SAT=0
dPAR, data parity
SPI fixed bits
SPI FRME=0
SPI PORST=0
SPI ST=0
SPI SAT=0
dPAR, data parity
Recommended operation sequence
Table 4: Reading of the acceleration data
Item
1
Procedure
Read acceleration data
Functions
Desired x, y,
or/and z-data
2
Repeat item 1 (N-1) times
3
Calculate average (AVE) of
N-samples
Read acceleration data
Noise
averaging
Noise
averaging
Desired x, y,
or/and z-data
(one read
before sending
4
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Check
 SPI fixed bits
 SPI FRME=0
 SPI PORST=0
 SPI ST=0
 SPI SAT=0
 dPAR, data
parity



SPI fixed bits
SPI FRME=0
SPI PORST=0
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Item
Procedure
Functions
AVE forward to
check SPI
failure bits)
5
6
Send calculated AVE forward
Jump back to item 2
-
Check
 SPI ST=0
 SPI SAT=0
 dPAR, data
parity
-
For detailed SPI failure bit information see chapter 4.2 Error Conditioning
2.7
Recommended procedures or optional features
Product family components have different features, which are not required during normal operation.
However, they are recommended in some cases if they are seen important from system
perspective.
2.7.1
2.7.1.1
SCA8x0/SCA21x0/SCA31x0
Read back procedure
It is recommended to read back every write command to compare read data to the write command.
This way it is detected very unlikely failures in MCU, in SPI wiring, in SPI interface, in system clock
or inside state machine.
2.7.1.2
Checksum during operation
Checksum is calculated for component register values that control the operation of product. Data is
read from non-volatile memory to these registers during start-up and checksum is calculated
automatically. It is possible to repeat checksum calculation during normal operation by CTRL
register command and test result can be seen from STATUS register (see more info in 3.2.1 and
3.1.6). In multi-axis products test result can be seen also from SPI frame. By repeating checksum
during normal operation, it is possible to detect very unlikely intermittent or static bit failures in
register map.
2.7.1.3
Saturated data
Output data saturates to predefined value if product dynamic range is exceeded. If output data has
been saturated it should be considered invalid and it should not be used for system controlling.
Output data saturation can also be indication of some very unlike component failure.
2.7.1.4
Noiseless output
Valid acceleration output includes always some noise. If output data is constant, it can be indication
of system error and data is not valid anymore. Therefore it is useful to monitor noise or deviation of
output data.
2.7.1.5
Component ID
Each product family component type has unique identification number, which is stored to nonvolatile memory (see 3.3.2). This number can be used for example in production line to check that
correct component is mounted to the system. In some cases it may be used for MCU software
controlling.
2.7.2
2.7.2.1
SCA8x0
Mass deflection during operation
Mass deflection self-test is performed automatically to both direction in start-up. Mass deflection
can be performed during operation if requested by user. Test is started and direction is controlled
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by CTRL register (see more info in 3.2.1). Note that acceleration output data is not valid during test
and after test is started to one direction there has to be 50ms wait time before output data is used.
2.7.2.2
Monitor acceleration data during mass deflection
Acceleration data can be read out from acceleration output registers during mass deflection selftest in start-up or during operation, in case that test is repeated by the request. Monitoring this data
it is possible to determine product frequency response and check product timing properties.
3
Addressing Space
Table 5 presents the registers of SCA8X0, SCA21X0 and SCA31X0 products.
Table 5: Register address space
Addr
hex
Name
00
01
02
03
04
05
06
07
08
09
0A
...
11
12
13
14
15
16
17
...
26
27
28
...
3F
3.1
Description
REVID
CTRL
STATUS
RESET
X_LSB
X_MSB
Y_LSB
Y_MSB
Z_LSB
Z_MSB
ASIC revision ID number
Control
Status
Reset component
X-axis (or Y- or Z-axis in SCA8X0) LSB frame
X-axis (or Y- or Z-axis in SCA8X0) MSB frame
Y-axis LSB frame in multi-axis components
Y-axis MSB frame in multi-axis components
Z-axis LSB frame in multi-axis components
Z-axis MSB frame in multi-axis components
Reserved
Reserved
Reserved
TEMP_LSB
Temperature LSB frame
TEMP_MSB Temperature MSB frame
Reserved
Reserved
INT_STATUS Interrupt status register in multi-axis components
Reserved
Reserved
Reserved
ID
Component ID
Reserved
Reserved
Reserved
Mode
(R/RW)
R
RW
R
RW
R
R
R
R
R
R
R
R
R
RW
-
Output registers
3.1.1
3.1.1.1
X axis acceleration output
X_LSB
Address: 4h
Bits
Mode
7:0
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R
Initial
Value
00h
Name
Description
DATA
X-axis LSB frame (or Y-axis or Z-axis in SCA8X0)
Read always X_MSB prior to X_LSB.
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3.1.1.2
X_MSB
Address: 5h
Bits
Mode
7:0
3.1.2
3.1.2.1
R
R
7:0
R
X-axis MSB frame (or Y-axis or Z-axis in SCA8X0)
Reading of this register latches X_LSB.
Initial
Value
00h
Name
Description
DATA
Y-axis LSB frame
Read always Y_MSB prior to Y_LSB.
Initial
Value
00h
Name
Description
DATA
Y-axis MSB frame
Reading of this register latches Y_LSB.
Initial
Value
00h
Name
Description
DATA
Z-axis LSB frame
Read always Z_MSB prior to Z_LSB.
Initial
Value
00h
Name
Description
DATA
Z-axis MSB frame
Reading of this register latches Z_LSB.
Z axis acceleration output
Z_LSB
Address: 8h
Bits
Mode
7:0
3.1.3.2
DATA
Y_MSB
Address: 7h
Bits
Mode
3.1.3.1
Description
Y_LSB
7:0
3.1.3
Name
Y axis acceleration output
Address: 6h
Bits
Mode
3.1.2.2
Initial
Value
00h
R
Z_MSB
Address: 9h
Bits
Mode
7:0
R
The bit level description of acceleration data from X_LSB ... Z_MSB registers is presented below
(Note that the available axis combination of xyz depends on product type). The acceleration data is
presented in 2's complement format. At 0 g acceleration the output is ideally 0000h.
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3.1.4
Output data conversion
3.1.4.1
2g products
+/-2g product
Bit number
SCA8x0
+1g position
-1g position
+Full-scale
-Full-scale
DOUT MSB bits(7:0)
15
14
13
s
1137.8
568.9
0
0
1
1
1
0
0
1
1
1
0
0
12
284.4
1
0
1
0
11
142.2
1
0
1
0
10
71.1
0
1
1
0
9
35.6
0
1
1
0
8
17.8
0
1
1
0
DOUT LSB bits(7:0)
7
6
5
8.89
4.44
2.22
0
1
0
1
1
0
1
1
1
0
0
0
4
1.11
0
0
1
0
3
x
x
x
x
x
2
x
x
x
x
x
1
x
x
x
x
x
0
x
x
x
x
x
[-]
[mg]
1000
-1000
2274
-2275
12b
12b
Bits (15:4) Bits (15:4)
[Dec]
[Hex]
900
384
-900
C7C
2047
7FF
-2048
800
+/-2g product
DOUT MSB bits(7:0)
Bit number
15
14
13
SCA31x0/SCA21x0
s
4551.1
2275.6
+1g position
0
0
0
-1g position
1
1
1
+Full-scale *)
0
0
0
-Full-scale *)
1
1
1
12
1137.8
0
1
1
0
11
568.9
1
0
1
0
10
284.4
1
0
1
0
9
142.2
1
0
1
0
8
71.1
0
1
1
0
DOUT LSB bits(7:0)
7
6
5
35.56 17.78
8.89
0
0
0
1
1
1
1
1
1
0
0
0
4
4.44
1
1
1
0
3
2.22
0
0
1
0
2
1.11
0
0
1
0
1
x
x
x
x
x
0
x
x
x
x
x
[-]
[mg]
1000
-1000
2274
-2275
Bits (15:2) Bits (15:2)
[Dec]
[Hex]
900
384
-900
3C7C
2047
7FF
-2048
3800
s = sign bit
x = not used/defined bit
*) = positive/negative full-scale or saturation limit of ±2 g product is 2.27 g.
In SCA8X0 acceleration bits can be converted to mg acceleration (Acc) using following equation
Acc mg  


10
 s  211  b14  210  b13  29  b12  28  b11  27  b10  26  b9  25  b8  24  b7  23  b6  22  b5  2  b4
9
and in SCA21X0/SCA31X0
Acc mg  
13
12
11
10
9
8
,
10  s  2  b14  2  b13  2  b12  2  b11  2  b10  2


7
6
5
4
3
2
9  b9  2  b8  2  b7  2  b6  2  b5  2  b4  2  b3  2  b2
where bits are defined according to following table.
Acceleration MSB-register: Address 5'hex / 7'hex / 9'hex
Acceleration LSB-register: Address 4'hex / 6'hex / 8'hex
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
In data output registers of SCA21X0/SCA31X0 there is reserved room for different g-ranges. To
make sure that same software works with different product types it is recommended to use
bits(15:2) for data conversion. If dynamic output range of product does not require bits b14 or b13
they include copy of sign bit b15.
If self-test (checksum, STC, STS) alarms it sets ST bit in SPI frame and forces output data to value
7FFF'hex (checksum fail) or to value FFFF'hex (STC/STS alarm).
In SCA21X0/SCA31X0 there is also possible to use 1-extra lsb bit (b1) for calculation to improve
resolution. In that case acceleration bits can be converted to mg acceleration (Acc) using following
equation
Acc mg  
14
13
12
11
10
9
8
10  s  2  b14  2  b13  2  b12  2  b11  2  b10  2  b9  2  .


18  b8  27  b7  26  b6  25  b5  24  b4  23  b3  22  b2  2  b1 
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3.1.4.2
6 g products
+/-6g product
Bit number
SCA8x0
+1g position
-1g position
+Full-scale
-Full-scale
DOUT MSB bits(7:0)
15
14
13
s
3150.8
1575.4
0
0
0
1
1
1
0
1
1
1
0
0
12
787.7
1
0
1
0
11
393.8
0
1
1
0
10
196.9
1
0
1
0
9
98.5
0
1
1
0
8
49.2
0
1
1
0
DOUT LSB bits(7:0)
7
6
5
24.6
12.31
6.15
0
1
0
1
0
1
1
1
1
0
0
0
4
3.08
1
1
1
0
3
x
x
x
x
x
2
x
x
x
x
x
1
x
x
x
x
x
0
x
x
x
x
x
[-]
[mg]
1000
-1000
6300
-6302
12b
12b
Bits (15:4) Bits (15:4)
[Dec]
[Hex]
325
145
-325
EBB
2047
7FF
-2048
800
+/-6g product
DOUT MSB bits(7:0)
Bit number
15
14
13
SCA31x0/SCA21x0
s
6301.5
3150.8
+1g position
0
0
0
-1g position
1
1
1
+Full-scale *)
0
0
1
-Full-scale *)
1
1
0
12
1575.4
0
1
1
0
11
787.7
1
0
1
0
10
393.8
0
1
1
0
9
196.9
1
0
1
0
8
98.5
0
1
1
0
DOUT LSB bits(7:0)
7
6
5
49.2
24.6
12.3
0
0
1
1
1
0
1
1
1
0
0
0
4
6.15
0
1
1
0
3
3.08
1
1
1
0
2
1.54
0
0
1
0
1
x
x
x
x
x
0
x
x
x
x
x
[-]
[mg]
1000
-1000
6300
-6302
Bits (15:2) Bits (15:2)
[Dec]
[Hex]
650
28A
-650
3D76
4095
FFF
-4096
3000
s = sign bit
x = not used/defined bit
*) = positive/negative full-scale or saturation limit of ±6 g product is 6.3 g.
In SCA8X0 acceleration bits can be converted to mg acceleration (Acc) using following equation

Acc mg  

1000
 s  211  b14  210  b13  29  b12  28  b11  27  b10  26  b9  25  b8  24  b7  23  b6  22  b5  2  b4
325
and in SCA21X0/SCA31X0
Acc mg  
3.1.4.3
13
12
11
10
9
8
,
1000  s  2  b14  2  b13  2  b12  2  b11 2  b10  2


7
6
5
4
3
2
650  b9  2  b8  2  b7  2  b6  2  b5  2  b4  2  b3  2  b2
1 g products
+/-1g product
Bit number
SCA8xx
+1g position
-1g position
+Full-scale
-Full-scale
DOUT MSB bits(7:0)
15
14
13
s
512,0
256,0
0
1
1
1
0
0
0
1
1
1
0
0
12
128,0
1
0
1
0
11
64,0
1
0
1
0
10
32,0
1
0
1
0
9
16,0
0
1
1
0
8
8,0
1
1
1
0
DOUT LSB bits(7:0)
7
6
5
4,00
2,00
1,00
0
0
0
0
0
0
1
1
1
0
0
0
4
0,50
0
0
1
0
3
0,25
0
0
1
0
2
0,13
0
0
1
0
1
0,06
0
0
1
0
16b
0
[-]
Bits (15:0)
0,03 [mg]
[Dec]
0
1000
32000
0
-1000
-32000
1
1023
32767
0
-1024
-32768
s = sign bit
Acceleration bits can be converted to mg acceleration (Acc) using following equation
15
14
13
12
11
10
9
8
7
6
5
4
4
1  s  2  b14  2  b13  2  b12  2  b11  2  b10  2  b9  2  b8  2  b7  2  b6  2  b5  2  b4  2  b3  2 
Acc mg  


32  b2  2 3  b1  21  b0

3.1.5
3.1.5.1
Temperature output
Temperature Register Low (TEMP_LSB)
Address: 12h
Bits
Mode
7:0
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R
Initial
Value
00h
Name
Description
DATA
Data bits [7:0] of temperature sensor.
Read always TEMP_MSB prior to TEMP_LSB.
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3.1.5.2
Temperature Register High (TEMP_MSB)
Address: 13h
Bits
Mode
7:0
R
Initial
Value
00h
Name
Description
DATA
Data bits [15:8] of temperature sensor.
Reading of this register latches TEMP_LSB.
The bit level description of temperature data:
In SCA8X0 temperature data is not factory calibrated and hence sensitivity and offset of
temperature data varies from part to part. Temperature data is in 2's complement format and 14
bits (13:0) of TEMP_MSB/TEMP_LSB are used for temperature. Here is presented temperature
calculation using 10bit but 4-extra LSB bit can be used to improve resolution in noise sense if
needed.
Table 6 Bit level description for SCA8X0 temperature registers
Register
TEMP_MSB
Bit number
B7:B6 B5 B4 B3 B2 B1 B0
Bit temperature weight [°C] xx
sign ~82 ~41 ~21 ~10 ~5.1
Bit in temperature register xx
t9 t8 t7 t6
T5 t4
TEMP_LSB
B7 B6 B5 B4 B3:B0
~2.6 ~1.3 ~0.6 ~0.3 rrrr
t3 t2 t1 t0 rrrr
x = not used bit
r=reserved
TempC   45  32C 
Tempdec
,
LSB
k o
C
where Temp[°C] is temperature in Celsius and Tempdec is temperature from TEMP_MSB and
TEMP_LSB registers in decimal format, bits(t9:0). k is temperature slope factor specified as
k
Min
2.8
Typ
3.1
Max
3.5
Unit
o
LSB/ C
In SCA21X0 and SCA31X0 offset of temperature data is factory calibrated but sensitivity of the
temperature data varies from part to part. Temperature data is in unsigned format and 13 bits
(13:1) of TEMP_MSB/TEMP_LSB are used for temperature. Here is presented temperature
calculation using 10bit but 3-extra LSB bit can be used to improve resolution in noise sense if
needed.
Table 7 Bit level description for SCA21X0/31X0 temperature registers
Register
TEMP_MSB
TEMP_LSB
Bit number
B7:B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3:B0
Bit temperature weight [°C] xx
~162 ~81 ~41 ~20 ~10 ~5.1 ~2.5 ~1.3 ~0.6 ~0.3 rrrx
Bit in temperature register xx
t9
t8 t7 T6 T5 t4 t3 t2 t1 t0 rrrx
x = not used bit
r=reserved
Temperature registers’ typical output at +23 °C is 512 counts and 1 °C change in temperature
typically corresponds to 3.2 LSB change in temperature output. Temperature information is
converted to [°C] as follows
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TempC   23  10C 
Tempdec  512 LSB
,
LSB
k
C
where Temp[°C] is temperature in Celsius and Tempdec is temperature from TEMP_MSB and
TEMP_LSB registers in decimal format, bits(t9:0). k is temperature slope factor specified as
Min
2.8
k
3.1.6
Max
3.6
Unit
o
LSB/ C
Status Register (STATUS)
Address: 2h
Bits
Mode
3.1.7
Typ
3.2
7:3
2
R
Initial
Value
0
Name
1
R
0
CSMERR
0
R
0
FRME
ATEST
Description
Reserved
Analog test mode status
1 – Test mode is active
0 – Test mode is not active
EEPROM Checksum Error. In
SCA21X0/SCA31X0 ST bit of SPI frame is also
set if CSMERR is set.
SPI frame error. Bit is reset, when next correct
SPI frame is received. Bit is also visible in SPI
frame.
Interrupt Status Register (INT_STATUS)
Address: 16h
Bits
Mode
7
6
R
R
Initial
Value
0
0
Name
5
R
0
STS
4
R
0
STC
3:0
R
0000
SAT
Description
Reserved
Saturation status of output data
1 – Over range detected, one or 2-3 of xyz axis is
saturated and output data is not valid.
0 – Data in range
SAT bit is also visible in SPI frame. This bit can be
active after start-up or reset stage before signal
path settles to final value and it has to be
acknowledged in start-up sequence (see Table 3)
or after SW reset or after PORST stage.
Status of gravitation based start-up self test
1 – Failure
0 – No failure
STS sets also ST bit in SPI frame.
Status of continuous self test
1 – Failure
0 – No failure
STC sets also ST bit in SPI frame.
Reserved
The bits in this interrupt status register and corresponding SPI frame bits are cleared after register
has been read. Register reading is treated as interrupt acknowledgement signal. These bits are
kept active even failure condition is over if they are not acknowledged.
This register is not defined in SCA8X0.
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3.2
3.2.1
Operation control registers
Control Register (CTRL)
Address: 1h
Bits
Mode
7
6
RW
RW
Initial
Value
0
0
Name
5
4
RW
RW
0
0
PDOW
SLEEP
3
RW
0
ST
PORST
Description
Reserved
1 means reset state. Bit gets set to 1 when the
digital gets reset by supply off control or under
voltage control. Bit is set after supply off/on
transition or startup. This bit can not be set by SPI
but it can be reset to 0 by writing a 0 over the SPI.
This bit is also sent as Bit3 of SPI output data frame
on MISO.
Set chip to power down mode
Set chip to sleep mode. This bit can not be set to 1
if PDOW is already 1 or if PDOW is being set by the
current SPI command. (bit is not used in SCA8X0)
Set chip to self-test mode.
SCA8X0:
This bit starts mass deflection self-test (see also
ST_CFG bit). This bit is set to 0, when test is
passed. This bit can not be set to 1 if PDOW is
already 1 or if PDOW is being set by the current
SPI command. Test is done automatically during
start-up and acceleration output data can be read
during test.
2
1
RW
RW
0
0
MST
ST_CFG
SCA21X0 and SCA31X0:
Start continuous self-test calculation (STC). This bit
can not be set to 1 if PDOW or SLEEP or MTST is
already 1 or if PDOW or SLEEP or MTST is being
set by the current SPI command. Use
INT_STATUS.STC and ST bit of SPI frame for test
result monitoring.
Memory self-test function is activated, when user
sets bit to ‘1’. This bit is reset to 0 when test is over.
During memory self test, SPI access is prevented
for 85us. This bit can not be set to 1 if PDOW or
SLEEP is already 1 or if PDOW or SLEEP is being
set by the current SPI command. Test is done
automatically during start-up. Set other bits to zero
in CTRL register by previous SPI command before
starting memory self-test by CTRL.MST command.
Use STATUS.CSMERR for test result monitoring
and in SCA21X0/SCA31X0 ST bit in SPI frame.
Self-test configuration.
SCA8X0:
Select direction of mass deflection.
SCA21X0 and SCA31X0:
Start gravitation based start-up self-test calculation
(STS).
This bit can not be set to 1 if PDOW or SLEEP or
MTST is already 1 or if PDOW or SLEEP or MTST
is being set by the current SPI command. STC and
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Bits
Mode
0
3.2.2
RW
7:0
3.3.1
Name
Description
0
MISO
STS have same priority and they can be set and
used simultaneously.
This bit is set to 0 when test is over. Use
INT_STATUS.STS and ST bit of SPI frame for test
result monitoring.
0 = Set MISO line to normal state (= High
impedance state between SPI transfers, data out
state during transfers)
1 = Set MISO like to a continuous high impedance
state (same write command to multiple slaves,
which share MISO line).
Initial
Value
00h
Name
Description
RST
Writing 0C'hex, 05'hex, 0F'hex in this order resets
component.
Initial
Value
1)
23h
2)
22h
Name
Description
REVID
ASIC revision identification number, each ASIC version
has different REVID-number.
Reset Register (RESET)
Address: 3h
Bits
Mode
3.3
Initial
Value
RW
Identification registers
Revision ID (REVID)
Address: 0h
Bits
Mode
7:0
R
1) SCA8X0
2) SCA21X0/SCA31X0
3.3.2
Component ID (ID)
Address: 27h
Bits
Mode
7:0
Initial
Value
RW
Name
Description
ID
Component identification number
(write operation by user is possible to this register but
not to non-volatile memory)
The ID register contains information about the product version and value is loaded from nonvolatile memory. Each Murata Automotive Digital Accelerometer Platform product will have a
unique identification number. Single axis products can be differentiated from multi axis products
through this register.
SCA8X0:
SCA21X0:
SCA31X0:
MSB = 0
MSB = 1
MSB = 1
Please refer to the product data sheet for correct ID number.
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4
SPI Interface
Serial peripheral interface (SPI) is a 4-wire synchronous serial interface. Data communication is
enabled with active low Slave Select or Chip Select wire (CSB). Data is transmitted via 3-wire
interface consisting of serial data input (MOSI), serial data output (MISO) and serial clock (SCK).
Every SPI system consists of one master and one or more slaves, where the master is defined as
the microcomputer that provides the SPI clock, and the slave is any integrated circuit that receives
the SPI clock from the master.
MASTER
MICROCONTROLLER
SLAVE
MOSI
MISO
SCK
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLK (SCK)
CSB0
CSB1
CSB2
CSB3
CSB
MOSI
MISO
SCK
CSB
MOSI
MISO
SCK
CSB
MOSI
MISO
SCK
CSB
Figure 2: Typical SPI connection
The SPI interface of Murata automotive series is designed to support almost any micro controller
that uses software implemented SPI. However it is not designed to support any particular hardware
implemented SPI found in many commercial micro controllers. SCA8X0/SCA21X0/SCA31X0
accelerometer operates always as a slave device in the master-slave operation mode. The data
transfer between the master (P test machine etc.) and accelerometer is performed serially with
four wire system.
MOSI
MISO
SCK
CSB
master out slave in
master in slave out
serial clock
chip select (low active)
µP  ASIC
ASIC  µP
µP  ASIC
µP  ASIC
Each transmission starts with a falling edge on CSB and ends with the rising edge. During the
transmission, commands and data are controlled by SCK and CSB according to the following rules:



commands and data are shifted MSB first LSB last
each output data/status-bits are shifted out on the falling edge of SCK (MISO line)
each bit is sampled on the rising edge of SCK (MOSI line)
SPI communication transfers data between SPI master
SCA8X0/SCA21X0/SCA31X0. Registers can be read and write.
and
registers
of
the
SPI communication is full duplex communication. Data is send and received simultaneously.
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SPI frame format and transfer protocol is presented in Figure 3.
Figure 3: SPI frame format


MOSI




MISO







A5:A0
RB/W
aPAR
DI7:DI0
Register address
Read/Write selection, '0'=read
Odd parity for bits A5:A0, RB/W
Input data for data write
Bit 1
not defined bit
FRME
Frame error indication (previous frame)
Bit 3-5 status bits
 PORST Power On Reset Status
 ST
Self Test error, not defined in SCA8X0
 SAT
Output SATuration indicator, not defined in SCA8X0
Bit 6
always ‘0’, fixed bit
Bit 7
always ‘1’, fixed bit
dPAR
Odd parity for output data (DO7:DO0)
DO7:DO0
Output data
Each communication frame contains 16 bits. Please see Figure 3 for SPI bit definition. The first 8
bits in MOSI line contains info about the operation (read/write) and the register address being
accessed. First 6 bits define 6 bit address for selected operation, which is defined by bit 7 (‘0’ =
read ‘1’ = write), which is followed by odd parity bit (aPAR) for 8 bit pattern. The later 8 bits in MOSI
line contain data for a write operation and are ignored in case of read operation.
The first bits in MISO line are frame error bit (FRME, bit2) of previous frame, reset status bit
(PORST, bit3), self-test status bit (ST, bit4), saturation status (SAT, bit5), fixed zero bit (bit6), fixed
one bit (bit7) and odd parity bit of output data (dPAR, bit8)). Parity is calculated from data, which is
currently sent. The later 8 bits contain data for a read operation. During the write operation, these
data bits are previous data bits of addressed register.
For write commands, data is written into the addressed register on the rising edge of CSB. If the
command frame is invalid, data will not be written into the register.
The output register is shifted out MSB first over MISO output. Attempt to read a reserved register
outputs data of 00h.
When CSB is high state between data transfers, MISO line is in high-impedance state. If bit
CTRL.MISO is set to ‘1’, MISO line is always in high-impedance state. In multi-chip SPI bus master
can send data to all slave chips simultaneously.
4.1
Output of Acceleration Data
16-bit data is sent in 8-bit data bytes during two frames. Each frame contains odd parity bit of data
bits. Number format of acceleration data is two’s complement number.
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4.1.1
Register read operation
An example of X-axis acceleration read command is presented in Figure 4. Master gives the
register address to be read via MOSI line: '05' in hex format and '000101' in binary format, register
th
th
name is X_MSB (X-axis MSB frame). 7 bit is set to '0' to indicate the read operation and 8 bit is 1
for odd parity.
The sensor replies to asked operation by transferring the register content via MISO line. After
transferring the asked X_MSB register content, master gives next register address to be read: '04'
in hex format and '000100' in binary format, register name is X_LSB (X-axis LSB frame). The
sensor replies to asked operation by transferring the register content MSB first.
Figure 4: Example of 16 bit acceleration data transfer from registers DOUT2-1 (05h,04h).
DO15…DO0 bits are acceleration data bits (DO15=MSB) and parity (dPAR) is odd parity of register
of 8 data bits. FRME is possible frame error bit of previous frame, PORST is reset bit, ST is selftest status bit and SAT is output saturation status bit.
4.1.2
Decremented register read operation
In Figure 5 is presented a decremented read operation where the content of four output registers is
read by one SPI frame. After normal register addressing and one register content reading the µC
keeps CSB line low and continues supplying the SCK pulses. After every 8 SCK pulses the output
data address is decremented by one and the previous DOUT register's content is shifted out
without parity bits. Parity bit is calculated and transferred only for the first data frame. From X_LSB
register address the SCA21X0/SCA31X0 jumps to Z_MSB. Decremented reading is possible only
for registers X_LSB ... Z_MSB in SCA21X0 and SCA31X0 series.
Decremented read is not recommended in fail-safe critical applications because output data parity
is only available for first 8bit data.
Figure 5: An example of decremented read operation.
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4.1.3
MOSI data of SPI commands
Table 8: MOSI data during SPI read command
Register to
be read
REVID
CTRL
STATUS
X_LSB
X_MSB
Y_LSB
Y_MSB
Z_LSB
Z_MSB
TEMP_LSB
TEMP_MSB
INT_STATUS
ID
Function
Read ASIC revision ID
Read CTRL register
Read Status register
Read acceleration on X-axis, LSB
Read acceleration on X-axis,
MSB
Read acceleration on Y-axis, LSB
Read acceleration on Y-axis,
MSB
Read acceleration on Z-axis, LSB
Read acceleration on Z-axis,
MSB
Read temperature, LSB
Read temperature, MSB
Read INT_STATUS register
Read product ID number
MOSI (15:0) [bits]
MOSI [hex]
000000 01 xxxxxxxx
000001 00 xxxxxxxx
000010 00 xxxxxxxx
000100 00 xxxxxxxx
000101 01 xxxxxxxx
01xx
04xx
08xx
10xx
15xx
000110 01 xxxxxxxx
000111 00 xxxxxxxx
19xx
1Cxx
001000 00 xxxxxxxx
001001 01 xxxxxxxx
20xx
25xx
010010 01 xxxxxxxx
010011 00 xxxxxxxx
010110 00 xxxxxxxx
100111 01 xxxxxxxx
49xx
4Cxx
58xx
9Dxx
Table 9: MOSI data during write command
4.2
4.2.1
Register to
be written
RESET
RESET
RESET
Function
MOSI (15:0) [bits]
MOSI [hex]
Reset component (data C'hex )
Reset component (data 5'hex )
Reset component (data F'hex )
000011 10 00001100
000011 10 00000101
000011 10 00001111
0E0C
0E05
0E0F
CTRL
CTRL
CTRL
CTRL
Set PORST to zero
Set chip to power down mode
Start self-diagnostic
Start memory self-test
000001 11 00000000
000001 11 00100000
000001 11 00001000
000001 11 00000100
0700
0720
0708
0704
Error Conditioning
FRME-bit
While sending a frame, if CSB is raised to 1 before sending 16 SCKs, the frame is considered
invalid. In SCA8X0 the frame error is raised if number of SCK pulses is not 16. In SCA21X0/3100
the frame error is raised only if number of SCK pulses is not divisible by 8 to support decremented
mode reading. When an invalid frame is received, the last command is simply ignored and the
register contents are left unchanged. Status bit STATUS.FRME is set to indicate this error
condition. During next SPI frame error bit send out as bit number 2. Bit STATUS.FRME will be
reseted, if correct frame is received.
4.2.2
PORST-bit
PORST length is 1bit in SPI frame. PORST bit is set if chip is reseted (HW reset by POR or supply
on/off) or under-voltage is detected. PORST bit is also set after power-up because chip has been in
reset state. PORST can be set to zero (reseted) by writing CTRL.PORST =0. Software (SW) reset
does not set PORST.
When CTRL.PORST bit is written to 0 via SPI, there is 300ns delay before register value is set to
zero.
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4.2.3
ST-bit (SCA21X0 / 3100)
Self-test frame status (ST) is set if STC or STS is alarmed or checksum is not passed.
 CASE 1: Checksum fails and ST-frame bit is set 1. ST is set back to zero when (and only
if) new checksum calculation is passed.

CASE 2: ST-frame bit is set because STC or STS is alarmed. In this case ST-frame bit can
be cleared by INT_STATUS register reading.
ST bit is not defined in SCA8X0 series.
4.2.4
SAT-bit (SCA21X0 / 3100)
Saturation status (SAT) is set if any of axis xyz is saturated and it can be cleared by INT_STATUS
register reading. This bit is kept active even failure condition is over if it is not acknowledged.
Saturation limit varies between different product types. For example:

SCA2100 2 g product: x and y channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to zdirection exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.

SCA2110 2 g product: x and z channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to ydirection exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.

SCA2120 2 g product: y and z channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to xdirection exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.
SAT bit is not defined in SCA8X0 series, but output saturates to the calibrated level. For example
acceleration output data of SCA8x0 2 g products saturates to 2.27 g.
4.2.5
aPAR-bit (SCA21X0 / 3100)
aPAR is odd parity bit of input address+RB/W-bit. Master write it and slave check that bit.
 If there is parity error and RB/W='1', write command is ignored and frame error bit is set to
STATUS-register and to SPI frame. Next correct SPI frame will zero this bit.

If there is parity error and RB/W='0', read command is performed normally and frame error
bit is set to STATUS-register and to SPI frame. Next correct SPI frame will zero this bit.
aPAR bit is not checked in SCA8X0 series.
Table 10: Address parity
A5
0
1
1
0
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A4
0
1
0
1
Address
A3
A2
0
0
1
1
1
0
0
1
Notes
A1
0
1
1
0
A0
0
1
0
1
RB/W
0
1
1
0
aPAR
1
0
1
0
correct frame
correct frame
correct frame
correct frame
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4.2.6
dPAR-bit
dPAR bit is odd parity bit of 8bit data that is currently sent in the frame. Master checks this bit and
compares to received data. Using dPAR at least one bit errors in data transmission can be
detected.
4.2.7
Fixed bits
Bits 6 and 7 are always fixed in MISO line. Bit 6 should always be '0' and bit 7 always '1'
4.2.8
Output data
1. Reset stage: When component is in reset or under voltage state, PORST bit in SPI frame and
CTRL.PORST bit is set. Furthermore, all register values are set to 00'hex.
2. Saturation: When acceleration exceeds measurement range, the output data is saturated to
specified positive or negative full-scale.
3. Self-diagnostic failure: In SCA21X0 and 31X0 the ST bit in SPI frame is set when memory
diagnostic or signal path diagnostic functions fail. Furthermore acceleration output data is
forced to 7FFF'hex if memory diagnostic fails or to FFFF'hex if signal path diagnostic functions
(STC/STS) fail.
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5
Electrical Characteristics
All voltages are referenced to ground. Currents flowing into the circuit have positive values.
5.1
Absolute maximum ratings
The absolute maximum ratings of Digital Family are presented in Table 11 below.
Table 11: Absolute maximum ratings
Parameter
Supply voltage (Vdd)
Voltage at input / output pins
ESD (Human body model)
Storage temperature
Operating temperature
Ultrasonic cleaning
5.2
Power Supply
5.3
Digital I/O Specification
5.3.1
Value
-0.3 to +3.6
-0.3 to (Vdd + 0.3)
±2
-40 ... +125
-40 ... +125
Unit
V
V
kV
°C
°C
Not allowed
DC Characteristics
Supply voltage is 3.3 V unless otherwise noted. Current flowing into the circuit has positive values.
Parameter
Conditions
Symbol
Min
Typ
Max
Input terminal CSB
1
Pull up current
VIN = 0 V
IPU
10
50
DVDD
2
Input high voltage
DVDD = 3.3 V
VIH
2
3
Input low voltage
DVDD = 3.3 V
VIL
0.8
4
Hysteresis
DVDD = 3.3 V
VHYST
0.18
Input terminal MOSI, SCK
5
Pull down current
VIN = 3.3 V
IPD
10
50
DVDD
6
Input high voltage
DVDD = 3.3 V
VIH
2
7
Input low voltage
DVDD = 3.3 V
VIL
0.8
8
Hysteresis
DVDD = 3.3 V
VHYST
0.18
Output terminal MISO
9
Output high voltage
I > -1mA
VOH
DVDD –
DVDD = 3.3 V
0.5
10
Output low voltage
I < 1 mA
VOL
0.5
11
Tri-state leakage
0 < VMISO < 3.3 V
ILEAK
-3
3
5.3.2
Conditions
3
4
SCK high time
2
A
V
V
V
A
V
V
V
V
V
uA
AC Characteristics
Parameter
Terminal CSB, SCK
Time from CSB (10%) to
SCK (90%)
Time from SCK (10%) to
CSB (90%)
Terminal SCK
SCK low time
1
Unit
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Symbol
Min
Typ
Max
Unit
TLS1
63
ns
TLS2
63
ns
Load capacitance at
MISO < 50 pF
tr=rise time
tf=fall time
TCL
60
Tper/2 –
(tr+tf)/2
ns
Load capacitance at
MISO < 50 pF
TCH
60
Tper/2 –
(tr+tf)/2
ns
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5
SCK Frequency
6
7
8
9
10
11
fsck =
1/Tper
Terminal MOSI, SCK
Time from changing
MOSI (10%, 90%) to
SCK (90%). Data setup
time
Time from SCK (90%) to
changing MOSI (10%,
90%). Data hold time
Terminal MISO, CSB
Time from CSB (10%) to
stable MISO (10%, 90%)
Time from CSB (90%) to
high impedance state of
MISO.
Terminal MISO, SCK
Time from SCK (10%) to
stable MISO (10%,
90%).
Terminal CSB
Time between SPI
cycles, CSB at high level
(90%)
TLS1
8
MHz
TSET
32
ns
THOL
32
ns
Load capacitance at
MISO < 50 pF
Load capacitance at
MISO < 50 pF
TVAL1
32
ns
TLZ
32
ns
Load capacitance at
MISO < 50 pF
TVAL2
41
ns
TLH
TCH
125
TCL
TLS2
ns
TLH
CSB
SCK
THOL
MOSI
MSB in
TVAL1
MISO
TSET
DATA in
LSB in
TVAL2
MSB out
TLZ
DATA out
LSB out
Figure 6: Timing diagram of SPI communication
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6
6.1
Application information
Package dimensions
The package dimensions are presented in the Figure 7 below (measures in mm with ±0.1 mm
tolerance). The part weights < 0.35 g.
Figure 7: Package dimensions
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6.2
Output to Angle Conversion
Product output is function of sin and it can be transferred to angle using the following equation for
conversion:
 Output LSB  Offset 0 g
Sensitivit y

  arcsin 

,

Where OutputLSB is output in g, Offset0g is offset at 0 g position and sensitivity is sensitivity of
product. Nominal sensitivity is determined at datasheet of product and 0 g can be used in Offset0g if
not measured after installation. To read output of product refer chapter Output Data Conversion.
Angles close to 0° inclination can be estimated quite accurately with straight line conversion but for
the best possible accuracy, arcsine conversion is recommended to be used. The following table
shows the angle measurement error if straight line conversion is used.
Straight line conversion equation:
 Output LSB  Offset 0 g
Sensitivit y

  

,

Where OutputLSB is output in g, Offset0g is offset at 0 g position and sensitivity is sensitivity of
product.
Tilt angle [°]
0
1
2
3
4
5
10
15
30
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Straight line conversion error [°]
0
0.0027
0.0058
0.0094
0.0140
0.0198
0.0787
0.2185
1.668
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6.3
Measuring Directions
X [mg]
ARCSIN(X) [o]
Y [mg]
o
ARCSIN(Y) [ ]
Z [mg]
ARCSIN(Z) [o]
1
0
0
0
0
1000
90
2
0
0
-707
-45
707
45
3
0
0
-1000
-90
0
0
4
0
0
-707
-45
-707
-45
X [mg]
ARCSIN(X) [o]
Y [mg]
o
ARCSIN(Y) [ ]
Z [mg]
ARCSIN(Z) [o]
5
0
0
0
0
-1000
-90
6
0
0
707
45
-707
-45
7
0
0
1000
90
0
0
8
0
0
707
45
707
45
Measuring direction of Z and Y axis of ADP-product and output in mg and degree
1
X [mg]
o
ARCSIN(X) [ ]
Y [mg]
o
ARCSIN(Y) [ ]
Z [mg]
o
ARCSIN(Z) [ ]
2
1000
90
0
0
0
0
5
X [mg]
o
ARCSIN(X) [ ]
Y [mg]
o
ARCSIN(Y) [ ]
Z [mg]
ARCSIN(Z) [o]
3
707
45
-707
-45
0
0
6
-1000
-90
0
0
0
0
4
0
0
-1000
-90
0
0
7
-707
-45
707
45
0
0
-707
-45
-707
-45
0
0
8
0
0
1000
90
0
0
707
45
707
45
0
0
Measuring direction of Z and Y axis of ADP-product and output in mg and degree
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6.4
Pin Description
1
2
3
4
5
6
12
11
10
9
8
7
Figure 8: Component pinout
No.
1
2
3
4
5
6
7
8
9
10
11
12
Table 12: Component pinout
1)
2)
Name
Type
PD/PU
Reserved
Reserved
PD
AVSS
AI
AVDD
AI
CSB
DI
PU
MISO
ZO
SCK
DI
PD
MOSI
DI
PD
PWM
ADO
DVDD
AI
DVSS
AI
EGnd
AI
Function
Not used
Factory use
Negative power supply (analog)
Positive power supply (analog)
Chip select
Data output
Serial clock
Data input
Pulse Width Modulation output
Positive power supply (digital)
Negative power supply (digital)
EMC ground
Connect
Gnd
Gnd
Gnd
Vdd
CSB
MISO
SCK
MOSI
3)
N.C. or PWM
Vdd
Gnd
Gnd
Notes:
1) A=Analog, D=Digital, I=Input, O=Output, Z=Tristate Output
2) PU=internal pullup, PD=internal pulldown
3) PWM output in some SCA8X0 products, N.C.= Not Connected
PWM pin is driven to '0' after start-up when PWM is disabled. During the mass deflection self-test
(STE) PWM pin goes to '1' and returns to '0' when STE is completed. In case of STE failure PWM
output will stay at '1'
6.5
Recommended circuit diagram
Recommended circuit diagram for all product family components with SPI interface is shown in
Figure 9. Following design rules and recommendations should be considered to achieve maximum
performance:
Required:
1
Connect (C4) 100 nF (ESR < 1) capacitor between AVDD and AVSS
2
Connect (C5) 100 nF (ESR < 1) capacitor between DVDD and DVSS
3
Use one power supply VDD for AVDD and DVDD (AVDD voltage level has to
be raised always same time or after DVDD during power up sequence)
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Recommended for improved PSRR (Note 1 in Figure 9):
4
Connect (C6) 10 µF capacitor between AVDD and AVSS
5
Connect serial resistance (R1) 10 Ω between VDD and AVDD/DVDD
 Specified operation voltage (VDD) range 3.05...3.6 V
6
To achieve high EMC DPI performance, add serial inductance (L1) to VDD line
before serial resistance (for example Murata: BLM18HG102S)
VDD
Note 1
L1
R1
10 Ω
C6
10 µF
C4
CSB
MISO
SCA8x0
SCA21x0
SCA3100
100 nF
1
2
3
4
5
6
NC
EGND
NC
DVSS
AVSS
DVDD
AVDD
PWM
CSB
MOSI
MISO
SCK
12
2
11
10
9
8
7
C5
100 nF
MOSI
SCK
Figure 9: Recommended circuit diagram
6.6
Recommended PWB layout
Recommended PWB layout for all product family components with SPI interface is shown in Figure
10 and Figure 11. Following design rules and recommendations should be considered:
Required:
1
Connect (C4) 100 nF SMD capacitor between AVDD and AVSS right next to
component pins AVDD and AVSS
2
Connect (C5) 100 nF SMD capacitor between DVDD and DVSS right next to
component pins DVDD and DVSS
3
Use separate ground levels AVSS and DVSS under and near the component
but connect them together on the PCB, see Figure 10
4
Locate ground plate under component
5
Do not route signals or power supplies under the component on top layer
6
Ensure good ground connection of Egnd (pin12) to AVSS
Recommended:
7
Locate digital ground under digital signal lines
8
Do not route digital signals one upon the other for long distance
9
Avoid crossing of AVDD path with digital signal especially between serial
resistance R1 and AVDD pin
10 Do not route digital signals under the component on 2nd layer
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Figure 10: Recommended PWB layout for product family components with SPI interface (Top
layer, Not actual size, for reference only)
Figure 11: Recommended PWB layout for product family components with SPI interface (2nd
layer, Not actual size, for reference only)
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Recommended PWB pad layout is presented in the Figure 12 below (dimensions in mm).
Figure 12: Component pad layout
6.7
Assembly instructions
The Moisture Sensitivity Level (MSL) of the component is 3 according to the IPC/JEDEC J-STD020C. Please refer to the document "TN53 Assembly Instructions for Dual Flat Lead Package" for
more detailed information of the assembly.
6.8
Tape and reel specifications
Please refer to the document "TN53 Assembly Instructions for Dual Flat Lead Package" for tape
and reel specifications.
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