LM75B

LM75B

Digital temperature sensor and thermal watchdog

Rev. 02 — 9 December 2008 Product data sheet

1.

General description

The LM75B is a temperature-to-digital converter using an on-chip band gap temperature sensor and Sigma-Delta A-to-D conversion technique with an overtemperature detection output. The LM75B contains a number of data registers: Configuration register (Conf) to store the device settings such as device operation mode, OS operation mode, OS polarity and OS fault queue as described in

Section 7 “Functional description” ; temperature

register (Temp) to store the digital temp reading, and set-point registers (Tos and Thyst) to store programmable overtemperature shutdown and hysteresis limits, that can be communicated by a controller via the 2-wire serial I

2

C-bus interface. The device also includes an open-drain output (OS) which becomes active when the temperature exceeds the programmed limits. There are three selectable logic address pins so that eight devices can be connected on the same bus without address conflict.

The LM75B can be configured for different operation conditions. It can be set in normal mode to periodically monitor the ambient temperature, or in shutdown mode to minimize power consumption. The OS output operates in either of two selectable modes:

OS comparator mode or OS interrupt mode. Its active state can be selected as either

HIGH or LOW. The fault queue that defines the number of consecutive faults in order to activate the OS output is programmable as well as the set-point limits.

The temperature register always stores an 11-bit 2's complement data giving a temperature resolution of 0.125

°

C. This high temperature resolution is particularly useful in applications of measuring precisely the thermal drift or runaway. When the LM75B is accessed the conversion in process is not interrupted (i.e., the I

2

C-bus section is totally independent of the Sigma-Delta converter section) and accessing the LM75B continuously without waiting at least one conversion time between communications will not prevent the device from updating the Temp register with a new conversion result. The new conversion result will be available immediately after the Temp register is updated.

The LM75B powers up in the normal operation mode with the OS in comparator mode, temperature threshold of 80

°

C and hysteresis of 75

°

C, so that it can be used as a stand-alone thermostat with those pre-defined temperature set points.

2.

Features

n

Pin-for-pin replacement for industry standard LM75 and LM75A and offers improved temperature resolution of 0.125

°

C and specification of a single part over power supply range from 2.8 V to 5.5 V n

I

2

C-bus interface with up to 8 devices on the same bus n

Power supply range from 2.8 V to 5.5 V n

Temperatures range from

−

55

°

C to +125

°

C

NXP Semiconductors

LM75B


n

Frequency range 20 Hz to 400 kHz with bus fault time-out to prevent hanging up the bus n

11-bit ADC that offers a temperature resolution of 0.125

°

C n

Temperature accuracy of: u

±

2

°

C from

−

25

°

C to +100

°

C u

±

3

°

C from

−

55

°

C to +125

°

C n

Programmable temperature threshold and hysteresis set points n

Supply current of 1.0

µ

A in shutdown mode for power conservation n

Stand-alone operation as thermostat at power-up n

ESD protection exceeds 4500 V HBM per JESD22-A114, 450 V MM per

JESD22-A115 and 2000 V CDM per JESD22-C101 n

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n

Small 8-pin package types: SO8, TSSOP8 and 3 mm

×

2 mm XSON8U

3.

Applications

n

System thermal management n

Personal computers n

Electronics equipment n

Industrial controllers

4.

Ordering information

Table 1.

Ordering information

Type number

Topside mark

Package

Name

LM75BD

LM75BDP

LM75BGD

Description

XSON8U plastic extremely thin small outline package; no leads; 8 terminals;

UTLP based; body 3

×

2

×

0.5 mm

Version

LM75BD SO8

LM75B TSSOP8 plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT96-1

SOT505-1

75B SOT996-2

LM75B_2

Product data sheet Rev. 02 — 9 December 2008

© NXP B.V. 2008. All rights reserved.

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LM75B


5.

Block diagram

V

CC

LM75B

BIAS

REFERENCE

BAND GAP

TEMP SENSOR

OSCILLATOR

POWER-ON

RESET

11-BIT

SIGMA-DELTA

A-to-D

CONVERTER

LOGIC CONTROL AND INTERFACE

POINTER

REGISTER

COUNTER

TIMER

COMPARATOR/

INTERRUPT

CONFIGURATION

REGISTER

TEMPERATURE

REGISTER

TOS

REGISTER

THYST

REGISTER

002aad453

GND A2 A1 A0

Fig 1.

Block diagram of LM75B

SCL SDA

6.

Pinning information

6.1 Pinning

OS

LM75B_2

Product data sheet

SDA 1

SCL 2

OS 3

GND 4

LM75BD

8 V

CC

7 A0

6 A1

5 A2

002aad454

Fig 2.

Pin configuration for SO8

SDA

SCL

OS

GND

3

4

1

2

LM75BDP

8

7

6

5

V

CC

A0

A1

A2

002aad455

Fig 3.

Pin configuration for TSSOP8

SDA 1

SCL 2

OS 3

GND 4

8 V

CC

7 A0

LM75BGD

Transparent top view

6 A1

5 A2

002aae234

Fig 4.

Pin configuration for XSON8U

Rev. 02 — 9 December 2008


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LM75B


6.2 Pin description

Table 2.

Pin description

Symbol

SDA

Pin

1

SCL

OS

GND

A2

2

3

4

5

A1

A0

V

CC

6

7

8

Description

Digital I/O. I

2

C-bus serial bidirectional data line; open-drain.

Digital input. I

2

C-bus serial clock input.

Overtemp Shutdown output; open-drain.

Ground. To be connected to the system ground.

Digital input. User-defined address bit 2.



Power supply.

7.

Functional description

7.1 General operation

The LM75B uses the on-chip band gap sensor to measure the device temperature with the resolution of 0.125

°

C and stores the 11-bit 2's complement digital data, resulted from

11-bit A-to-D conversion, into the device Temp register. This Temp register can be read at any time by a controller on the I

2

C-bus. Reading temperature data does not affect the conversion in progress during the read operation.

The device can be set to operate in either mode: normal or shutdown. In normal operation mode, the temp-to-digital conversion is executed every 100 ms and the Temp register is updated at the end of each conversion. During each ‘conversion period’ (T conv

) of about

100 ms the device takes only about 10 ms, called ‘temperature conversion time’ (t conv(T)

), to complete a temperature-to-data conversion and then becomes idle for the time remaining in the period. This feature is implemented to significantly reduce the device power dissipation. In shutdown mode, the device becomes idle, data conversion is disabled and the Temp register holds the latest result; however, the device I

2

C-bus interface is still active and register write/read operation can be performed. The device operation mode is controllable by programming bit B0 of the configuration register. The temperature conversion is initiated when the device is powered-up or put back into normal mode from shutdown.

In addition, at the end of each conversion in normal mode, the temperature data (or Temp) in the Temp register is automatically compared with the overtemperature shutdown threshold data (or T th(ots)

) stored in the Tos register, and the hysteresis data (or T hys

) stored in the Thyst register, in order to set the state of the device OS output accordingly.

The device Tos and Thyst registers are write/read capable, and both operate with 9-bit

2's complement digital data. To match with this 9-bit operation, the Temp register uses only the 9 MSB bits of its 11-bit data for the comparison.

The way that the OS output responds to the comparison operation depends upon the OS operation mode selected by configuration bit B1, and the user-defined fault queue defined by configuration bits B3 and B4.

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LM75B


In OS comparator mode, the OS output behaves like a thermostat. It becomes active when the Temp exceeds the T th(ots)

, and is reset when the Temp drops below the T hys

.

Reading the device registers or putting the device into shutdown does not change the state of the OS output. The OS output in this case can be used to control cooling fans or thermal switches.

In OS interrupt mode, the OS output is used for thermal interruption. When the device is powered-up, the OS output is first activated only when the Temp exceeds the T th(ots)

; then it remains active indefinitely until being reset by a read of any register. Once the OS output has been activated by crossing T th(ots) and then reset, it can be activated again only when the Temp drops below the T hys

; then again, it remains active indefinitely until being reset by a read of any register. The OS interrupt operation would be continued in this sequence:

T th(ots) trip, Reset, T hys trip, Reset, T th(ots) trip, Reset, T hys trip, Reset, etc. Putting the device into the shutdown mode by setting the bit 0 of the configuration register also resets the OS output.

In both cases, comparator mode and interrupt mode, the OS output is activated only if a number of consecutive faults, defined by the device fault queue, has been met. The fault queue is programmable and stored in the two bits, B3 and B4, of the Configuration register. Also, the OS output active state is selectable as HIGH or LOW by setting accordingly the configuration register bit B2.

At power-up, the device is put into normal operation mode, the T th(ots)

is set to 80

°

C, the

T hys is set to 75

°

C, the OS active state is selected LOW and the fault queue is equal to 1.

The temp reading data is not available until the first conversion is completed in about

100 ms.

The OS response to the temperature is illustrated in

Figure 5

.

LM75B_2


T th(ots)

T hys reading temperature limits

OS reset

OS active

OS output in comparator mode

OS reset

OS active

(1) (1) (1)

OS output in interrupt mode

002aae334

(1) OS is reset by either reading register or putting the device in shutdown mode. It is assumed that the fault queue is met at each T th(ots)

and T hys

crossing point.

Fig 5.

OS response to temperature

Rev. 02 — 9 December 2008


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LM75B


7.2 I

2

C-bus serial interface

The LM75B can be connected to a compatible 2-wire serial interface I

2

C-bus as a slave device under the control of a controller or master device, using two device terminals, SCL and SDA. The controller must provide the SCL clock signal and write/read data to/from the device through the SDA terminal. Notice that if the I

2

C-bus common pull-up resistors have not been installed as required for I

2

C-bus, then an external pull-up resistor, about 10 k

Ω

, is needed for each of these two terminals. The bus communication protocols are described in

Section 7.10

.

7.2.1 Bus fault time-out

If the SDA line is held LOW for longer than t to

(75 ms minimum / 13.3 Hz; guaranteed at

50 ms minimum / 20 Hz), the LM75B will reset to the idle state (SDA released) and wait for a new START condition. This ensures that the LM75B will never hang up the bus should there be conflict in the transmission sequence.

7.3 Slave address

The LM75B slave address on the I

2

C-bus is partially defined by the logic applied to the device address pins A2, A1 and A0. Each of them is typically connected either to GND for logic 0, or to V

CC

for logic 1. These pins represent the three LSB bits of the device 7-bit address. The other four MSB bits of the address data are preset to ‘1001’ by hard wiring inside the LM75B.

Table 3 shows the device’s complete address and indicates that up to

8 devices can be connected to the same bus without address conflict. Because the input pins, SCL, SDA and A2 to A0, are not internally biased, it is important that they should not be left floating in any application.

Table 3.

Address table

1 = HIGH; 0 = LOW.

MSB

1 0 0 1 A2 A1

LSB

A0

7.4 Register list

The LM75B contains four data registers beside the pointer register as listed in

Table 4

.

The pointer value, read/write capability and default content at power-up of the registers are also shown in

Table 4 .

Table 4.

Register table

Register name

Pointer value

R/W

Conf 01h R/W

Temp

Tos

Thyst

00h

03h

02h

POR state

00h

Description

read only

R/W

R/W n/a

Configuration register: contains a single 8-bit data byte; to set the device operating condition; default = 0.

Temperature register: contains two 8-bit data bytes; to store the measured Temp data.

5000h Overtemperature shutdown threshold register: contains two 8-bit data bytes; to store the overtemperature shutdown T th(ots)

limit; default = 80

°

C.

4B00h Hysteresis register: contains two 8-bit data bytes; to store the hysteresis T hys

limit; default = 75

°

C.

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LM75B


7.4.1 Pointer register

The Pointer register contains an 8-bit data byte, of which the two LSB bits represent the pointer value of the other four registers, and the other 6 MSB bits are equal to 0, as shown in

Table 5 and Table 6 . The Pointer register is not accessible to the user, but is used to

select the data register for write/read operation by including the pointer data byte in the bus command.

Table 5.

Pointer register

B7 B6 B5

0 0 0

B4

0

B3

0

B2

0

B[1:0]

pointer value

0

1

1

Table 6.

Pointer value

B1

0

B0

0

Selected register

Temperature register (Temp)

1

0

1

Configuration register (Conf)

Hysteresis register (Thyst)

Overtemperature shutdown register (Tos)

Because the Pointer value is latched into the Pointer register when the bus command

(which includes the pointer byte) is executed, a read from the LM75B may or may not include the pointer byte in the statement. To read again a register that has been recently read and the pointer has been preset, the pointer byte does not have to be included. To read a register that is different from the one that has been recently read, the pointer byte must be included. However, a write to the LM75B must always include the pointer byte in the statement. The bus communication protocols are described in

Section 7.10

.

At power-up, the Pointer value is equal to 00 and the Temp register is selected; users can then read the Temp data without specifying the pointer byte.

7.4.2 Configuration register

The Configuration register (Conf) is a write/read register and contains an 8-bit non-complement data byte that is used to configure the device for different operation conditions.

Table 7 shows the bit assignments of this register.

Table 7.

Conf register

Legend: * = default value.

Bit

B[7:5]

Symbol

reserved

Access Value Description

R/W 000* reserved for manufacturer’s use; should be kept as zeroes for normal operation

B[4:3] OS_F_QUE[1:0] R/W OS fault queue programming

00*

01

10

11 queue value = 1 queue value = 2 queue value = 4 queue value = 6

B2 OS_POL R/W

0*

1

OS polarity selection

OS active LOW

OS active HIGH

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LM75B


Table 7.

Conf register

…continued

Legend: * = default value.

Bit

B1

Symbol Access Value Description

OS_COMP_INT R/W OS operation mode selection

B0 SHUTDOWN R/W

0*

1

0*

1

OS comparator

OS interrupt device operation mode selection normal shutdown

7.4.3 Temperature register

The Temperature register (Temp) holds the digital result of temperature measurement or monitor at the end of each analog-to-digital conversion. This register is read-only and contains two 8-bit data bytes consisting of one Most Significant Byte (MSByte) and one

Least Significant Byte (LSByte). However, only 11 bits of those two bytes are used to store the Temp data in 2’s complement format with the resolution of 0.125

°

C.

Table 8

shows the bit arrangement of the Temp data in the data bytes.

Table 8.

Temp register

MSByte LSByte

7 6 5 4 3 2 1 0 7 6 5 4

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X

3

X

2

X

1

X

0

X

When reading register Temp, all 16 bits of the two data bytes (MSByte and LSByte) are provided to the bus and must be all collected by the controller to complete the bus operation. However, only the 11 most significant bits should be used, and the 5 least significant bits of the LSByte are zero and should be ignored. One of the ways to calculate the Temp value in

°

C from the 11-bit Temp data is:

1. If the Temp data MSByte bit D10 = 0, then the temperature is positive and Temp value

(

°

C) = +(Temp data)

×

0.125

°

C.

2. If the Temp data MSByte bit D10 = 1, then the temperature is negative and

Temp value (

°

C) =

−

(2’s complement of Temp data)

×

0.125

°

C.

Examples of the Temp data and value are shown in

Table 9 .

Table 9.

Temp register value

11-bit binary

(2’s complement)

Hexadecimal value

011 1111 1000 3F8

011 1111 0111

011 1111 0001

011 1110 1000

000 1100 1000

3F7

3F1

3E8

0C8

000 0000 0001

000 0000 0000

111 1111 1111

001

000

7FF

Decimal value

1016

1015

1009

1000

200

1

0

−

1

Value

+127.000

°

C

+126.875

°

C

+126.125

°

C

+125.000

°

C

+25.000

°

C

+0.125

°

C

0.000

°

C

−

0.125

°

C

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LM75B


Table 9.

Temp register value

…continued

11-bit binary


Hexadecimal value

111 0011 1000 738

110 0100 1001

110 0100 1000

649

648

Decimal value

−

200

−

439

−

440

Value

−

25.000

°

C

−

54.875

°

C

−

55.000

°

C

For 9-bit Temp data application in replacing the industry standard LM75, just use only

9 MSB bits of the two bytes and disregard 7 LSB of the LSByte. The 9-bit Temp data with

0.5

°

C resolution of the LM75B is defined exactly in the same way as for the standard

LM75 and it is here similar to the Tos and Thyst registers.

The only MSByte of the temperature can also be read with the use of a one-byte reading command. Then the temperature resolution will be 1.00

°

C instead.

7.4.4 Overtemperature shutdown threshold (Tos) and hysteresis (Thyst) registers

These two registers, are write/read registers, and also called set-point registers. They are used to store the user-defined temperature limits, called overtemperature shutdown threshold (T th(ots)

) and hysteresis temperature (T hys

), for the device watchdog operation.

At the end of each conversion the Temp data will be compared with the data stored in these two registers in order to set the state of the device OS output; see

Section 7.1

.

Each of the set-point registers contains two 8-bit data bytes consisting of one MSByte and one LSByte the same as register Temp. However, only 9 bits of the two bytes are used to store the set-point data in 2’s complement format with the resolution of 0.5

°

C.

Table 10

and

Table 11 show the bit arrangement of the Tos data and Thyst data in the data bytes.

Notice that because only 9-bit data are used in the set-point registers, the device uses only the 9 MSB of the Temp data for data comparison.

Table 10.

Tos register

MSByte LSByte

7 6 5 4 3 2 1 0 7 6

D8 D7 D6 D5 D4 D3 D2 D1 D0 X

5

X

4

X

3

X

2

X

1

X

0

X

Table 11.

Thyst register

MSByte LSByte

7 6 5 4 3 2 1 0 7 6

D8 D7 D6 D5 D4 D3 D2 D1 D0 X

5

X

4

X

3

X

2

X

1

X

0

X

When a set-point register is read, all 16 bits are provided to the bus and must be collected by the controller to complete the bus operation. However, only the 9 most significant bits should be used and the 7 LSB of the LSByte are equal to zero and should be ignored.

Table 12 shows examples of the limit data and value.

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LM75B


Table 12.

Tos and Thyst limit data and value

11-bit binary


Hexadecimal value Decimal value

0 1111 1010 0FA 250

0 0011 0010

0 0000 0001

0 0000 0000

1 1111 1111

1 1100 1110

1 1001 0010

032

001

000

1FF

1CE

192

50

1

0

−

1

−

50

−

110

Value

+125.0

°

C

+25.0

°

C

+0.5

°

C

0.0

°

C

−

0.5

°

C

−

25.0

°

C

−

55.0

°

C

7.5 OS output and polarity

The OS output is an open-drain output and its state represents results of the device watchdog operation as described in

Section 7.1

. In order to observe this output state, an external pull-up resistor is needed. The resistor should be as large as possible, up to

200 k

Ω

, to minimize the Temp reading error due to internal heating by the high OS sinking current.

The OS output active state can be selected as HIGH or LOW by programming bit B2

(OS_POL) of register Conf: setting bit OS_POL to logic 1 selects OS active HIGH and setting bit B2 to logic 0 sets OS active LOW. At power-up, bit OS_POL is equal to logic 0 and the OS active state is LOW.

7.6 OS comparator and interrupt modes

As described in

Section 7.1

, the device OS output responds to the result of the comparison between register Temp data and the programmed limits, in registers Tos and

Thyst, in different ways depending on the selected OS mode: OS comparator or

OS interrupt. The OS mode is selected by programming bit B1 (OS_COMP_INT) of register Conf: setting bit OS_COMP_INT to logic 1 selects the OS interrupt mode, and setting to logic 0 selects the OS comparator mode. At power-up, bit OS_COMP_INT is equal to logic 0 and the OS comparator is selected.

The main difference between the two modes is that in OS comparator mode, the OS output becomes active when Temp has exceeded T th(ots)

and reset when Temp has dropped below T hys

, reading a register or putting the device into shutdown mode does not change the state of the OS output; while in OS interrupt mode, once it has been activated either by exceeding T th(ots)

or dropping below T hys

, the OS output will remain active indefinitely until reading a register, then the OS output is reset.

Temperature limits T th(ots)

and T hys

must be selected so that T th(ots)

> T hys

. Otherwise, the

OS output state will be undefined.

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7.7 OS fault queue

Fault queue is defined as the number of faults that must occur consecutively to activate the OS output. It is provided to avoid false tripping due to noise. Because faults are determined at the end of data conversions, fault queue is also defined as the number of consecutive conversions returning a temperature trip. The value of fault queue is selectable by programming the two bits B4 and B3 (OS_F_QUE[1:0]) in register Conf.

Notice that the programmed data and the fault queue value are not the same.

Table 13

shows the one-to-one relationship between them. At power-up, fault queue data = 0 and fault queue value = 1.

0

1

1

Table 13.

Fault queue table

Fault queue data

OS_F_QUE[1]

0

1

0

OS_F_QUE[0]

0

1

2

4

6

Fault queue value

Decimal

1

7.8 Shutdown mode

The device operation mode is selected by programming bit B0 (SHUTDOWN) of register

Conf. Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting bit SHUTDOWN to logic 0 will return the device to normal mode.

In shutdown mode, the device draws a small current of approximately 1.0

µ

A and the power dissipation is minimized; the temperature conversion stops, but the I

2

C-bus interface remains active and register write/read operation can be performed. When the shutdown is set, the OS output will be unchanged in comparator mode and reset in interrupt mode.

7.9 Power-up default and power-on reset

The LM75B always powers-up in its default state with:

•

Normal operation mode

•

OS comparator mode

•

T th(ots)

= 80

°

C

•

T hys

= 75

°

C

•

OS output active state is LOW

•

Pointer value is logic 00 (Temp)

When the power supply voltage is dropped below the device power-on reset level of approximately 1.0 V (POR) for over 2

µ s and then rises up again, the device will be reset to its default condition as listed above.

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7.10 Protocols for writing and reading the registers

The communication between the host and the LM75B must strictly follow the rules as defined by the I

2

C-bus management. The protocols for LM75B register read/write operations are illustrated in

Figure 6

to

Figure 11 together with the following definitions:

1. Before a communication, the I

2

C-bus must be free or not busy. It means that the SCL and SDA lines must both be released by all devices on the bus, and they become

HIGH by the bus pull-up resistors.

2. The host must provide SCL clock pulses necessary for the communication. Data is transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by

1-bit status of the acknowledgement.

3. During data transfer, except the START and STOP signals, the SDA signal must be stable while the SCL signal is HIGH. It means that the SDA signal can be changed only during the LOW duration of the SCL line.

4. S: START signal, initiated by the host to start a communication, the SDA goes from

HIGH to LOW while the SCL is HIGH.

5. RS: RE-START signal, same as the START signal, to start a read command that follows a write command.

6. P: STOP signal, generated by the host to stop a communication, the SDA goes from

LOW to HIGH while the SCL is HIGH. The bus becomes free thereafter.

7. W: write bit, when the write/read bit = LOW in a write command.

8. R: read bit, when the write/read bit = HIGH in a read command.

9. A: device acknowledge bit, returned by the LM75B. It is LOW if the device works properly and HIGH if not. The host must release the SDA line during this period in order to give the device the control on the SDA line.

10. A’: master acknowledge bit, not returned by the device, but set by the master or host in reading 2-byte data. During this clock period, the host must set the SDA line to

LOW in order to notify the device that the first byte has been read for the device to provide the second byte onto the bus.

11. NA: Not Acknowledge bit. During this clock period, both the device and host release the SDA line at the end of a data transfer, the host is then enabled to generate the

STOP signal.

12. In a write protocol, data is sent from the host to the device and the host controls the

SDA line, except during the clock period when the device sends the device acknowledgement signal to the bus.

13. In a read protocol, data is sent to the bus by the device and the host must release the

SDA line during the time that the device is providing data onto the bus and controlling the SDA line, except during the clock period when the master sends the master acknowledgement signal to the bus.

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LM75B


1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL

SDA S 1 0 0 1 A2 A1 A0 W A

START device address write device acknowledge

0 0 0 0 0 pointer byte

0 0 device acknowledge

1 A 0 0 0 D4 D3 D2 D1 D0 A configuration data byte device acknowledge

P

STOP

001aad624

Fig 6.

Write configuration register (1-byte data)

SCL

SDA S

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 1 A2 A1 A0 W A

(next)

0 0 0 0 0 0 0 1 A RS (next)

SCL (cont.)


1 2 3 4 5 6 7 8

SDA (cont.) 1 0 0

9 1 2 3 pointer byte

4 5 acknowledge

6 device

7 8 9

1 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 NA P

RE-START device address read device acknowledge data byte from device master not acknowledged

STOP

001aad625

Fig 7.

Read configuration register including pointer byte (1-byte data)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL

SDA

S

1 0 0 1 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 NA

START device address read device acknowledge data byte from device master not acknowledged

P

STOP

001aad626

Fig 8.

Read configuration or temp register with preset pointer (1-byte data)

LM75B_2



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LM75B


SCL

SDA S

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 1 A2 A1 A0 W A 0 0 0 0 0 0 P1 P0 A

SCL (cont.)


1 2 3 4 5 6 7 8 pointer byte

9 1 2 3 4 5 device acknowledge

6 7 8 9

(next)

(next)

SDA (cont.) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A

MSByte data LSByte data device acknowledge device acknowledge

P

STOP

002aad036

Fig 9.

Write Tos or Thyst register (2-byte data)

SCL

SDA S

1 2 3 4 5 6 7 8 9

1 0 0 1 A2 A1 A0 W A

1 2 3 4 5 6 7 8 9 0

(next)

0 0 0 0 0 0 P1 P0 A RS (next)

SCL (cont)

SDA (cont) device address pointer byte

START write device acknowledge

RE-START device acknowledge

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 1 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A' D7 D6 D5 D4 D3 D2 D1 D0 NA P device address read device acknowledge

MSByte from device master acknowledge

LSByte from device master not

acknowledged

STOP

002aad037

Fig 10. Read Temp, Tos or Thyst register including pointer byte (2-byte data)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL

SDA S 1 0 0 1 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A' D7 D6 D5 D4 D3 D2 D1 D0 NA P device address

START read device acknowledge

MSByte from device master acknowledge

LSByte from device master not acknowledged

STOP

002aad038

Fig 11. Read Temp, Tos or Thyst register with preset pointer (2-byte data)

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14 of 29 Rev. 02 — 9 December 2008


LM75B


8.

Application design-in information

8.1 Typical application

power supply

BUS

10 k

Ω

PULL-UP

RESISTORS

I

2

C-BUS

DIGITAL LOGIC

10 k

Ω

SCL

2

SDA

1

0.1

µ

F

8

V

CC

LM75B

A2

5

A1

6

A0

7

4

GND

3

OS

10 k

Ω

DETECTOR OR

INTERRUPT LINE

002aad457

Fig 12. Typical application

8.2 LM75A and LM75B comparison

Table 14.

LM75A and LM75B comparison

Description

availability of the XSON8U (3 mm

×

2 mm) package type

OS output auto-reset when SHUTDOWN bit is set in interrupt mode

[1] support single-byte reading of the Temp registers without bus lockup

[2] bus fault time-out (75 ms, 200 ms)

[3]

minimum data hold time (t

HD;DAT

)

[4]

ratio of conversion time / conversion period (typical)

[5]

supply current in shutdown mode (typical value)

HBM ESD protection level (minimum)

MM ESD protection level (minimum)

CDM ESD protection level (minimum)

LM75A

no no no no

10 ns

100 ms / 100 ms

3.5

µ

A

>2000 V

>200 V

>1000 V

LM75B

yes yes yes yes

0 ns

10 ms / 100 ms

0.2

µ

A

>4500 V

>450 V

>2000 V

[1] This option is updated to be compatible with the competitive parts. When the OS output has been activated in the interrupt mode due to a temp limit violation, if the Configuration Shutdown bit B0 is set (to the LM75A), then the OS output activated status remains unchanged, while (to the LM75B) the OS will be reset. The latter is compatible with the operation condition of the competitive parts.

[2] The LM75 series is intentionally designed to provide two successive temperature data bytes (MSByte and LSByte) for the 11-bit data resolution and both bytes should be read in a typical application. In some specific applications, when only the MSByte is read using a single-byte read command, it often happens that if bit D7 of the LSByte is zero, then the device will hold the SDA bus in a LOW state forever, resulting in a bus hang-up problem, and the bus cannot be released until the device power is reset. This condition exists for the

LM75A but not for the LM75B. For the LM75B the temperature can be read either one byte or two bytes without a hang-up problem.

[3] The bus time-out is included for releasing the LM75B device operation whenever the SDA input is kept at a LOW state for too long

(longer than the LM75B time-out duration) due to a fault from the host. The trade-off for this option is the limitation of the I

2

C-bus low frequency operation to be limited to 20 Hz. This option is compatible with some of the latest versions of the competitive parts.

[4] The data hold time is improved to increase the timing margin in I

2

C-bus operation.

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LM75B


[5] The LM75B performs the temperature-to-data conversions with a much higher speed than the LM75A. While the LM75A takes almost the whole of conversion period (T conv

) time of about 100 ms to complete a conversion, the LM75B takes only about

1

⁄

10 of the period, or about 10 ms. Therefore, the conversion period (T conv

) is the same, but the temperature conversion time (t conv(T)

) is different between the two parts. A shorter conversion time is applied to significantly reduce the device’s average power dissipation. During each conversion period, when the conversion is completed, the LM75B becomes idled and the power is reduced, resulting in a lesser average power consumption.

8.3 Temperature accuracy

Because the local channel of the temperature sensor measures its own die temperature that is transferred from its body, the temperature of the device body must be stabilized and saturated for it to provide the stable readings. Because the LM75B operates a a low power level, the thermal gradient of the device package has a minor effect on the measurement.

The accuracy of the measurement is more dependent upon the definition of the environment temperature, which is affected by different factors: the printed-circuit board on which the device is mounted; the air flow contacting the device body (if the ambient air temperature and the printed-circuit board temperature are much different, then the measurement may not be stable because of the different thermal paths between the die and the environment). The stabilized temperature liquid of a thermal bath will provide the best temperature environment when the device is completely dipped into it. A thermal probe with the device mounted inside a sealed-end metal tube located in consistent temperature air also provides a good method of temperature measurement.

8.4 Noise effect

The LM75B device design includes the implementation of basic features for a good noise immunity:

•

The low-pass filter on both the bus pins SCL and SDA;

•

The hysteresis of the threshold voltages to the bus input signals SCL and SDA, about

500 mV minimum;

•

All pins have ESD protection circuitry to prevent damage during electrical surges. The

ESD protection on the address, OS, SCL and SDA pins it to ground. The latch-back based device breakdown voltage of address/OS is typically 11 V and SCL/SDA is typically 9.5 V at any supply voltage but will vary over process and temperature. Since there are no protection diodes from SCL or SDA to V

CC

, the LM75B will not hold the

I

2

C lines LOW when V

CC

is not supplied and therefore allow continued I

2

C-bus operation if the LM75B is de-powered.

However, good layout practices and extra noise filters are recommended when the device is used in a very noisy environment:

•

Use decoupling capacitors at V

CC

pin.

•

Keep the digital traces away from switching power supplies.

•

Apply proper terminations for the long board traces.

•

Add capacitors to the SCL and SDA lines to increase the low-pass filter characteristics.

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16 of 29 Rev. 02 — 9 December 2008


LM75B


9.

Limiting values

Table 15.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

V

CC

V

I

I

I

I

O(sink)

V

O

T stg

T j supply voltage input voltage input current output sink current output voltage storage temperature junction temperature at input pins at input pins on pin OS on pin OS

-

Min

−

0.3

−

0.3

−

5.0

-

−

0.3

−

65

10. Recommended operating conditions

Table 16.

Recommended operating characteristics


V

CC

T amb supply voltage ambient temperature

Min

2.8

−

55 -

-

Typ

Max

+6.0

+6.0

+5.0

10.0

+6.0

+150

150

Max

5.5

+125

Unit

V

°

C

Unit

V

V mA mA

V

°

C

°

C

LM75B_2



17 of 29


LM75B


11. Static characteristics

Table 17.

Static characteristics

V

CC

= 2.8 V to 5.5 V; T amb

=

−

55

°

C to +125

°

C; unless otherwise specified.

Symbol Parameter

T acc temperature accuracy

Conditions

T amb

=

−

25

°

C to +100

°

C

T amb

=

−

55

°

C to +125

°

C

T res t conv(T) temperature resolution temperature conversion time

11-bit digital temp data normal mode

T conv

I

DD(AV) conversion period average supply current normal mode normal mode: I

2

C-bus inactive normal mode: I

2

C-bus active; f

SCL

= 400 kHz shutdown mode

V

IH

V

IL

V

I(hys)

HIGH-level input voltage

LOW-level input voltage digital pins (SCL, SDA, A2 to A0) digital pins hysteresis of input voltage SCL and SDA pins

A2, A1, A0 pins

I

I

IH

I

IL

V

OL

N

T

T

LO

C hys i fault th(ots)

HIGH-level input current digital pins; V

I

= V

CC

LOW-level input current digital pins; V

I

= 0 V

LOW-level output voltage SDA and OS pins; I

OL

= 3 mA output leakage current

I

OL

= 4 mA

SDA and OS pins; V

OH

= V

CC number of faults programmable; conversions in overtemperature-shutdown fault queue default value overtemperature shutdown threshold temperature hysteresis temperature input capacitance default value digital pins

[1] Typical values are at V

CC

= 3.3 V and T amb

= 25

°

C.

-

-

-

-

-

-

-

-

Min

−

2

−

3

-

1

-

-

0.7

×

V

CC

−

0.3

-

-

-

−

1.0

−

1.0

-

-

0.2

-

-

300

150

-

-

-

-

-

-

Typ

[1]

Max

+2

+3

0.125

10 -

-

100

-

100

-

200

300 ms

µ

A

µ

A

-

-

1.0

µ

A

V

CC

+ 0.3

V

0.3

×

V

CC

V mV

+1.0

+1.0

0.4

0.8

10

6 mv

µ

A

µ

A

V

V

µ

A

Unit

°

C

°

C

°

C ms

80

75

20 -

-

-

°

C

°

C pF

LM75B_2



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LM75B


002aae198

300

I

DD(AV)

(

µ

A)

200

V

CC

= 5.5 V

4.5 V

3.3 V

2.8 V

100

002aae199

300

I

DD(AV)

(

µ

A)

200

V

CC

= 5.5 V

4.5 V

3.3 V

2.8 V

100

0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 13. Average supply current versus temperature;

I

2

C-bus inactive

V

CC

= 5.5 V

4.5 V

3.3 V

2.8 V

002aae200

0.5

I

DD(sd)

(

µ

A)

0.4

0.3

0.2

0.1

0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 15. Shutdown mode supply current versus temperature

002aae202

0.5

V

OL(SDA)

(V)

0.4

0.3

0.2

0.1

V

CC

= 5.5 V

4.5 V

3.3 V

2.8 V

0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 17. LOW-level output voltage on pin SDA versus temperature; I

OL

= 4 mA

0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 14. Average supply current versus temperature;

I

2

C-bus active

V

CC

= 5.5 V

4.5 V

3.3 V

2.8 V

002aae201

0.5

V

OL(OS)

(V)

0.4

0.3

0.2

0.1

0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 16. LOW-level output voltage on pin OS versus temperature; I

OL

= 4 mA

002aae203

2.0

T acc

(

°

C)

1.0

0

−

1.0

−

2.0

−

75

−

25 25 75

T amb

(

°

C)

125

Fig 18. Typical temperature accuracy versus temperature; V

CC

= 3.3 V

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19 of 29 Rev. 02 — 9 December 2008


LM75B


12. Dynamic characteristics

Table 18.

I

2

C-bus interface dynamic characteristics

[1]

V

CC

= 2.8 V to 5.5 V; T amb

=

−

55

°

C to +125

°

C; unless otherwise specified.


f

SCL t

HIGH t

LOW t

HD;STA t

SU;DAT t

HD;DAT t

SU;STO t f

SCL clock frequency

HIGH period of the SCL clock

LOW period of the SCL clock hold time (repeated) START condition data set-up time data hold time set-up time for STOP condition fall time see

Figure 19

SDA and OS outputs;

C

L

= 400 pF; I

OL

= 3 mA t to time-out time

[2][3]

-

Min

0.02

0.6

1.3

100

100

0

100

75

-

-

-

-

-

-

-

-

Typ

250

-

-

-

-

-

-

-

Max

400

200 ms

[1] These specifications are guaranteed by design and not tested in production.

[2] This is the SDA time LOW for reset of serial interface.

[3] Holding the SDA line LOW for a time grater than t to

(SDA set HIGH).

will cause the LM75B to reset SDA to the idle state of the serial bus communication ns ns ns ns

Unit

kHz

µ s

µ s ns

SDA t f

SCL t

LOW t r t

SU;DAT t f

S

Fig 19. Timing diagram

t

HD;STA t

HIGH t

HD;DAT t

SU;STA

Sr t

HD;STA t

SP t r t

BUF t

SU;STO

P S

002aab271

LM75B_2



20 of 29


LM75B


13. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

8

Z y pin 1 index

1 e

D E A

X c

H

E

5 b p

4 w

M

A

2

A

1

L

L p detail X

Q

θ

A v

M A

0 2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c D

(1)

E

(2) e H

E

mm inches

1.75

0.069

0.25

0.10

0.010

0.004

1.45

1.25

0.057

0.049

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

5.0

4.8

0.20

0.19

4.0

3.8

0.16

0.15

1.27

0.05

6.2

5.8

0.244

0.228

L L p

Q

1.05

0.041

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

v

0.25

0.01

w y Z

(1)

0.25

0.01

0.1

0.004

0.7

0.3

0.028

0.012

θ

8 o

0 o

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE

VERSION

SOT96-1

IEC

076E03

REFERENCES

JEDEC JEITA

MS-012

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

03-02-18

Fig 20. Package outline SOT96-1 (SO8)

LM75B_2



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LM75B


TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

D y

8

Z

5 c pin 1 index

1 e bp

4 w

M

A2

A1

E

HE

A

X v

M A

L

Lp detail X

(A3)

A

θ

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A1 A2 A3 bp c

mm

1.1

0.15

0.05

0.95

0.80

0.25

0.45

0.25

0.28

0.15

D

(1)

3.1

2.9

E

(2)

3.1

2.9

e

0.65

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

IEC

REFERENCES

JEDEC JEITA

HE

5.1

4.7

SOT505-1

L

0.94

Lp

0.7

0.4

v

0.1

w

0.1

y

0.1

Z

(1)

0.70

0.35

θ

6

°

0

°

EUROPEAN

PROJECTION

ISSUE DATE

99-04-09

03-02-18

Fig 21. Package outline SOT505-1 (TSSOP8)

LM75B_2



22 of 29


XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

LM75B


SOT996-2

D B A

E terminal 1 index area

L

1

L

2

1

e e

1 b

4

v

M w

M

C

C

A B

A

A

1 detail X y

1

C

C y

L

8 5

X

0 1 scale

DIMENSIONS (mm are the original dimensions)

UNIT

A max

A

1 b D E e

mm 0.5

0.05

0.00

0.35

0.15

2.1

1.9

3.1

2.9

0.5

OUTLINE

VERSION

SOT996-2

IEC

- - -

e

1

1.5

L

0.5

0.3

L

1

0.15

0.05

REFERENCES

JEDEC JEITA

- - -

L

2

0.6

0.4

2 mm

v w y y

1

0.1

0.05

0.05

0.1

EUROPEAN

PROJECTION

Fig 22. Package outline SOT996-2 (XSON8U)

LM75B_2


ISSUE DATE

07-12-18

07-12-21


23 of 29


LM75B


14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

14.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

•

Through-hole components

•

Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•

Board specifications, including the board finish, solder masks and vias

•

Package footprints, including solder thieves and orientation

•

The moisture sensitivity level of the packages

•

Package placement

•

Inspection and repair

•

Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave

•

Solder bath specifications, including temperature and impurities

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24 of 29 Rev. 02 — 9 December 2008


LM75B


14.4 Reflow soldering

Key characteristics in reflow soldering are:

•

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23 ) than a SnPb process, thus reducing the process window

•

Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board

•

Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 19 and 20

Table 19.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

°

C)

Volume (mm

3

)

< 350

≥

350

< 2.5

≥

2.5

235

220

220

220

Table 20.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

°

C)

Volume (mm

3

)

< 350 350 to 2000

< 1.6

1.6 to 2.5

> 2.5

260

260

250

260

250

245

> 2000

260

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23 .

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LM75B


temperature maximum peak temperature

= MSL limit, damage level minimum peak temperature

= minimum soldering temperature peak

temperature time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

Table 21.

Abbreviations

Acronym Description

A-to-D

CDM

Analog-to-Digital

Charged Device Model

ESD

HBM

I

2

C-bus

I/O

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit bus

Input/Output

LSB

LSByte

MM

MSB

MSByte

POR

Lease Significant Bit

Least Significant Byte

Machine Model

Most Significant Bit

Most Significant Byte

Power-On Reset

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LM75B


16. Revision history

Table 22.

Revision history

Document ID

LM75B_2

Modifications:

Release date Data sheet status Change notice Supersedes

20081209 Product data sheet LM75B_1

•

added XSON8U package option (affects

Section 2 “Features” ,

Table 1 “Ordering information” ,

Section 6.1 “Pinning” ,

Table 14 “LM75A and LM75B comparison”

,

Section 13 “Package outline” )

LM75B_1 20081204 Product data sheet -

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27 of 29


LM75B


17. Legal information

17.1

Data sheet status

Document status

[1][2]

Objective [short] data sheet

Product status

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[3]

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

17.2

Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

17.3

Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

17.4

Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I

2

C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

LM75B_2



28 of 29 Rev. 02 — 9 December 2008


LM75B


19. Contents

9

10

11

12

8

8.1

8.2

8.3

8.4

7.5

7.6

7.7

7.8

7.9

7.10

13

14

14.1

14.2

14.3

14.4

15

16

17

17.1

17.2

1

2

3

4

5

6

6.1

6.2

7

7.1

7.2

7.2.1

7.3

7.4

7.4.1

7.4.2

7.4.3

7.4.4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional description . . . . . . . . . . . . . . . . . . . 4

General operation . . . . . . . . . . . . . . . . . . . . . . . 4

I

2

C-bus serial interface . . . . . . . . . . . . . . . . . . . 6

Bus fault time-out . . . . . . . . . . . . . . . . . . . . . . . 6

Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pointer register . . . . . . . . . . . . . . . . . . . . . . . . . 7

Configuration register . . . . . . . . . . . . . . . . . . . . 7

Temperature register. . . . . . . . . . . . . . . . . . . . . 8

Overtemperature shutdown threshold (Tos) and hysteresis (Thyst) registers . . . . . . . . . . . . 9

OS output and polarity . . . . . . . . . . . . . . . . . . 10

OS comparator and interrupt modes . . . . . . . 10

OS fault queue . . . . . . . . . . . . . . . . . . . . . . . . 11

Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . 11

Power-up default and power-on reset . . . . . . . 11

Protocols for writing and reading the registers 12

Application design-in information . . . . . . . . . 15

Typical application. . . . . . . . . . . . . . . . . . . . . . 15

LM75A and LM75B comparison . . . . . . . . . . . 15

Temperature accuracy . . . . . . . . . . . . . . . . . . 16

Noise effect . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Recommended operating conditions. . . . . . . 17

Static characteristics. . . . . . . . . . . . . . . . . . . . 18

Dynamic characteristics . . . . . . . . . . . . . . . . . 20

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

Soldering of SMD packages . . . . . . . . . . . . . . 24

Introduction to soldering . . . . . . . . . . . . . . . . . 24

Wave and reflow soldering . . . . . . . . . . . . . . . 24

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27

Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

17.3

17.4

18

19

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Contact information . . . . . . . . . . . . . . . . . . . . 28

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 9 December 2008

Document identifier: LM75B_2

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