MB 1516 A
DS04–21323–2aE
DATA SHEET
MB1516A ASSP
1.1GHz High-Speed Tuning PLL Frequency Synthesizer
DESCRIPTION
The Fujitsu MB1516A is a serial input phase-locked loop (PLL) frequency synthesizer with
a pulse-swallow function. MB1516A achieves the low noise performance as well as the
high–speed lock-up which is required for digital mobile communications.
The MB1516A can operate from a single +3 V supply. Fujitsu’s advanced technology
achieves an Icc of 6.5 mA (typical).
FUNCTION
•
•
•
•
•
•
•
•
•
•
High operating frequency
Pulse-swallow function
: fIN = 1.1 GHz (PIN = –10 dBm)
: High-speed dual-modulus prescaler with selectable
64/65 and 128/129 divide ratios
Low supply current
: ICC = 6.5 mA typ. at 3 V
Power saving funtion
: IPS = 100 µA typ.
Serial input, 18-bit programmable divider consisting of:
Binary 7-bit swallow counter
: 0 to 127
Binary 11-bit programmable counter : 5 to 2,047
Serial input 16-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 6 to 16,383
1-bit switch counter sets prescaler divide ratio
1-bit power saving function control
On-chip high performance charge pump circuit and phase comparator, achieving
high-speed lock-up and low phase noise
Two types of phase comparator outputs selectable
On-chip charge pump output
Output for an external charge pump
Wide operating temperature range: –40 to +85°C
Plastic 16–pin SSOP (shrink small outline) package (Suffix : –PFV)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Parameter
Rating
Unit
VCC
–0.5 to +5.0
V
VP
VCC to 5.5
V
Output voltage
VO
–0.5 to VCC +0.5
V
Open drain voltage
VOOP
–0.5 to 6.0
V
Output current
IO
±10
mA
Storage temperature
Tstg
–55 to +125
°C
Supply voltage
NOTE:
Symbol
Remark
PIN ASSIGNMENT
(TOP VIEW)
OSCIN
1
16
ΦR
OSCOUT
2
15
ΦP
VP
3
14
fOUT
VCC
4
13
NC
DO
5
12
FC
GND
6
11
LE
LD
7
10
Data
fIN
8
9
Clock
ΦP, fout
Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
1
MB1516A
BLOCK DIAGRAM
OSCIN
1
Crystal
Oscillator
circuit
Programmable
reference divider
OSCOUT 2
Binary 14-bit
reference counter
16
ΦR
15
ΦP
Phase
comparator
fr
fp
FC
Intermittent
mode control
(power save)
PS
12
FC
14
fOUT
fr
16-bit latch
Monitor
frequency
selector
16-bit latch
LE
FC
fp
LE
11
19-bit shift register
Data
Clock
10
1-bit
control
latch
19-bit shift register
DATA
9
18-bit latch
LE
7-bit latch
11-bit latch
SW
Programmable divider
fIN
2
8
GND
6
VCC
4
Prescaler
64/65,
128/129
Binary 7-bit
swallow
counter
MC
Binary 11-bit
programmable
counter
Control circuit
fp
Charge
pump
3
VP
Super
charger II
5
DO
MB1516A
PIN DESCRIPTION
Pin No. Pin name
I/O
Description
1
OSCIN
I
Programmable reference divider input
Oscillator input
Connection for external crystal or TCXO.
2
OSCOUT
O
Oscillator output
Connection for external crystal.
3
VP
–
Power supply input for charge pump
4
VCC
–
Power supply
5
DO
O
Charge pump output
Phase of charge pump can be reversed based on FC input.
6
GND
–
Ground
7
LD
O
Lock detector output
The output level is usually high. Only when there is a phase error between fr and fp,
LD becomes low for the period corresponding to the error.
8
fIN
I
Prescaler input
Connection with an external VCO should be done AC coupled.
9
Clock
I
Clock input for 19-bit shift register
Data is shifted into the shift register on the rising edge of the clock.
10
Data
I
Serial data input using binary code
The last bit of the data is a control bit.
When the control bit is high, data is transmitted to the 16-bit latch.
When it is low, data is transmitted to the 18-bit latch.
11
LE
I
Load enable signal input (with internal pull up resistor)
When LE is high, the data of the shift register are transferred to a latch, depending on the
control bit in the serial data.
12
FC
I
Phase switch input for phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of the charge pump and phase comparator are reversed
The FC input signal is also used to control the fOUT pin (test pin) output (fR or fP).
13
NC
–
No connection
14
fOUT
O
Monitor pin of phase comparator
When FC is high, fOUT outputs programmable reference divider output(fr). When FC is low, fOUT
outputs programmable divider output(fp).
15
ΦP
O
Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.
ΦP pin is a N-ch open drain output.
16
ΦR
O
Phase comparator output for an external charge pump
Phase of the output is reversed depending on FC input.
ΦR pin is a C-MOS output.
3
MB1516A
FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
M
: Preset divide ratio of modules prescaler (64 or 128)
Serial data input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 16-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:
Control data
(a)
Destination of serial data
H
16 bit latch
L
18 bit latch
Programmable reference divider ratio
The programmable reference divider consists of a 16-bit latch and a 14-bit reference counter. The serial 17-bit data format is
shown below:
Direction of data shift
Control bit
LSB
C
S
1
S
2
S
3
S
4
Divide ratio setting bit for prescaler
MSB
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
SW PS
Divide ratio setting bit for programmable reference counter
Power saving control bit
4
MB1516A
•
14-bit programmable reference counter divide ratio
Divide ratio
R
S
14
S
13
S
12
S
11
S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
7
0
0
0
0
0
0
0
0
0
0
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 6 to 16,383)
Notes: 1. Divide ratios less than 6 are prohibited.
2. SW : This bit selects the divide ratio of the prescaler.
Low: 128 or 129
High: 64 or 65
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (6 to 16,383).
4. C: Control bit: Set high.
5. PS: This bit controls stand by mode.
High : Nomal mode
Low : Stand by mode
6. Start data input with MSB first .
(b)
Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, a 18-bit latch, a 7-bit swallow counter, and a 11-bit programmable
counter. The serial 19-bit data format is shown below:
Direction of data shift
Control bit
LSB
C
S
1
S
2
S
3
S
4
MSB
S
5
S
6
Divide ratio setting bit for
swallow counter
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
S
17
S
18
Divide ratio setting bit for programmable counter
5
MB1516A
•
•
7-bit swallow counter divide ratio
11-bit programmable counter divide ratio
Divide
ratio
A
S
7
S
6
S
5
S
4
S
3
S
2
S
1
Divide
ratio
N
S
18
S
17
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
6
0
0
0
0
0
0
0
0
1
1
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
(Divide ratio = 0 to 127)
Notes: 1.
2.
3.
4.
5.
(Divide ratio = 5 to 2,047)
Divide ratios less than 5 are prohibited for 11–bit programmable counter.
S1 to S7: These bits select the divide ratio of swallow counter (0 to 127).
S8 to S18: These bits select the divide ratio of programmable counter (5 to 2,047).
C: Control bit: (Set low)
Start data input with MSB first.
Serial data input timing
t1, t2, t3, t4 ≥ 30ns, t5, t6 ≥ 100ns, t7, t8 ≥ 200ns
Data
(LSB)
(MSB)
Clock
LE
t5
t1
t6
t2
t8
t7
Notes: One bit of data is shifted into the shift registor on the rising edge of the clock.
6
t3
t4
MB1516A
Power saving mode (Intermittent operation control circuit)
Setting PS bit to Low, MB1516A enters into power saving mode resultatly current sonsumption can be limited to 100µA (typ.).
Setting PS bit to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. If a PLL is
powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fR) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power
up, thus keeping the loop locked.
Relation between the FC input and phase characteristics
The FC pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the
phase comparator output (ΦR, ΦP) are reversed depending on the FC pin input level. Also, the monitor pin (fOUT) output is controlled
by the FC pin. The relationship between the FC input level and each of DO, ΦR, and ΦP is shown below:
FC = High or open
FC = Low
Do
ΦR
ΦP
fOUT
Do
ΦR
ΦP
fOUT
fR > fP
H
L
L
(fr)
L
H
Z(∗1)
(fp)
fR < fP
L
H
Z(∗1)
(fr)
H
L
L
(fp)
fR = fP
Z(∗1)
L
Z (∗1)
(fr)
Z(∗1)
L
Z(∗1)
(fp)
∗1: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
1
∗: When the LPF and VCO characteristics are
similar to 1 , set FC high or open.
∗: When the VCO characteristics are similar to
2 , set FC low.
VCO
output
frequency
2
PLL
LPF
VCO
LPF input voltage
7
MB1516A
Phase comparator output waveforms
fr
fp
tWU
tWL
LD
[ FC = ”H” ]
ΦP
ΦR
H
Do
Z
L
[ FC = ”L” ]
ΦP
ΦR
H
Do
L
Z
Notes: 1. Phase difference detection range: –2π to +2π
2. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or
less and continues to be so for three cysles or more.
3. tWU and tWL depend on OSCin input frequency.
tWU ≥ 8/fosc (e. g. tWU ≥ 625ns, foscin = 12.8 MHz)
tWL ≤ 16/fosc (e. g. tWL ≤ 1250ns, foscin = 12.8 MHz)
8
MB1516A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Value
Typ
Max
Unit
VCC
2.7
3.0
3.6
V
Vp
Vcc
–
5.0
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Remark
Supply voltage
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
–
Store and transport devices in conductive containers.
–
Use properly grounded workstations, tools, and equipment.
–
Turn off power before inserting or removing this device into or from a socket.
–
Protect leads with conductive sheet, when transporting a board mounted device.
9
MB1516A
ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Supply current
ICC
Min
–
Value
Typ
6.5
Max
–
Unit
Condition
mA
With fIN = 1.1 GHz, OSCIN
= 12 MHz, VCC = 3.0 V.
In locked state.
AC coupling. The minimum
operating frequency is measured with a 1000pF capacitor connected.
fIN
300
–
1100
MHz
OSCIN
fOSC
–
12
23
MHz
fIN
Pf IN
–10
–
6
dBm
OSCIN
VOSC
0.5
–
–
Vp–p
VIH
VCC x 0.7
–
–
V
VIL
–
–
VCC x 0.3
V
IIH
–
–
1.0
µA
IIL
–
–
–1.0
µA
OSCIN
IOSC
–
±50
–
µA
FC, LE
ILE
–
–60
–
µA
VOH
2.1
–
–
V
VCC = 3 V, IOH = –1.0mA
VOL
–
–
0.4
V
Vcc = 3V, IOL = 1.0mA
IOFF
–
–
1.1
µA
VCC = 3.6V
VP = 5 V
IOH
–1.0
–
–
mA
Vcc = 3V
IOL
–
–
1.0
mA
Vcc = 3V
fIN
Operating frequency
50Ω
Input sensitivity
High-level input voltage
Low-level input voltage
Except fIN and
OSCIN
High-level input current
Data, Clock
Low-level input current
Input current
High-level output voltage
10
Low-level output voltage
Except DO and
OSCOUT
High-impedance
Cut off current
DO, fout, ΦP
Output current
Except DO and
OSCOUT
MB1516A
TEST CIRCUIT
(FOR MEASURING INPUT SENSITIVITY fin/OSCin)
VCC = VP = 3V
0.1 µ
0.1 µ
1000 p
1000 p
P·G
P·G
50 Ω
8
7
6
5
4
3
2
1
50 Ω
9 10 11 12 13 14 15 16
2kΩ
Frequency counter
Controller
(setting divide ratio)
Select fout monitor output
11
MB1516A
TYPICAL CHARACTERISTIC CURVES
Charge pump current vs. Do voltage
Charge pump current vs. Do voltage
Vcc =3.0V
Vcc =3.0V
5
5
4
Vp = 5V
VOL (V)
VOH (V)
4
3
2
3
2
Vp = 3V
1
1
0
–5
–10
–15
–20
0
–25
5
10
IOH (mA)
15
20
25
IOL (mA)
Fin Input sensitivity vs. Input frequency
[dBm]
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
CATALOG–SPEC
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
x
+10
x
+5
x
PIN (dBm)
+0
–5
x
–10
x
–15
x
x
–20
–25
x
–30
–35
x
x
x
x
x
–40
200
400
Vcc = 2.7 3 3.6
MARK = x 12
x
600
800
1000
1200
Fin [MHz]
1400
1600
1800
2000
MB1516A
TYPICAL CHARACTERISTIC CURVES (Continued)
Prescaler Input
Impedance Characteristics
S11
4:
10.102
Ω
–37.453 Ω
3.8631
pF
1100 MHz
1:
14.539
–125.61
500
2: 9.6484
–69.262
800
3: 9.9023
–46.156
1
MB1516A fIN [MHz]
Ω
Ω
MHz
Ω
Ω
MHz
Ω
Ω
GHz
4
1
3
START
Crystal Input
Impedance Characteristics
100 MHz
S11
4:
670.13
2
STOP 1500 MHz
Ω
–1.8371 Ω
3.4653
pF
25 MHz
1:
4
MB1516A OSCIN [MHz]
32
START
1.425
–3.5698
10
2: 1.0444
–2.637
15
3: 800.75
–2.2129
20
kΩ
kΩ
MHz
kΩ
kΩ
MHz
kΩ
kΩ
MHz
STOP 100 MHz
13
MB1516A
APPLICATION EXAMPLE
Output
Vpx (6V)
LPF
VCO
10 k
12 k
12 k
10 k
From
controller
ΦR
16
ΦP
15
fOUT
14
NC
13
FC
12
LE
Data
Clock
11
10
9
6
7
8
47 k
MB1516A
1
2
OSCIN
3
OSCOUT
4
5
VP
VCC
3V
3V
0.1 µ
0.1 µ
DO
GND
LD
fIN
1000 p
X’ tal
C1
VPX
C1, C2
LE, FC
ΦP
ΦR
14
:
:
:
:
:
C2
Maximum 6 V
Depend on the crystal parameters
With internal pull-up resistor
N-ch open drain output
C-MOS output
Lock det.
47 k
MB1516A
REFERENCE INFORMATION
Typical plots measured
with the test circuit shown
on the right of this description are shown below.
Each plot shows lock up
time, phase noise with
various span.
Test Circuit
OSC in
Do
fin
S.G
•
•
•
•
•
LPF
fvco= 825 MHz
K v= 10 MHz/v
f r= 300 KHz
f osc= 19.2 MHz
LPF :
15k
1.5k
VCO
Spectrum
Analyzer
4700p
330 p
0.047µ
PLL Phase Noise
PLL Lock Up Time
520.02811 µs
10dB/
REF
10.0 dBm
ATT 10 dB
10.00150
MHz
RBW
100 Hz
500
Hz/div
VBW
10 Hz
9.999000
MHz
10.1699 µs
1.9904199 ms
SPAN 20 kHz
PLL Phase Noise
10dB/
REF
10.0 dBm
PLL Reference Leakage
ATT 10 dB
10dB/
RBW
30 Hz
RBW
10 kHz
VBW
10 Hz
VBW
30 Hz
SPAN 2.0 kHz
CENTER 825 MHz
CENTER 825 MHz
REF
10.0 dBm
ATT 10 dB
SPAN 1.0 MHz
CENTER 825 MHz
15
MB1516A
PACKAGE AND DIMENSION
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M05)
+.008
.049 –.004
+0.20
(1.25 –0.10 )
∗.197±.004
(5.00±0.10)
(MOUNTING HEIGHT)
.004(0.10)
.252±.008
(6.40±0.20)
INDEX
∗.173±.004
(4.40±0.10)
.213(5.40) NOM
”A”
.009 +.004
–.002
+0.10
(0.22
)
–0.05
.0256±.0047
(0.65±0.12)
.006 +.002 (0.15 +0.05 )
–.001
–0.02
Details of ”A” part
.004±.004
(0.10±0.10)
(STAND OFF
HEIGHT)
.179(4.55)
REF
0°to10°
.020±.008
(0.50±0.20)
∗:This dimension does not include resin protruction.
1991 FUJITSU LIMITED F16013S-2C
16
Dimensions in
inches (millimeters)
MB1516A
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete information sufficient for construction purposes
is not necessarily given.
The information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
17
MB1516A
MEMO
18
MB1516A
MEMO
19
MB1516A
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: (044) 754–3753
FAX: (044) 754–3332
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134–1804, USA
Tel: (408) 922–9000
FAX: (408) 432–9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10
63303 Dreieich–Buchschlag,
Germany
Tel: (06103) 690–0
FAX: (06103) 690–122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06–04 to #06–07
Singapore 0718
Tel: 336–1600
FAX: 336–1609
I9506
 FUJITSU LIMITED Printed in Japan
20
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