EZ-USB FX3: SuperSpeed USB Controller ® CYUSB301X/CYUSB201X

CYUSB301X/CYUSB201X

EZ-USB

®

FX3: SuperSpeed USB Controller

Features

■

Universal serial bus (USB) integration

❐

❐

❐

❐

❐

USB 3.1, Gen 1 and USB 2.0 peripherals compliant with USB

3.1 Specification Revision 1.0 (TID # 340800007)

5-Gbps SuperSpeed PHY compliant with USB 3.1 Gen 1

High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0

Thirty-two physical endpoints

Support for battery charging Specification 1.1 and accessory charger adaptor (ACA) detection

■

General Programmable Interface (GPIF™ II)

❐

❐

❐

Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices

8-, 16-, 24-, and 32-bit data bus

Up to16 configurable control signals

■

Fully accessible 32-bit CPU

❐

❐

ARM926EJ core with 200-MHz operation

512-KB or 256-KB embedded SRAM

❐

❐

❐

❐

■

Additional connectivity to the following peripherals

SPI master at up to 33 MHz

I

I

UART support of up to 4 Mbps

2

2

C master controller at 1 MHz

S master (transmitter only) at sampling frequencies of

32 kHz, 44.1 kHz, and 48 kHz

■

Selectable clock input frequencies

❐

❐

19.2, 26, 38.4, and 52 MHz

19.2-MHz crystal input support

■

Ultra low-power in core power-down mode

❐

Less than 60 µA with VBATT on and 20 µA with VBATT off

■

Independent power domains for core and I/O

❐

❐

❐

Core operation at 1.2 V

I

I2S, UART, and SPI operation at 1.8 to 3.3 V

2

C operation at 1.2 V to 3.3 V

■

Package options

❐

❐

❐

121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array

(BGA)

131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale package (WLCSP)

See Table 20

for details on the eight FX3 variants

■

EZ-USB

®

Software Development Kit (SDK) for code development of firmware and PC Applications

❐

❐

❐

Includes RTOS Framework (using ThreadX Version 5)

Firmware examples covering all I/O modules

Visual Studio host examples using C++ and C#

■

SuperSpeed Explorer Board available for rapid prototyping

❐

Several accessory boards also available:

• Adapter boards for Xilinx/Altera FPGA development

• Adapter board for Video development

• CPLD board for concept testing and initial development

Applications

■

Digital video camcorders

■

Digital still cameras

■

Printers

■

Scanners

■

Video capture cards

■

Test and measurement equipment

■

Surveillance cameras

■

Personal navigation devices

■

Medical imsaging devices

■

Video IP phones

■

Portable media players

■

Industrial cameras

■

Data loggers

■

Data acquisition

■

High-performance Human Interface Devices (gesture recognition)

For a complete list of related documentation, click here .

Cypress Semiconductor Corporation

• 198 Champion Court

Document Number: 001-52136 Rev. *R

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised March 27, 2015

Logic Block Diagram


Document Number: 001-52136 Rev. *R Page 2 of 52


More Information

Cypress provides a wealth of data at www.cypress.com

to help you to select the right <product> device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA87889, How to design with FX3/FX3S .

■

Overview: USB Portfolio , USB Roadmap

■

USB 3.0 Product Selectors: FX3 , FX3S , CX3 , HX3 , West

Bridge Benicia

■

❐

❐

❐

Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FX3 are:

❐

❐

❐

❐

❐

AN75705 - Getting Started with EZ-USB FX3

AN76405 - EZ-USB FX3 Boot Options

AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines and Schematic Checklist

AN65974 - Designing with the EZ-USB FX3 Slave FIFO Interface

AN75779 - How to Implement an Image Sensor Interface with

EZ-USB FX3 in a USB Video Class (UVC) Framework

AN86947 - Optimizing USB 3.0 Throughput with EZ-USB

FX3

AN84868 - Configuring an FPGA over USB Using Cypress

EZ-USB FX3

AN68829 - Slave FIFO Interface for EZ-USB FX3: 5-Bit Address Mode

❐

❐

❐

❐

AN73609 - EZ-USB FX2LP/ FX3 Developing Bulk-Loop Example on Linux

AN77960 - Introduction to EZ-USB FX3 High-Speed USB

Host Controller

AN76348 - Differences in Implementation of EZ-USB FX2LP and EZ-USB FX3 Applications

AN89661 - USB RAID 1 Disk Design Using EZ-USB FX3S

■

❐

❐

❐

Code Examples: < Modify as required >

USB Hi-Speed

USB Full-Speed

USB SuperSpeed

■

Technical Reference Manual (TRM):

❐

EZ-USB FX3 Technical Reference Manual

■

❐

❐

Development Kits:

CYUSB3KIT-003 , EZ-USB FX3 SuperSpeed Explorer Kit

CYUSB3KIT-001 , EZ-USB FX3 Development Kit

■

Models: IBIS

EZ-USB FX3 Software Development Kit

Cypress delivers the complete software and firmware stack for FX3, in order to easily integrate SuperSpeed USB into any embedded application. The Software Development Kit (SDK) comes with tools, drivers and application examples, which help accelerate application development.

GPIF™ II Designer

The GPIF II Designer is a graphical software that allows designers to configure the GPIF II interface of the EZ-USB FX3 USB 3.0

Device Controller.

The tool allows users the ability to select from one of five Cypress supplied interfaces, or choose to create their own GPIF II interface from scratch. Cypress has supplied industry standard interfaces such as Asynchronous and Synchronous Slave FIFO, Asynchronous and Synchronous SRAM, and Asynchronous SRAM. Designers who already have one of these pre-defined interfaces in their system can simply select the interface of choice, choose from a set of standard parameters such as bus width (x8, 16, x32) endianess, clock settings, and compile the interface. The tool has a streamlined three step GPIF interface development process for users who need a customized interface. Users are able to first select their pin configuration and standard parameters. Secondly, they can design a virtual state machine using configurable actions. Finally, users can view output timing to verify that it matches the expected timing. Once the three step process is complete, the interface can be compiled and integrated with FX3.



Contents

Functional Overview ..........................................................5

Application Examples ....................................................5

USB Interface ......................................................................6

OTG ...............................................................................6

ReNumeration ...............................................................7

EZ-Dtect ........................................................................7

VBUS Overvoltage Protection .......................................7

Carkit UART Mode ........................................................7

GPIF II ..................................................................................8

CPU ......................................................................................8

JTAG Interface ....................................................................8

Other Interfaces ..................................................................8

SPI Interface ..................................................................8

UART Interface ..............................................................9

I2C Interface ..................................................................9

I2S Interface ..................................................................9

Boot Options .......................................................................9

Reset ....................................................................................9

Hard Reset ....................................................................9

Soft Reset ......................................................................9

Clocking ............................................................................10

32-kHz Watchdog Timer Clock Input ...........................10

Power .................................................................................10

Power Modes ..............................................................11

Digital I/Os .........................................................................13

GPIOs .................................................................................13

System-level ESD .............................................................13

Pin Configurations ...........................................................14

Pin Description .................................................................15

Electrical Specifications ..................................................19

Absolute Maximum Ratings .........................................19

Operating Conditions ...................................................19

DC Specifications ........................................................19

AC Timing Parameters .....................................................21

GPIF II Timing .............................................................21

Slave FIFO Interface ...................................................24

Host Processor Interface (P-Port) Timing ...................30

Serial Peripherals Timing ............................................37

Reset Sequence ..........................................................42

Package Diagram ..............................................................43

Ordering Information ........................................................45

Ordering Code Definitions ...........................................45

Acronyms ..........................................................................46

Document Conventions ...................................................46

Units of Measure .........................................................46

Errata .................................................................................47

Qualification Status .....................................................47

Errata Summary ..........................................................47

Document History Page ...................................................49

Sales, Solutions, and Legal Information ........................52

Worldwide Sales and Design Support .........................52

Products ......................................................................52

PSoC® Solutions ........................................................52

Cypress Developer Community ...................................52

Technical Support .......................................................52



Functional Overview

Cypress’s EZ-USB FX3 is a SuperSpeed peripheral controller, providing integrated and flexible features.

FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor,

ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in

FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and glueless connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA.

FX3 has integrated the USB 3.1 Gen 1 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables

375-MBps data transfer from GPIF II to the USB interface.

An integrated USB 2.0 OTG controller enables applications in which FX3 may serve dual roles; for example, EZ-USB FX3 may function as an OTG Host to MSC as well as HID-class devices.

FX3 contains 512 KB or 256 KB of on-chip SRAM (see

Ordering

Information on page 45) for code and data. EZ-USB FX3 also

provides interfaces to connect to serial peripherals such as

UART, SPI, I

2

C, and I

2

S.

FX3 comes with application development tools. The software development kit comes with firmware and host application examples for accelerating time to market.

FX3 complies with the USB 3.1, Gen 1.0 specification and is also backward compatible with USB 2.0. It also complies with the

Battery Charging Specification v1.1 and USB 2.0 OTG

Specification v2.0.

Application Examples

In a typical application (see

Figure 1 ), the FX3 functions as the

main processor running the application software that connects external hardware to the SuperSpeed USB connection.

Additionally, FX3 can function as a coprocessor connecting via the GPIF II interface to an application processor (see

Figure 2 )

and operates as a subsystem providing SuperSpeed USB connectivity to the application processor.

Figure 1. EZ-USB FX3 as Main Processor

Crystal*

Clock

USB

Host

* A clock input may be provided on the

CLKIN pin instead of a crystal input

USB Ez-USB FX3 GPIF II

I

2

C

EEPROM

External Slave

Device

(e.g. Image

Sensor)



Figure 2. EZ-USB FX3 as a Coprocessor

Crystal*

Clock

USB

Host

USB Ez-USB FX3 GPIF II

External Master

(e.g. MCU/CPU/

FPGA/ASIC)

I

2

C

* A clock input may be provided on the

CLKIN pin instead of a crystal input

USB Interface

FX3 complies with the following specifications and supports the following features:

■

Supports USB peripheral functionality compliant with USB 3.1

Specification Revision 1.0 and is also backward compatible with the USB 2.0 Specification.

■

FX3 Hi-Speed parts (CYUSB201X) only support USB 2.0.

■

Complies with OTG Supplement Revision 2.0. It supports

High-Speed, Full-Speed, and Low-Speed OTG dual-role device capability. As a peripheral, FX3 is capable of SuperSpeed,

High-Speed, and Full-Speed. As a host, it is capable of

High-Speed, Full-Speed, and Low-Speed.

■

Supports Carkit Pass-Through UART functionality on USB

D+/D– lines based on the CEA-936A specification.

■

Supports 16 IN and 16 OUT endpoints.

■

Supports the USB 3.0 Streams feature. It also supports USB

Attached SCSI (UAS) device-class to optimize mass-storage access performance.

■

As a USB peripheral, application examples show that the FX3 supports UAS, USB Video Class (UVC), and Mass Storage

Class (MSC) USB peripheral classes. All other device classes can be supported by customer firmware; a template example is provided as a starting point.

■

As an OTG host, application examples show that FX3 supports

MSC and HID device classes.

Note When the USB port is not in use, disable the PHY and transceiver to save power.

EEPROM

OTG

FX3 is compliant with the OTG Specification Revision 2.0. In

OTG mode, FX3 supports both A and B device modes and supports Control, Interrupt, Bulk, and Isochronous data transfers.

FX3 requires an external charge pump (either standalone or integrated into a PMIC) to power VBUS in the OTG A-device mode.

The Target Peripheral List for OTG host implementation consists of MSC- and HID-class devices.

FX3 does not support Attach Detection Protocol (ADP).



OTG Connectivity

In OTG mode, FX3 can be configured to be an A, B, or dual-role device. It can connect to the following:

■

ACA device

■

Targeted USB peripheral

■

SRP-capable USB peripheral

■

HNP-capable USB peripheral

■

OTG host

■

HNP-capable host

■

OTG device

FX3's charger detects a dedicated wall charger, Host/Hub charger, and Host/Hub.

VBUS Overvoltage Protection

The maximum input voltage on FX3's VBUS pin is 6 V. A charger can supply up to 9 V on VBUS. In this case, an external overvoltage protection (OVP) device is required to protect FX3 from damage on VBUS.

Figure 3

shows the system application diagram with an OVP device connected on VBUS. Refer to

Table 8 for the operating range of VBUS and VBATT.

Figure 3. System Diagram with OVP Device For VBUS

POWER SUBSYSTEM

ReNumeration

Because of FX3's soft configuration, one chip can take on the identities of multiple distinct USB devices.

When first plugged into USB, FX3 enumerates automatically with the Cypress Vendor ID (0x04B4) and downloads firmware and

USB descriptors over the USB interface. The downloaded firmware executes an electrical disconnect and connect. FX3 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called

ReNumeration, happens instantly when the device is plugged in.

8

9

6

7

3

4

5

1

2

OVP device

VBUS

OTG_ID

SSRX-

SSRX+

SSTX-

SSTX+

D-

D+

EZ-USB FX3

EZ-Dtect

FX3 supports USB Charger and accessory detection (EZ-Dtect).

The charger detection mechanism complies with the Battery

Charging Specification Revision 1.1. In addition to supporting this version of the specification, FX3 also provides hardware support to detect the resistance values on the ID pin.

FX3 can detect the following resistance ranges:

■

Less than 10



■

Less than 1 k



■

65 k

 to 72 k

■

35 k

to 39 k

■

99.96 k

 to 104.4 k (102 k2%)

■

119 k

 to 132 k

■

Higher than 220 k



■

431.2 k

 to 448.8 k (440 k2%)

GND

Carkit UART Mode

The USB interface supports the Carkit UART mode (UART over

D+/D–) for non-USB serial data transfer. This mode is based on the CEA-936A specification.

In the Carkit UART mode, the output signaling voltage is 3.3 V.

When configured for the Carkit UART mode, TXD of UART

(output) is mapped to the D– line, and RXD of UART (input) is mapped to the D+ line.

In the Carkit UART mode, FX3 disables the USB transceiver and

D+ and D– pins serve as pass-through pins to connect to the

UART of the host processor. The Carkit UART signals may be routed to the GPIF II interface or to GPIO[48] and GPIO[49], as

shown in Figure on page 8.

In this mode, FX3 supports a rate of up to 9600 bps.

Figure 4. Carkit UART Pass-through Block Diagram

Carkit UART Pass-through

Carkit UART Pass-through

Interface on GPIF II

( )

UART_ TXD

UART_ RXD

Carkit UART Pass-through

Interface on GPIOs

GPIO[48]

(UART_TX)

GPIO[49]

( UART_RX)

TXD

RXD

USB PHY

DP

DM

RXD (DP)

TXD (DM)



GPIF II

The high-performance GPIF II interface enables functionality similar to, but more advanced than, FX2LP’s GPIF and Slave

FIFO interfaces.

The GPIF II is a programmable state machine that enables a flexible interface that may function either as a master or slave in industry-standard or proprietary interfaces. Both parallel and serial interfaces may be implemented with GPIF II.

Here is a list of GPIF II features:

■

Functions as master or slave

■

Provides 256 firmware programmable states

■

Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus

■

Enables interface frequencies up to 100 MHz

■

Supports 14 configurable control pins when a 32- bit data bus is used. All control pins can be either input/output or bidirectional.

■

Supports 16 configurable control pins when a 16/8 data bus is used. All control pins can be either input/output or bi-directional.

GPIF II state transitions are based on control input signals. The control output signals are driven as a result of the GPIF II state transitions. The INT# output signal can be controlled by GPIF II.

Refer to the GPIFII Designer tool. The GPIF II state machine’s behavior is defined by a GPIF II descriptor. The GPIF II descriptor is designed such that the required interface specifications are met. 8 KB of memory (separate from the 256/512 KB of embedded SRAM) is dedicated to the GPIF II waveform where the GPIF II descriptor is stored in a specific format.

Cypress’s GPIFII Designer Tool enables fast development of

GPIF II descriptors and includes examples for common interfaces.

Example implementations of GPIF II are the asynchronous slave

FIFO and synchronous slave FIFO interfaces.

Slave FIFO interface

The Slave FIFO interface signals are shown in

Figure 5 . This

interface allows an external processor to directly access up to four buffers internal to FX3. Further details of the Slave FIFO

interface are described on page 24.

Note Access to all 32 buffers is also supported over the slave

FIFO interface. For details, contact Cypress Applications

Support.

Figure 5. Slave FIFO Interface

SLCS#

PKTEND

External M aster

(For exam ple,

M CU/CPU/

FPGA/ASIC)

FLAGB

FLAGA

A[1:0]

D[31:0]

SLW R#

SLRD#

EZ-USB FX3

SLOE#

Note: M ultiple Flags m ay be configured.


CPU

FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 KB of Instruction Tightly

Coupled Memory (TCM) and 8 KB of Data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware debugging.

FX3 offers the following advantages:

■

Integrates 256/512 KB of embedded SRAM for code and data and 8 KB of Instruction cache and Data cache.

■

Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, GPIF II, I

2

S, SPI, UART,

I

2

C), requiring firmware only to configure data accesses between peripherals, which are then managed by the DMA fabric.

■

Allows easy application development using industry-standard development tools for ARM926EJ-S.

Examples of the FX3 firmware are available with the Cypress

EZ-USB FX3 Development Kit.

JTAG Interface

FX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware through the

CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core can be used for the FX3 application development.

Other Interfaces

FX3 supports the following serial peripherals:

■

SPI

■

UART

■

I

2

C

■

I

2

S

The SPI, UART, and I

2 peripheral port.

S interfaces are multiplexed on the serial

The

CYUSB3012 and CYUSB3014 Pin List on page 15 shows

details of how these interfaces are multiplexed. Note that when

GPIF II is configured for a 32-bit data bus width (CYUSB3012 and CYUSB3014), then the SPI interface is not available.

SPI Interface

FX3 supports an SPI Master interface on the Serial Peripherals port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see

SPI Timing Specification on page 40 for details on the

modes) with the Start-Stop clock. This controller is a single-master controller with a single automated SSN control. It supports transaction sizes ranging from four bits to 32 bits.

Page 8 of 52


UART Interface

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Table 1 .

Table 1. UART Interface Signals

Signal

TX

RX

CTS

RTS

Description

Output signal

Input signal

Flow control

Flow control

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control is enabled, then FX3's UART only transmits data when the CTS input is asserted. In addition to this, FX3’s UART asserts the RTS output signal, when it is ready to receive data.

I

2

C Interface

FX3’s I

2

C interface is compatible with the I

Revision 3. This I

2

2

C Bus Specification

C interface is capable of operating only as I

2 master; therefore, it may be used to communicate with other I

2

C connected to the I

2

C interface, as a selectable boot option.

C slave devices. For example, FX3 may boot from an EEPROM

FX3’s I

2

C Master Controller also supports multi-master mode functionality.

The power supply for the I

2

C interface is VIO5, which is a separate power domain from the other serial peripherals. This gives the I

2

C interface the flexibility to operate at a different voltage than the other serial interfaces.

The I

2

C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz and 1 MHz. The I

2

C controller supports clock-stretching to enable slower devices to exercise flow control.

The I

2

C interface’s SCL and SDA signals require external pull-up resistors. The pull-up resistors must be connected to VIO5.

I

2

S Interface

FX3 has an I

2

S port to support external audio codec devices.

FX3 functions as I

2

S Master as transmitter only. The I

2

S interface consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

The sampling frequencies supported by the I

2

32 kHz, 44.1 kHz, and 48 kHz.

S interface are

Boot Options

FX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are the FX3 boot options:

■

Boot from USB

■

Boot from I

2

C

■

Boot from SPI (SPI devices supported are M25P32 (32 Mbit),

M25P16 (16 Mbit), M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

■

Boot from GPIF II ASync ADMux mode

■

Boot from GPIF II Sync ADMux mode

■

Boot from GPIF II ASync SRAM mode

Table 2. FX3 Booting Options

PMODE[2:0]

[1]

F00

F01

F11

F0F

F1F

1FF

0F1

Boot From

Sync ADMux (16-bit)

Async ADMux (16-bit)

USB boot

Async SRAM (16-bit)

I

2

C, On Failure, USB Boot is Enabled

I

2

C only

SPI, On Failure, USB Boot is Enabled

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3. The specific reset sequence and timing requirements are detailed in

Figure 30 on page 42 and Table 19 on page 42. All I/Os are

tristated during a hard reset. Note however, that the on-chip bootloader has control after a hard reset and it will configure I/O signals depending on the selected boot mode; see AN76405 -

EZ-USB® FX3™ Boot Options for more details.

Soft Reset

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

■

CPU Reset – The CPU Program Counter is reset. Firmware does not need to be reloaded following a CPU Reset.

■

Whole Device Reset – This reset is identical to Hard Reset.

■

The firmware must be reloaded following a Whole Device

Reset.

Note

1. F indicates Floating.



Clocking

FX3 allows either a crystal to be connected between the XTALIN and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer to the specification of the crystal used to determine the appropriate load capacitance. The FSLC[2:0] pins must be configured appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3 .

Table 4. FX3 Input Clock Specifications

Parameter

Phase noise

Maximum frequency deviation

Duty cycle

Overshoot

Undershoot

Rise time/fall time

Description

100-Hz offset

1-kHz offset

10-kHz offset

100-kHz offset

1-MHz offset

–

–

–

–

–

32-kHz Watchdog Timer Clock Input

FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the

FX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from an external source on a dedicated FX3 pin.

The firmware can disable the watchdog timer. Requirements for

the optional 32-kHz clock input are listed in Table 5 .

Table 5. 32-kHz Clock Input Requirements

Parameter

Duty cycle

Frequency deviation

Rise time/fall time

Min

40

–

–

Max

60

±200

200

Units

% ppm ns


Clock inputs to FX3 must meet the phase noise and jitter requirements specified in

Table 4 on page 10.

The input clock frequency is independent of the clock and data rate of the FX3 core or any of the device interfaces. The internal

PLL applies the appropriate clock multiply option depending on the input frequency.

Table 3. Crystal/Clock Frequency Selection

FSLC[2]

0

1

1

1

1

FSLC[1]

0

0

0

1

1

FSLC[0]

0

0

1

0

1

Crystal/Clock

Frequency

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

–

–

–

30

Min

–

–

–

–

–

–

Specification

Max

–75

–104

–120

–128

–130

150

70

3

–3

3

Units

dB ppm

% ns

Power

FX3 has the following power supply domains:

■

❐

❐

❐

❐

❐

❐

IO_VDDQ: This is a group of independent supply domains for digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.

FX3 provides six independent supply domains for digital I/Os listed as follows (see

Table 7 on page 15 for details on each of

the power domain signals):

❐

VIO1: GPIF II I/O

VIO2: IO2

VIO3: IO3

VIO4: UART-/SPI/I

VIO5: I

2

2

S

C and JTAG (supports 1.2 V to 3.3 V)

CVDDQ: This is the supply voltage for clock and reset I/O. It should be either 1.8 V or 3.3 V based on the voltage level of the CLKIN signal.

V

DD

: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the core logic circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscillator, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply voltages for the USB 3.0 interface.

■

VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3's internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Page 10 of 52


Power Modes

FX3 supports the following power modes:

■

Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are enabled in this mode.

❐

Normal operating power consumption does not exceed the sum of I

CC

Core max and I

CC

USB max (see

Table 7 on page

15 for current consumption specifications).

❐

The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface is used in the application.

■

❐

❐

❐

❐

Low-power modes (see

Table 6 on page 11):

Suspend mode with USB 3.0 PHY enabled (L1)

Suspend mode with USB 3.0 PHY disabled (L2)

Standby mode (L3)

Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Suspend Mode with

USB 3.0 PHY

Enabled (L1)

■

■

USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block alone is operational with its internal clock while all other clocks are shut down

■

■

Power supply for the wakeup source and core power must be retained. All other power domains can be turned on/off individually

■

Characteristics

The power consumption in this mode does not exceed ISB

1

All I/Os maintain their previous state

The states of the configuration registers, buffer memory, and all internal RAM are maintained

■

All transactions must be completed before

FX3 enters Suspend mode (state of outstanding transactions are not preserved)

Methods of Entry

■

Firmware executing on

ARM926EJ-S core can put FX3 into suspend mode. For example, on

USB suspend condition, firmware may decide to put FX3 into suspend mode

■

■

Methods of Exit

D+ transitioning to low or high

D- transitioning to low or high

■

External Processor, through the use of mailbox registers, can put FX3 into suspend mode

■

Impedance change on

OTG_ID pin

■

Resume condition on

SSRX±

■

■

■

■

Detection of VBUS

Level detect on

UART_CTS

(programmable polarity)

GPIF II interface assertion of CTL[0]

Assertion of RESET#

■

The firmware resumes operation from where it was suspended (except when woken up by RESET# assertion) because the program counter does not reset



Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode

Suspend Mode with

USB 3.0 PHY

Disabled (L2)

Characteristics

■


2

■

USB 3.0 PHY is disabled and the USB interface is in suspend mode

■

■

The clocks are shut off. The PLLs are disabled

All I/Os maintain their previous state


■


ARM926EJ-S core can put FX3 into suspend mode. For example, on

USB suspend condition, firmware may decide to put FX3 into suspend mode

■

■

Methods of Exit

D+ transitioning to low or high

D- transitioning to low or high

■

External Processor, through the use of mailbox registers can put FX3 into suspend mode

■

Impedance change on

OTG_ID pin

■

Resume condition on

SSRX±

■

USB interface maintains the previous state

■

Detection of VBUS

■


■

Level detect on

UART_CTS

(programmable polarity)

■

The states of the configuration registers, buffer memory and all internal RAM are maintained

■

All transactions must be completed before

FX3 enters Suspend mode (state of outstanding transactions are not preserved)

■

■


Assertion of RESET#

■

The firmware resumes operation from where it was suspended (except when woken up by RESET# assertion) because the program counter does not reset

Standby Mode (L3)

■

The power consumption in this mode does not exceed ISB3

■

All configuration register settings and program/data RAM contents are preserved. However, data in the buffers or other parts of the data path, if any, is not guaranteed. Therefore, the external processor should take care that the data needed is read before putting FX3 into this

Standby Mode

■


ARM926EJ-S core or external processor configures the appropriate register

■

Detection of VBUS

■

Level detect on

UART_CTS

(Programmable

Polarity)

■

■


Assertion of RESET#

■

The program counter is reset after waking up from Standby

■

GPIO pins maintain their configuration

■

Crystal oscillator is turned off

■

Internal PLL is turned off

■

USB transceiver is turned off

■

ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs the program stored in the program/data

RAM

■




Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode

Core Power Down

Mode (L4)

■

Characteristics


4

■

Core power is turned off

■

All buffer memory, configuration registers, and the program RAM do not maintain state. After exiting this mode, reload the firmware


■

Turn off V

DD

■

In this mode, all other power domains can be turned on/off individually

Digital I/Os

Methods of Exit

■

Reapply VDD

■

Assertion of RESET#

EMI

FX3 meets EMI requirements outlined by FCC 15B (USA) and

EN55022 (Europe) for consumer electronics. FX3 can tolerate

EMI, conducted by the aggressor, outlined by these specifications and continue to function as expected.

System-level ESD

FX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal 50-k

 resistor pulls the pins high, while an internal 10-k

 resistor pulls the pins low to prevent them from floating. The I/O pins may have the following states:

■

Tristated (High-Z)

■

Weak pull-up (via internal 50 k

)

■

Pull-down (via internal 10 k

)

■

Hold (I/O hold its value) when in low-power modes

■

The JTAG TDI, TMS, and TRST# signals have fixed 50-k

 internal pull-ups, and the TCK signal has a fixed 10-k

 pull-down resistor.

All unused I/Os should be pulled high by using the internal pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength, half-strength, or quarter-strength. These drive strengths are configured separately for each interface.

GPIOs

EZ-USB enables a flexible pin configuration both on the GPIF II and the serial peripheral interfaces. Any unused control pins

(except CTL[15]) on the GPIF II interface can be used as GPIOs.

Similarly, any unused pins on the serial peripheral interfaces may be configured as GPIOs. See

Pin Configurations for pin

configuration options.

All GPIF II and GPIO pins support an external load of up to 16 pF for every pin.

FX3 has built-in ESD protection on the D+, D–, and GND pins on the USB interface. The ESD protection levels provided on these ports are:

■

±2.2-kV human body model (HBM) based on JESD22-A114

Specification

■

±6-kV contact discharge and ±8-kV air gap discharge based on IEC61000-4-2 level 3A

■

± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C.

This protection ensures the device continues to function after

ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-kV HBM internal ESD protection.



Pin Configurations

G

H

J

K

L

E

F

A

B

C

D

1

U3VSSQ

VIO4

GPIO[54]

GPIO[50]

GPIO[47]

VIO2

VSS

VDD

GPIO[38]

GPIO[35]

VSS

2

U3RXVDDQ

FSLC[0]

GPIO[55]

GPIO[51]

VSS

GPIO[45]

GPIO[42]

GPIO[39]

GPIO[36]

GPIO[33]

VSS

3

SSRXM

Figure 6. FX3 121-ball BGA Ball Map (Top View)

4 5 6 7 8

SSRXP SSTXP SSTXM AVDD VSS

R_USB3

VDD

GPIO[52]

VIO3

GPIO[44]

GPIO[43]

GPIO[40]

GPIO[37]

VSS

VSS

FSLC[1]

GPIO[57]

GPIO[53]

GPIO[49]

GPIO[41]

GPIO[30]

GPIO[31]

GPIO[34]

VSS

GPIO[32]

U3TXVDDQ CVDDQ

RESET# XTALIN

GPIO[56]

GPIO[48]

CLKIN_32

FSLC[2]

GPIO[46]

GPIO[25]

GPIO[29]

GPIO[28]

GPIO[27]

VDD

TCK

GPIO[22]

GPIO[26]

GPIO[16]

GPIO[23]

VSS

AVSS

XTALOUT

CLKIN

TDI

GPIO[2]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

VDD

VSS

R_USB2

VSS

TMS

GPIO[5]

GPIO[15]

GPIO[24]

GPIO[14]

GPIO[17]

INT#

9

DP

VSS

OTG_ID

10

DM

VDD

TDO

I2C_GPIO[58] I2C_GPIO[59]

VDD VBATT

GPIO[1]

GPIO[4]

GPIO[7]

GPIO[0]

GPIO[3]

GPIO[6]

GPIO[9]

GPIO[13]

VIO1

GPIO[8]

GPIO[12]

GPIO[11]

11

NC

TRST#

VIO5

O[60]

VBUS

VDD

VSS

VIO1

VDD

GPIO[10]

VSS

G

H

J

K

L

D

E

F

A

B

C

12

VSS

GPIO[55]

GPIO[56]

GPIO[49]

GPIO[57]

VSS

VIO2

VSS

VIO2

GPIO[35]

VDD

Figure 7. FX3 131-Ball WLCSP Ball Map (Bottom View)

11

VSS

VIO4

VIO3

GPIO[50]

GPIO[48]

GPIO[46]

GPIO[43]

GPIO[40]

GPIO[38]

GPIO[34]

VSS

10

SSRXM

9

SSRXP R_USB3

U3RXVDDQ U3VSSQ

GPIO[53] GPIO[54]

GPIO[51]

GPIO[47]

GPIO[44]

GPIO[41]

GPIO[37]

GPIO[33]

VDD

GPIO[52]

FSLC[1]

GPIO[45]

GPIO[42]

GPIO[36]

GPIO[32]

GPIO[30]

8

SSTXM

SSTXP

U3TXVDDQ

RESET#

O[60]

TDI

VSS

GPIO[39]

GPIO[31]

GPIO[28]

GPIO[29]

7

FSLC[0]

FSLC[2]

CVDDQ

VDD

VSS

VDD

VSS

VSS

GPIO[27]

GPIO[26]

VIO1

6

AVSS

XTALIN

CLKIN_32

I2C_GPIO[58

]

VSS

VDD

VDD

GPIO[20]

GPIO[25]

GPIO[16]

GPIO[23]

5

AVDD

XTALOUT

CLKIN

TMS

VSS

VDD

VSS

GPIO[18]

GPIO[22]

GPIO[21]

VSS

VSS

VDD

GPIO[9]

GPIO[14]

GPIO[19]

INT#

VIO1

4

DP

NC

VSS

VIO5

3

VSS

R_USB2

OTG_ID

TCK

GPIO[3]

GPIO[4]

GPIO[7]

GPIO[12]

GPIO[15]

GPIO[24]

GPIO[17]

2

DM

NC

TDO

I2C_GPIO[59

]

VBATT

GPIO[1]

GPIO[6]

GPIO[8]

GPIO[10]

GPIO[11]

GPIO[13]

1

VDD

VDD

TRST#

VSS

VBUS

GPIO[0]

GPIO[2]

VIO1

GPIO[5]

VSS

VSS

F

G

D

E

A

B

C

H

J

K

L

Note No ball is populated at location A9.

Figure 8. FX3 Hi-Speed 121-Ball BGA Ball Map (Top View)

1

U3VSSQ

VIO4

GPIO[54]

GPIO[50]

GPIO[47]

VIO2

VSS

VDD

GPIO[38]

GPIO[35]

VSS

2

VDD

FSLC[0]

GPIO[55]

GPIO[51]

VSS

GPIO[45]

GPIO[42]

GPIO[39]

GPIO[36]

GPIO[33]

VSS

3

NC

NC

VDD

GPIO[52]

VIO3

GPIO[44]

GPIO[43]

GPIO[40]

GPIO[37]

VSS

VSS

4

NC

FSLC[1]

GPIO[57]

GPIO[53]

GPIO[49]

GPIO[41]

GPIO[30]

GPIO[31]

GPIO[34]

VSS

GPIO[32]

5

NC

VDD

RESET#

GPIO[56]

GPIO[48]

GPIO[46]

GPIO[25]

GPIO[29]

GPIO[28]

GPIO[27]

VDD

6

NC

CVDDQ

XTALIN

CLKIN_32

FSLC[2]

TCK

GPIO[22]

GPIO[26]

GPIO[16]

GPIO[23]

VSS

7

AVDD

AVSS

XTALOUT

CLKIN

TDI

GPIO[2]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

VDD

8

VSS

VSS

R_USB2

VSS

TM S

GPIO[5]

GPIO[15]

GPIO[24]

GPIO[14]

GPIO[17]

INT#

9

DP

VSS

10

DM

VDD

OTG_ID TDO

I2C_GPIO[58] I2C_GPIO[59]

VDD

GPIO[1]

VBATT

GPIO[0]

GPIO[4]

GPIO[7]

GPIO[9]

GPIO[13]

VIO1

GPIO[3]

GPIO[6]

GPIO[8]

GPIO[12]

GPIO[11]

11

NC

TRST#

VIO5

O[60]

VBUS

VDD

VSS

VIO1

VDD

GPIO[10]

VSS



Pin Description

Table 7. CYUSB3012 and CYUSB3014 Pin List

BGA WLCSP

Power

Domain

I/O Name

H8

G5

H6

K5

H7

G7

G6

K6

J6

K8

K7

J7

K10

K9

J8

G8

J5

H5

G4

H4

L4

L8

F8

H10

H9

J10

J9

K11

L10

F10

F9

F7

G10

G9

K2

J4

K1

J2

J3

K3

J6

K7

J7

H6

K5

J5

L6

K6

L3

H5

J4

H3

L2

H4

J3

K8

L8

L9

J8

K9

K4

J1

G2

G3

H2

G4

J2

K2

F1

F2

G1

E3

F3

K10

K11

K12

J9

J10

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[16]

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

GPIO[21]

GPIO[22]

GPIO[23]

GPIO[24]

GPIO[25]

GPIO[26]

GPIO[27]

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

GPIO[10]

GPIO[11]

GPIO[28]

GPIO[29]

GPIO[30]

GPIO[31]

GPIO[32]

INT#

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO1

VIO2

VIO2

VIO2

VIO2

VIO2

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GPIO[33]

GPIO[34]

GPIO[35]

GPIO[36]

GPIO[37]

Description

32-bit Data

Bus

CTL[3]

CTL[4]

CTL[5]

CTL[6]

CTL[7]

CTL[8]

CTL[9]

CTL[10]

DQ[12]

DQ[13]

DQ[14]

DQ[15]

PCLK

CTL[0]

CTL[1]

CTL[2]

GPIF II Interface

DQ[0]

DQ[1]

DQ[2]

DQ[3]

DQ[4]

DQ[5]

DQ[6]

DQ[7]

DQ[8]

DQ[9]

DQ[10]

DQ[11]

CTL[11]

CTL[12]

PMODE[0]

PMODE[1]

PMODE[2]

INT#/CTL[15]

16 - bit Data Bus +

UART+SPI+I2S

DQ[16]

DQ[17]

DQ[18]

DQ[19]

DQ[20]

GPIO

GPIO

GPIO

GPIO

GPIO

16 - bit Data

Bus +

UART+GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Slave FIFO Interface

DQ[0]

DQ[1]

DQ[2]

DQ[3]

DQ[4]

DQ[5]

DQ[6]

DQ[7]

DQ[8]

DQ[9]

DQ[10]

DQ[11]

A1

A0

PMODE[0]

PMODE[1]

16 - bit

Data Bus +

SPI+GPIO

PMODE[2]

CTL[15]

16 - bit Data

Bus +

I2S+GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

DQ[12]

DQ[13]

DQ[14]

DQ[15]

CLK

SLCS#

SLWR#

SLOE#

SLRD#

FLAGA

FLAGB

GPIO

PKTEND#

GPIO

GPIO

GPIO

GPIO only

GPIO

GPIO

GPIO

GPIO

GPIO



B2

C6

C7

B4

E6

D7

Table 7. CYUSB3012 and CYUSB3014 Pin List (continued)

BGA WLCSP

E5

E4

D1

D2

F3

F2

F5

E1

J1

H2

H3

F4

G2

G3

D3

D4

C1

C2

D5

C4

G10

G09

F11

F10

E11

D12

D11

E10

J11

H8

H11

H10

H9

G11

E9

D10

D9

B12

C12

E12

GPIO[38]

GPIO[39]

GPIO[40]

GPIO[41]

GPIO[42]

GPIO[43]

GPIO[44]

GPIO[45]

GPIO[46]

GPIO[47]

GPIO[48]

GPIO[49]

GPIO[50]

GPIO[51]

GPIO[52]

GPIO[53]

GPIO[54]

GPIO[55]

GPIO[56]

GPIO[57]

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VIO2

VIO2

VIO3

VIO3

VIO3

VIO3

VIO3

VIO3

Power

Domain

VIO2

VIO2

VIO2

VIO2

VIO2

VIO2

VIO3

VIO4

VIO4

VIO4

VIO4

VIO4

I/O Name

DQ[21]

DQ[22]

DQ[23]

DQ[24]

DQ[25]

DQ[26]

DQ[27]

GPIO

DQ[28]

DQ[29]

DQ[30]

DQ[31]

I2S_CLK

I2S_SD

I2S_WS

UART_RTS

UART_CTS

UART_TX

UART_RX

I2S_MCLK

B3

C9

A9

A3

A4

A6

A5

A10

C8

B9

C3

A4

A10

B10

A8

B8

A2

B3

U3RXVD

DQ

U3RXVD

DQ

U3TXVD

DQ

U3TXVD

DQ

U3TXVD

DQ

VBUS/

VBATT

VBUS/V

BATT

VBUS/V

BATT

VBUS/VBAT

T

I/O

I/O

O

O

I

I

I/O

I

I/O

SSRXM

SSRXP

SSTXM

SSTXP

R_usb3

OTG_ID

DP

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

UART_RT S

UART_CT S

UART_TX

UART_R X

I2S_CLK

I2S_SD

I2S_WS

SPI_SCK

SPI_SSN

SPI_MIS O

SPI_MOS I

I2S_MCL K

CYUSB301X

SSRX-

SSRX+

SSTX-

SSTX+

Precision resistor for USB 3.0 (Connect a 200

±1% resistor between this pin and GND)

OTG_ID

D+

Description

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

UART_RTS

UART_CTS

UART_TX

UART_RX

GPIO

USB Port

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

SPI_SCK

SPI_SSN

SPI_MISO

SPI_MOSI

GPIO

CYUSB201X

NC

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

I2S_CLK

I2S_SD

I2S_WS

I2S_MCL K

NC

NC

NC

NC

A7

B6

B5

F9

B7

C5

CVDDQ

AVDD

AVDD

CVDDQ

CVDDQ

CVDDQ

I

I/O

I

I

I/O

I

DM

R_usb2

FSLC[0]

XTALIN

XTALOUT

FSLC[1]

FSLC[2]

CLKIN

D–

Precision resistor for USB 2.0 (Connect a 6.04 k ±1% resistor between this pin and GND)

Clock and Reset

FSLC[0]

XTALIN

XTALOUT

FSLC[1]

FSLC[2]

CLKIN

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO



BGA WLCSP

D6

C5

C6

D8

Power

Domain

CVDDQ

CVDDQ

I/O

I

I

Name

CLKIN_32

RESET#

VIO5

VIO5

VIO5

VIO5

VIO5

VIO5

VIO5

VIO5

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

I

I

I

O

I/O I2C_GPIO[58

]

I/O I2C_GPIO[59

]

I

O

TDI

TDO

TRST#

TMS

TCK

O[60]

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

VSS

VIO2

VIO3

VSS

VIO4

VSS

VSS

CVDDQ

PWR U3TXVDDQ

PWR U3RXVDDQ

PWR

PWR

VIO5

VSS

PWR

PWR

PWR

PWR

PWR

AVDD

AVSS

VDD

VSS

VDD

VBATT

VDD

VDD

U3VSSQ

VBUS

VSS

VIO1

VSS

VIO1

VSS

VIO1

VSS

VIO2

D6

D2

F8

C2

C1

D5

D3

E8

A5

A6

F4

D1

C8

C10

D4

A3

F5

B11

A11

A12

C7

H12

G12

C11

F12

L5

L7

L1

J12

C4

H1

K1

L4

E2

B1

A1

C9

E1

E10

B10

–

A1

E11

D8

H11

E2

L9

G1

–

–

F1

G11

E3

L1

B1

L6

–

B6

A7

B7

C3

B8

B5

A2

C11

L11

E9

D9

D10

E7

C10

B11

E8

F6

D11



Description

CLKIN_32

RESET#

I2C and JTAG

I

2

C_SCL

I

2

C_SDA

TDI

TDO

TRST#

TMS

TCK

Charger detect output

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Power

–

–

–

Page 17 of 52

K4

L3

K3

L2

A8

–

A11

B9

F11

–

–

–

–

H1

L7

J11

L5


BGA WLCSP

H7

G7

L11

G8

G6

D7

L10

L12

G5

B4

B2

E4

F6

E5

F7

E6

E7

Power

Domain

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

I/O

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

–

–

Name

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VDD

VSS

VDD

VSS

VSS

VSS

NC

NC


Description

–

–

GND

–

GND

GND

–

–

–

–

–

–

–

–

–

No Connect

No Connect



Electrical Specifications

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device.

Storage temperature .................................... –65 °C to +150 °C

Ambient temperature with power supplied (Industrial) ............................ –40 °C to +85 °C

Ambient temperature with power supplied (Commercial) ............................. 0 °C to +70 °C

Supply voltage to ground potential

V

DD

, A

VDDQ

......................................................................1.25 V

V

IO1

,V

IO2

, V

IO3

, V

IO4

, V

IO5

................................................3.6 V

U3TX

VDDQ

, U3RX

VDDQ

...................................................1.25 V

DC input voltage to any input pin ........................... .V

CC

+ 0.3 V

DC voltage applied to outputs in high Z state ............................................ V

CC

+ 0.3 V

(VCC is the corresponding I/O voltage)

Static discharge voltage ESD protection levels:

■

± 2.2-kV HBM based on JESD22-A114

■

Additional ESD protection levels on D+, D–, and GND pins, and serial peripheral pins

■

± 6-kV contact discharge, ± 8-kV air gap discharge based on

IEC61000-4-2 level 3A, ± 8-kV contact discharge, and ± 15-kV air gap discharge based on IEC61000-4-2 level 4C

Latch-up current .........................................................> 200 mA

Maximum output short-circuit current for all I/O configurations. (Vout = 0 V) ........................ –100 mA

Operating Conditions

T

A

(ambient temperature under bias)

Industrial ........................................................ –40 °C to +85 °C

Commercial ....................................................... 0 °C to +70 °C

V

DD

, A

VDDQ

, U3TX

VDDQ

, U3RX

VDDQ

Supply voltage ..................................................1.15 V to 1.25 V

V

BATT

supply voltage ...............................................3.2 V to 6 V

V

IO1

, V

IO2

, V

IO3

, V

IO4

, C

VDDQ

Supply voltage ......................................................1.7 V to 3.6 V

V

IO5

supply voltage ............................................ 1.15 V to 3.6 V

DC Specifications

Table 8. DC Specifications

Parameter

V

DD

A

VDD

V

IO1

V

IO2

V

IO3

V

IO4

V

BATT

V

BUS

U3TX

VDDQ

U3RX

VDDQ

C

VDDQ

V

IO5

V

IH1

V

IH2

V

IL

Description

Core voltage supply

Analog voltage supply

GPIF II I/O power supply domain

IO2 power supply domain

IO3 power supply domain

UART/SPI/I2S power supply domain

USB voltage supply

USB voltage supply

USB 3.0 1.2-V supply

USB 3.0 1.2-V supply

Clock voltage supply

I

2

C and JTAG voltage supply

Input HIGH voltage 1

Input HIGH voltage 2

Input LOW voltage

Min

1.15

1.15

1.7

Max

1.25

1.25

3.6

Units

V 1.2-V typical

Notes

V 1.2-V typical

V 1.8-, 2.5-, and 3.3-V typical

1.7

1.7

1.7

3.2

4.0

3.6

3.6

3.6

6

6

V

V

V

V

1.8-, 2.5-, and 3.3-V typical

1.8-, 2.5-, and 3.3-V typical

1.8-, 2.5-, and 3.3-V typical

3.7-V typical

1.15

1.25

V 5-V typical

V

1.2-V typical. A 22-µF bypass capacitor is required on this power supply.

N/A for CYUSB201X

1.15

1.25

V

1.2-V typical. A 22-µF bypass capacitor is required on this power supply.

N/A for CYUSB201X

V 1.8-, 3.3-V typical 1.7

3.6

1.15

0.625 ×

VCC

3.6

VCC + 0.3

V 1.2-, 1.8-, 2.5-, and 3.3-V typical

V

For 2.0 V

 V

CC

 3.6 V (except USB port).

VCC is the corresponding I/O voltage supply.

VCC – 0.4 VCC + 0.3

V

For 1.7 V

 V

CC

2.0 V

(except USB port). VCC is the corresponding

I/O voltage supply.

–0.3

0.25 × VCC V VCC is the corresponding I/O voltage supply.



Table 8. DC Specifications (continued)

I

I

I

I

I

I

I

I

V

V

OH

OL

IX

Parameter

OZ

CC

CC

Core

USB

SB1

SB2

SB3

SB4

Output HIGH voltage

Output LOW voltage

Input leakage current for all pins except

Description

SSTXP/SSXM/SSRXP/SSRXM

Output High-Z leakage current for all pins except SSTXP/ SSXM/

SSRXP/SSRXM

Core and analog voltage operating current

USB voltage supply operating current

Total suspend current during suspend mode with USB 3.0 PHY enabled (L1)

Total suspend current during suspend mode with USB 3.0 PHY disabled (L2)

Total standby current during standby mode (L3)

Total standby current during core power-down mode (L4)

Min

0.9 × VCC

–

–1

Max

–

0.1 × VCC

1

Units

V

V

µA

Notes

I

OH

(max) = –100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply.

I

OL

(min) = +100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply.

All I/O signals held at V

DDQ

(For I/Os with a pull-up or pull-down resistor connected, the leakage current increases by

V

DDQ

/R pu

or V

DDQ

/R

PD

–1

–

–

–

–

–

–

1

200

60

–

–

–

–

µA All I/O signals held at V

DDQ mA Total current through A

VDD

, V

DD mA mA mA

µA

µA

–

Core current: 1.5 mA

I/O current: 20 µA

USB current: 2 mA

For typical PVT (typical silicon, all power supplies at their respective nominal levels at

25 °C)

Core current: 250 µA

I/O current: 20 µA

USB current: 1.2 mA

For typical PVT (Typical silicon, all power supplies at their respective nominal levels at

25 °C)

Core current: 60 µA

I/O current: 20 µA

USB current: 40 µA


25 °C)

Core current: 0 µA

I/O current: 20 µA

USB current: 40 µA


25 °C)

I

V

V

V

RAMP

N

N_AVDD

SS

Voltage ramp rate on core and I/O supplies

Noise level permitted on V

DD supplies

and I/O

Noise level permitted on A

VDD

supply

GPIO current source and sink

0.2

–

–

–

50

100

20

20

V/ms Voltage ramp must be monotonic except A mV Max p-p noise level permitted on A mA

VDD

VDD

This rating is for quarter drive strength.

Source/Sink capacity is higher for higher drive strengths.



AC Timing Parameters

GPIF II Timing

Figure 9. GPIF II Timing in Synchronous Mode

tCLKH tCLKL

CLK tCLK tLZ tDS tDH

Data ( IN) tLZ tCO E tCO tDO H

Data 1

( O UT) tHZ tDO H

Data 2

( O UT) tS tH

CTL(IN)

CTL ( O UT) tCTLO tCO H

Table 9. GPIF II Timing Parameters in Synchronous Mode

[2]

Parameter

Frequency tCLK tCLKH tCLKL tS tH tDS tDH tCO tCOE tCTLO tDOH tCOH tHZ tLZ

Interface clock frequency

Interface clock period

Clock high time

Clock low time

CTL input to clock setup time

CTL input to clock hold time

Data in to clock setup time

Data in to clock hold time

Description

Clock to data out propagation delay when DQ bus is already in output direction

Clock to data out propagation delay when DQ lines change to output from tristate and valid data is available on the DQ bus

Clock to CTL out propagation delay

Clock to data out hold

Clock to CTL out hold

Clock to high-Z

Clock to low-Z

4

2

0.5

2

Min

–

10

4

0.5

–

–

0

–

–

2

0

Units

MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns

–

–

–

–

Max

100

–

–

–

8

9

–

8

8

–

–

Note

2. All parameters guaranteed by design and validated through characterization.



DATA/ ADDR

CTL#

(I/P , ALE/ DLE)

DATA OUT

CTL#

(I/P, non ALE/ DLE

ALPHA

O/P

BETA

O/P tCTL#

(O/P)

1. n is an integer >= 0 tCTLbeta tCTLassert

Figure 10. GPIF II Timing in Asynchronous Mode

tDS/ tAS tDH/tAH

DATA IN

tCHZ tCTLassert_DQlatch tAA/tDO tCLZ/ tOELZ tCTLdeassert_DQlatch tCHZ/tOEHZ

DATA OUT

tCTLassert tCTLdeassert tCTLalpha

1 tCTLdeassert

1 tDST tDHT

DATA/

ADDR

CTL#

I/P (non DLE/ALE) tCTLassert_DQassert tCTLdeassert_DQassert

CTL#

(I/P)

Figure 11. GPIF II Timing in Asynchronous DDR Mode

tDS tCTLdeassert_DqlatchDDR tCTLassert_DQlatchDDR tDS tDH tDH

DATA IN



Table 10. GPIF II Timing in Asynchronous Mode

[3, 4]

Note The following parameters assume one state transition

Parameter

tDS tDH tAS tAH tCTLassert tCTLdeassert tCTLassert_DQassert tCTLdeassert_DQassert tCTLassert_DQdeassert tCTLdeassert_DQdeassert tCTLassert_DQlatch tCTLdeassert_DQlatch tCTLassert_DQlatchDDR

Description

Data In to DLE setup time. Valid in DDR async mode.

Data In to DLE hold time. Valid in DDR async mode.

Address In to ALE setup time

Address In to ALE hold time

CTL I/O asserted width for CTRL inputs without DQ input association and for outputs.

CTL I/O deasserted width for CTRL inputs without DQ input association and for outputs.

CTL asserted pulse width for CTL inputs that signify DQ inputs valid at the asserting edge but do not employ in-built latches (ALE/DLE) for those DQ inputs.

CTL deasserted pulse width for CTL inputs that signify DQ input valid at the asserting edge but do not employ in-built latches (ALE/DLE) for those DQ inputs.

CTL asserted pulse width for CTL inputs that signify DQ inputs valid at the deasserting edge but do not employ in-built latches (ALE/DLE) for those DQ inputs.

CTL deasserted pulse width for CTL inputs that signify DQ inputs valid at the deasserting edge but do not employ in-built latches (ALE/DLE) for those DQ inputs.

CTL asserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built latches are always close at the deasserting edge.

CTL deasserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built latches always close at the deasserting edge.

CTL asserted pulse width for CTL inputs that employ in-built latches

(DLE) to latch the DQ inputs in DDR mode.

Min

2.3

2

2.3

2

7

7

20

7

7

20

7

10

10

Max

–

–

–

–

–

–

–

–

–

–

–

–

– ns ns ns ns ns ns ns ns

10 – ns tAA tDO tOELZ tOEHZ tCLZ tCHZ tCTLalpha tCTLbeta tDST tDHT

DQ/CTL input to DQ output time when DQ change or CTL change needs to be detected and affects internal updates of input and output

DQ lines.

CTL to data out when the CTL change merely enables the output flop update whose data was already established.

CTL designated as OE to low-Z. Time when external devices should stop driving data.

CTL designated as OE to high-Z

CTL (non-OE) to low-Z. Time when external devices should stop driving data.

CTL (non-OE) to high-Z

CTL to alpha change at output

CTL to beta change at output

Addr/data setup when DLE/ALE not used

Addr/data hold when DLE/ALE not used

–

–

0

8

0

30

–

–

2

20

30

25

Notes


4. "alpha" output corresponds to "early output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs.

–

8

–

30

25

30

–

– ns ns ns ns ns ns ns ns ns ns

Units

ns ns ns ns ns



Slave FIFO Interface

Synchronous Slave FIFO Read Sequence Description

■

■

■

■

FIFO address is stable and SLCS is asserted

FLAG indicates FIFO not empty status

SLOE is asserted. SLOE is an output-enable only, whose sole function is to drive the data bus.

SLRD is asserted

The FIFO pointer is updated on the rising edge of the PCLK, while the SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tco (measured from the rising edge of PCLK), the new data value is present. N is the first data value read from the

FIFO. To have data on the FIFO data bus, SLOE must also be asserted.

The same sequence of events is applicable for a burst read.

FLAG Usage:

The FLAG signals are monitored for flow control by the external processor. FLAG signals are outputs from FX3 that may be configured to show empty, full, or partial status for a dedicated thread or the current thread that is addressed.

Socket Switching Delay (Tssd):

The socket-switching delay is measured from the time

EPSWITCH# is asserted by the master, with the new socket address on the address bus, to the time the

Current_Thread_DMA_Ready flag is asserted. For the Producer socket, the flag is asserted when it is ready to receive data in the

DMA buffer. For the Consumer socket, the flag is asserted when it is ready to drive data out of the DMA buffer. For a synchronous slave FIFO interface, the switching delay is measured in the number of GPIF interface clock cycles; for an asynchronous slave FIFO interface, in PIB clock cycles. This is applicable only for the 5-bit Slave FIFO interface; there is no socket-switching delay in FX3's 2-bit Slave FIFO interface, which makes use of thread switching in the GPIF™ II state machine.

Note For burst mode, the SLRD# and SLOE# are asserted during the entire duration of the read. When SLOE# is asserted, the data bus is driven (with data from the previously addressed

FIFO). For each subsequent rising edge of PCLK, while the

SLRD# is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.

Figure 12. Synchronous Slave FIFO Read Mode

Synchronous Read Cycle Timing

t

CYC

PCLK t

CH t

CL t

ACCD

SLCS t

AS t

AH

FIFO ADDR t

RDS t

RDH

An Am

SLRD

SLOE

Tssd t

ACCD t

CFLG

Tssd

FLAGA

( dedicated thread Flag for An )

( 1 = Not Empty 0 = Empty )

FLAGB

(dedicated thread Flag for Am )

( 1 = Not Empty 0 = Empty ) t

CFLG

Data Out

SLWR ( HIGH)

High-Z t

OELZ

Data driven:D

N

(An) t

OEZ

High-Z

D

N

(An) t

CDH t

CO

D

N

( Am)

D

N+1

(Am)

D

N+2

(Am) t

OEZ

High-Z



Synchronous Slave FIFO Write Sequence Description

■

FIFO address is stable and the signal SLCS# is asserted

■

External master or peripheral outputs the data to the data bus

■

SLWR# is asserted

■

While the SLWR# is asserted, data is written to the FIFO and on the rising edge of the PCLK, the FIFO pointer is incremented

■

The FIFO flag is updated after a delay of t

WFLG edge of the clock

from the rising

The same sequence of events is also applicable for burst write

Note For the burst mode, SLWR# and SLCS# are asserted for the entire duration, during which all the required data values are written. In this burst write mode, after the SLWR# is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of PCLK. The FIFO pointer is updated on each rising edge of PCLK.

Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND# assertion.

Zero-Length Packet: The external device or processor can signal a Zero-Length Packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and address must

be driven as shown in Figure 13

Figure 13. Synchronous Slave FIFO Write Mode

.

Synchronous Write Cycle Timing

t

CYC

PCLK t

CH t

CL

SLCS

FIFO ADDR

SLWR

FLAGA dedicated thread FLAG for An

( 1 = Not Full 0 = Full)

FLAGB current thread FLAG for Am

( 1 = Not Full 0 = Full)

Data IN

PKTEND

SLOE

( HIGH) t

AS t

AH

Tssd t

WRS

An

t

WRH

Am

High-Z t

DS t

DH

D

N

(An)

tFAD

Tssd t

CFLG t

DS t

DH t

DH

D

N

(Am) D

N+1

(Am) D

N+2

(Am)

t

PES t

PEH tFAD t

CFLG



Figure 14. Synchronous Slave FIFO ZLP Write Cycle Timing

Synchronous ZLP Write Cycle Timing

CYC

PCLK t

CH t

CL

SLCS t

AS t

AH

FIFO ADDR

SLWR

(HIGH)

PKTEND t

PES t

PEH

FLAGA dedicated thread FLAG for An

(1 = Not Full 0= Full)

FLAGB current thread FLAG for Am

(1 = Not Full 0= Full)

Data IN High-Z

SLOE

(HIGH)

Table 11. Synchronous Slave FIFO Parameters

[5]

Parameter

FREQ tCYC tCH tCL tRDS tRDH tWRS tWRH tCO tDS tDH tAS tAH tOELZ tCFLG tOEZ tPES tPEH tCDH tSSD tACCD tFAD


Clock period

Clock high time

Clock low time

SLRD# to CLK setup time

SLRD# to CLK hold time

SLWR# to CLK setup time

SLWR# to CLK hold time

Clock to valid data

Data input setup time

CLK to data input hold

Address to CLK setup time

CLK to address hold time

SLOE# to data low-Z

Description

CLK to flag output propagation delay

SLOE# deassert to Data Hi Z

PKTEND# to CLK setup

CLK to PKTEND# hold

CLK to data output hold

Socket switching delay

Latency from SLRD# to Data

Latency from SLWR# to FLAG

Note Three-cycle latency from ADDR to DATA/FLAGS.

An

Note


Document Number: 001-52136 Rev. *R t

CFLG

0.5

2

0.5

0

2

0.5

–

2

Min

–

10

4

4

2

0.5

2

3

2

2

–

–

2

0.5

–

–

–

–

8

–

–

–

Max

100

–

–

–

–

–

–

68

2

3

–

–

8

8 ns ns ns ns ns ns ns ns

Units

MHz ns ns ns ns ns ns ns ns ns ns

Clock cycles

Clock cycles

Clock cycles

Page 26 of 52


Asynchronous Slave FIFO Read Sequence Description

■

FIFO address is stable and the SLCS# signal is asserted.

■

SLOE# is asserted. This results in driving the data bus.

■

SLRD # is asserted.

■

Data from the FIFO is driven after assertion of SLRD#. This data is valid after a propagation delay of tRDO from the falling edge of SLRD#.

■

FIFO pointer is incremented on deassertion of SLRD#

In Figure 15 , data N is the first valid data read from the FIFO. For

data to appear on the data bus during the read cycle, SLOE# must be in an asserted state. SLRD# and SLOE# can also be tied.

The same sequence of events is also shown for a burst read.

Note In the burst read mode, during SLOE# assertion, the data bus is in a driven state (data is driven from a previously addressed FIFO). After assertion of SLRD# data from the FIFO is driven on the data bus (SLOE# must also be asserted). The

FIFO pointer is incremented after deassertion of SLRD#.

Figure 15. Asynchronous Slave FIFO Read Mode

Asynchronous Read Cycle Timing

SLCS

FIFO ADDR t

AS t

AH

An t

RDl t

RDh

SLRD

SLOE t

FLG

FLAGA dedicated thread Flag for An

(1=Not empty 0 = Empty)

FLAGB dedicated thread Flag for Am

(1=Not empty 0 = Empty)

Data Out High-Z t

OE t

LZ t

RDO t

OH

D

N

(An) t

RFLG

SLWR

(HIGH)

Am t

OE t

RDO

D

N

(An) D

N

(Am) t

RDO

D

N+1

(Am) D

N+2

(Am) t

OH



Asynchronous Slave FIFO Write Sequence Description

■

■

■

■

FIFO address is driven and SLCS# is asserted

SLWR# is asserted. SLCS# must be asserted with SLWR# or before SLWR# is asserted

Data must be present on the tWRS bus before the deasserting edge of SLWR#

Deassertion of SLWR# causes the data to be written from the data bus to the FIFO, and then the FIFO pointer is incremented

■

The FIFO flag is updated after the tWFLG from the deasserting edge of SLWR.

The same sequence of events is shown for a burst write.

Note that in the burst write mode, after SLWR# deassertion, the data is written to the FIFO, and then the FIFO pointer is incremented.

Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND# assertion.

Zero-Length Packet: The external device or processor can signal a zero-length packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and the address

must be driven as shown in Figure 17 on page 29.

FLAG Usage: The FLAG signals are monitored by the external processor for flow control. FLAG signals are FX3 outputs that can be configured to show empty, full, and partial status for a dedicated address or the current address.

Figure 16. Asynchronous Slave FIFO Write Mode

Asynchronous Write Cycle Timing

SLCS

FIFO ADDR

SLWR t

FLG

FLAGA dedicated thread Flag for An

(1= Not Full 0 = Full)

FLAGB dedicated thread Flag for Am

(1= Not Full 0 = Full)

DATA In

High-Z t

AS t

AH

An t

WRl t

WRh t

WR

S t

WFLG t

WRH

D

N

(An)

PKTEND

SLOE

( HIGH)

Am t

WFLG t

WR

S t

WRH

D

N

(Am) D

N+1

(Am) D

N+2

(Am) t t

PEh

Note:



Figure 17. Asynchronous ZLP Write Cycle Timing

S L C S

t

A S

t

A H

F IF O A D D R

A n

S L W R

( H IG H)

P K T E N D

F L A G A d e d ica te d th re a d F la g fo r A n

(1 = N o t F u ll 0 = F u ll)

F L A G B d e d ic a te d th re a d F la g fo r A m

(1 = N o t F u ll 0 = F u ll)

t

P E l

t

P E h

t

W F L G

D A T A In

H ig h-Z

S L O E

( H IG H)

Table 12. Asynchronous Slave FIFO Parameters

[6]

tLZ tOH tWRI tWRh tWRS tWRH tWFLG tPEI tPEh tWRPE tRDI tRDh tAS tAH tRFLG tFLG tRDO tOE

Parameter Description

SLRD# low

SLRD# high

Address to SLRD#/SLWR# setup time

SLRD#/SLWR#/PKTEND to address hold time

SLRD# to FLAGS output propagation delay

ADDR to FLAGS output propagation delay

SLRD# to data valid

OE# low to data valid

OE# low to data low-Z

SLOE# deassert data output hold

SLWR# low

SLWR# high

Data to SLWR# setup time

SLWR# to Data Hold time

SLWR#/PKTEND to Flags output propagation delay

PKTEND low

PKTEND high

SLWR# deassert to PKTEND deassert

Note



10

7

2

–

–

0

–

20

–

–

2

–

Min

20

10

7

20

7.5

2 ns ns ns ns ns ns ns ns ns ns ns ns

Units

ns ns ns ns ns ns

–

–

–

35

25

–

22.5

–

Max

–

–

–

–

35

22.5

25

–

–

–

Page 29 of 52


Host Processor Interface (P-Port) Timing

Asynchronous SRAM Timing

Figure 18. Non-multiplexed Asynchronous SRAM Read Timing

Socket Read – Address Transition Controlled Timing (OE# is asserted)

A[0]

DATA

OUT

HIGH

IMPEDANCE tOH tAA

DATA VALID

DATA VALID DATA VALID

OE# tOE

OE# Controlled Timing

ADDRESS

WE# (HIGH) tAOS

CE#

OE#

DATA OUT tOLZ

HIGH

IMPEDANCE tOE tRC

DATA

VALID tOHH tOEZ

HIGH

IMPEDANCE tOHC

DATA

VALID tAH

HIGH

IMPEDANCE



Figure 19. Non-multiplexed Asynchronous SRAM Write Timing (WE# and CE# Controlled)

Write Cycle 1 WE# Controlled, OE# High During Write

tWC

ADDRESS tCW

CE# tAW tAH tWP

WE# tAS tWPH

OE#

DATA I/O tDS

VALID DATA tWHZ

Write Cycle 2 CE# Controlled, OE# High During Write

tWC

ADDRESS tDH tAS tCW

CE# tAW tAH tWP

WE# tCPH

VALID DATA

OE#

DATA I/O tDS

VALID DATA tDH

VALID DATA tWHZ



Figure 20. Non-multiplexed Asynchronous SRAM Write Timing (WE# controlled, OE# LOW)

Write Cycle 3 WE# Controlled. OE# Low

tWC tCW

CE# tAW tAS tWP

WE#

DATA I/O tDS

VALID DATA tWHZ

Note: tWP must be adjusted such that tWP > tWHZ + tDS tAH tDH tOW

Table 13. Asynchronous SRAM Timing Parameters

[7]

tWPH tCPH tDS tDH tWHZ tOEZ tOW tOE tOLZ tWC tCW tAW tAS tAH tWP tRC tAA

Parameter

– tAOS tOH tOHH tOHC

Description

SRAM interface bandwidth

Read cycle time

Address to data valid

Address to OE# LOW setup time

Data output hold from address change

OE# HIGH hold time

OE# HIGH to CE# HIGH

OE# LOW to data valid

OE# LOW to LOW-Z

Write cycle time

CE# LOW to write end

Address valid to write end

Address setup to write start

Address hold time from CE# or WE#

WE# pulse width

WE# HIGH time

CE# HIGH time

Data setup to write end

Data hold to write end

Write to DQ HIGH-Z output

OE# HIGH to DQ HIGH-Z output

End of write to LOW-Z output

Min

–

32.5

–

7

3

7.5

2

–

0

30

30

30

7

2

20

10

10

7

2

–

–

0

–

–

–

–

25

–

–

–

–

–

–

–

Max

61.5

–

30

22.5

22.5

–

–

–

–

– ns ns ns ns ns ns ns ns ns ns ns ns

Units

Mbps ns ns ns ns ns ns ns ns ns

Note




ADMux Timing for Asynchronous Access

Figure 21. ADMux Asynchronous Random Read

tRC tACC

A[0:7]/DQ[0:15]

Valid Data

ADV#

Valid Address tAVS tVP tAVH

WE# (HIGH) tCEAV

CE# tCPH

OE# tCO tOLZ tOE tHZ tHZ tAVOE

Note:

1. Multiple read cycles can be executed while keeping CE# low.

2. Read operation ends with either de-assertion of either OE# or CE#, whichever comes earlier.

A[0:7]/DQ[0:15]

ADV# tCEAV

CE# tCPH

Figure 22. ADMux Asynchronous Random Write

tWC

Address Valid Data Valid tAVS tVP tAW tAVH tVPH tDS tDH tCW

WE# tWP tAVWE tWPH

Note:

1. Multiple write cycles can be executed while keeping CE# low.

2. Write operation ends with de-assertion of either WE# or CE#, whichever comes earlier.

Valid

Addr

Valid

Addr



Table 14. Asynchronous ADMux Timing Parameters

[8]

Parameter

tRC tACC tCO tAVOE tOLZ tOE tHZ tWC tAW tCW tAVWE tWP tWPH tDS tDH tAVS tAVH tVP tCPH tVPH tCEAV

Description

ADMux Asynchronous READ Access Timing Parameters

Read cycle time (address valid to address valid)

Address valid to data valid

CE# assert to data valid

ADV# deassert to OE# assert

OE# assert to data LOW-Z

Min

54.5

–

–

2

0

Max

–

32

34.5

–

–

Units

ns ns ns ns ns

This parameter is dependent on when the P-port processors deasserts OE#

OE# assert to data valid

Read cycle end to data HIGH-Z

–

–

25

22.5

ns ns

ADMux Asynchronous WRITE Access Timing Parameters

Write cycle time (Address Valid to Address

Valid)

– 52.5

ns

Address valid to write end

CE# assert to write end

ADV# deassert to WE# assert

WE# LOW pulse width

WE# HIGH pulse width

Data valid setup to WE# deassert

Data valid hold from WE# deassert

Address valid setup to ADV# deassert

Address valid hold from ADV# deassert

ADV# LOW pulse width

CE# HIGH pulse width

ADV# HIGH pulse width

CE# assert to ADV# assert

30

30

2

20

10

18

2

5

2

7.5

10

15

0

–

–

–

–

–

–

–

–

–

–

–

–

– ns ns ns ns ns ns ns

ADMux Asynchronous Common READ/WRITE Access Timing Parameters

ns ns ns ns ns ns

Notes

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Note




Synchronous ADMux Timing

Figure 23. Synchronous ADMux Interface – Read Cycle Timing

2- cycle latency from OE# to DATA tCLK tCLKH tCLKL

CLK tCO

A[0:7]/DQ[0:31] tS tH

Valid Address tS tH

Valid Data

ADV# tOHZ tS

CE# tAVOE tOLZ

OE#

RDY tKW tKW tCH

WE# (HIGH)

Note:

1) External P-Port processor and FX3 operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The data is held until OE # deasserts

4) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Figure 24. Synchronous ADMux Interface – Write Cycle Timing

2-cycle latency between

WE# and data being latched

2-cycle latency between this clk edge and RDY deassertion seen by the host

CLK

A[0:7]/DQ[0:31] tS tH

Valid Address tCLK tS tH tDS tDH

Valid Data

ADV# tS

CE# tAVWE tS tH

WE#

RDY tKW tKW

Note:


2) External processor sees RDY assert 2 cycles after WE # asserts and deassert 3 cycles after the edge sampling the data.

3) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader )



Figure 25. Synchronous ADMux Interface – Burst Read Timing

2-cycle latency from OE# to Data tCLK tCLKH tCLKL

CLK tCO

A[0:7]/DQ[0:31] tS tH

Valid Address tS tH

D0 tCH

D1 D2 D3

ADV# tHZ tS

CE# tAVOE tOLZ

OE#

RDY tKW

Note:

1) External P-Port processor and FX3 work operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE # deasserts

4) Burst size of 4 is shown. Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst.

5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader) tKW

Figure 26. Sync ADMux Interface – Burst Write Timing

2-cycle latency between

WE# and data being latched tCLKH tCLKL

2-cycle latency between this clk edge and RDY deassertion seen by the host

CLK tCLK

A[0:7]/DQ[0:31] tS tH

Valid Address tS tH tDS tDH

D0

D1 D2 D3 tDH

ADV#

CE#

WE#

RDY tS tAVWE tKW tKW

Note:


2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data.

3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown

4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)



Table 15. Synchronous ADMux Timing Parameters

[9]

Parameter

FREQ tCLK tCLKH tCLKL tS tH tCH tDS tDH tAVDOE tAVDWE tHZ tOHZ tOLZ tKW


Clock period

Clock HIGH time

Clock LOW time

CE#/WE#/DQ setup time

CE#/WE#/DQ hold time

Clock to data output hold time

Data input setup time

Clock to data input hold

ADV# HIGH to OE# LOW

ADV# HIGH to WE# LOW

CE# HIGH to Data HIGH-Z

OE# HIGH to Data HIGH-Z

OE# LOW to Data LOW-Z

Clock to RDY valid

Description

Serial Peripherals Timing

I

2

C Timing

Figure 27. I

2

C Timing Definition

0

–

–

–

2

0.5

0

0

4

2

0.5

0

Min

–

10

4

–

8

8

8

–

–

–

–

–

–

–

–

Max

100

–

– ns ns ns ns ns ns ns ns ns ns ns ns

Unit

MHz ns ns

Note



fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF tVD:DAT tVD:ACK tSP fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF tVD:DAT tVD:ACK tSP

Table 16. I

2

C Timing Parameters

[10]

Parameter Description

I

2

C Standard Mode Parameters

SCL clock frequency

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

Setup time for a repeated START condition

Data hold time

Data setup time

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

Data valid ACK

Pulse width of spikes that must be suppressed by input filter

I

2

C Fast Mode Parameters

SCL clock frequency

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

Setup time for a repeated START condition

Data hold time

Data setup time

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

Data valid ACK

Pulse width of spikes that must be suppressed by input filter


Max

1000

300

–

–

3.45

3.45

n/a

–

–

–

–

100

–

–

300

–

–

0.9

0.9

50

–

–

–

300

400

–

–

–

Units

ns ns

µs

µs

µs

µs kHz

µs

µs

µs

µs

µs ns ns

µs

µs

µs

µs ns

µs

µs ns ns kHz

µs

µs

µs

Min

–

–

4

4.7

–

– n/a

0

4

4.7

4

4.7

0

250

–

0.6

1.3

–

–

0

0.6

0

100

–

0

0.6

1.3

0.6

Note





SPI Timing Specification

Figure 29. SPI Timing

SSN

(output)

SCK

(CPOL=0,

Output)

SCK

(CPOL=1,

Output)

MISO

(input)

MOSI

(output)

t sdd t lead t wsck t sdi

LSB t hoi t d v

LSB t sck t wsck t di t rf

SPI Master Timing for CPHA = 0

MSB

MSB t lag t ssnh t dis

SSN

(output)

SCK

(CPOL=0,

Output)

SCK

(CPOL=1,

Output)

MISO

(input)

MOSI

(output)

t lead t sck t wsck t wsck t dv t sdi

LSB t hoi t di

LSB t rf t lag t ssnh

MSB t dis

MSB

SPI Master Timing for CPHA = 1


Table 18. SPI Timing Parameters

[12]

tsdd tdv tdi tssnh tsdi thoi tdis

Parameter

fop tsck twsck tlead tlag trf

Operating frequency

Cycle time

Clock high/low time

SSN-SCK lead time

Enable lag time

Rise/fall time

Description

Output SSN to valid data delay time

Output data valid time

Output data invalid

Minimum SSN high time

Data setup time input

Data hold time input

Disable data output on SSN high


Min

0

30

13.5

1/2 tsck

[13 ]

-5

0.5

–

–

–

0

10

8

0

0

Max

33

–

–

1.5 tsck

[13]

+ 5

1.5 tsck

[13]

+5

8

–

–

–

–

–

5

5 ns ns ns ns ns ns ns

Units

MHz ns ns ns ns ns

Notes


13. Depends on LAG and LEAD setting in the SPI_CONFIG register.



Reset Sequence

FX3’s hard reset sequence requirements are specified in this section.

Table 19. Reset and Standby Timing Parameters

Parameter Definition

tRPW Minimum RESET# pulse width tRH tRR tSBY tWU tWH

Minimum high on RESET#

Reset recovery time (after which Boot loader begins firmware download)

Time to enter standby/suspend (from the time MAIN_CLOCK_EN/

MAIN_POWER_EN bit is set)

Time to wakeup from standby

Minimum time before Standby/Suspend source may be reasserted

Figure 30. Reset Sequence

VDD

( core ) xVDDQ

Conditions Min (ms) Max (ms)

Clock Input 1 –

Crystal Input

–

1

5

–

–

Clock Input

Crystal Input

1

5

–

– – 1

Clock Input

Crystal Input

–

1

5

5

–

–

–

XTALIN/

CLKIN

XTALIN/ CLKIN must be stable before exiting Standby/Suspend

Mandatory

Reset Pulse tRR

Hard Reset tRh

RESET # tRPW tSBY tWH tWU

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit is set)

Standby/Suspend source Is deasserted


Package Diagram

Figure 31. 121-ball BGA Package Diagram


001-54471 *D



Figure 32. 131-ball WLCSP (5.099 × 4.695 × 0.60 mm) Package Diagram

Note Underfill is required on the board design. Contact [email protected]

for details.

001-62221 *C



Ordering Information

Table 20. Ordering Information

Ordering Code

CYUSB3011-BZXC

CYUSB3012-BZXC

CYUSB3013-BZXC

CYUSB3014-BZXC

CYUSB3014-BZXI

CYUSB3014-FBXCT

CYUSB3014-FBXIT

CYUSB2014-BZXC

CYUSB2014-BZXI

USB

USB 3.0

USB 3.0

USB 3.0

USB 3.0

USB 3.0

USB 3.0

USB 3.0

USB 2.0

USB 2.0

SRAM (kB) GPIF II Data Bus Width

256 16-bit

256

512

32-bit

16-bit

512

512

512

512

512

512

32-bit

32-bit

32-bit

32-bit

32-bit

32-bit

Operating Temperature

0 °C to +70 °C

0 °C to +70 °C

0 °C to +70 °C

0 °C to +70 °C

–40°C to +85°C

0 °C to +70 °C

–40 °C to +85 °C

0 °C to +70 °C

–40 °C to +85 °C

Package Type

121-ball BGA

121-ball BGA

121-ball BGA

121-ball BGA

121-ball BGA

131-ball WLCSP

131-ball WLCSP

121-ball BGA

121-ball BGA

Ordering Code Definitions



Acronyms

SDIO

SLC

SLCS

SLOE

SLRD

SLWR

SPI

SRP

PMIC

PVT

RTOS

SCL

SCLK

SD

SD

SDA

SSN

UART

UVC

USB

WLCSP

MOSI

MMC

MSC

MTP

OTG

OVP

PHY

PLL

Acronym

DMA

FIFO

GPIF

HNP

I

2

C

I

2

S

MISO

Description

direct memory access first in, first out general programmable interface host negotiation protocol inter-integrated circuit inter IC sound master in, slave out master out, slave in multimedia card mass storage class media transfer protocol on-the-go overvoltage protection physical layer phase locked loop power management IC process voltage temperature real-time operating system serial clock line serial clock secure digital secure digital serial data clock secure digital input / output single-level cell

Slave Chip Select

Slave Output Enable

Slave Read

Slave Write serial peripheral interface session request protocol

SPI slave select (Active low) universal asynchronous receiver transmitter

USB Video Class universal serial bus wafer level chip scale package

Document Conventions

Units of Measure

MHz ms ns

 pF

V

Symbol

°C

µA

µs mA

Mbps

MBps

Unit of Measure

degree Celsius microamperes microseconds milliamperes

Megabits per second

Megabytes per second mega hertz milliseconds nanoseconds ohms pico Farad volts



Errata

This section describes the errata for Revision C of the FX3. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CYUSB301x-xxxx

CYUSB201x-xxxx

Device Characteristics

All Variants

All Variants

Qualification Status

Product Status: Production

Errata Summary

The following table defines the errata applicability to available Rev. C EZ-USB FX3 SuperSpeed USB Controller family devices.

Items

1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working.

2. USB enumeration failure in USB boot mode when FX3 is self-powered.

3. Extra ZLP is generated by the COMMIT action in the

GPIF II state.

4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.

[Part Number]

CYUSB301x-xxxx

CYUSB201x-xxxx

CYUSB301x-xxxx

CYUSB201x-xxxx

CYUSB301x-xxxx

CYUSB201x-xxxx

CYUSB301x-xxxx

CYUSB201x-xxxx

CYUSB301x-xxxx

CYUSB201x-xxxx

Silicon Revision

Rev. C, B, ES

Rev. C, B, ES

Rev. C, B, ES

Rev. C, B, ES

Rev. C, B, ES

Fix Status

Workaround provided

Workaround provided

Workaround provided

Workaround provided

Workaround provided

1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the FX3 to stop working.

■

Problem Definition

Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the FX3 to stop working.

■

Parameters Affected

N/A

■

Trigger Conditions

This condition is triggered when the VIO1 is turned off during Normal, Suspend, and Standby modes.

■

Scope Of Impact

FX3 stops working.

■

Workaround

VIO1 must stay on during Normal, Suspend, and Standby modes.

■

Fix Status

No fix. Workaround is required.

2. USB enumeration failure in USB boot mode when FX3 is self-powered.

■


FX3 device may not enumerate in USB boot mode when it is self-powered. The bootloader is designed for bus power mode. It does not make use of the VBUS pin on the USB connector to detect the USB connection and expect that USB bus is connected to host if it is powered. If FX3 is not already connected to the USB host when it is powered, then it enters into low-power mode and does not wake up when connected to USB host.

■


N/A

■


This condition is triggered when FX3 is self-powered in USB boot mode.

■

Scope Of Impact

Device does not enumerate



■

Workaround

Reset the device after connecting to USB host.

■

Fix Status


3. Extra ZLP is generated by the COMMIT action in the GPIF II state.

■


When COMMIT action is used in a GPIF-II state without IN_DATA action then an extra Zero Length Packet (ZLP) is committed along with the data packets.

■


N/A

■


This condition is triggered when COMMIT action is used in a state without IN_DATA action.

■

Scope Of Impact

Extra ZLP is generated.

■

Workaround

Use IN_DATA action along with COMMIT action in the same state.

■

Fix Status


4. Invalid PID Sequence in USB 2.0 ISOC data transfer.

■


When the FX3 device is functioning as a high speed USB device with high bandwidth isochronous endpoints, the PID sequence of the ISO data packets is governed solely by the isomult setting. The length of the data packet is not considered while generating the PID sequence during each microframe. For example, even if a short packet is being sent on an endpoint with MULT set to 2; the PID used will be DATA2

■


N/A

■


This condition is triggered when high bandwidth ISOC transfer endpoints are used.

■

Scope Of Impact

ISOC data transfers failure.

■

Workaround

This problem can be worked around by reconfiguring the endpoint with a lower isomult setting prior to sending short packets, and then switching back to the original value.

■

Fix Status


5. USB data transfer errors are seen when ZLP is followed by data packet within same microframe.

■


Some data transfer errors may be seen if a Zero Length Packet is followed very quickly (within one microframe or 125 us) by another data packet on a burst enabled USB IN endpoint operating at super speed.

■


N/A

■


This condition is triggered in SuperSpeed transfer with ZLPs

■

Scope Of Impact

Data failure and lower data speed.

■

Workaround

The solution is to ensure that some time is allowed to elapse between a ZLP and the next data packet on burst enabled USB IN endpoints. If this cannot be ensured at the data source, the CyU3PDmaChannelSetSuspend() API can be used to suspend the corresponding USB DMA socket on seeing the EOP condition. The channel operation can then be resumed as soon as the suspend callback is received.

■

Fix Status




Document History Page

Document Title: CYUSB301X/CYUSB201X, EZ-USB

®

Document Number: 001-52136

FX3: SuperSpeed USB Controller

Revision

**

*A

ECN

2669761

2758370

Orig. of

Change

VSO /

PYRS

VSO

Submission

Date

03/06/2009 New data sheet

Description of Change

09/01/2009 Updated the part# from CYX01XXBB to CYUSB3011-BZXI

Changed the title from “ADVANCE” to “ADVANCE INFORMATION”

In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz” to first sub bullet.

In page 1, changed the second bullet “Flexible Host Interface” to General

Programmable Interface”.

In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave

Support” and "MMC Slave support with Pass through Boot" sub bullets.

In page 1, third bullet, changed "50

Power"



A with Core Power" to "60

In page 1, fifth bullet, added "at 1 MHz"

In page 1, seventh bullet, added "up to 4MHz" to UART



A with Core

In page 1, Applications Section, move “Digital Still Cameras” to second line.

In page 1, Applications Section, added “Machine Vision” and Industrial

Cameras”

Added ™ to GPIF and FX3.

In page 1, updated Logic Block Diagram.

In page 2, section of “Functional Overview”, updated the whole section.

In page 2, removed the section of “Product Interface”

In page 2, removed the section of “Processor Interface (P-Port)”

In page 2, removed the section of “USB Interface (U-Port)”

In page 2, removed the section of “Other Interfaces”

In page 2, added a section of "GPIF II"

In page 2, added a section of "CPU"

In page 2, added a section of "JTAG Interface"

In page 2, added a section of "Boot Options"

In page 2, added a section of "ReNumeration"

In page 2, added a section of "Power"

In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3.

In the section of “Package”, added 0.8 mm pitch in front of BGA.

Added Pin List ( Table 1 )

*B

*C

*D

2779196 VSO/PYRS 09/29/2009

Features

:

Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of embedded SRAM”

Added the thrid line “EZ USB™ Software and DVK for easy code development”

Table 1 : Pin 74, corrected to NC - No Connect.

Changed title to EZ-USB™ FX3: SuperSpeed USB Controller

2823531 OSG 12/08/2009 Added data sheet to the USB 3.0 EROS spec 001-51884. No technical updates.

3080927 OSG 11/08/2010 Changed status from Advance to Preliminary

Changed part number from CYUSB3011 to CYUSB3014

Added the following sections:

Power ,

Digital I/Os

,

Digital I/Os

,

System-level

ESD ,

Electrical Specifications ,

AC Timing Parameters ,

Reset Sequence ,

Package Diagram

Added

DC Specifications table

Updated feature list

Updated Pin List

Added support for selectable clock input frequencies.

Updated block diagram

Updated part number

Updated package diagram




(continued)


®



Revision

*E

ECN

3204393

Orig. of

Change

OSG

Submission

Date


03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol

Changed GPIFII asynchronous tDO parameter

Changed Async Slave FIFO tOE parameter

Changed Async Slave FIFO tRDO parameter

Added tCOE parameter to GPIFII Sync mode timing parameters

Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0

Modified description of GPIFII Sync tCO (previously tDO) parameter

Changed tAH(address hold time) parameter in Async Slave FIFO modes to be with respect to rising edge of SLWR#/SLRD# instead of falling edge.

Correspondingly, changed the tAH number.

Removed 24 bit data bus support for GPIFII.

*F 3219493 OSG 04/07/2011 Minor ECN - Release to web. No content changes.

*G

*H

3235250

3217917

GSZ

OSG

*I

*J

*K

*L

*M

*N

3305568

3369042

3534275

3649782

3848148

4016006

DSG

OSG

OSG

OSG

OSG

OSG

04/20/2011 Minor updates in Features.

04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.

Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST# pull-up/pull-down configuration. Minor updates to block diagrams.

Corrected Synchronous Slave FIFO tDH parameter.

07/07/2011 Minor ECN - Correct ECN number in revision *F. No content changes.

12/06/2011 Changed datasheet status from Preliminary to Final.

Changed tWRPE parameter to 2ns

Updated tRR and tRPW for crystal input

Added clarification regarding I

OZ

and I

IX

Updated Sync SLave FIFO Read timing diagram

Updated SPI timing diagram

Removed tGRANULARITY parameter

Updated I2S Timing diagram and tTd parameter

Updated 121-ball BGA package diagram.

Added clarification regarding VCC in DC Specifications table

In Power Modes description, stated that VIO1 cannot be turned off at any time if the GPIFII is used in the application

Updated Absolute Maximum Ratings

Added requirement for by-pass capacitor on U3RX

VDDQ and U3TX

VDDQ

Updated tPEI parameter in Async Slave FIFO timing table

Updated Sync Slave FIFO write and read timing diagrams

Updated I2C interface tVD:ACK parameter for 1MHz operation

Clarified that CTL[15] is not usable as a GPIO

02/24/2012 Corrected typo in the block diagram.

08/16/2012 Changed part number to CYUSB301X.

Added 256 KB range for embedded SRAM.

Updated Functional Overview, Other Interfaces, and Clocking sections.

Added Pin List for CYUSB3011 and CYUSB3013 parts.

Updated Ordering Information with new part numbers.

12/20/2012 Updated 121-ball BGA package diagram to current revision.

05/31/2013 Updated

Features

(Added 131-ball WLCSP under Package option).

Updated Pin Configurations (Added FX3 131-ball WLCSP Ball Map ( Figure 7

)).

Updated

Pin Description (Updated Table 7

).

Updated

Electrical Specifications (Included Commercial Temperature Range

related information).

Updated

Operating Conditions (Included Commercial Temperature Range

related information).

Updated

Package Diagram

(Added 131-ball WLCSP Package Diagram

(

Figure 32 )).

Updated

Ordering Information (Updated part numbers).




(continued)


®



Revision

*O

*P

ECN

4368374

4474200

Orig. of

Change

RSKV

ANOP

Submission

Date


05/02/2014 Updated

Package Diagram

: spec 001-62221 – Changed revision from *B to *C.

Updated to new template.

Completing Sunset Review.

08/14/2014 Added CYUSB201x MPNs, ball map, and pin list to the datasheet.

*Q

*R

4668496

4703347

DBIR

AMDK

02/24/2015 Updated

Features

.

Updated

Logic Block Diagram .

Added related documentation hyperlink in page 1.

Added

More Information .

Updated

Functional Overview

:

Updated

Application Examples :

Updated

Figure 1 .

Updated

Figure 2 .

Updated

USB Interface :

Updated description.

Removed Figure “USB Interface Signals”.

Updated

Pin Configurations

:

Updated

Figure 6 .

Updated

Reset

:

Updated

Hard Reset

:

Updated description.

Updated

Pin Description :

Updated

Table 7

:

Updated entire table.

Modified CVDDQ power domain description.

Removed Table “CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit

Data Bus Width)”.

Removed Table “CYUSB2014 Pin List (GPIF II with 32-bit Data Bus Width)”.

Updated

Electrical Specifications :

Updated

DC Specifications :

Added ISS parameter and its details.

Updated

Slave FIFO Interface

:

Updated

Synchronous Slave FIFO Read Sequence Description

:

Updated

Figure 12 .

Updated

Synchronous Slave FIFO Write Sequence Description

:

Updated

Figure 13 .

Updated

Table 11 .

Updated

AC Timing Parameters :

Added

Host Processor Interface (P-Port) Timing

.

Updated

Acronyms .

Added

Errata .

Replaced West Bridge Benicia with FX3.

03/27/2015 Updated

Slave FIFO Interface

:

Updated

Synchronous Slave FIFO Read Sequence Description

:

Updated

Figure 12 .

Updated

Synchronous Slave FIFO Write Sequence Description

:

Updated

Figure 13 .

Updated

Table 11 :

Updated minimum value of tSSD parameter.

Added tACCD, tFAD parameters and their details.



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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-52136 Rev. *R Revised March 27, 2015 Page 52 of 52

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® respective holders.

is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their

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