IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008 11 Electronic Ballast Control IC With Digital Phase Control and Lamp Current Regulation Yan Yin, Member, IEEE, Mariko Shirazi, and Regan Zane, Senior Member, IEEE Abstract—A digital control architecture is presented for electronic ballasts that provides a phase sweep for reliable, soft lamp ignition and a smooth transition to lamp current regulation mode. The controller is based on an inner phase loop for fast regulation of the resonant tank operating point and an outer current loop for lamp current regulation. The inner loop operates on a simple digital control law that computes the required gate timing relative to the inductor current positive zero crossing. Phase control provides reliable drive of the resonant converter in the presence of large dynamic changes in the load impedance during lamp ignition and warm up and natural tracking of component variations with temperature and time. The primarily digital approach provides programmability for broad application, insensitivity to process and temperature variations, realization in low cost CMOS processes and few external components. Experimental results are presented for an integrated ballast controller fabricated in a 0.8 CMOS process used in a 400 W, 150 kHz HID electronic ballast. Index Terms—Current regulation, digital control, electronic ballast, integrated circuit, over voltage protection, phase control. I. INTRODUCTION H IGH frequency electronic ballasts are used to provide stable ac drive to a variety of discharge lamps. In many cases, different lamp technologies and applications require unique operating modes and conditions for lamp ignition, normal operation, dimming and protection –. This paper presents a digital control architecture for electronic ballasts that provides a phase sweep for reliable, soft lamp ignition and a smooth transition to lamp current regulation mode. The controller is based on an inner phase loop for fast regulation of the resonant tank operating point and an outer current loop for lamp current regulation, as shown in the simplified diagram of Fig. 1. The inner phase loop operates on a simple digital control law that computes the required gate timing relative to the inductor current zero crossing, resulting in near cycle-by-cycle regulation of the phase of the resonant inductor current with respect to the square wave drive . Phase control provides reliable drive of the resonant converter in the presence of large Manuscript received March 30, 2007; revised July 11, 2007. This work was supported in part by the National Science Foundation under Grant 0348772, in part by General Electric Global Research (through CoPEC) and in part by the Department of Energy’s National Energy Technology Laboratory under Cooperative Agreement DE-FC26-02NT41252. Recommended for publication by Associate Editor A. J. Marcos. The authors are with Colorado Power Electronics Center (CoPEC), Department of Electrical and Computer Engineering, University of Colorado at Boulder, Boulder, CO 80309-0425 USA (e-mail: [email protected], [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2007.911869 dynamic changes in the load impedance during lamp ignition and warm up, natural tracking of component variations with temperature and time, simplified control to output dynamics and a more linear relationship between phase command and lamp current when compared to frequency control –. Application of phase control to electronic ballasts have been shown using analog phase-locked loop (PLL) techniques –, self-oscillating circuits , , and digital PLL . The digital timing techniques in this paper were first presented in –, with the benefits of realization in scalable low cost CMOS processes, programmability for broad application, insensitivity to process and temperature variations, and the ability to directly interface with system level digital controllers. A benefit of the system interface is to allow a single core controller to operate independently for lower cost applications (e.g., standard and dimming linear and compact fluorescent lamps, LFL and CFL) that require only basic ignition and current regulation. The same controller may utilize an external system controller for more specialized applications (e.g., high intensity discharge (HID) lamp control with hot re-strike protection and power regulation). The digital interface provides the external controller with sampled information on the ac lamp current and voltage and receives current reference and startup setting commands. The overall architecture was designed for application to a broad range of lamp technologies in order to leverage high volumes for low cost CMOS processing, while limiting the overhead associated with more specialized requirements. The digital phase control algorithm as applied to the ballast control architecture is presented in Section II, followed by integration of the phase controller with lamp ignition and current regulation blocks in Section III. Experimental results are presented in Section IV for an integrated ballast controller fabricated in a 0.8 CMOS process used in a 400 W, 150 kHz HID electronic ballast. Conclusions on the presented work are summarized in Section V. Design details of the analog components in the integrated circuit (IC) controller are given in the Appendix. II. DIGITAL PHASE CONTROLLER The direct digital phase control concept, strategy and discrete hardware verification were first presented in , . The key concept and control algorithm for realization in the ballast control architecture are given here. When the LCC resonant inverter of Fig. 1 is operated above resonance, the resonant inductor dominates the resolags the mid-point nant tank and thus the inductor current from 0 to 90 as the switching frequency shifts voltage 0885-8993/$25.00 © 2007 IEEE Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. 12 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008 Fig. 1. Simplified block diagram of the digital control architecture with two primary ballast control loops: (1) inner phase control and (2) outer lamp current regulation. Fig. 3. State machine for digital phase controller. current to the falling edge of the mid-point voltage can be computed as (1) Fig. 2. Phase control using inductor current i and midpoint voltage v in a half-bridge LCC resonant inverter where HS and LS indicate the high side and low side of the half-bridge, respectively. away from resonance. The output power decreases as the frequency increases above the resonant frequency and the phase angle between mid-point voltage and inductor current increases from 0 to 90 . Thus the output power can be regulated by controlling the phase angle between the midpoint voltage and the inductor current. The benefits of phase control over frequency control have been described in –, as noted in Section I. The strategy to control the inductor current phase is illustrated in Fig. 2. The essence of the control is to measure the resonant period by detecting the inductor current zero crossing, then compute the required time delays from the zero crossing to determine when to turn on or off the high and low side (HS and LS) gate drives to achieve the desired phase. Given a phase command, the time delay from the zero crossing of the inductor is the digital phase comwhere is the measured period, , is the number of bits in the digmand, ital phase command. Note that corresponds to while corresponds to . The final param, is the delay in the gate driver measured in the eter, previous cycle. This optional component is used to compensate phase errors due to gate drive delay . The parameter is measured in each period by counting the time between the edges of from the actual the LS command and a feedback signal LS gate (after the driver). Another control approach based on gate drive timing relative to the inductor current waveform is given in . The control algorithm based on Fig. 2 is implemented in the state machine of Fig. 3. Outputs are generated for both the HS and LS gates based on a programmable dead-time. As seen in Fig. 3, phase control is achieved using a single timer to set the gate drive waveforms relative to the inductor current zero crossing. The state machine can be implemented using a microcontroller or directly synthesized in digital logic gates using automated tools, as in the results presented in Section IV. III. START-UP CONTROLLER AND LAMP CURRENT REGULATION The purpose of the core outer loop blocks including the start-up controller and compensator block and lamp current peak detector in Fig. 1 is to generate appropriate phase commands to perform lamp ignition, warm-up and closed-loop lamp current regulation. Peak detection is performed on the Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. YIN et al.: ELECTRONIC BALLAST CONTROL IC WITH DIGITAL PHASE CONTROL 13 Fig. 4. Block diagram of the peak detector. Fig. 6. Small-signal control-to-output transfer function G command, ', to peak lamp current, i (L = 180 H, C = 3:4 nF, R = 40 , # = 73:8 , f = 140 kHz, V Fig. 5. Block diagram of the combined startup controller and lamp current loop compensator. C = from phase = 5 nF, 400 V). to the small-signal transfer function from the phase command to the sampled peak lamp current . A simulation of is shown in Fig. 6 for the operating parameters shown in the caption. The simulation is generated using the small-signal model developed in , neglecting any higher order dynamics of the inner phase control loop. The results show a single pole open-loop response approximated by (2) lamp current in order to detect lamp ignition and regulate the envelope of the lamp current waveform. Fig. 4 shows a block diagram of the peak detector, which searches for the maximum in each switching period. The clock sampled lamp current signal is generated by the phase controller. Fig. 5 shows a block diagram of the combined start-up module and current regulation compensator. The combined block is used to provide smooth transitions between lamp ignition and current regulation. A multiplexer, MUX, is used to and closed-loop select between a phase sweep command , based on a minimum lamp current current regulation . The start-up module uses a subtractor and a threshold programmable sweep rate to perform a phase sweep for a controlled progression towards resonance and lamp ignition. Once the peak lamp current exceeds the specified threshold , the lamp current compensator takes over. Start phase and minimum phase parameters are also used to protect the ballast, but are not shown in Fig. 5 for simplicity. The in the feedback integral component of the compensator, ( of Fig. 5), is placed on the output of the MUX in order to pre-set the compensator to the phase command at the time of lamp ignition. This avoids a sudden step in the command during mode transitions and helps maintain a stable arc in the lamp. Both the peak detector output and compensator delay are , from the phase latched by the once-per-cycle pulse, controller. The compensator is a simple integral only compensator with programmable gain. The design of the compensator is according Based on (2) a simple integral-type compensator is sufficient to achieve a desired phase margin and high low frequency gain for good lamp current regulation. If the lamp current A/D (analog to digital converter) and effective D/A (digital to analog converter) from the phase controller are interpreted to have unity gain, the loop gain of the outer lamp current regulation loop is given by (3) where is the compensator transfer function and is the lamp current sensing gain. The loop gain in (3) includes a . This is also negative sign due to the 180 phase shift in in Fig. 5 is positive. The integral-type why the summation of compensator is given by (4) where is the discrete-time equivalent of . The hardware implementation of shown in Fig. 5, where and in (4) is (5) and is the error signal. The coefficient in (5) determined from (2)through (4) by extracting from to achieve a desired bandwidth or simulation and solving phase margin from (3). Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. 14 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008 Fig. 7. Block diagram for the custom IC ballast controller. Fig. 8. Experimental setup used to test the ballast IC controller with a half bridge resonant circuit driving a 400 W MH HID lamp. IV. EXPERIMENTAL RESULTS Experimental results are presented here for a custom IC ballast controller fabricated in a 0.8 CMOS process. A more detailed block diagram of the IC controller is shown in Fig. 7. The prototype IC measures 4 mm 3 mm, including test circuitry and I/O pads. An on-chip oscillator provides 10 ns timing resolution, resulting in 0.18 of resolution in phase regulation at 50 kHz operation and 0.72 of resolution in phase regulation at 200 kHz operation. The phase controller provides the based on inductor current posonce-per-cycle pulse itive zero crossing detection to synchronize the peak detector and compensator and also provides a higher frequency synchroat 32 times the cycle clock frequency for nized clock the A/D converter. The phase controller and all logic blocks are synthesized and placed using automated tools. A digitally controlled oscillator (DCO) block and MUX are used to initiate oscillations in the resonant ballast prior to enabling the phase controller for lamp ignition. If the startup module reaches minimum phase without the lamp current exceeding the threshold, the ballast controller drops back into DCO mode and repeats the ignition sequence. The IC also includes ac buffers for inductor and lamp current and lamp voltage sensing, where ac buffers are used to avoid losses and delays associated with external rectifying circuitry. Lamp voltage sensing is used for over-voltage protection, where the controller will drop back into DCO mode in an over-voltage condition and repeat the ignition sequence. The controller also sends a shutdown signal to the gate driver during an over-voltage condition. Thus high voltage ignitions are avoided and the phase sweep is repeated multiple times until the lamp ignites at a sufficiently low voltage. Details of the analog components of the IC are given in the Appendix. The controller of Fig. 7 was evaluated on the LCC half-bridge ballast shown in Fig. 8, using a 400 W high output metal halide (MH) high intensity discharge (HID) lamp from GE (MVR400HO). The ballast has a start-up frequency of 170 kHz and full power operation at 135 kHz. The power MOSFETs are Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. YIN et al.: ELECTRONIC BALLAST CONTROL IC WITH DIGITAL PHASE CONTROL Fig. 9. HID lamp ignition sequence with operating modes labeled, 300 V, i = 4:8 A. V = Fig. 10. Zoom in on HID lamp glow-to-arc dynamics in the first few cycles after ignition. 500 V, 20 A (STW20NM50). A current transformer is used to sense the inductor current , a 0.1 sense resistor is used to and a resistor divider is used to sense the lamp current . sense the lamp voltage Based on the results of Section III and Fig. 6, the compensator gain is selected as 0.25 to achieve a lamp current regulation loop crossover frequency of approximately 1 kHz. This selection also allows a simple hardware implementation by shifting the bits of the error signal two positions to the left and adding it to the previous phase command. To improve accuracy, the two additional bits are always kept during the internal computation, as an 11-bit signal. The final output is trunwhich gives cated to give a 9-bit phase command. Fig. 9 shows a successful lamp ignition sequence with operating modes labeled. Once the lamp ignites, it goes through a short glow-to-arc phase, followed by a warm-up period. During ignition and transition to the warm-up period, the lamp arc is maintained with near cycle-by-cycle regulation of inductor current phase despite dramatic changes in the lamp impedance. Fig. 10 shows a detail view of the challenging lamp dynamics during the glow-to-arc phase. The lamp current waveform is not sinusoidal due to higher order harmonics associated with lamp ignition, including rectifying behavior prior to stable arc operation. The phase controller is unaffected by these dynamics as 15 Fig. 11. Steady-state operating waveforms for i = 2:56 A in Table I. Upper waveform v and lower waveform i . The switching period, T = 7:1 s, i peak-to-peak amplitude and operating phase # = 71 are measured by the oscilloscope. TABLE I LAMP CURRENT REGULATION RESULTS it tracks near constant phase despite variations in the tank input impedance. Changes in the frequency of the midpoint voltage are observed as the phase controller maintains an approximately constant phase (due to the small compensator gain used, the phase command is held approximately constant over the several cycles shown). It should be noted that the controller is regulating the peak value of the lamp current in each switching period. As seen during the glow-to-arc operating conditions, the lamp current peaks are not a good representation of the lamp RMS current. A simple improvement to the controller would be to perform a cycle-by-cycle average of the rectified current waveform as a closer approximation to the RMS value with relatively little processing overhead. This would provide higher currents during initial operation and could help to force the lamp out of the glow-to-arc mode more quickly. Fig. 11 shows steady-state operation of the ballast at a current . A Tektronix TDS 3012B 100 Mz oscommand, cilloscope with calibrated probes is used to measure the phase between the midpoint voltage and inductor current . Table I shows the phase and lamp current regulation results over a range of lamp current reference settings, where internal digital values are shown in hexadecimal (H) and scaled decimal values. The first row, DCO, represents fixed frequency operation prior to the phase sweep for ignition. The next four rows represent separate current commands during normal operation. The lamp current measured by the A/D is approximately 90% of the actual current due to a scale factor in the effective anti-aliasing filter at Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. 16 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008 Fig. 13. Analog ac buffer block diagram. Fig. 12. Repeated ignition attempts of HID lamp with over-voltage protection near 3500 V. the input of the IC. The phase regulation has higher accuracy at higher current levels due to the lower switching frequency and corresponding increase in on-chip phase command resolution. The remaining error is due to a delay between the LS gate drive signal and the midpoint voltage, . The error could be removed directly, requiring an additional high voltage reby sensing sistor divider. The absolute phase is only relevant for protection in setting the minimum phase during the ignition sweep and a few degrees of error is allowable. Finally, Fig. 12 demonstrates over-voltage protection operation with the over-voltage limit set near 3500 V. As shown, the ballast controller repeats the ignition sequence indefinitely until the lamp can ignite below the over-voltage limit. V. CONCLUSIONS A digital control architecture is presented for electronic ballasts that provides a phase sweep for reliable, soft lamp ignition and a smooth transition to lamp current regulation mode. The controller is based on an inner phase loop for fast regulation of the resonant tank operating point and an outer current loop for lamp current regulation. The inner loop operates on a simple digital control law that computes the required gate timing relative to the inductor current positive zero crossing using a single timer and a simple finite state machine. Phase control provides reliable drive of the resonant converter in the presence of large dynamic changes in the load impedance during lamp ignition and warm up and natural tracking of component variations with temperature and time. The primarily digital approach provides programmability for broad application, insensitivity to process and temperature variations, realization in low cost CMOS processes and few external components. Experimental results are presented for an integrated ballast controller fabricated in a 0.8 CMOS process used in a 400 W, 150 kHz HID electronic ballast demonstrating reliable operation during all operating modes of the lamp. Fig. 14. Current mode comparator structure. APPENDIX ANALOG INTERFACE BLOCKS Additional details are given here for the analog interface blocks in the custom IC of Fig. 7, including the ac buffer, A/D and zero-crossing detector circuits. Buffered ac sensing of phase and lamp current and voltage facilitate fast detection, improved efficiency and lower cost by removing external rectifying diodes and filtering. Current-mode circuitry is used for all analog blocks to facilitate ac sensing with minimal external components. The basic ac buffer structure is shown in Fig. 13, configured for a single-ended input. The buffer provides an output current proportional to the driving voltage with matched external resistors [based on two operational transconductance amplifiers (OTAs)]. The OTAs were used instead of operational amplifiers (OPAs) to achieve current-mode outputs and avoid the need for external feedback resistors. The OTAs were implemented using folded cascode techniques with a PMOS input differential pair for an input common mode range that includes the analog in Fig. 13 is ground. The relationship for the output current given by (6) For inductor current zero-crossing detection, a simple current-mode comparator follows the buffer. This comparator is based on the high speed current-mode approach proposed in , with the structure shown in Fig. 14. The output of the comparator is a square wave with a rising edge synchronous to the positive zero crossing of the inductor current waveform. This signal is used by the phase controller to determine the switching period . Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. YIN et al.: ELECTRONIC BALLAST CONTROL IC WITH DIGITAL PHASE CONTROL 17 Fig. 15. Block diagram for current-mode A/D conversion. The output of the A/D is also sampled by the adc clk . Fig. 18. First two MSBs of the asynchronous pipelined A/D converter. Fig. 16. Simplified conceptual diagram of the current-mode rectifier. Fig. 17. Simplified diagram of the current mode sample and hold circuit. For lamp current and voltage A/D conversion, the output current is piped through a channel including an analog current mode rectifier (to simplify A/D), sample and hold, and an asynchronous pipelined A/D converter, as shown in Fig. 15. A conceptual block diagram and description of the current-mode rectifier is shown in Fig. 16. The current-mode comparator and switch are used to steer the input current to the upper mirror for positive values and lower mirror for negative values. A is added into the current small bias current of mirrors to avoid distortion for small input currents, . The current-mode sample and hold circuit is based on a complete clock-feedthrough (CFT) cancellation approach as described in , with a simplified diagram shown in Fig. 17. The sample and hold block samples the full-wave rectified current with a Fig. 19. Experimentally measured digital output vs. analog input for the lamp current A/D converter clocked at 16 times the ballast frequency. selectable sampling frequency of 16 or 32 times the ballast frequency, based on the synchronized clock from the phase controller. This ensures that exactly 16 or 32 samples of output waveforms are taken in each switching period, despite variations in switching frequency. The 6-bit current-mode A/D is realized using an asynchronous pipelined structure, as shown in Fig. 18 for the first two MSBs (most significant bits). The input current to each stage is compared to 1/2 the reference current to get the digital output for that bit. If the input current is greater than 1/2 the reference current, the bit will be on and 1/2 the reference current is subtracted from the input current. The result is multiplied by two, and then passed to the next stage. If the input current is less than 1/2 the reference current, the bit will be off, and the input current is directly multiplied by two and then passed to the next stage. Two identical copies of the sampling and A/D blocks shown in Fig. 15 are used on the IC for lamp current and voltage sensing. Experimental results of one complete ac buffer and A/D converter pipeline are shown in Fig. 19 for the lamp current A/D converter. The output is approximately linear and monotonic, but does include a flat band at one half full scale due to mismatch in the binary weighted pipeline cells. The effect of the flat band is to create a nonlinearity in the response. This has minimal effect on the transient behavior through this band since the converter is still monotonic. However, the mismatch error creating the flat band would have to be fixed in order to achieve Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply. 18 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008 stable lamp current regulation in the flat band region. The experimental results in Section IV with the 400 W HID lamp were performed in the bottom half of the A/D full scale range (below 5 A) in order to avoid the flat band region. REFERENCES  M. C. Cosby and R. M. Nelms, “A resonant inverter for electronic ballast applications,” IEEE Trans. Ind. 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Yan Yin (S’02–M’06) received the B.Eng. and the M.Eng. degrees in electrical engineering from Tsinghua University, Beijing, China, in 1998 and 2000, respectively, and the Ph.D. degree in electrical engineering from the University of Colorado, Boulder, in 2004. Since 2004, he has been with National Semiconductor Corporation, Longmont, CO, as a Senior Circuit Design Engineer for the Power Management Division. His working and research interests include analog and mixed-signal IC design for power management applications, modeling and control of switching converters. Mariko Shirazi received the B.S. degree in mechanical engineering from the University of Alaska, Fairbanks, in 1996 and the M.S. degree in electrical engineering from the University of Colorado, Boulder, in 2007, where she is currently pursuing the Ph.D. degree in electrical engineering. From 1996 to 2004, she was an Engineer at the National Renewable Energy Laboratory’s National Wind Technology Center where she was involved with the design and deployment of hybrid wind-diesel power systems for village power applications. Her current research interests include system-identification and autotuning of digitally controlled switched-mode power supplies. Regan Zane (SM’07) received the B.S, M.S., and Ph.D. degrees in electrical engineering from the University of Colorado, Boulder, in 1996, 1998, and 1999, respectively. He is currently an Assistant Professor of electrical engineering at the University of Colorado. From 1999 to 2001, he worked as a Senior Research Engineer at the GE Global Research Center, Niskayuna, NY. At GE, he developed custom integrated circuit controllers for power management in electronic ballasts and lighting systems. In 2001, he joined the University of Colorado as a faculty member, where he has ongoing research programs in energy-efficient lighting systems, adaptive and robust power management systems, and low power energy harvesting for wireless sensors. Dr. Zane received the NSF Career Award in 2004 for his work in energy efficient lighting systems, the 2005 IEEE Microwave Best Paper Prize, the University of Colorado 2006 Inventor of the Year award and 2006 Provost Faculty Achievement award. He currently serves as Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS LETTERS. Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on November 12, 2008 at 12:37 from IEEE Xplore. Restrictions apply.
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