AT89C51RD2/ED2 Errata

AT89C51RD2/ED2 Errata
Active Errata List
• During UART Reception, Clearing REN May Generate Unexpected IT
• Timer 2 – Baud Rate Generator – Long Start Time
• C51 Core – Bad Exit of Power-down in X2 Mode
Errata History
Lot Number
Errata List
All
1, 2, 3
80C51 MCUs
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is cleared between start bit detection and
the end of reception, the UART will not discard the data (RI is set).
AT89C51RD2
AT89C51ED2
Workaround
Test REN at the beginning of Interrupt routine directly after CLR RI, and run the
Interrupt routine code only if REN is set.
Errata Sheet
2. Timer 2 – Baud Rate Generator – Long Start Time
When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H
at the beginning, then UART is not operational before 10,000 machine cycles.
Workaround
Add the initialization of TH2 and TL2 in the initialization of Timer 2.
3. C51 Core – Bad Exit of Power-down in X2 Mode
When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to
bad execution of the first instruction run when CPU restarts.
Workaround
Set the CPU in X1 mode diretly before entering power-down mode.
Rev. 4257A–8051–06/03
1
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