null  null
CH7313A
Chrontel
CH7313A DVI Transmitter
FEATURES
GENERAL DESCRIPTION
•
The CH7313A is a Display Controller device, which accepts a
digital graphics input signal, encodes and transmits data
through a DVI link (DFP can also be supported) with optional
HDCP support. The device accepts one channel of RGB data
over three pairs of serial data ports.
•
•
•
•
•
•
•
•
•
•
•
Digital Visual Interface (DVI) Transmitter up to
165M pixels/second
High-bandwidth Digital Content Protection (HDCP)
support
DVI low jitter PLL
DVI hot plug detection
High-speed SDVO◊ (1G~2Gbps) AC-coupled serial
differential RGB inputs
Programmable power management
Fully programmable through serial port
Configuration through Intel® Opcodes◊
Complete Windows and DOS driver support
Offered in a 48-pin LQFP package
Boundary scan support
Integrated HDCP Key
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit the
data. The CH7313A is able to drive a DFP display at a
pixel rate of up to 165MHz, supporting UXGA
(1600x1200) resolution displays.
The CH7313A has the ability to become a HDCP rev1.1
Down-stream compliant DVI transmitter by using an
internal HDCP key containing the proper device keys
which can be obtained from Chrontel, Inc.
CH7313A is pin to pin compatible with CH7307C DVI
transmitter and CH7312A.
◊
Intel® Proprietary.
SDVO _R(+,-)
SDVO _G(+,-)
SDVO _B(+,-)
6
Data Latch ,
Serial to Parallel
10bit-8bit
decoder
30
Interrept
Generation
H,V,DE
SDVO _Clk(+,-)
2
SDVO_INT (+/-)
HPDET
Clock Driver
HDCP
Encrypter
HDCP Key
BSCAN
T1
2
DVI PLL
2
2
DVI
Encoder
Test Block
FIFO
DVI
Serializer
DVI
Driver
2
2
2
Reset & Control
RESET *
AS
SPC
SPD
Serial Port
Control
TLC, TLC *
TDC 0, TDC 0*
TDC 1, TDC 1*
TDC 2, TDC 2*
VSWING
SC_PROM
SD_PROM
SC_DDC
SD_DDC
Figure 1: Functional Block Diagram
201-0000-075
Rev. 1.12,
6/1/2006
1
CHRONTEL
CH7313A
Table of Contents
1.0
1.1
1.2
2.0
2.1
2.2
2.3
2.4
2.5
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________5
Functional Description________________________________________________________ 7
Input Interface______________________________________________________________________7
DVI Transmitter ____________________________________________________________________8
HDCP Compatibility ________________________________________________________________8
Command Interface _________________________________________________________________9
Boundary scan Test_________________________________________________________________10
3.0
Register Control ____________________________________________________________ 12
4.0
Electrical Specifications ______________________________________________________ 13
4.1
4.2
4.3
4.4
4.5
2
Pin-Out ____________________________________________________________________ 4
Absolute Maximum Ratings __________________________________________________________13
Recommended Operating Conditions ___________________________________________________13
Electrical Characteristics ____________________________________________________________13
DC Specifications __________________________________________________________________14
AC Specifications __________________________________________________________________16
5.0
Package Dimensions _________________________________________________________ 18
6.0
Revision History ____________________________________________________________ 19
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
Figures and Tables
List of Figures
Figure 1: Functional Block Diagram .............................................................................................................................1
Figure 2: 48-Pin LQFP Pin Out .....................................................................................................................................4
Figure 3: Possible Connection Diagram for HDCP.......................................................................................................9
Figure 4: Control Bus Switch ........................................................................................................................................9
Figure 5: NAND Tree Connection...............................................................................................................................10
Figure 6: 48 Pin LQFP Package ..................................................................................................................................18
List of Tables
Table 1: Pin Description ................................................................................................................................................5
Table 2: CH7313A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................7
Table 3: DVI Output Formats........................................................................................................................................8
Table 4: Popular Panel Sizes .........................................................................................................................................8
Table 5: Signal Order in the NAND Tree Testing .......................................................................................................11
Table 6: Signals not Tested in NAND Test .................................................................................................................11
Table 7: Revisions .......................................................................................................................................................19
201-0000-075
Rev. 1.12,
6/1/2006
3
CHRONTEL
CH7313A
1. PIN-OUT
AVDD
SDVO_CLK-
SDVO_CLK+
AGND
SDVO_B-
SDVO_B+
AVDD
SDVO_G-
SDVO_G+
AGND
SDVO_R-
SDVO_R+
47
46
45
44
43
42
41
40
39
38
37
19
20
21
22
23
24
TDC1*
TDC1
TVDD
TDC2*
TDC2
TGND
DVDD
11
12
18
SC_DDC
TGND
SD_DDC
17
SC_PROM
TDC0
SD_PROM
16
DGND
TDC0*
AGND_PLL
CHRONTEL
CH7313
15
SPD
TVDD
SPC
14
AS
TLC
RESET*
1
2
3
4
5
6
7
8
9
10
13
AVDD_PLL
48
Package Diagram
TLC*
1.1
36
AVDD
35
T1
34
BSCAN
33
SDVO_INT-
32
SDVO_INT+
31
AGND
30
DGND
29
HPDET
28
27
DVDD
26
Reserved
25
VSWING
Reserved
Figure 2: 48-Pin LQFP Pin Out
4
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
1.2
CH7313A
Pin Description
Table 1: Pin Description
Pin #
2
Type
In
Symbol
RESET*
Description
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When
this pin is high, reset is controlled through the serial port register.
3
In
AS
Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0).
When AS is low the address is 72h, when high the address is 70h.
4
In
SPC
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with inputs
from 0 to 2.5V. This pin requires an external 4kΩ - 9kΩ pull up resistor to
2.5V.
5
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin
requires an external 4kΩ - 9 kΩ pull up resistor to 2.5V.
8
In/Out
SD_PROM
Routed Data to PROM
This pin functions as the bi-directional data pin of the serial port for PROM on
ADD2 card. This pin will require a pull-up resistor to the desired high state
voltage. Leave open if unused.
9
Out
SC_PROM
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port to PROM on ADD2 card.
This pin will require a pull-up resistor to the desired high state voltage. Leave
open if unused.
10
In/Out
SD_DDC
Routed Serial Port Data to DDC
This pin functions as the bi-directional data pin of the serial port to DDC
receiver. This pin will require a pull-up resistor to the desired high state
voltage. Leave open if unused.
11
In/Out
SC_DDC
Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver. This pin
will require a pull-up resistor to the desired high state voltage. Leave open if
unused.
13, 14
Out
TLC*, TLC
DVI Clock Outputs
These pins provide the differential clock output for the DVI interface
corresponding to data on the TDC[2:0] outputs.
16,17
Out
TDC0*, TDC0
DVI Data Channel 0 Outputs
19, 20
Out
TDC1*, TDC1
DVI Data Channel 1 Outputs
22, 23
Out
TDC2*, TDC2
DVI Data Channel 2 Outputs
25
In
VSWING
DVI Swing Control
These pins provide the DVI differential outputs for data channel 0 (blue).
These pins provide the DVI differential outputs for data channel 1 (green).
These pins provide the DVI differential outputs for data channel 2 (red).
This pin sets the swing level of the DVI outputs. A 1.2K ohm resistor should
be connected between this pin and TGND using short and wide traces.
26
Out
Reserved
27
Out
Reserved
29
In
HPDET
Reserved
This pin should be left open in the application.
Reserved
This pin should be left open in the application.
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI output driver is connected to a DVI
monitor. When terminated, the monitor is required to apply a voltage greater
than 2.4 volts. Changes on the status of this pin will be relayed to the graphics
controller via the SDVO_INT+/- pins, where toggling between 100MHz and
200MHz is considered an assertion (‘1’ value), not toggling at all is considered
a de-assertion (‘0’ value).
201-0000-075
Rev. 1.12,
6/1/2006
5
CHRONTEL
CH7313A
Table 1: Pin Description (contd.)
Pin #
32, 33
Type
Out
Symbol
SDVO_INT+/-
34
In
BSCAN
Description
Interrupt Output Pair associated with SDVO Data Channel
This pair is used as a hot plug attach/detach notification to VGA controller of a
monitor driven by data SDVO_R+/-, SDVO_G+/-, SDVO_B+/-.
Toggling between 100MHz and 200MHz on this pair is considered an assertion
(‘1’ value); not toggling at all is considered a de-assertion (‘0’ value).
BSCAN (internal pull low)
This pin must be left open (not connected) in the application. This pin enables
the boundary scan for in-circuit testing. See section 12.5 for details. Voltage
level is 0 to DVDD.
35
In
T1
Test Pin (internal pull-down)
This pin must be left open (not connected) in the application.
37, 38, 40, In
41, 43, 44
SDVO_R+/-,
SDVO_G+/-,
SDVO_B+/-
46, 47
In
SDVO_CLK+/-
These pins accept 3 AC-coupled differential pair of inputs from a digital video
port of a graphics controller. These 3 pairs of inputs are R, G, B. The
differential p-p input voltage has a max. value of 1.2V, with a min. value of
175mV.
Differential Clock Input associated with SDVO Data channel
The range of this clock pair is 100~200MHz. For specified pixel rates in
specified modes this clock pair will run at an integer multiple of the pixel rate.
Refer to section 12.1.3 for details. The differential p-p input voltage has a max.
value of 1.2V, with a min. value of 175mV.
12,28
7,30
15, 21
18, 24
36, 42, 48
31, 39, 45
1
6
Power
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
TVDD
TGND
AVDD
AGND
AVDD_PLL
AGND_PLL
Digital Supply Voltage (2.5V)
Digital Ground
DVI Transmitter Supply Voltage (3.3V)
DVI Transmitter Ground
Analog Supply Voltage (2.5V)
Analog Ground
DVI PLL Supply Voltage (3.3V)
DVI PLL Ground
6
SDVO Data Channel Inputs
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
2. FUNCTIONAL DESCRIPTION
2.1
Input Interface
2.1.1 Overview
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The
input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate
(SDVO_CLK+/-). The CH7313A de-serializes the input into 10-bit parallel data with synchronization and alignment.
Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).
2.1.2 Interface Voltage Levels
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level
for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The
differential p-p output voltage has a min of 0.8V, with a max of 1.2V.
2.1.3 Input Clock and Data Timing
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of
the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.
The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate
do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so
that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a
multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters
(‘0001111010’) are used to stuff the data stream. The CH7313A supports the following clock rate multipliers and
fill patterns shown in Table 2.
Table 2: CH7313A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns
Pixel Rate
25~50 MP/s
50~100 MP/s
100~200 MP/s
Clock Rate – Multiplier
100~200 MHz – 4xPixel Rate
100~200 MHz – 2xPixel Rate
100~200 MHz – 1xPixel Rate
Stuffing Format
Data, Fill, Fill, Fill
Data, Fill
Data
Data Transfer Rate - Multiplier
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
2.1.4 Synchronization
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during
the blank period. The CH7313A synchronizes during the initialization period and subsequently uses the blank
periods to re-synch to the data stream.
201-0000-075
Rev. 1.12,
6/1/2006
7
CHRONTEL
2.2
CH7313A
DVI Transmitter
Serialized input data, sync and clock signals are input to the CH7313A from the graphics controller’s digital output
port. Input is through three differential data pairs and one differential clock pair. The data rate is in the range of
1.0~2.0Gbits/s. The clock rate, independent with pixel rate, is 1/10 of the data rate, resulting in the range of
100M~200MHz. Horizontal sync and vertical sync information are embedded in the data stream. Some examples of
modes supported are shown in the Table 3. For Table 3, input pixel frequencies for given modes were taken from
VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING
DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications.
Any values of input pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below
165MHz.
Table 3: DVI Output Formats
Graphics
Resolution
720x400
640x400
640x480
800x600
1024x768
1280x720
1280x768
1280x1024
1366x768
1360x1024
1400x1050
1600x1200
Active Aspect
Ratio
Pixel Aspect
Ratio
Refresh Rate
(Hz)
4:3
8:5
4:3
4:3
4:3
16:9
15:9
4:3
16:9
4:3
4:3
4:3
1.35:1.00
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
<85
<85
<85
<85
<85
<85
<85
<85
<85
<75
<75
<60
Input pixel
Frequency
(MHz)
<35.5
<31.5
<36
<57
<95
<110
<119
<158
<140
<145
<156
<165
DVI
Frequency
(Mbits/Sec)
<355
<315
<360
<570
<950
<1100
<1190
<1580
<1400
<1450
<1560
<1650
Table 4: Popular Panel Sizes
UXGA
SXGA+
SXGA
XGA
SVGA
2.3
1600x1200
1400x1050
1360x1024
1280x1024
1280x960
1024x768
1024x600
800x600
HDCP Compatibility
High Bandwidth Digital Content Protection (HDCP) provides a means of protecting the video transmission between
a DVI video transmitter and a DVI video receiver. The content protection system includes a process of (a)
authentication in which the video transmitter verifies that a given video receiver is licensed to receive protected
content; (b) encryption in which the transmitted video data is encrypted based on secret codes exchanged during the
authentication process; and (c) renewability in which the video transmitter can identify compromised receivers and
prevent the transmission of protected content.
Each HDCP authorized device (transmitter or receiver) has an array of 40, 56-bit secret device keys and a Key
Selection Vector (KSV) obtainable from Digital Content Protection LLC (http://www.digital-cp.com/). With the
addition of the encrypted HDCP device keys, the CH7313A can be configured to be a HDCP compliant transmitter.
A possible connection diagram is shown in the following figure.
8
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
SDVO Data
SDVO Clock
/
6
/
2
SDVO Data
DVI Data Output
/
6
SDVO Clock
CH7313
Serial Data
SPD
Serial Clock
SPC
SDVO
Graphics
Controller
AKSV,
DVI Clock
/
2
HDCP compliant
DVI
receiver
AKEYS,
Internal storage
Authentication exchange
Figure 3: Possible Connection Diagram for HDCP
When the CH7313A is configured as an HDCP non-compliant device, it will not send necessary information to the
graphics controller to be identified as an HDCP compliant device. As a result, the graphics controller will not send
any data that require content protection. Also, the HDCP process is bypassed inside the CH7313A. In this
configuration, the CH7313A operates as DVI Transmitter device similar to the CH7307.
Details of the CH7313A HDCP operation are available in a separate document. Contact Chrontel for details. See
also the “High Bandwidth Digital Content Protection System” specification available at http://www.digital-cp.com/.
2.4
Command Interface
Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7313A accepts incoming
control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM,
DDC, or CH7313A internal registers. The control bus is able to run up to 1MHz when communicating with internal
registers, up to 400kHz for the PROM and up to 100kHz for the DDC.
Internal
Device
Registers
observer
control
the
switch
on/off
Control Bus
from VGA
DDC
default
position
PROM
Figure 4: Control Bus Switch
Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage,
the CH7313A observes the control bus traffic. If the observing logic sees a control bus transaction destined for the
internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers.
In the condition that traffic is to the internal registers, an opcode command is used to set the redirection circuitry to
the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of
traffic to DDC occurs on observing a STOP after a START on the control bus.
201-0000-075
Rev. 1.12,
6/1/2006
9
CHRONTEL
2.5
CH7313A
Boundary scan Test
CH7313A provides so called “NAND TREE Testing” to verify IO cell function at the PC board level. This test will
check the interconnect between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed
circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode,
connects all inputs with NAND gates as shown in Figure 5 and switches each signal to high or low according to the
sequence in
Table 5. The test results then pass out at pin #25 (VSWING).
Figure 5: NAND Tree Connection
Testing Sequence
Set BSCAN =1; (internal weak pull low)
Set all signals listed in
Table 5 to 1.
Set all signals listed in
Table 5 to 0, toggle one by one with certain time period, suggested 100 ns. Pin #25 will change its value each time
an input value changed.
10
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
Table 5: Signal Order in the NAND Tree Testing
Order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
Reserved
Reserved
HPDET
SDVO_INT+
SDVO_INTAS
SPC
SPD
SD_PROM
SC_PROM
SD_DDC
SC_DDC
TLC*
TLC
TDC0*
TDC0
TDC1*
TDC1
TDC2*
TDC2
LQFP Pin
26
27
29
32
33
3
4
5
8
9
10
13
14
16
17
18
19
20
22
23
Table 6: Signals not Tested in NAND Test
Pin Name
SDVO_R+
SDVO_RSDVO_G+
SDVO_GSDVO_B+
SDVO_BSDVO_CLK+
SDVO_CLKRESET*
BSCAN
Reserved
VSWING
201-0000-075
Rev. 1.12,
LQFP Pin
37
38
40
41
43
44
46
47
2
26
27
25
6/1/2006
11
CHRONTEL
CH7313A
3. REGISTER CONTROL
The CH7313A is controlled via a serial control port. The serial bus uses only the SC clock to latch data into
registers, and does not use any internally generated clocks so that the device can be written to in all power down
modes. The device will retain all register values during power down modes.
Registers 00h to 11h are reserved for opcode use. All registers except bytes 00h to 11h are reserved for internal
factory use. For details regarding Intel® SDVO opcodes, please contact Intel®.
12
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
4. ELECTRICAL SPECIFICATIONS
4.1
Absolute Maximum Ratings
Symbol
Description
Min
All 2.5V power supplies relative to GND
All 3.3V power supplies relative to GND
-0.5
-0.5
TSC
Analog output short circuit duration
TAMB
Ambient operating temperature
TSTOR
Storage temperature
TJ
TVPS
Typ
Max
Units
3.0
5.0
V
Indefinite
Sec
0
85
°C
-65
150
°C
Junction temperature
150
°C
Vapor phase soldering (5 second )
260
°C
Vapor phase soldering (11 second )
245
°C
Vapor phase soldering (60 second )
225
°C
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce
destructive latchup.
4.2
Recommended Operating Conditions
Symbol
Description
Min
Typ
Max
Units
AVDD
Analog Power Supply Voltage
2.375
2.5
2.625
V
AVDD_PLL
Analog PLL Power Supply Voltage
3.100
3.3
3.500
V
DVDD
Digital Power Supply Voltage
2.375
2.5
2.625
V
TVDD
DVI Power Supply
3.100
3.3
3.500
V
VDD33
Generic for all 3.3V supplies
3.100
3.3
3.500
V
VDD25
Generic for all 2.5V supplies
2.375
2.5
2.625
V
Typ
Max
Units
4.3
Electrical Characteristics
(Operating Conditions: TA = 0°C – 70°C, VDD25 =2.5V ± 5%, VDD33=3.3V± 5%)
Symbol
Description
IVDD25
Total VDD25 supply current (2.5V supplies)
Pixel Rate=162MHz
Total VDD33 supply current (3.3V supply)
Pixel Rate=162MHz
IVDD33
IPD
201-0000-075
Min
Total Power Down Current (all supplies)
Rev. 1.12,
6/1/2006
210
mA
75
mA
100
µA
13
CHRONTEL
4.4
CH7313A
DC Specifications
Symbol
Description
Test Condition
VRX-DIFFp-p = 2 *
⏐VRX-D+ - VRX-D-⏐
Min
Typ
Max
Unit
1.200
V
VRX-DIFFp-p
SDVO Receiver Differential
Input Peak to Peak Voltage
ZRX-DIFF-DC
SDVO Receiver DC
Differential Input Impedance
80
100
120
Ω
ZRX-COM-DC
SDVO Receiver DC Common
40
50
60
Ω
5
50
60
Ω
0.175
Mode Input Impedance
ZRX-COMINITIAL-DC
SDVO Receiver Initial DC
Common Mode Input
Impedance
Impedance allowed
when receiver
terminations are first
turned on
SDVO INT Differential Output
Peak to Peak Voltage
VINT-DIFFp-p
VSPOL 1
Serial Port
0.8
IOL = 2.0 mA
1.2
V
0.4
V
V
Output Low Voltage
VSPIH 2
VSPIL 2
VHYS 2
Serial Port
Input High Voltage
2.0
VDD25 +
0.5
Serial Port
Input Low Voltage
GND-0.5
0.4
V
Serial Port
VDDCIH
VDDCIL
VPROMIH
VPROMIL
VSD_DDCOL3
V
Input Hysteresis
0.25
DDC Serial Port
Input High Voltage
4.0
VDD5 +
0.5
DDC Serial Port
Input Low Voltage
GND-0.5
0.4
V
PROM Serial Port
VDD5 +
Input High Voltage
4.0
0.5
PROM Serial Port
Input Low Voltage
GND-0.5
0.4
SPD (serial port data) Output
Low Voltage from SD_DDC
(or SD_PROM)
V
Input is VINL at
SD_DDC or
SD_PROM.
0.9*VINL +
0.25
V
0.933*VINL
+ 0.35
V
0.933*VINL
+ 0.35
V
4.0kΩ pullup to 2.5V.
VDDCOL
4
SC_DDC and SD_DDC
Output Low Voltage
Input is VINL at SPC
and SPD.
5.6kΩ pullup to 5.0V.
VPROMOL5
SC_PROM and SD_PROM
Output Low Voltage
Input is VINL at SPC
and SPD.
5.6kΩ pullup to 5.0V.
VMISC1IH
6
VMISC1IL 6
RESET*, BSCAN
Input High Voltage
2.7
VDD33 +
0.5
V
RESET*, BSCAN
GND-0.5
0.5
V
2.0
VDD25 +
V
Input Low Voltage
VMISC2IH7
AS, T1
Input High Voltage
14
0.5
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
Symbol
VMISC2IL
7
CH7313A
Description
Test Condition
AS, T1
DVDD=2.5V
Min
Typ
Max
Unit
GND-0.5
0.5
V
2.0
VDD33 +
0.5
V
GND-0.5
0.5
V
Input Low Voltage
VMISC3IH8
HPDET
Input High Voltage
VMISC3IL8
HPDET
Input Low Voltage
DVDD=2.5V
IMISC1PD
BSCAN
Pull Down Current
VIN = 3.3V
10
40
µA
IMISC1PU
RESET*
Pull Up Current
VIN = 0V
10
40
µA
IMISC2PD
HPDET,
Pull Down Current
VIN = 2.5V
5
20
µA
IMISC2PU
AS
Pull Up Current
VIN = 0V
10
40
µA
DVI Single Ended Output
High Voltage
TVDD = 3.3V ± 5%
TVDD –
0.01
TVDD +
0.01
V
TVDD –
0.6
TVDD –
0.4
V
400
600
mVp-p
TVDD –
0.01
TVDD +
0.01
V
VH
VL
VSWING
VOFF
DVI Single Ended Output Low
Voltage
DVI Single Ended Output
Swing Voltage
DVI Single Ended Standby
Output Voltage
RTERM = 50Ω ± 1%
RSWING = 1200Ω ± 1%
Notes:
1. Refers to SPD. VSPOL is the output low voltage from SPD when transmitting from internal registers not from DDC or EEPROM.
2. Refers to SPC, SPD.
3. VSD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_PROM is VINL. Maximum output voltage
has been calculated with a worst case pull up of 4.0kΩ to 2.5V on SPD.
4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output
voltage has been calculated with 5.6k pull up to 5V on SC_DDC and SD_DDC.
5. VPROMOL is the output low voltage at the SC_PROM and SD_PROM pins when the voltage at SPC and SPD is VINL. Maximum
output voltage has been calculated with 5.6kΩ pull up to 5V on SC_PROM and SD_PROM.
6. VMISC1 refers to RESET* and BSCAN inputs which are 3.3V compliant.
7. VMISC2 refers to AS which are 2.5V compliant.
8. VMISC3 refers to HPDET which are 2.5V/3.3V compliant.
201-0000-075
Rev. 1.12,
6/1/2006
15
CHRONTEL
4.5
CH7313A
AC Specifications
Symbol
Description
UIDATA
SDVO Receiver Unit Interval
for Data Channels
Test Condition
Min
Typ
Max
Unit
Typ. –
300ppm
1/[Data
Transfer
Typ. +
300ppm
ps
Rate]
fSDVO_CLK
SDVO CLK Input Frequency
100
200
MHz
DVI Transmitter Pixel Rate
25
165
MHz
fSYMBOL
SDVO Receiver Symbol
Frequency
1
2
GHz
tRX-EYE
SDVO Receiver Minimum Eye
Width
fPIXEL
tRX-EYE-JITTER
0.4
UI
SDVO Receiver Max. time
0.3
UI
150
mV
between jitter median and
max. deviation from median
VRX-CM-Acp
SDVO Receiver AC Peak
Common Mode Input Voltage
RLRX-DIFF
Differential Return Loss
50MHz – 1.25GHz
15
dB
RLRX-CM
Common Mode Return Loss
50MHz – 1.25GHz
6
dB
tSKEW
SDVO Receiver Total Lane to
Lane Skew of Inputs
Across all lanes
tDVIR
DVI Output Rise Time
fXCLK = 165MHz
fXCLK = 165MHz
2
ns
75
242
ps
75
242
ps
(20% - 80%)
tDVIF
DVI Output Fall Time
(20% - 80%)
TSPR
TSPF
SPC, SPD Rise Time
Standard mode 100k
1000
ns
(20% - 80%)
Fast mode 400k
300
ns
1M running speed
150
ns
SPC, SPD Fall Time
Standard mode 100k
300
ns
(20% - 80%)
Fast mode 400k
300
ns
1M running speed
150
ns
TPROMR
SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K
300
ns
TPROMF
SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K
300
ns
TDDCR
SC_DDC, SD_DDC Rise
Time (20% - 80%)
Standard mode 100k
1000
ns
TDDCF
SC_DDC, SD_DDC Fall
Standard mode 100k
300
ns
Time (20% - 80%)
TDDCR-DELAY1
SC_DDC, SD_DDC Rise
Time Delay (50%)
Standard mode 100k
0
ns
TDDCF-DELAY1
SC_DDC, SD_DDC Fall
Standard mode 100k
3
ns
Time Delay (50%)
tSKDIFF
16
DVI Output intra-pair skew
fXCLK = 165MHz
90
201-0000-075
Rev. 1.12,
ps
6/1/2006
CHRONTEL
Symbol
CH7313A
Description
Test Condition
Min
Typ
Max
Unit
tSKCC
DVI Output inter-pair skew
fXCLK = 165MHz
1.2
ns
tDVIJIT
DVI Output Clock Jitter
fXCLK = 165MHz
150
ps
Notes:
1.
Refers to the figure below, the delay refers to the time pass through the internal switches.
3.3V typ.
2.5V typ.
R=5K
To SPC/SPD pin
To DDC pin
201-0000-075
Rev. 1.12,
6/1/2006
17
CHRONTEL
CH7313A
5. PACKAGE DIMENSIONS
TOP VIEW
BOTTOM VIEW
A
B
K
25
36
24
37
B
48
A
K
13
12
1
EXPOSED PAD
D
C
F
E
I
.008"
J
H
G
Figure 6: 48 Pin LQFP Package
Table of Dimensions
No. of Leads
48 (7 X 7 mm)
MilliMIN
meters
MAX
Notes:
18
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
9
7
0.50
0.17
0.27
1.35
1.45
0.05
0.15
1.00
0.45
0.75
0.09
0.20
0°
7°
4
5.5
1.
Conforms to JEDEC standard JESD-30 MS-026D.
2.
Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3.
Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
201-0000-075
Rev. 1.12,
6/1/2006
CHRONTEL
CH7313A
6. REVISION HISTORY
Table 7: Revisions
Rev. #
0.41
0.9
1.0
1.1
1.11
Date
3/9/05
8/4/05
8/31/05
9/27/05
9/30/05
201-0000-075
Section
All
All
All
4.5
4.4
Rev. 1.12,
6/1/2006
Description
First draft based on Eng. Spec. 0.41.
Update all
Official Release
Updated timing spec
Updated DC spec and ordering information
19
CHRONTEL
CH7313A
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
CH7313A-DEF
CH7313A-DEF-TR
Package Type
Number of
Pins
Voltage Supply
48
2.5V & 3.3V
48
2.5V & 3.3V
Lead free LQFP with
exposed pad
Lead free LQFP with
exposed pad in Tape
& Reel
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: [email protected]
©2006 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
20
201-0000-075
Rev. 1.12,
6/1/2006
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement