PIC16C712/716 PIC16C712/716 Rev. A Silicon/Data Sheet Errata The PIC16C712/716 parts you have received conform functionally to the Device Data Sheet (DS41106A), except for the anomalies described below. Note: The problem here will be addressed in future revisions of the PIC16C712/716 silicon. 1. The TCCP bit of the TRISCCP register functions as described in Figure 7-2 of the Device Data Sheet, when using the MPLAB® ICE 2000 in-circuit emulator Module: CCP Work around When using the PIC16C712/716 in the Compare or PWM mode, the TCCP bit of the TRISCCP register will not tristate the output on pin RB3, as described in Figure 7-2 of the Device Data Sheet. The TCCP bit of the TRISCCP register has no effect on the output of pin RB3. There is no way to tristate the output on pin RB3 in the Compare or PWM mode. However, there are steps you can do in firmware to stop the RB3 pin from changing and leave it in a known state. Examples are shown below. EXAMPLE 1: (Assumes that the T2CON and CCP1CON values are determined at assembly time and remain fixed.) Software License Agreement The software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, the Company’s customer, for use solely and exclusively with products manufactured by the Company. The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. Code Example 1A: ;*********************************************************************** ; Call these routines to turn the PWM off or on and ensure a Zero output on RB3 ; when PWM is off. ; ; PWMreset - Clear T2CON Disabling Timer2 and Clearing Timer 2 Prescaler, ; then fill the TMR2 register with the CCPR1H value. This will cause ; a Reset or Zero value on RB3. ; ; ; ; PWMrestart - Restore the T2CON register with the appropriate value for your system needs. IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE CORRECT VALUE FOR T2CON. Assembly Code To Stop PWM Once Started: PWMreset bcf clrf movf movwf return STATUS,RP0 T2CON CCPR1H,W TMR2 2003 Microchip Technology Inc. ; ; ; ; Select Bank 0 Clear T2CON, Timer2-Disable & Pre/Post Scalers = 1 Load CCPR1H value in Write register Move CCPR1H value into TMR2 to cause Reset of RB3 pin DS80072D-page 1 PIC16C712/716 Assembly Code To Start PWM Once Stopped: PWMrestart bcf movlw movwf return STATUS,RP0 T2CONVAL T2CON ; ; ; ; Select Bank 0 Load T2CON value in ‘w’ register - USER RESPONSIBLE FOR SUPPLYING THE CORRECT T2CON VALUE. Initialize T2CON enabling scalers and Timer2 Code Example 1B: ;*********************************************************************** ; ; Call these routines to turn the CCP Mode off or on and ensure RB3 is a known Input or Output value when CCP Mode is off. ; ; ; ; ; ; CCPstop - First sets RB3 to an Input or an Output. If RB3 is an Output then it’s state is made either High or Low. The CCP is then Disabled. CCPstart - Enable CCP Mode. IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE CORRECT VALUE FOR CCP1CON. Assembly Code To Stop CCP Mode Once Started: CCPstop bsf bcf STATUS,RP0 TRISB,3 bcf bcf STATUS,RP0 PORTB,3 movlw movwf return 0x30 CCP1CON ; ; ; ; ; ; ; ; ; Select Bank 1 RB3 as an Output - set bit TRISB, 3 when RB3 as an Input is desired. Select Bank 0 RB3 as a Low Level Output - Set bit TRISB,3 for RB3 to be a High Level Output. Load CCP1CON value in Working register Turn Off CCP1CON all Modes Assembly Code To Start CCP Mode Once Stopped: CCPstart bcf movlw movwf return DS80072D-page 2 STATUS,RP0 CCP1CONVAL CCP1CON ; ; ; ; Select Bank 0 Load CCP1CON value in Working register. THE USER IS RESPONSIBLE FOR SUPPLYING THE CORRECT CCP1CON VALUE. Initialize CCP1CON for desired Mode of operation. 2003 Microchip Technology Inc. PIC16C712/716 EXAMPLE 2: (Assumes that the T2CON and CCP1CON values may change during program execution. One SRAM location is used for temporary storage of T2CON or CCP2CON.) Code Example 2A: ;*********************************************************************** ; Call these routines to turn the PWM off or on and ensure a Zero output on RB3 ; when PWM is off. ; ; PWMreset - Saves T2CON value in RAM location. IT IS THE RESPONSIBILITY OF THE USER TO SUPPLY ; RAM MEMORY SPACE TO SAVE THE T2CON VALUE. ; Clears T2CON register Disabling Timer2 and clearing Timer2 Prescaler. ; The TMR2 register is then filled with the CCPR1H value. This causes a Reset ; or Zero value on RB3. ; ; PWMrestart - Enable Timer2 Assembly Code To Stop PWM Once Started: T2CONSAV equ 0x?? ; USER RESPONSIBLE FOR SUPPLYING RAM MEMORY SPACE ; TO SAVE T2CON VALUE. PWMreset bcf movf movwf clrf movf movwf return STATUS,RP0 T2CON,W T2CONSAV T2CON CCPR1H,W TMR2 ; ; ; ; ; ; Select Bank 0 Move T2CON Value to ‘w’ register Save T2CON register value Clear T2CON, Timer2-Disable & Pre/Post Scalers=1 Load CCPR1H value in Write register Move CCPR1H value into TMR2 to cause Reset of RB3 pin Assembly Code To Start PWM Once Stopped: PWMrestart bcf movf movwf return STATUS,RP0 T2CONSAV,W T2CON 2003 Microchip Technology Inc. ; Select Bank 0 ; Move T2CONSAV Value to ‘w’ register ; Restore T2CON register value DS80072D-page 3 PIC16C712/716 Code Example 2B: ;*********************************************************************** ; ; Call these routines to turn the CCP Mode off or on and ensure RB3 is a known Input or Output value when CCP Mode is off. ; ; ; ; ; ; CCPstop - First sets RB3 to an Input or an Output. If RB3 is an Output then it’s state is made either High or Low. The CCP is then Disabled. CCPstart - Enable CCP Mode. IT IS THE RESPONSIBILITY OF THE USER TO DETERMINE THE CORRECT VALUE FOR CCP1CON. Assembly Code To Stop CCP Mode Once Started: CCP1CONSAV equ 0X?? CCPstop bsf bcf STATUS,RP0 TRISB,3 bcf bcf STATUS,RP0 PORTB,3 movf movwf movlw movwf return CCP1CON,W CCP1CONSAV 0x30 CCP1CON ; USER IS RESPONSIBLE FOR SUPPLYING RAM MEMORY SPACE ; TO SAVE CCP2CON VALUE. ; ; ; ; ; ; ; ; ; ; ; Select Bank 1 RB3 as an Output - set bit TRISB, 3 when RB3 as an Input is desired. Select Bank 0 RB3 as a Low Level Output - set bit PORTB,3 for RB3 to be a High Level Output. Move CCP1CON to ‘W’ register Save CCP1CON register value Load CCP1CON value in Working register Turn Off CCP1CON all Modes Assembly Code To Start CCP Mode Once Stopped: CCPstart bcf movf movwf return DS80072D-page 4 STATUS,RP0 CCP1CONSAV,W CCP1CON ; Select Bank 0 ; Move CCP1CONSAV value to ‘W’ register ; Restore CCP1CON to desired Mode of operation. 2003 Microchip Technology Inc. PIC16C712/716 2. Module: Timer1 When Timer1 is configured to operate as an asynchronous counter, care must be taken that there is no incoming pulse while the module is being turned off. If an incoming pulse arrives while Timer1 is being turned off (i.e., TMR1ON transitions from 1 to 0), the value of registers TMR1L and TMR1H will be unpredictable. Work around This solution involves changing Timer1 from Asynchronous to Synchronous mode before turning off Timer1. No additional resources are required for this solution. Timer1 synchronization will start, effectively stopping Timer1, one Q period after the Synchronous mode is enabled, or one Q period later than would have been realized by simply clearing the TMR1ON bit. One additional count, in excess of the counts accrued during this extra Q period, may be accumulated before the TMR1ON bit is eventually cleared in the next instruction. The occurrence of this additional count is dependent on the phase relationship between OSC1, or the internal system clock, and T1CKI. Code Example: ************************************************************************************** ; Call this routine to stop Timer1 asynchronous counting ; ; Timer1 is stopped after the timer is changed to synchronous mode ; The captured timer value resides in TMR1H and TMR1L at the completion of this ; routine. TMR1Capture ; entry point bcf T1CON,NOT_T1SYNC ; set for synchronous mode bcf T1CON,TMR1ON ; stop timer bsf T1CON,NOT_T1SYNC ; restore asynchronous mode return 2003 Microchip Technology Inc. ; return to calling routine DS80072D-page 5 PIC16C712/716 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS41106A), the following clarifications and corrections should be noted. 1. The following register and bit names need the following corrections: Page 2. Where Occurrence Data Sheet Name Correct Name 10 Figure 2-3, Address 0Fh 1 TRM1H TMR1H 10 Figure 2-3, Address 11h 1 TRM2 TMR2 41 Table 7-2, Address 07h, bit 0 1 TT1CK DT1CK 44 Table 7-5, Control Bits column 4 TR1SCCP TRISCCP Figure 3-4, page 24, of the Device Data Sheet should show the following block diagram for RB1/T1OSO/T1CK1: FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN RBPU(1) T1OSCEN T1CS TMR1CS 1 Data Bus RD DATACCP 0 DATACCP<0> D WR DATACCP CK VDD Q Weak P Pull-up Q TRISCCP<0> D WR TRISCCP CK 1 Q WR PORTB CK RB1/T1OSO/T1CKI 0 Q PORTB<1> D VDD 1 Q VSS 0 Q TRISB<1> D WR TRISB CK Q Q T1OSCEN TMR1CS 1 TTL Buffer RD PORTB 0 T1CLKIN ST Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). DS80072D-page 6 2003 Microchip Technology Inc. PIC16C712/716 3. Figure 12-1, page 76, of the Device Data Sheet should show the following valid region of operation: FIGURE 12-5: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 20 10 40 30 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 4. Parameter No. D001, page 77, of the Device Data Sheet should show the following values: 12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No. D001 D001A Sym VDD Characteristic Supply Voltage Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C for commercial -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Unit s 4.0 4.5 — — — 5.5 5.5 5.5 V V V VBOR* 2003 Microchip Technology Inc. Conditions XT, RC and LP osc mode HS osc mode BOR enabled(7) DS80072D-page 7 PIC16C712/716 5. Module: Packaging The package information contained in the data sheet is incorrect. Please refer to the following tables for correct package data. 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing § .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS80072D-page 8 MAX 4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15 2003 Microchip Technology Inc. PIC16C712/716 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15 MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 2003 Microchip Technology Inc. DS80072D-page 9 PIC16C712/716 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § Window Width Window Length * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010 DS80072D-page 10 A A2 A1 E E1 D L c B1 B eB W1 W2 MIN .170 .155 .015 .300 .285 .880 .125 .008 .050 .016 .345 .130 .190 INCHES* NOM 18 .100 .183 .160 .023 .313 .290 .900 .138 .010 .055 .019 .385 .140 .200 MAX .195 .165 .030 .325 .295 .920 .150 .012 .060 .021 .425 .150 .210 MILLIMETERS NOM 18 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 22.35 22.86 3.18 3.49 0.20 0.25 1.27 1.40 0.41 0.47 8.76 9.78 3.30 3.56 4.83 5.08 MIN MAX 4.95 4.19 0.76 8.26 7.49 23.37 3.81 0.30 1.52 0.53 10.80 3.81 5.33 2003 Microchip Technology Inc. PIC16C712/716 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MIN MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 2003 Microchip Technology Inc. DS80072D-page 11 PIC16C712/716 APPENDIX A: REVISION HISTORY Rev. A Document (6/2000) First revision of this document. Rev. B Document (4/2001) Added issue 1 (CCP), page 1, and issue 2 (Timer1), page 5. Rev. C Document (1/2002) Under Clarifications/Corrections to the Data Sheet, Item 5 (SSOP), on page 8 was added. Rev. D Document (3/2003) Under Clarifications/Corrections to the Data Sheet, Item 5, Packaging: correct package data was added. DS80072D-page 12 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. 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Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. 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