K6F4006U2E

K6F4006U2E
K6F4008U2E Family
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
October 25, 2000
Preliminary
1.0
Finalize
March 12, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
•
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•
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The K6F4008U2E families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and Chip Scale Package for user
flexibility of system design. The families also supports low data
retention voltage for battery back-up operation with low data
retention current.
Process Technology: Full CMOS
Organization: 512K x8 bit
Power Supply Voltage: 2.7~3.3V
Low Data Retention Voltage: 1.5V(Min)
Three State Outputs
Package Type: 48(36)-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1, Max)
PKG Type
K6F4008U2E-F
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
1.0µA2)
2mA
48(36)-TBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
2. Typical value are at VCC=3.0V, TA=25°C and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
A
A0
A1
CS2
A3
A6
A8
B
I/O5
A2
WE
A4
A7
I/O1
C
I/O6
DNU
A5
D
VSS
Clk gen.
I/O2
Row
Address
Row
select
Precharge circuit.
Memory
Cell
Array
VCC
48(36)-TBGA
E
VCC
F
I/O7
G
I/O8
H
A9
VSS
Data
cont
I/O 1
Name
A18
A17
OE
CS1
A16
A15
I/O4
A10
A11
A12
A13
A14
Function
CS1, CS 2 Chip Select Inputs
I/O3
Name
I/O 8
I/O Circuit
Column select
Data
cont
Column Address
CS1
Function
CS2
WE
I/O1~I/O8 Data Inputs/Outputs
Control
logic
OE
OE
Output Enable Input
WE
A0~A18
Vcc
Power
Write Enable Input
Vss
Ground
Address Inputs
DNU
Do Not Use
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6F4008U2E-EF55
K6F4008U2E-EF70
48(36)-TBGA, 55ns, 3.0V
48(36)-TBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
CS 1
CS2
OE
WE
I/O
Mode
Power
H
X1)
X1)
X1)
High-Z
Deselected
Standby
1)
1)
Deselected
Standby
X
L
X
X
High-Z
L
H
H
H
High-Z
Output Disabled
Active
1)
L
H
L
H
Dout
Read
Active
L
H
X1)
L
Din
Write
Active
1. X means don′t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
VIN, VOUT
-0.5 to VCC+0.3V(Max. 3.6V)
V
Voltage on Vcc supply relative to Vss
VCC
-0.3 to 3.6
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
2.7
3.0
3.3
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.2
-
Vcc+0.3
Input low voltage
VIL
-
0.6
-0.3
3)
V
V
2)
V
Note:
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+2.0V in case of pulse width ≤20ns.
3. Undershoot: -2.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Symbol
Test Condition
Min
Max
Unit
Input capacitance
Item
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ1)
Max
Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS1=VIH, CS 2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V,
CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
2
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty,
CS1=VIL , CS2=VIH, VIN=VIL or VIH
70ns
-
-
15
55ns
-
-
20
IOL = 2.1mA
-
-
0.4
V
2.4
-
-
V
-
1
12
µA
Average operating current
Output low voltage
VOL
Output high voltage
VOH
IOH = -1.0mA
ISB1
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
0V≤CS2≤0.2V(CS2 controlled), Other inputs=0~Vcc
Standby Current (CMOS)
mA
1. Typical value are measured at V CC=3.0V, TA=25°C, and not 100% tested.
-4-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
VTM3)
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
R12)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C L= 100pF+1TTL
CL=30pF+1TTL
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070Ω, R2 =3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Write
Units
70ns
Min
Max
Min
Max
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
Read Cycle Time
Read
55ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
Min
Typ
Max
Unit
1.5
-
3.3
V
3
µA
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS1≥Vcc-0.2V1)
Data retention current
IDR
Vcc=1.5V, CS1≥Vcc-0.2V , VIN≥0V
Data retention set-up time
tSDR
Recovery time
tRDR
1)
See data retention waveform
-
0.5
0
-
-
tRC
-
-
2)
ns
1. CS1 ≥Vcc-0.2V, CS 2≥Vcc-0.2V(CS1 controlled) or 0≤CS2≤0.2V(CS2 controlled).
2. Typical value are measured at TA=25°C and not 100% tested.
-5-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH )
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
-6-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
-7-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS 1
tAW
CS 2
tCW(2)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, t WP
is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS 2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
2.7V
2.2V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS 2≤0.2V
0.4V
GND
-8-
Revision 1.0
March 2001
K6F4008U2E Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeters
48(36) TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
Bottom View
A1 INDEX MARK
B
B
B1
0.65
0.65
6
5
4
3
2
1
A
B
#A1
C
C
C
C1
D
C1/2
E
F
G
H
B/2
Detail A
Side View
A
Y
0.55/Typ.
E1
E
0.35/Typ.
E2
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
1. Bump counts: 48(8 row x 6 column)
B1
-
3.75
-
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
0.80
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.08
Notes.
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
-9-
Revision 1.0
March 2001
This datasheet has been downloaded from:
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