AOZ8804A Ultra-Low Capacitance TVS Diode General Description

AOZ8804A Ultra-Low Capacitance TVS Diode  General Description

AOZ8804A

Ultra-Low Capacitance TVS Diode

General Description

The AOZ8804A is a transient voltage suppressor array designed to protect high speed data lines such as HDMI,

USB 3.0, MDDI, SATA, and Gigabit Ethernet from damaging ESD events.

This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground.

The AOZ8804A provides a typical line to line capacitance of 0.3pF and low insertion loss up to 6GHz providing greater signal integrity making it ideally suited for HDMI

1.3 or USB 3.0 applications, such as Digital TVs,

DVD players, Computing, set-top boxes and MDDI applications in mobile computing devices.

The AOZ8804A comes in a RoHS compliant and

Halogen Free 2.5mm x 1.0mm x 0.55mm DFN-10 package and is rated -40°C to +85°C junction temperature range.

Features

ESD protection for high-speed data lines:

– IEC 61000-4-2, level 4 (ESD) immunity test

– Air discharge: ±15kV; contact discharge: ±15kV

– IEC61000-4-4 (EFT) 40A (5/50nS)

– IEC61000-4-5 (Lightning) 2.5A (8/20µS)

– Human Body Model (HBM) ±24kV

Array of surge rated diodes with internal TVS diode

Small package saves board space

Protects four I/O lines

Low capacitance between I/O lines: 0.3pF

Low clamping voltage

Low operating voltage: 5.0V

Applications

HDMI, USB 3.0, MDDI, SATA ports

Monitors and flat panel displays

Set-top box

Video graphics cards

Digital Video Interface (DVI)

Notebook computers

Typical Applications

AOZ8802A

AOZ8804A AOZ8804A

USB 3.0

Transceiver

D+

D-

SSRX+

SSRX-

SSTX+

SSTX-

D+

D-

USB 3.0

Connector

SSRX+

SSRX-

SSTX+

SSTX-

TX2+

TX2-

HDMI

TX1+

TX1-

Transmitter

TX0+

TX0-

CLK+

CLK-

RX2+

RX2-

RX1+

RX1-

HDMI

Receiver

RX0+

RX0-

CLK+

CLK-

Connector Connector

AOZ8804A

Figure 1. USB 3.0 Ports

AOZ8804A

Figure 2. HDMI Ports

AOZ8804A www.aosmd.com

Rev. 2.1 April 2015 Page 1 of 11

Ordering Information

Part Number

AOZ8804ADI

Ambient Temperature Range Package

-40°C to +85°C DFN-10

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/media/AOSGreenPolicy.pdf

for additional information.

Pin Configuration

CH1

1

10

NC

CH2

2

9

NC

VN

3

8

VN

AOZ8804A

Environmental

Green Product

CH3 4

7

NC

CH4

5

6

NC

DFN-10

(Top View)

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage the device.

Parameter

Storage Temperature (T

S

)

ESD Rating per IEC61000-4-2, contact

(1)

ESD Rating per IEC61000-4-2, air

(1)

ESD Rating per Human Body Model

(2)

Notes:

1. IEC 61000-4-2 discharge with C

Discharge

= 150pF, R

Discharge

= 330

.

2. Human Body Discharge per MIL-STD-883, Method 3015 C

Discharge

= 100pF, R

Discharge

= 1.5k

.

Maximum Operating Ratings

Parameter

Junction Temperature (T

J

)

Rating

-65°C to +150°C

±15kV

±15kV

±24kV

Rating

-40°C to +125°C

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AOZ8804A

Electrical Characteristics

T

A

= 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.

Symbol

V

RWM

V

V

I

BR

V

R

F

CL

Parameter

Reverse Working Voltage

Reverse Breakdown Voltage

Reverse Leakage Current

Diode Forward Voltage

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Any I/O Pin to Ground

Channel Input Capacitance

I

I

I

Conditions

Between I/O and VN

(3)

I

T

= 1mA, between I/O and VN

(4)

V

RWM

= 5V, between I/O and VN

I

F

= 15mA

I

PP

= 1A, tp = 100ns, any I/O pin to Ground

(5)

PP

PP

PP

= 5A, tp = 100ns, any I/O pin to Ground

= 12A, tp = 100ns, any I/O pin to Ground

= 1A, tp = 8/20µs

(5)

(5)

Min.

6.0

0.70

Typ.

0.85

Max.

C j

V

R

= 0V, f = 1MHz, between I/O pins

V

R

= 0V, f = 1MHz, any I/O pin to Ground

0.30

0.60

Notes:

3. The working peak reverse voltage, V

RWM

, should be equal to or greater than the DC or continuous peak operating voltage level.

4. V

BR

is measured at the pulse test current I

T

.

5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.

5.0

1

1

12.0

-3.0

14.0

-5.0

16.5

-7.0

12.0

0.35

0.75

Units

V pF pF

V

V

µA

V

V

V

V

V

V

V

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Typical Performance Characteristics

7

6

5

4

3

2

1

0

8

Forward Voltage vs. Forward Peak Pulse Current

(t period

= 100ns, t r

= 1ns)

Forward Current, I

PP

(A)

10

8

6

4

2

18

16

14

12

Clamping Voltage vs. Peak Pulse Current

(t period

= 100ns, t r

= 1ns)

Peak Puse Current, I

PP

(A)

Capacitance vs. Frequency (IO to GND)

1E-12

8E-13

6E-13

4E-13

2E-13

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000

Frequency (MHz)

AOZ8804A

0.00E+00

-5.00E+00

-1.00E+01

-1.50E+01

-2.00E+01

-2.50E+01

-3.00E+01

1

I/O – Gnd Insertion Loss (S21) vs. Frequency

10 100

Frequency (MHz)

1000 10000

0

-20

-40

-60

-80

-100

-120

1

Analog Crosstalk (I/O–I/O) vs. Frequency

10 100

Frequency (MHz)

1000 10000

USB3.0 Eye Diagram with AOZ8804A (5Gbps)

0.6

0.5

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.2

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Unit Intervals

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AOZ8804A

TDR for HDMI 1.3

The AOZ8804A TDR test results indicates the minimal effect the low capacitance has on the HDMI 1.3 TDR measurements. Figure 3 and Figure 4 below are the graphs from the TDR measurements. The two graphs show the before and after results of the TDR differential data line of the HDMI when the AOZ8804A was populated onto the PCB. The use of "Skinny Traces" can further limit the TDR to within 100

 ± 5. Below are the

TDR measurements with the use of skinny traces to compensate the added capacitor from the AOZ8804.

Figure 3 shows the increase in impedance from the skinny traces between M1 and M2 cursors. With the increase in impedance the AOZ8804A added capacitor will now reduce the TDR within the 100

 ± 5.

125

120

115

110

105

100

95

90

85

80

75

-0.2500 ns

(Step 2.56 ps)

0.2000 ns/ 1.7500 ns

Figure 3. Compensated Stripe-Line

Figure 5 shows the graphical representation of the scope photo of the TDR and the PCB board. The cursor M1 represent the edge of the connector in which the

Compensated Stripe-Line

M1 M1

125

120

115

110

105

100

95

90

85

80

75

-0.2500 ns

(Step 2.56 ps)

0.2000 ns/ 1.7500 ns

Figure 4. Compensated Stripe-Line with

AOZ8804A Device on the Board

equipment was calibrated to. The cursor M2 represent the leveling off of the100

 when the signal passes through the AOZ8804A.

Number of Layers

Copper Trace Thickness

Dielectric Constant,

 r

Overall Board Thickness

Dielectric Thickness Between

Top and Ground Layer

4

1.4 mils

4.6

62 mils

10 mils

AOZ8804A

Figure 5. AOS HDMI Compensated Evaluation Board

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AOZ8804A

High Speed PCB Layout Guidelines

Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines.

The location of the protection devices on the PCB is the simplest and most important design rule to follow. The

AOZ8804A devices should be located as close as possible to the noise source. The placement of the

AOZ8804A devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8804A devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8804A device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced.

Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible.

The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design.

The AOZ8804A ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges.

When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8804A is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8804A is designed to simply drop onto the IO lines of a High

Definition Multimedia Interface (HDMI) or USB 3.0 design without having to divert the signal lines that may add more parasitic inductance. Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface.

Clock

Data0

Ground

Clock

Data0

Ground

SSRX+

SSRX–

Ground

SSRX+

SSRX–

Ground

Data1 Data1 SSTX+ SSTX+

Data2 Data2 SSTX– SSTX–

Figure 6. Flow Through Layout for HDMI Figure 7. Flow Through Layout for USB 3.0

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AOZ8804A

High Speed PCB Layout Guidelines

(Continued)

Based on the AOZ8804A DFN-10 package design a very straight forward layout can be achieved. To give the TDR an extra level of margin the traces may be compensated to have a nominal impedance of 90

Ω for USB or 100

Ω for HDMI throughout the differential pair. To make the design perfect the added capacitance of the device will have to be compensated by the use of “Skinny Traces”.

The skinny traces are a narrow stripe line acting to lower the parasitic capacitance on the differential stripe line.

The differential impedance of the transmission line becomes well centered to 90

Ω or to 100

. A layout EM field simulator is recommended before fabrication to insure a perfect stripe line. With careful layout and placement of the device, the AOZ8804A can protect the

USB 3.0 and HDMI data line effectively and safely and meet the ESD immunity requirements of the

IEC61000-4-2, level 4, ±15kV air discharge, ±8kV contact discharge.

Figure 8. USB 3.0 PCB Layout with Compensated Traces

Number of Layers

Copper Trace Thickness

Dielectric Constant,

 r

Overall Board Thickness

Dielectric Thickness Between

Top and Ground Layer

4

1.4 mils

4.6

62 mils

10 mils

.

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Page 7 of 11

AOZ8804A

Figure 9. HDMI PCB Layout with Compensated Traces

Number of Layers

Copper Trace Thickness

Dielectric Constant,

 r

Overall Board Thickness

Dielectric Thickness Between

Top and Ground Layer

4

1.4 mils

4.6

62 mils

10 mils

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Page 8 of 11

Package Dimensions, DFN-10 2.5mm x 1.0mm x 0.5mm

D b b1

AOZ8804A

e

E

Pin #1 Dot by Marking

TOP VIEW

L

5 e

1

Pin #3 Identification R 0.130

BOTTOM VIEW

c

A

A1

SIDE VIEW

RECOMMENDED LAND PATTERN

0.30

0.50

0.10

0.15

0.36

1.20 0.24

0.48

0.72

Dimensions in millimeters

Symbols

A

A1 b b1 c

D

E e

L

Min.

0.50

0.00

0.15

Nom.

0.55

0.20

Max.

0.60

0.05

0.25

2.45

0.95

0.40

0.152 Ref.

2.50

1.00

2.55

1.05

0.33

0.50 BSC

0.38

0.43

Dimensions in inches

Symbols

A

A1 b b1 c

D

E e

L

Min.

0.020

0.000

0.006

Nom.

0.022

0.008

Max.

0.024

0.002

0.010

0.096

0.037

0.016

0.006 Ref.

0.098

0.039

0.100

0.041

0.013

0.020 BSC

0.015

0.017

0.20

0.40

Note:

1. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.

Rev. 2.1 April 2015

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Page 9 of 11

Tape and Reel Dimensions, DFN-10 2.5mm x 1.0mm x 0.5mm

Carrier Tape

P1

P2

D0 D1

K0

E1

E2

E

B0

T

Ref 5

°

P0

A0

A–A

Feeding Direction

UNIT: mm

Package

DFN 2.5x1.0

A0

1.12

±0.05

B0

2.62

±0.05

K0

0.70

±0.05

D0

ø1.55

±0.05

D1

ø0.55

±0.05

E

8.00

+0.3/-0.1

E1

1.75

±0.1

E2

3.50

±0.05

P0

4.00

±0.10

P1

4.0

±0.10

P2

2.0

±0.05

T

0.25

±0.05

AOZ8804A

Reel

W1

S K

M

N

G

R

H

W

UNIT: mm

Tape Size

8mm

Reel Size

ø178

M

ø178.0

±1.0

N

ø60.0

±0.5

W

11.80

±0.5

W1

9.0

±0.5

H

ø13.0

+0.5 / –0.2

S

2.40

±0.10

K

10.25

±0.2

E

ø9.8

R

Leader / Trailer & Orientation

Rev. 2.1 April 2015

Trailer Tape

300mm Min.

Components Tape

Orientation in Pocket

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Leader Tape

500mm Min.

Page 10 of 11

Part Marking

Part Number Code

AOZ8804ADI

(2.5 x 1.0 DFN)

DC12

Assembly Lot Code

Week and Year Code

AOZ8804A

LEGAL DISCLAIMER

Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or completeness of the information provided herein and takes no liabilities for the consequences of use of such information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes to such information at any time without further notice. This document does not constitute the grant of any intellectual property rights or representation of non-infringement of any third party’s intellectual property rights.

LIFE SUPPORT POLICY

ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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