Flash Memory Erase Mode Comparison

Flash Memory Erase Mode Comparison
Flash Memory Erase Mode Comparison
Simultaneous Read/Write vs Erase Suspend
Application Note
Introduction
Simultaneous Read/Write devices are designed to allow reading from a Flash device at the same
time an erase (or program) operation is being executed. The Erase Suspend/Resume feature is
intended to be used occasionally to interrupt an erase operation to read data from the Flash device. With this in mind the question arises: How often can an erase be suspended before it affects
system performance and a Simultaneous Read/Write device needs to be used instead?
Timing and Performance Comparison
Most systems that use either Simultaneous Read/Write or Erase Suspend do so because of interrupt-driven events that read from the flash during an erase. When using a simultaneous read/
write device, an erase operation will be not be affected by reading the device (assuming the data
is in a separate bank), because both the read and erase happen in parallel. When Erase Suspend
is used to handle an interrupt, the erase operation is paused while data is read from the device.
This serial approach can drastically increase the total time of the erase operation (see Figure 1).
Simultaneous Operation
Erase
Read
Eras e Sus pend / R e a d
Erase
Resume
Resume
Resume
Resume
Resume
Resu
Read
Figure 1.
Simultaneous Operation vs. Erase Suspend
Comparison
During a sector erase, as the number of Erase Suspend operations increases, the erase operation
becomes less efficient. During an erase operation the flash is issuing a number of erase pulses
to the memory array. When an erase is suspended, any erase pulse that wasn’t completed must
be restarted.
If a flash device is continually issued suspend/resume commands in rapid succession, the device
will frequently be restarting the same erase pulse. This will greatly degrade the performance of
the erase function, and possibly extend the total erase time beyond the stated maximum values,
but will not affect device reliability or future performance. The solution to this problem is to either,
set a minimum time between the beginning of an erase (or resume) and the suspend command,
or use a simultaneous read/write device.
Publication Number erase_mode_comp_AN
Revision A
Amendment 0
Issue Date August 4, 2005
Regardless of the type of flash device used, a complete erase pulse is needed to make any
progress during an erase operation. But how long is an erase pulse? The length of an erase pulse
changes depending on the process technology and device family. The general rule is that highspeed parts have shorter erase pulses than data storage parts, but even the longest erase pulses
are under 10 ms.
Some would assume that a system issuing regular suspends every 4 ms would not affect the erase
performance of a S29WS256N (a 256M-bit, 1.8 V burst device with MirrorBitTM technology), which
uses 2 ms erase pulses. This is not true because the system is not synchronized with the internal
pulse generator of the flash device. Therefore, approximately half of the erase pulses would not
have completed, doubling the time required to erase a sector (see Figure 2).
Increase in Erase Time vs. Frequency of Suspends
For the S29WS256N
10
Times Longer than Normal
9
8
7
6
5
4
3
2
1
2.25 2.50
2.75
3.00 3.25
3.50
3.75 4.00
4.25 4.50
4.75
5.00 5.25
Time Between Suspends (ms)
Figure 2.
Effect of Erase Suspend on Total Erase Time
A simple equation can be used to calculate the performance impact of using Erase Suspend vs.
Simultaneous Read/Write:
1
Times longer than normal =
__________________
Length of Erase Pulse
1 -
2
Time Between Suspends
Flash Memory Erase Mode Comparison
erase_mode_comp_AN_A0 August 4, 2005
Erase Suspension Capacity
On all floating gate devices built using a 170 nm or large process technology (except the
Am29BDD and S29CD families), a sector erase may fail if suspended more than 5,680 times. Reissuing the sector erase command will erase the sector correctly (assuming the number of
suspends is limited to under 5,680). MirrorBit devices don't have a preset limit, but still do require that a complete erase pulse (which are between 0.5 ms and 4 ms long) is issued before any
progress can be made on an erase operation.
Conclusions
For systems that need to suspend program/erase operations sporadically, but infrequently, like
most interrupt-driven controllers or computer systems, simultaneous read/write is not needed.
Systems that continuously need to read from the device (such as real-time systems), or those
that must repeatedly suspend program/erase operations, should use a simultaneous read/write
device.
August 4, 2005 erase_mode_comp_AN_A0
Flash Memory Erase Mode Comparison
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Revision History
Revision A0 (August 4, 2004)
Initial release.
Colophon
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Flash Memory Erase Mode Comparison
erase_mode_comp_AN_A0 August 4, 2005
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