datasheet for VL41B5663A-K9S

datasheet for VL41B5663A-K9S
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
General Information
2GB 256MX72 DDR3 SDRAM ECC SO-UDIMM 204 PIN
Description
The VL41B5663A is a 256Mx72 DDR3 SDRAM high density SO-UDIMM. This memory module consists of eighteen
CMOS 128Mx8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin MLF
package. This module is a 204-pin small-outline dual in-line memory module and is intended for mounting into a
connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM.
Features
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Pin Description
204-pin, small-outline unbuffered dual in-line memory module (SO-UDIMM)
Support ECC error detection and correction
Fast data transfer rates: PC3-10600, PC3-8500, PC3-6400
VDD = VDDQ = 1.5V +/-0.075V
JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible)
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency: 9 (DDR3-1333), 7 (DDR3-1066),
6 (DDR3-800)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD)
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 30.00mm (1.181”), double sided components
Operating temperature (TOPER): -40oC to +85oC (module screening)
Pin Name
Function
A0~A13
Address Inputs
A10/AP
Address Input/ Autoprecharge
A12/BC#
Address Input/ Burst Chop
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
ODT0, ODT1
On-die Termination Control
CK0,CK0#,
CK1,CK1#
Clock Input
CKE0, CKE1
Clock Enables
CS0#, CS1#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
VDD
Voltage Supply 1.5V +/- 0.075V
VSS
Ground
SA0~SA1
SPD Address
SDA
SPD Data Input/Output
Order Information:
SCL
SPD Clock Input
DM0~DM8
Data Masks
VL41B5663A-K9 S X- S1
CB0~CB7
Data Check Bits I/O
VREFCA
Reference Voltage for CA
VREFDQ
Reference Voltage for DQ
VDDSPD
SPD Voltage Supply 3.0V to 3.6V
S1: Temperature screening
DRAM DIE (option)
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
K9: PC3-10600 @ CL9
F8: PC3-8500 @ CL7
E7: PC3-6400 @ CL6
VTT
Termination Voltage
RESET#
Register and SDRAM Control
NC
No Connect
VL: Lead-free/RoHS
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1
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Pin Configuration
204-PIN DDR3 SO-UDIMM FRONT
204-PIN DDR3 SO-UDIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREFDQ
53
VSS
105
A1
157
DM5
2
VSS
54
DQ28
106
A2
158
VSS
3
VSS
55
DQ24
107
A0
159
DQ42
4
DQ4
56
DQ29
108
BA1
160
DQ46
5
DQ0
57
DQ25
109
VDD
161
DQ43
6
DQ5
58
VSS
110
VDD
162
DQ47
111
CK0
163
DQS3#
112
CK1
164
7
DQ1
59
DM3
VSS
8
VSS
60
VSS
9
VSS
61
VSS
113
CK0#
165
DQ48
10
DQS0#
62
DQS3
114
CK1#
166
DQ52
11
DM0
63
DQ26
115
VDD
167
DQ49
12
DQS0
64
VSS
116
VDD
168
DQ53
13
DQ2
65
DQ27
117
A10/AP
169
VSS
14
VSS
66
DQ30
118
NC/CS3#
170
VSS
15
DQ3
67
VSS
119
BA0
171
DQS6#
16
DQ6
68
DQ31
120
NC/CS2#
172
DM6
17
VSS
69
CB0
121
WE#
173
DQS6
18
DQ7
70
VSS
122
RAS#
174
DQ54
19
DQ8
71
CB1
123
VDD
175
VSS
20
VSS
72
CB4
124
VDD
176
DQ55
21
DQ9
73
VSS
125
CAS#
177
DQ50
22
DQ12
74
CB5
126
ODT0
178
VSS
23
VSS
75
DQS8#
127
CS0#
179
DQ51
24
DQ13
76
DM8
128
ODT1
180
DQ60
25
DQS1#
77
DQS8
129
CS1#
181
VSS
26
VSS
78
VSS
130
A13
182
DQ61
27
DQS1
79
VSS
131
VDD
183
DQ56
28
DM1
80
CB6
132
VDD
184
VSS
29
VSS
81
CB2
133
DQ32
185
DQ57
30
RESET#
82
CB7
134
DQ36
186
DQS7#
31
DQ10
83
CB3
135
DQ33
187
VSS
32
VSS
84
VREFCA
136
DQ37
188
DQS7
33
DQ11
85
VDD
137
VSS
189
DM7
34
DQ14
86
VDD
138
VSS
190
VSS
35
VSS
87
CKE0
139
DQS4#
191
DQ58
36
DQ15
88
A15*
140
DM4
192
DQ62
37
DQ16
89
CKE1
141
DQS4
193
DQ59
38
VSS
90
A14*
142
DQ38
194
DQ63
39
DQ17
91
BA2
143
VSS
195
VSS
40
DQ20
92
A9
144
DQ39
196
VSS
41
VSS
93
VDD
145
DQ34
197
SA0
42
DQ21
94
VDD
146
VSS
198
EVENT#*
43
DQS2#
95
A12/BC#
147
DQ35
199
VDDSPD
44
DM2
96
A11
148
DQ44
200
SDA
45
DQS2
97
A8
149
VSS
201
SA1
46
VSS
98
A7
150
DQ45
202
SCL
47
VSS
99
A5
151
DQ40
203
VTT
48
DQ22
100
A6
152
VSS
204
VTT
49
DQ18
101
VDD
153
DQ41
50
DQ23
102
VDD
154
DQS5#
51
DQ19
103
A3
155
VSS
52
VSS
104
A4
156
DQS5
Notes:
* These pins are not used in this module.
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2
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Function Block Diagram
CS1#
CS0#
DQS4
DQS0
DQS0#
DM0
DQS4#
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D0
DM
CS# DQS DQS#
D9
Vss
CS# DQS DQS#
D13
ZQ
Vss
DQS5
DQS5#
DM5
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
CS# DQS DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D1
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
D5
DM
CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D14
ZQ
ZQ
ZQ
ZQ
Vss
Vss
Vss
Vss
DQS6
DQS6#
DM6
DQS2
DQS2#
DM2
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
CS# DQS DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D2
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS# DQS DQS#
D6
DM
CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D15
ZQ
ZQ
Vss
Vss
Vss
DQS3
DQS3#
Vss
DQS7
DQS7#
DM7
DM3
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D4
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Vss
DQS1
DQS1#
DM1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS# DQS DQS#
ZQ
ZQ
ZQ
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
CS# DQS DQS#
CS# DQS DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D3
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
ZQ
CS# DQS DQS#
D7
DM
CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D16
ZQ
Vss
Vss
ZQ
Vss
Vss
DQS8
DQS8#
DM8
Command, address, control, and clock line terminations
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS# DQS DQS#
CS# DQS DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D8
A0-A13, BA0-BA2
RAS#, CAS#, WE#,
CS0#, CS1#, CKE0,
CKE1, ODT 0, ODT 1
DDR3
SDRAM
D17
36 ohm +/-5%
VT T
36 ohm +/-5%
CK0, CK1
CK0#, CK1#
ZQ
DDR3
SDRAM
VDD
0.1uF
ZQ
Vss
Vss
VDDSPD
A0-A13: D0-D17
BA0-BA2: D0-D17
RAS#: D0-D17
CAS#: D0-D17
WE#: D0-D17
CKE0: D0-D8
CKE1: D9-D17
ODT0: D0-D8
ODT1: D9-D17
RESET#: D0-D17
A0-A13
BA0-BA2
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
CK0
D0-D8
CK0#
Serial PD
SCL
WP
Vss
CK1
D9-D17
CK1#
A0
A1
A2
SDA
Serial PD
VDD
D0-D17
VT T
D0-D17
VREFCA
D0-D17
VREFDQ
D0-D17
VSS
D0-D17
SA0 SA1 Vss
Notes:
1. Unless otherwise noted, resistor value are 15 ohm +/-5%
2. ZQ resistors are are 240 ohm +/-1%
3.3pF
3.3pF
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3
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-0.4
1.975
V
Voltage on VDDQ pin relative to VSS
-0.4
1.975
V
Voltage on any pin relative to VSS
-0.4
1.975
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, RAS#,
CAS#, WE#, BA
-36
36
uA
CS#, CKE, ODT,
CK, CK#
-18
18
uA
DM
-4
4
uA
-10
10
uA
-18
18
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
VDD
VDDQ
Parameter
Min
Typical
Max
Unit
Notes
Supply Voltage
1.425
1.5
1.575
V
1,2
I/O Supply Voltage
1.425
1.5
1.575
V
1,2
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VREFDQ (DC)
I/O reference voltage DQ bus
VREFCA (DC)
Input reference voltage CMD/ADD bus
VTT
Termination Reference Voltage
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
-0.483 x VDDQ
0.5 x VDDQ
+0.517 x VDDQ
V
5
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
TOPER
Parameter
Operating temperature
Rating
Units
-40 to +85
o
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At -40 to +85 C, operation temperature range, all DRAM specifications will be supported.
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4
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(DC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.100
VDD
V
VILCA(DC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
VSS
VREF - 0.100
V
VIHDQ(DC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.100
VDD
V
VILDQ(DC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
VSS
VREF - 0.100
V
Min
Max
Unit
DQ and DM
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Command and Address
VIHCA(AC)
Input High (Logic 1) Voltage DDR3-800/1066/1333
VREF + 0.175
-
V
VILCA(AC)
Input Low (Logic 0) Voltage DDR3-800/1066/1333
-
VREF - 0.175
V
DQ and DM
VIHDQ(AC)
Input High (Logic 1) Voltage DDR3-800/1066
VREF + 0.175
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage DDR3-800/1066
-
VREF - 0.175
V
VIHDQ(AC)
Input High (Logic 1) Voltage DDR3-1333
VREF + 0.150
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage DDR3-1333
-
VREF - 0.150
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
Symbol
DDR3-1333
DDR3-1066
DDR3-800
Min
Max
Min
Max
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
17.5
27.4
17.5
31
17.5
31
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)
CIN2
10.75
15.7
10.75
17.5
10.75
17.5
pF
Input capacitance (CK0, CK0#, CK1, CK1#)
CIN3
11.2
16.6
11.2
18.4
11.2
18.4
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
CIO
7
9
7
9.4
7
10
pF
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5
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
IDD Specification
Condition
Symbol
DDR3-1333
(-K9)
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
IDD0*
675
630
585
mA
IDD1*
810
765
720
mA
IDD2P-F**
450
450
450
mA
IDD2P-S**
180
180
180
mA
IDD2N**
630
540
540
mA
IDD2Q**
630
540
450
mA
IDD3P**
450
450
450
mA
IDD3N**
900
810
720
mA
IDD4R*
1215
1080
945
mA
IDD4W*
1305
1125
855
mA
IDD5**
2880
2700
2700
mA
IDD6**
180
180
180
mA
IDD7*
2160
1755
1620
mA
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC=
tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
Precharge power-down current;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other
control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS
MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL
= CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP=
tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD);
AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is
HIGH; CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL =
tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD =
tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R.
Note: IDD specification is based on Samsung E-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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6
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
tCK(DLL_OFF)
8
-
8
-
8
-
ns
tCK(avg)
1.5
<1.875
1.875
<2.5
2.5
3.3
ns
ns
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
tCK(abs)
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)ma
x+
tJIT(per)ma
x
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-80
80
-90
90
-100
100
ps
tJIT(per, lck)
-70
70
-80
80
-90
90
ps
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(cc)
160
180
200
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
140
160
180
ps
Cumulative error across 2 cycles
tERR(2per)
-118
118
-132
132
-147
147
ps
Cumulative error across 3 cycles
tERR(3per)
-140
140
-157
157
-175
175
ps
Cumulative error across 4 cycles
tERR(4per)
-155
155
-175
175
-194
194
ps
Cumulative error across 5 cycles
tERR(5per)
-168
168
-188
188
-209
209
ps
Cumulative error across 6 cycles
tERR(6per)
-177
177
-200
200
-222
222
ps
Cumulative error across 7 cycles
tERR(7per)
-186
186
-209
209
-232
232
ps
Cumulative error across 8 cycles
tERR(8per)
-193
193
-217
217
-241
241
ps
Cumulative error across 9 cycles
tERR(9per)
-200
200
-224
224
-249
249
ps
Cumulative error across 10 cycles
tERR(10per)
-205
205
-231
231
-257
257
ps
Cumulative error across 11 cycles
tERR(11per)
-210
210
-237
237
-263
263
ps
Cumulative error across 12 cycles
tERR(12per)
-215
215
-242
242
-269
269
ps
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min
tERR(nper)max =(1+ 0.68ln(n))*tJIT(per)max
tERR(nper)
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
tDQSQ
-
125
-
150
-
200
ps
Data Timing
DQS,DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-500
250
-600
300
-800
400
ps
DQ high-impedance time from CK, CK#
tHZ(DQ)
-
250
-
300
-
400
ps
tDS(base)
30
-
25
-
75
-
ps
tDH(base)
65
-
100
-
150
-
ps
tDIPW
400
-
490
-
600
-
ps
Data setup time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
Data hold time to DQS, DQS# referenced to
Vih(ac)Vil(ac) levels
DQ and DM Input pulse width for each input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
7
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS# READ Preamble
tRPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# differential READ Postamble
tRPST
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS# output high time
tQSH
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# output low time
tQSL
0.4
-
0.38
-
0.38
-
tCK(avg)
DQS, DQS# WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK
tDQSCK
-255
255
-300
300
-400
400
ps
tLZ(DQS)
-500
250
-600
300
-800
400
ps
DQS, DQS# rising edge output access time from rising
CK, CK#
DQS, DQS# low-impedance time (Referenced from
RL-1)
DQS, DQS# high-impedance time (Referenced from
RL+BL/ 2)
tHZ(DQS)
-
250
-
300
-
400
ps
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,DQS# failing edge setup time to CK, CK# rising
edge
tDSS
0.2
-
0.2
-
0.2
-
tCK(avg)
DQS,DQS# failing edge hold time to CK, CK# rising edge
tDSH
0.2
-
0.2
-
0.2
-
tCK(avg)
tDLLK
512
-
512
-
512
-
nCK
tRTP
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
tWTR
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
tWR
15
-
15
-
15
-
ns
tMRD
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
Command and Address Timing
DLL locking time
Internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time
Mode Register Set command cycle time
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
nCK
1
-
1
-
1
-
nCK
tRAS
36
9*tREFI
37.5
9*tREFI
37.5
9*tREFI
ns
tRRD
max
(4tCK,6ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
ACTIVE to ACTIVE command period for 2KB page size
tRRD
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
max
(4tCK,10ns)
-
Four activate window for 1KB page size
tFAW
30
-
37.5
-
40
-
ns
Four activate window for 2KB page size
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
tMPRR
nCK
tFAW
45
-
50
-
50
-
ns
Command and Address setup time to CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIS(base)
65
-
125
-
200
-
ps
Command and Address hold time from CK, CK#
referenced to Vih(ac) / Vil(ac) levels
tIH(base)
140
-
200
-
275
-
ps
tIPW
620
-
780
-
900
-
ps
Control & Address Input pulse width for each input
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
8
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
-
110
-
110
-
Refresh Timing
2Gb REFRESH to REFRESH OR REFRESH to ACTIVE
command interval
tRFC
110
Average periodic refresh interval
(0°C<= TCASE <= 85 °C)
tREFI
7.8
7.8
7.8
us
Average periodic refresh interval
(85°C<= TCASE <= 95 °C)
tREFI
3.9
3.9
3.9
us
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
tCK
Normal operation Short calibration time
tZQCS
64
-
64
-
64
-
tCK
tXPR
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
max
(5tCK, tRFC
+ 10ns)
-
Exit Self Refresh to commands not requiring a locked
DLL
tXS
max(5tCK,
tRFC +10ns)
-
max(5tCK,
tRFC +10ns)
-
max(5tCK,
tRFC +10ns)
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry (SRE)
tCKSRE
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit (SRX)
tCKSRX
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
tXP
max
(3tCK,6ns)
-
max
(3tCK,7.5ns)
-
max
(3tCK,7.5ns)
-
tXPDLL
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
tCKE
max (3tCK,
5.625ns)
-
max (3tCK,
5.625ns)
-
max (3tCK,
7.5ns)
-
tCPDED
1
-
1
-
1
-
nCK
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
Timing of ACT command to Power Down entry
tACTPDEN
1
-
1
-
1
-
nCK
Timing of PRE command to Power Down entry
tPRPDEN
1
-
1
-
1
-
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
tWRPDEN
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
WL + 4
+(tWR/ tCK)
-
nCK
tWRAPDEN
WL+4+WR+
1
-
WL+4+WR+1
-
WL+4+WR+1
-
nCK
tWRPDEN
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
WL + 2
+(tWR/ tCK)
-
nCK
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN
WL+2+WR+
1
-
WL+2+WR+1
-
WL+2+WR+1
-
nCK
Timing of REF command to Power Down entry
tREFPDEN
1
-
1
-
1
-
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
ns
Calibration Timing
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
nCK
Power Down Timing
Exit Power Down with DLL to any valid command; Exit
Precharge Power Down with DLL frozen to commands
not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of WR command to Power Down entry BL8 (OTF,
MRS), BL4OTF
Timing of WRA command to Power Down entry BL8
(OTF, MRS), BL4OTF
Timing of WR command to Power Down entry (BL4MRS)
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
9
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR3-1333
(-K9)
Symbol
DDR3-1066
(-F8)
DDR3-800
(-E7)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
ODT Timing
ODT high time without write command or with write
command and BC4
ODTH4
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
nCK
Asynchronous RTT turn-on delay (Power-Down with DLL
frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down with DLL
frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
ODT turn-on
tAON
-250
250
-300
300
-400
400
ps
RTT_NOM and RTT_WR turn-off time from ODTL off
reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
tWLMRD
40
-
40
-
40
-
tCK
tWLDQSEN
25
-
25
-
25
-
tCK
Setup time for tDQSS latch
tWLS
195
-
245
-
325
-
ps
Hold time for tDQSS latch
tWLH
195
-
245
-
325
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode
is programmed
DQS/DQS delay after tDQS margining mode is
programmed
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
10
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Package Dimensions
3.40
MAX
FRONT VIEW
67.60
4.0 +/- 0.10 (2X)
TYP
30.00
1.80 (2X)
TYP
20.00 TYP
6.00 TYP
2.15 TYP
0.5 R
1.0 +/- 0.10
TYP
0.60 TYP
PIN 1
0.45 TYP
PIN 203
1.0 +/- 0.10
63.60 TYP
BACK VIEW
4.00 TYP
2.55 TYP
3.00 TYP
PIN 204
39.00 TYP
21.00 TYP
PIN 2
24.80 TYP
Note: 1. All dimension are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
11
Product Specifications
PART NO.:
VL41B5663A-K9S/F8S/E7S-S1
REV: 1.0
Revision History:VN-121009
Date
Rev.
Page
03/23/09
12/02/09
0.01
1.0
All
All
Changes
Preliminary spec
Updated information for temperature screening
Spec release
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
12
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