User manual | datasheet for S518324-44ZTR7 by RF Micro Devices, Inc.

S518324-44Z

UPSTREAM

CATV AMPLI-

FIER

S518324-44Z

UPSTREAM CATV AMPLIFIER

Package: QFN, 20-Pin, 4mm x 4mm

Features



Single 3.3V Supply Operation



Low Power Consumption:

143mA Typical



63db Dynamic Range:

-2.5dBm To 61dBmV Output



Excellent Linearity

2nd/3rd Harmonics>60dBc

Typical



Programmable Gain In 0.5dB

Steps



Ultra Low On/Off Transients



DOCSIS 2.0 & EuroDOCSIS 2.0

Compliant



DOCSIS 3.0 compliant to a maximum of +54dBmV RF power output (64-QAM signal, 25.6MHz channel bonded bandwidth using four 6.4MHz bonded channels)

Applications



Set-Top Boxes



Cable Telephony



Cable Modems



CATV Infrastructure

Functional Block Diagram

Product Description

The S518324 is a high performance, CMOS, low power programmable power amplifier designed for use in CATV upstream applications. The amplifier operates over a frequency range from 5MHz to 65MHz and has a maximum output of 61dBmV. A 3wire serial interface controls the gain over a 63.5dB range in 0.5dB steps. The

S518324 is available in a thermally enhanced QFN, 20-Pin, 4mm x 4mm. Meets

DOCSIS 3.0 specifications including four-channel bonding (F=25.6MHz for four

6.4MHz bonded US channels) up to a maximum RF output of +54dBmV.

Ordering Information

S518324-44ZSQ

S518324-44ZSR

Sample bag with 25 pieces

7" Reel with 100 pieces

S518324-44ZTR7

S518324-44ZTR13

7" Reel with 750 pieces

13" Reel with 2500 pieces

S518324-44ZPCK-410 5MHz to 65MHz PCBA with 5-piece sample bag

DS120511

GaAs HBT

GaAs MESFET

InGaP HBT

Optimum Technology Matching

®

Applied



SiGe BiCMOS

Si BiCMOS

SiGe HBT

GaAs pHEMT

Si CMOS

Si BJT

GaN HEMT

BiFET HBT

RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2012, RF Micro Devices, Inc.

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S518324-44Z

Absolute Maximum Ratings

Parameter

Supply Voltage

Operating Temperature

Storage Temperature

Junction Temperature

Thermal Resistance

Parameter

Overall

Gain

Gain Flatness

Attenuation Range

Attenuation Step Size

Output Return Loss

Isolation

Transmit Mode Noise

Transmit Disable Mode Noise

Second Harmonic Distortion

Third Harmonic Distortion

DC Performance

Supply Voltage

Supply Current

Logic Inputs

Input High Voltage

Input Low Voltage

V

DD

-0.4

31

28

1.75

3.0

63.5

0.5

15

-90

-30

-45

-52

-68

60

58

3.3

143

70

30

Rating

-0.3 to +3.6

-40 to +85

-65 to 150

150

34

Unit

V

°C

°C

°C

°C/W

ESD sensitive device.

Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum

Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied.

The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of

RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.

RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric materials and red phosphorus as a flame retardant, and <2% antimony in solder.

Min.

Specification

Typ.

Max.

Unit

26

25.2

2

3.5

10

-28

-43

-50 dBc dBc dBc dB dB dB dB dB dB dB dB dB

Condition

T=25 °C, V

DD

=3.3V, unless otherwise specified

F

IN

=5MHz, Gain Code=127

F

IN

=65MHz, Gain Code=127

F

IN

=5MHz to 42MHz

F

IN

=5MHz to 65 MHz

Gain Code =0 to 127

Gain Code =0 to 127

5MHz to 65MHz

5MHz to 65MHz, TXEN=0 (Transmit Disable

Mode)

5MHz to 65MHz, BW=160KHz, Gain

Code=127 to 96

5MHz to 65MHz, BW=160KHz, Gain

Code=95 to 32

5MHz to 65MHz, BW=160KHz, Gain

Code=31 to 0

5MHz to 65MHz, BW=160KHz, TXEN=0

V

OUT

=60dBm, 5MHz to 65MHz

V

OUT

=60dBm, 5MHz to 65MHz

3.2

3.5

160

10

0.4

V mA mA mA

A

V

V

TXEN=1, D7=0, SLEEP=1,Gain Code=127

TXEN=1, D7=0, SLEEP=1,Gain Code=60 to 0

TXEN=0, D7=0, SLEEP=1,

D7=1, SLEEP=0,

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S518324-44Z

150

140

130

120

110

100

90

80

70

60

50

0

40

30

20

10

0

-10

-20

-30

-40

0

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

50

Typical Performance Curves

VOLTAGE GAIN vs. GAIN CODE

TRANSMIT NOISE vs. GAIN CODE

20 40 60 80

Gain Code

Gain Code

2ND HARMONIC vs. GAIN CODE

(POUT=60dBmV @ GCW=127)

7MHz

43MHz

100 120

-25

-30

-35

-40

-45

-50

-55

-60

0 20 40 60 80 100

Gain Code

Gain Code

3RD HARMONIC vs. GAIN CODE

(POUT = 60dBmV @ GCW = 127)

7MHz

43MHz

120

60 70 80 90 100 110

7MHz

43MHz

120

-65

-70

-75

-80

-85

-90

50

-40

-45

-50

-55

-60

60 70 80 90 100 110

7MHz

43MHz

120

Gain Code

Gain Code

SUPPLY CURRENT vs. GAIN CODE

20 40 60 80 100 120

Gain Code

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DS120511 3 of 11

S518324-44Z

13

14

15

16

17

18

19

20

9

10

11

12

7

8

5

6

Pin

3

4

1

2

Function Description

GND

GND

VIN+

VIN-

Ground.

Ground.

Positive Input.

Negative Input.

Ground.

GND

LE

DATA

CLK

GND

SLEEP

NC

TERM

VOUT-

VOUT+

RAMP

Serial Interface Enable. TTL compatible input. See Serial Interface section.

Serial Interface Data. TTL compatible input. See Serial Interface section.

Serial Interface Clock. TTL compatible input. See Serial Interface section.

Ground.

Hardware Shutdown. For fast shutdown, TXEN must be low when SLEEP is set low.

No Connect.

A resistor of 60

 and a bypass cap must be connected in series to the output of the transformer to ensure proper output impedance when output-amp is disable.

Negative output of the output-amp stage. Along with VOUT+, the two ports form a differential impedance of

75

.

Positive output of the output-amp stage. Along with VOUT+, the two ports form a differential impedance of 75

.

An external capacitor to ground is connected to control the ramp-up and ramp-down during transmit enable and disable.

Transmit enable. Drive TXEN high to turn on the output stage.

TXEN

VCC

GND

GND

VCC

3.3V.

Ground.

Ground.

3.3V.

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S518324-44Z

Functional Description

Upstream CATV Amplifier

The upstream CATV amplifier consists of an input attenuator (ATTN1), pre-amp, intermediate attenuator (ATTN2), power amp, serial data interface, bias control, ramp generator, and a switch. The amplifier and the attenuator blocks are capable of providing a gain range of 63.5dB with 0.5dB steps across the specified frequencies of operation. The gain and current of the whole chain is determined by a 7-bit word programmed using the serial data interface.

Input Interface

The differential input impedance of the upstream CATV amplifier is 150

. The input anti-aliasing filter should be designed to the same impedance for proper operation. The output impedance of the DAC should also be set accordingly. In order to achieve the specified performance, the inputs should be driven differentially.

Output Interface

The differential output impedance of the upstream CATV amplifier is 75

 provided that the suggested value of the shunt feedback resistor of the power amp stage is used. The differential output is converted to a single-ended output with a 1:1 turn ratio transformer.

Switch

During transmit disable mode, the 75

 output impedance is maintained by switching in a shunt 60 resistor connected from the single-ended output of the transformer to Pin 12. The switch is toggled by the TXen pin, SLEEP pin, and D7 bit. When TXEN and SLEEP are high and D7=0 (transmit mode), the switch is open. It is closed when TXEN or SLEEP is low or D7=1.

Power Amp (PA)

The power amplifier stage is a Class A differential amplifier with shunt feedback and series feedback. It is capable of providing an output level of 61dBmV. The 3.3V bias of the PA stage comes from the center-tap of the 1:1 turn ratio transformer. The transformer will suppress the even-order distortion and the transients caused by enabling and disabling the PA.

Ramp Generator

This block is a simple RC charging circuit consisting of an internal 1k

 resistor and an external capacitor Cext. This circuit controls the ramp up and down time of the PA stage during bursts.

Bias Control

The bias control sets the current of the PA stage at various gain states. In the lower gain states, the current of the PA is reduced and overall power consumption decreases.

Serial Interface

The serial interface becomes active when LE (latch enable) is low. The overall gain, current, and chip shutdown are determined by the programming of the bits D0 - D7. See Table 1, Table 2, Table 3, and Serial-Interface Timing Diagram for programming details. For fast shutdown, TXEN must be low when D7 is set low.

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S518324-44Z

Attenuator States

1

1

1

1

0

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

X

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Attenuator Values

D0

D1

D2

D3

D4

D5

D6

0.5

1.0

2.0

4.0

8.0

16.0

32.0

0

0

0

0

1

0

X

X

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

X

1

X

X

1

0

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

X

1

X

X

1

1

0

1

1

0

0

0

0

0

0

0

0

1

0

0

1

X

1

X

X

1

0

1

1

1

1

1

1

0

0

1

0

0

1

0

0

1

X

1

X

X

1

0

1

1

0

1

1

0

0

0

1

1

0

0

1

0

1

X

1

X

X

1

0

1

1

0

1

1

1

0

0

1

0

0

0

0

0

1

X

1

X

X

0

0

1

0

0

1

0

0

0

0

0

0

0

Serial-Interface Control Word

MSB7

6

5

4

3

2

1

LSB0

D2

D1

D0

D7

D6

D5

D4

D3

1

1

1

1

X

1

X

X

1

1

1

1

1

1

1

1

1

0

1

1

1

121

101

97

95

X

X

X

127

125

93

81

65

63

31

29

21

61

41

33

1

0

Shutdown

Transmit Disable

Shutdown

A

V

=30.0dB

A

V

=29.0dB

A

V

=27.0dB

A

V

=17.0dB

A

V

=15.0dB

A

V

=14.0dB

A

V

=13.0dB

A

V

=7.0dB

A

V

=-1.0dB

A

V

=-2.0dB

A

V

=-3.0dB

A

V

=-13.0dB

A

V

=-17.0dB

A

V

=-18.0dB

A

V

=-19.0dB

A

V

=-23.0dB

A

V

=-33.0dB

A

V

=-33.5dB

Shutdown (TXEN=0)

Gain control, bit 6

Gain control, bit 5

Gain control, bit 4

Gain control, bit 3

Gain control, bit 2

Gain control, bit 1

Gain control, bit 0

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A

Serial-Interface Timing Diagram

S518324-44Z

G B C D E F

LE

CLK

DATA D7 D6 D5

A. t

SENS

B. t

SDAS

C. t

SDAH

D. t

SCKL

D4 D3 D2

E. t

SCKH

F. t

SENH

G. t

DATAH

/t

DATAL

D1 D0

Application Circuit

DS120511

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S518324-44Z

Evaluation Board Schematic

C21

.01uF

C20

.01uF

GND GND

GND GND

R4

1k

R14

0

GND

C14

1000pF

J3

3

2

1

-4.77dB

GND

R9

24

GND

R12

NL

GND

C12

.01uF

4

R8

75

GND

GND

6

T1

C2

2.2pF

3

GND GND

C4 GND

.01uF

2

R13

NL

1

2

3

4

GND

5

TOKO 1:1

TOKO Footprint

1

C5

.01uF

GND

GND

TXin+

TXin-

GND

GND

3.3V

TX_LE

DA

CK

TX_SH

TX_EN

4

5

6

7

1

2

3

JP2

7PIN

R16

0

GND

C16

NL

R17

1k

C17

NL

GND

R18

0

U1

S518324-44Z

RAMP

Vout+

15

C1

1000pF

GND

14

1

Vout-

13

R20

0

0

12

TERM

NC

11

GND

C13

NL

GND

R3

75

GND

C15

1000pF

R2

0

.01uF

GND

C10

2

.01uF

3

C9

T1

6

TOKO 1:1

4

GND

C11

.01uF

R6

43

R7

43

GND

R22

NL

GND

GND

R11

43

GND

1

2

3

J1

-4.77dB

R19

1k

R21

1k

GND

C18

NL

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DS120511

Package Drawing

S518324-44Z

Package Information:

1. Dimensions and tolerances conform to ASME Y14.5-1994.

2. All dimensions are in millimeters. All angles are in degrees.

3. The exposed thermal pad is also an electrical ground.

DS120511

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S518324-44Z

Land Pattern for Terminals and Thermal/Ground Pad

Pin Out

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DS120511

S518324-44Z

DS120511

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