User manual | phyCARD-M Hardware Manual Document No.:

phyCARD-M
Hardware Manual
Document No.: L-750e_2
SBC Prod. No.: PCA-A-M1-xxx
SBC PCB. No.: 1328.2
CB Prod. No.:
CB PCB. No.:
Edition:
PBA-A-01
1333.2
September 2010
A product of a PHYTEC Technology Holding company
phyCARD-M [PCA-A-M1-xxx]
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark (™) and copyright (©) symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
© Copyright 2010 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
Address:
EUROPE
NORTH AMERICA
PHYTEC Technologie Holding AG
Robert-Koch-Str.
39
D-55129
Mainz
GERMANY
PHYTEC
America
LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
+49 (800) 0749832
Information: [email protected]
1 (800) 278-9913
[email protected]
Technical
Support:
+49 (6131) 9221-31
[email protected]
1 (800) 278-9913
[email protected]
Fax:
+49 (6131) 9221-33
1 (206) 780-9135
Web Site:
http://www.phytec.de
http://www.phytec.com
2nd Edition September 2010
2
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Contents
List of Figures..............................................................................................iii
List of Tables ...............................................................................................iv
Conventions, Abbreviations and Acronyms ............................................vii
Preface..........................................................................................................ix
1
Introduction......................................................................................... 1
1.1 Block Diagram ............................................................................. 4
1.2 View of the phyCARD-M ............................................................ 5
1.3 Minimum Requirements to Operate the phyCARD-M................ 7
2
Pin Description .................................................................................... 9
3
Jumpers.............................................................................................. 17
4
Power.................................................................................................. 23
4.1 Primary System Power (VCC_3V3) .......................................... 23
4.2 Standby Voltage (VBAT)........................................................... 24
4.3 On-board Voltage Regulator (U1).............................................. 24
4.4 Supply Voltage for external Logic ............................................. 25
5
Power Management .......................................................................... 27
6
System Configuration and Booting ................................................. 31
7
System Memory................................................................................. 35
7.1 DDR2-SDRAM (U8 - U11) ....................................................... 35
7.2 NAND Flash Memory (U13) ..................................................... 36
7.3 I²C EEPROM (U6)..................................................................... 36
7.3.1 Setting the EEPROM Lower Address Bits (J1, J3, J4). 37
7.3.2 EEPROM Write Protection Control (J16) .................... 38
7.4 Memory Model........................................................................... 38
8
SD / MMC Card Interfaces .............................................................. 39
9
Serial Interfaces................................................................................. 41
9.1 Universal Asynchronous Interface ............................................. 42
9.2 USB-OTG Interface ................................................................... 43
9.3 USB-Host Interface .................................................................... 44
9.4 Ethernet Interface ....................................................................... 45
9.4.1 PHY Physical Layer Transceiver (U7) ......................... 45
9.4.2 MAC Address................................................................ 47
9.5 I2C Interface ............................................................................... 47
9.6 SPI Interface ............................................................................... 48
9.7 Synchronous Serial Interface (SSI) ............................................ 48
10 General Purpose I/Os........................................................................ 51
11 Debug Interface (X1) ........................................................................ 53
12 LVDS Display Interface.................................................................... 57
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phyCARD-M [PCA-A-M1-xxx]
13
14
15
16
17
ii
12.1 Signal configuration (J22).......................................................... 58
12.2 LVDS Display Interface pixel mapping .................................... 58
LVDS Camera Interface .................................................................. 61
13.1 Signal configuration (J21).......................................................... 62
Technical Specifications ................................................................... 63
Component Placement Diagram ..................................................... 67
Hints for Integrating and Handling the phyCARD-M.................. 69
16.1 Integrating the phyCARD-M ..................................................... 69
16.2 Handling the phyCARD-M........................................................ 71
The phyCARD-M on the phyBase................................................... 73
17.1 Concept of the phyBASE Board ................................................ 74
17.2 Overview of the phyBASE Peripherals ..................................... 75
17.2.1 Connectors and Pin Header........................................... 76
17.2.2 Switches ........................................................................ 77
17.2.3 LEDs ............................................................................. 80
17.2.4 Jumpers ......................................................................... 81
17.3 Functional Components on the phyBASE Board ...................... 84
17.3.1 phyCARD-M SBC Connectivity (X27)........................ 84
17.3.2 Power Supply (X28) ..................................................... 85
17.3.3 RS-232 Connectivity (P1)............................................. 88
17.3.4 Ethernet Connectivity (X10)......................................... 89
17.3.5 USB Host Connectivity (X6, X7, X8, X9, X33) .......... 90
17.3.6 USB OTG Connectivity (X29) ..................................... 92
17.3.7 Display / Touch Connectivity (X6, X32)...................... 93
17.3.7.1 Display Data Connector (X6) ........................ 94
17.3.7.2 Display Power Connector (X32) ................... 96
17.3.7.3 Touch Screen Connectivity ........................... 97
17.3.8 Camera Interface (X5) .................................................. 99
17.3.9 Audio Interface (X1,X2,X3) ....................................... 100
17.3.10 I2C Connectivity.......................................................... 102
17.3.11 SPI Connectivity ......................................................... 103
17.3.12 User programmable GPIOs......................................... 103
17.3.13 Expansion connectors (X8A, X9A) ............................ 104
17.3.14 Secure Digital Memory Card/ MultiMedia Card (X26)
..................................................................................... 106
17.3.15 Boot Mode Selection (JP1) ......................................... 107
17.3.16 System Reset Button (S1) ........................................... 108
17.3.17 RTC at U3 ................................................................... 109
17.3.18 PLD at U25 ................................................................. 110
17.3.19 Carrier Board Physical Dimensions............................ 111
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Contents
18 Revision History .............................................................................. 112
Index.......................................................................................................... 113
List of Figures
Figure 1:
Block Diagram of the phyCARD-M.......................................... 4
Figure 2:
Top view of the phyCARD-M (controller side) ........................ 5
Figure 3:
Bottom view of the phyCARD-M (connector side)................... 6
Figure 4:
Pin-out of the phyCARD-Connector (top view, with cross
section insert) ........................................................................... 10
Figure 5:
Typical jumper pad numbering scheme ................................... 17
Figure 6:
Jumper locations (top view)..................................................... 18
Figure 7:
Jumper locations (bottom view)............................................... 19
Figure 8:
Power Supply Diagram ............................................................ 25
Figure 9:
JTAG interface at X1 (top view).............................................. 53
Figure 10: JTAG interface at X1 (bottom view) ....................................... 54
Figure 11: Physical dimensions ................................................................. 63
Figure 12: phyCARD-M component placement (top view)...................... 67
Figure 13: phyCARD-M component placement (bottom view)................ 68
Figure 14: Footprint of the phyCARD-M.................................................. 70
Figure 15: phyBASE Overview of Connectors, LEDs and Buttons ......... 75
Figure 16: Typical jumper numbering scheme.......................................... 81
Figure 17: phyBASE jumper locations...................................................... 82
Figure 18: phyCARD-M SBC Connectivity to the Carrier Board ............ 84
Figure 19: Power adapter........................................................................... 85
Figure 20: Connecting the Supply Voltage at X28.................................... 86
Figure 21: RS-232 connection interface at connector P1 .......................... 88
Figure 22: RS-232 connector P1 signal mapping...................................... 89
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phyCARD-M [PCA-A-M1-xxx]
Figure 23: Ethernet interface at connector X10 ........................................ 89
Figure 24: Components supporting the USB host interface...................... 90
Figure 25: USB OTG interface at connector X29..................................... 92
Figure 26: Universal LVDS interface at connector X6............................. 93
Figure 27: Camera interface at connectors X5.......................................... 99
Figure 28: Audio interface at connectors X1,X2,X3 .............................. 100
Figure 29: Expansion connector X8A, X9A ........................................... 104
Figure 30: SD / MM Card interface at connector X26............................ 106
Figure 31: Boot Mode Selection Jumper JP1.......................................... 107
Figure 32: Boot Mode Selection Jumper JP1.......................................... 108
Figure 33: System Reset Button S1......................................................... 108
Figure 34: The RTC at U3 with the battery connector BAT1................. 109
Figure 35: Carrier Board Physical Dimensions....................................... 111
List of Tables
Table 1:
Abbreviations and Acronyms used in this Manual................. viii
Table 2:
X-Arc Bus Pin-out ................................................................... 12
Table 3:
Pin-out of the phyCARD-Connector X2 ................................. 16
Table 4:
Jumper settings ........................................................................ 21
Table 5:
Power Management Pins ......................................................... 27
Table 6:
Power States............................................................................. 28
Table 7:
Power management jumpers J2 and J9 .................................... 29
Table 8:
Boot Modes of i.MX35 module............................................... 32
Table 9:
Further Boot Configuration Pins.............................................. 33
Table 10:
Compatible NAND Flash devices............................................ 36
Table 11:
U6 EEPROM I²C address via J1, J3, and J4............................ 37
Table 12:
EEPROM write protection states via J16 ................................ 38
iv
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Contents
Table 13:
Location of SD/ MMC Card interface signals ......................... 39
Table 14:
Location of the UART signals ................................................. 42
Table 15:
Location of the USB-OTG signals........................................... 43
Table 16:
Location of the USB-Host signals ........................................... 44
Table 17:
Location of the Ethernet signals............................................... 45
Table 18:
Fast Ethernet controller memory map...................................... 46
Table 19:
I2C Interface Signal Location................................................... 47
Table 20:
SPI Interface Signal Location .................................................. 48
Table 21:
SSI Interface Signal Location .................................................. 49
Table 22:
Location of GPIO and IRQ pins .............................................. 51
Table 23:
JTAG connector X1 signal assignment.................................... 55
Table 24:
Display Interface Signal Location............................................ 57
Table 25:
LVDS signal configuration J22................................................ 58
Table 26:
Pixel mapping of 18-bit LVDS display interface .................... 58
Table 27:
Pixel mapping of 24-bit LVDS display interface .................... 59
Table 28:
Camera Interface Signal Location............................................ 61
Table 29:
LVDS signal configuration J21................................................ 62
Table 30:
phyBASE Connectors and Pin Headers ................................... 76
Table 31:
phyBASE push buttons descriptions........................................ 77
Table 32:
phyBASE DIP-Switch S3 descriptions .................................... 79
Table 33:
phyBASE LEDs descriptions................................................... 80
Table 34:
phyBASE jumper descriptions................................................. 83
Table 35:
LEDs assembled on the Carrier Board..................................... 86
Table 36:
Distribution of the USB hub's (U4) ports ................................ 91
Table 37:
Universal USB pin header X33 signal description .................. 91
Table 38:
Display data connector signal description ............................... 95
Table 39:
SPI and GPIO connector selection........................................... 96
Table 40:
LVDS power connector X32 signal description ...................... 96
Table 41:
Selection of the touch screen controller................................... 98
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
Table 42:
PHYTEC camera connector X5............................................... 99
Table 43:
Selection of the audio codec .................................................. 101
Table 44:
I2C connectivity ..................................................................... 102
Table 45:
I2C addresses in use ............................................................... 102
Table 46:
SPI connector selection.......................................................... 103
Table 47:
SPI and GPIO connector selection......................................... 105
Table 48:
PHYTEC expansion connector X8A, X9A ........................... 105
vi
© PHYTEC Messtechnik GmbH 2010
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Conventions, Abbreviations and Acronyms
Conventions, Abbreviations and Acronyms
This hardware manual describes the PCA-A-M1 Single Board
Computer in the following referred to as phyCARD-M. The manual
specifies the phyCARD-M's design and function. Precise
specifications for the Freescale i.MX35 microcontrollers can be found
in the enclosed microcontroller Data Sheet/User's Manual.
Conventions
The conventions used in this manual are as follows:
ƒ Signals that are preceded by a "n", "/", or “#”character (e.g.: nRD,
/RD, or #RD), or that have a dash on top of the signal name (e.g.:
RD) are designated as active low signals. That is, their active state
is when they are driven low, or are driving low.
ƒ A "0" indicates a logic zero or low-level signal, while a "1"
represents a logic one or high-level signal.
ƒ Tables which describe jumper settings show the default position in
bold, blue text.
ƒ Text in blue italic indicates a hyperlink within, or external to the
document. Click these links to quickly jump to the applicable
URL, part, chapter, table, or figure.
ƒ References made to the phyCARD-Connector always refer to the
high density molex connector on the undersides of the
phyCARD-M Single Board Computer.
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual.
Use the table below to navigate unfamiliar terms used in this
document.
Abbreviation Definition
BSP
Board Support Package (Software delivered with the
Development Kit including an operating system
(Windows, or Linux) preinstalled on the module and
Development Tools).
CB
Carrier Board; used in reference to the phyBASE
Development Kit Carrier Board.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
Abbreviation
DFF
EMB
EMI
GPI
GPIO
GPO
IRAM
J
JP
PCB
POR
RTC
SBC
SMT
Sx
Sx_y
VBAT
Table 1:
Definition
D flip-flop.
External memory bus.
Electromagnetic Interference.
General purpose input.
General purpose input and output.
General purpose output.
Internal RAM; the internal static RAM on the
Freescale i.MX35 microcontroller.
Solder jumper; these types of jumpers require solder
equipment to remove and place.
Solderless jumper; these types of jumpers can be
removed and placed by hand with no special tools.
Printed circuit board.
Power-on reset
Real-time clock.
Single Board Computer; used in reference to the
PCA-A-M1
/phyCARD-A-M1
Single
Board
Computer
Surface mount technology.
User button Sx (e.g. S1, S2, etc.) used in reference to
the available user buttons, or DIP-Switches on the
Carrier Board.
Switch y of DIP-Switch Sx; used in reference to the
DIP-Switch on the Carrier Board.
SBC standby voltage input
Abbreviations and Acronyms used in this Manual
Note: The BSP delivered with the phyCARD-M usually includes
drivers and/or software for controlling all components such as
interfaces, memory, etc.. Therefore programming close to hardware at
register level is not necessary in most cases. For this reason, this
manual contains no detailed description of the controller's registers, or
information relevant for software development. Please refer to the
i.MX35 Reference Manual, if such information is needed to connect
customer designed applications.
viii
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Preface
Preface
As a member of PHYTEC's new phyCARD product family the
phyCARD-M is one of a series of PHYTEC Single Board Computers
(SBCs) that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1)
as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2)
as insert-ready, fully functional phyCARD OEM modules,
which can be embedded directly into the user’s peripheral
hardware design.
Implementation of an OEM-able SBC subassembly as the "core" of
your embedded design allows you to focus on hardware peripherals
and firmware without expending resources to "re-invent"
microcontroller circuitry. Furthermore, much of the value of the
phyCARD module lies in its layout and test.
PHYTEC's new phyCARD product family consists of a series of
extremely compact embedded control engines featuring various
processing performance classes while using the newly developed
X-Arc embedded bus standard. The standardized connector footprint
and pin assignment of the X-Arc bus makes this new SBC generation
extremely scalable and flexible. This also allows to use the same
carrier board to create different applications depending on the required
processing power. With this new SBC concept it is possible to design
entire embedded product families around vastly different processor
performances while optimizing overall system cost. In addition, future
advances in processor technology are already considered with this new
embedded bus standard making product upgrades very easy. Another
major advantage is the forgone risk of potential system hardware
redesign steps caused by processor or other critical component
discontinuation. Just use one of PHYTEC's other phyCARD SBCs
thereby ensuring an extended product life cycle of your embedded
application.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
Production-ready Board Support Packages (BSPs) and Design
Services for our hardware will further reduce your development time
and risk and allow you to focus on your product expertise. Take
advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With
this new innovative full system solution you will be able to bring your
new ideas to market in the most timely and cost-efficient manner.
For more information go to:
http://www.phytec.com/services/
Ordering Information
The part numbering of the phyCARD has the following structure:
PCA-A-M1-xxxxxx
Generation
A
=
First generation
Performance class
S
M
L
XL
=
=
=
=
small
middle
large
largest
Controller No. of specified performance class
Assembly options (depending on model)
In order to receive product specific information on changes and
updates in the best way also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html
You can also get technical support and additional information
concerning your product.
x
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Preface
The support section of our web site provides product specific
information, such as errata sheets, application notes, FAQs, etc.
http://www.phytec.de/de/support/faq/faq-phyCARD-M.html
Declaration of Electro Magnetic Conformity of the
PHYTEC phyCARD-M
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
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© PHYTEC Messtechnik GmbH 2010
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Introduction
1
Introduction
The phyCARD-M belongs to PHYTEC’s phyCARD Single Board
Computer module family. The phyCARD SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCARD boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
PHYTEC's phyCARD family introduces the newly developed X-Arc
embedded bus standard. Apart from processor performance, a large
number of embedded solutions require a corresponding number of
standard interfaces. Among these process interfaces are for example
Ethernet, USB, UART, SPI, I2C, audio, display and camera
connectivity. The X-Arc bus exactly meets this requirement. As well
the location of the commonly used interfaces as the mechanical
specifications are clearly defined. All interface signals of PHYTEC's
new X-Arc bus are available on a single, 100-pin, high-density pitch
(0.635 mm) connector, allowing the phyCARDs to be plugged like a
"big chip" into a target application. The reduced complexity of the
phyCARD SBC as well as the smaller number of interface signals
greatly simplifies the SBC carrier board design helping you to reduce
your time-to-market.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments approximately 20 % of all pin header connectors on the
X-Arc bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications
meeting EMI and EMC guidelines using phyCARD boards even in
high noise environments.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
phyCARD boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCARD users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCARD-M is a subminiature (60 x 60 mm) insert-ready Single
Board Computer populated with the Freescale i.MX35
microcontroller. Its universal design enables its insertion in a wide
range of embedded applications.
Precise specifications for the controller populating the board can be
found in the applicable controller Reference Manual or datasheet. The
descriptions in this manual are based on the Freescale i.MX35. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCARD-M.
The phyCARD-M offers the following features:
• Subminiature Single Board Computer ( 60 x 60 mm) achieved
through modern SMD technology
• Populated with the Freescale i.MX35 microcontroller (BGA400
packaging)
• Improved interference safety achieved through multi-layer PCB
technology and dedicated ground pins
• X-Arc bus including commonly used interfaces such as Ethernet,
USB, UART, SPI, I2C, audio, display and camera connectivity
(both LVDS) available at one 100-pin high-density (0.635 mm)
Molex connector, enabling the phyCARD-M to be plugged like a
"big chip" into target application
• Max. 532 MHz core clock frequency
• Boot from NAND Flash
• 128 MByte (up to 1 GByte) on-board NAND Flash 1
• 32 MByte (up to 256 MByte) DDR 2 SDRAM on-board
• 4KB (up to 32kB) I2C EEPROM
1
Please contact PHYTEC for more information about additional module configurations.
2
© PHYTEC Messtechnik GmbH 2010
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Introduction
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Serial interface with 4 lines (TTL) allowing simple hardware
handshake
High-Speed USB OTG transceiver
High-Speed USB HOST transceiver
Auto HDX/FDX 10/100MBit Ethernet interface, with HP Auto
MDI/MDI-X support
Single supply voltage of 3.3V (max. 600mA) with on-board power
management
All controller required supplies generated on board
4 Channel LVDS (18Bit) LCD-Interface
Support of standard 20 pin debug interface through JTAG
connector
One I2C interfaces
One SPI interfaces
SD/MMC card interface with DMA
SSI Interface (AC97)
Optional LVDS Camera Interface1
3 GPIO/IRQ ports
2 Power State outputs to support applications requiring a power
management
1 Wake Up input
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
1.1
Block Diagram
532 MHz Clock
i.MX35
DDR2 SDRAM Bus
ARM1136JF-S
core
external 24MHz Quartz
64 to 256MB
DDR2 SDRAM Bank I + II
133MHz
32 bit
128MB to 1GB
NAND Flash
8 bit
EMI
16k L1 D-cache
High-Speed
USB-Host Contr.
16k L1 I-cache
6
USB-OTG+ HS Phy
Vector floating
point Unit
Reset-Logic
+1V37
+1V
+1V
+2V77
1
8
Power
Management
2
2
I C-Memory
EEPROM
4KByte
I2C1
I2C3
FEC FastEthernet
2
Ethernet PHY
SSI / AC97
6
SPI 1
6
4
UART1
7
SDIO1
3
GPIO1_1, GPIO2_7 / 23
24-BitLVDS-Transmitter
CSI
10-Bit LVDS-Deserializer
IPU
DI
JTAG
Figure 1:
4
6
Power State Output
phyCARD-Connecto
1
GPIO (GPIO2_12)
/RESET_IN_B; /POR_B;
GPIO (GPIO2_6)
Boot Configuration
Input
2
GPIO (GPIO2_29 / 3_10)
MMU
Memory Management
Unit
USB OTG
2
Boot_Mode 0 / 1
VFP
High-Speed
USB Host
4
USB2-Host + FS Phy
128k L2 cache
Wake Up Input
VBat +3V3
Power +3V3
Reset Input /
Reset
I2C Master
Interface
10/100 Mbit
Ethernet
AC97 /
Synchronous
SPI Interface
UART TTL
SD / MMC-Card
Interface
3 * GPIO / IRQ
10
LVDS-Display
Interface
4
LVDS-Camera
Interface
Card-Edge Connector
JTAG Debug-/
Test Port
Block Diagram of the phyCARD-M
© PHYTEC Messtechnik GmbH 2010
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Introduction
1.2
View of the phyCARD-M
J10
J17
J11
J12
U13
XT4
U9
U7
20
U3
J5
XT3
X1
U10
J6
J25
XT2
U8
2
U1
U11
J2
J7
XT1
J9
Figure 2:
Top view of the phyCARD-M (controller side)
© PHYTEC Messtechnik GmbH 2010
L-750e_2
5
phyCARD-M [PCA-A-M1-xxx]
U16
J26
X2
U14
U17
X1
U5
19
J21
J20 J13
U2
J19
J8
J14
J15
U4
1
J18
J27
U15
J22
J4
J1
J3
1B 1A
Figure 3:
6
U6
J16
Bottom view of the phyCARD-M (connector side)
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Introduction
1.3
Minimum Requirements to Operate the phyCARD-M
Basic operation of the phyCARD-M only requires supply of a +3V3
input voltage with 600 mA load and the corresponding GND
connection.
These supply pins are located at the phyCARD-Connector X2:
VDD_3V3_IN:
X2
1A, 2A, 3A, 1B, 2B, 3B
Connect all +3.3V VCC input pins to your power supply and at least
the matching number of GND pins.
Corresponding GND:
X2 4A, 8A, 13A, 4B, 8B, 13B
Please refer to section 2 for information on additional GND Pins
located at the phyCARD-Connector X2
Caution:
We recommend connecting all available +3V3 input pins to the power
supply system on a custom carrier board housing the phyCARD-M
and at least the matching number of GND pins neighboring the +3V3
pins.
In addition, proper implementation of the phyCARD-M module into a
target application also requires connecting all GND pins neighboring
signals that are being used in the application circuitry.
Please refer to section 4 for more information.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
7
phyCARD-M [PCA-A-M1-xxx]
8
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Pin Description
2
Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user's responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 4 indicates, all X-Arc bus signals extend to one surface
mount technology (SMT) connector (0.635 mm) lining on side of the
module (referred to as phyCARD-Connector). This allows the
phyCARD-M to be plugged into any target application like a "big
chip".
The numbering scheme for the phyCARD-Connector is based on a
two dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin
connector rows progresses alphabetically from left to right (refer to
Figure 4).
The numbered matrix can be aligned with the phyCARD-M (viewed
from above; phyCARD-Connector pointing down) or with the socket
of the corresponding phyCARD Carrier Board/user target circuitry.
The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCARD-M marked with a triangle.
The numbering scheme is always in relation to the PCB as viewed
from above, even if all connector contacts extend to the bottom of the
module.
The numbering scheme is thus consistent for both the module’s
phyCARD-Connector as well as the mating connector on the
phyBASE Carrier Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
9
phyCARD-M [PCA-A-M1-xxx]
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCARD-Connector is usually assigned a
single designator for its position (X1 for example). In this manner the
phyCARD-Connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socketed
connector.
The following figure illustrates the numbered matrix system. It shows
a phyCARD-M with SMT phyCARD-Connectors on its underside
(defined as dotted lines) mounted on a Carrier Board. In order to
facilitate understanding of the pin assignment scheme, the diagram
presents a cross-view of the phyCARD-module showing these
phyCARD-Connectors mounted on the underside of the module’s
PCB.
X2
Figure 4:
10
Pin-out of the phyCARD-Connector (top view, with cross section
insert)
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Pin Description
Table 2 shows the Pin-out of the X-Arc bus with the functional
grouping of the signals, while Table 3 provides an overview of the
Pin-out of the phyCARD-Connector with signal names and
descriptions specific to the phyCARD-M. It also provides the
appropriate signal level interface voltages listed in the SL (Signal
Level) column and the signal direction.
The Freescale i.MX35 is a multi-voltage operated microcontroller and
as such special attention should be paid to the interface voltage levels
to avoid unintentional damage to the microcontroller and other onboard components. Please refer to the Freescale i.MX35 Reference
Manual for details on the functions and features of controller signals
and port pins.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
11
Display
Ethernet
USB OTG
SD/MMC
SPI
AC97/HDA
I/O
In
In
In
Out
In
Out
Out
Out
Out
Out
In
In
Out
Bi
Out
In
In
Out
In
Out
Bi
Bi
Out
Bi
Bi
Bi
Out
Out
In
In
Out
Bi
Out
Out
In
Bi
Bi
In
I2 C
USB Host
USB Host
UART
AC97/HDA
12
Signal
VCC
VCC
VCC
GND
VCC_LOGIC
VSTBY
nRESET_OUT
GND
LVDS_TX1+
LVDS_TX1LVDS_TX3+
LVDS_TX3GND
LVDS_CAM_RX+
LVDS_CAM_RXLVDS_CAM_nLOCK
I2C_DATA
GND
ETH_LINK
ETH_RX+
ETH_RXGND
USB_PWR2
USB_OC2
GND
nSuspend_to_RAM
USB_D2USB_D2+
nPower_Off
GND
SDIO_D1
SDIO_D3
SDIO_CMD
GND
SPI_CS1
SPI_MOSI
SPI_MISO
GND
UART_RXD
UART_CTS
GND
AC97/HDA_BIT_CLK
AC97/HDA_SYNC
AC97/HDA_nRESET
GND
SDIO_CD
GPIO1/IRQ1
for internal use only
GND
CONFIG1
SPI
Table 2:
Pin
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
27B
28B
29B
30B
31B
32B
33B
34B
35B
36B
37B
38B
39B
40B
41B
42B
43B
44B
45B
46B
47B
48B
49B
50B
SD/MMC
Boot Opt.
Pin
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
25A
26A
27A
28A
29A
30A
31A
32A
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
43A
44A
45A
46A
47A
48A
49A
50A
Ethernet
GPIO
VCC
VCC
VCC
GND
VCC_LOGIC
FEEDBACK
nRESET_IN
GND
LVDS_TX0+
LVDS_TX0LVDS_TX2+
LVDS_TX2GND
LVDS_TXCLK+
LVDS_TXCLKLVDS_CAM_MCLK
I2C_CLK
GND
ETH_SPEED
ETH_TX+
ETH_TXGND
USB_OTG_PWR1
USB_OTG_OC1
GND
USB_OTG_VBUS1
USB_OTG_D1USB_OTG_D1+
USB_OTG_UID1
GND
SDIO_D0
SDIO_D2
SDIO_CLK
GND
SPI_CS0
SPI_RDY
SPI_CLK
GND
UART_TXD
UART_RTS
GND
HDA_SEL/AC97_INT
AC97/HDA_SDATA_OUT
AC97/HDA_SDATA_IN
GND
GPIO0/IRQ0
GPIO2/IRQ2/PWM
nWKUP
GND
CONFIG0
Camera
UART
Signal
Display
Camera
I2 C
I/O
In
In
In
Out
In
Out
Out
Out
Out
Out
Out
Out
Bi
Out
Out
Out
Out
In
Bi
Bi
Bi
In
Bi
Bi
Out
Out
In
Out
Out
In
Bi
Out
In
Bi
Bi
In
In
Supply
Supply
phyCARD-M [PCA-A-M1-xxx]
X-Arc Bus Pin-out
© PHYTEC Messtechnik GmbH 2010
L-750e_2
SD/MMC
GPIO
Boot Opt.
Pin Description
Note:
SL is short for Signal Level (V) and is the applicable logic level to
interface a given pin.
Those pins marked as “N/A” have a range of applicable values that
constitute proper operation.
Please refer to the phyCARD Design-In Guide (LAN-051) for
layout recommendations and example circuitry.
Pin Row X2A
Pin # Signal
1A
VDD_3V3_IN
2A
VDD_3V3_IN
3A
VDD_3V3_IN
4A
GND
5A
VDD_3V3_IN
I/O
I
I
I
O
SL
Power
Power
Power
VDD_3V3
6A
VCC_FEEDBACK
O
-
7A
X_MASTER_RESET I
VDD_3V3 Active low Reset In
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
GND
X_TXOUT0+
X_TXOUT0X_TXOUT2+
X_TXOUT2GND
X_TXCLKOUT+
X_TXCLKOUTX_CSI_MCLK
X_I2C3_SCL
GND
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
VDD_3V3
VDD_3V3
-
19A
X_ETH_SPEED
20A
X_ETH_TX+
21A
X_ETH_TX-
22A
GND
O
O
O
O
O
O
O
O
-
Description
3.3V Primary Voltage Supply Input
3.3V Primary Voltage Supply Input
3.3V Primary Voltage Supply Input
Ground 0V
VCC Logic Output
Feedback Output to indicate the
supply voltage required (3V3 or 5V)
Ground 0V
LVDS Chanel 0 positive Output
LVDS Chanel 0 negative Output
LVDS Chanel 2 positive Output
LVDS Chanel 2 negative Output
Ground 0V
LVDS Clock positive Output
LVDS Clock negative output
Clock Output for Camera Interface
I2C Clock Output
Ground 0V
Ethernet Speed Indicator (Open
O
VDD_3V3
Drain)
Transmit positive output (normal)
O (I) ETH
Receive positive input (reversed)
Transmit negative output (normal)
O (I) ETH
Receive negative input (reversed)
Ground 0V
© PHYTEC Messtechnik GmbH 2010
L-750e_2
13
phyCARD-M [PCA-A-M1-xxx]
23A
X_USBOTG_PWR
O
VDD_3V3
24A
25A
26A
27A
28A
X_USBOTG_OC
GND
X_USBPHY1_VBUS
X_USBPHY1_DM
X_USBPHY1_DP
I
I
I/O
I/O
VDD_3V3
5V
USB
USB
29A
X_USBPHY1_UID
I
30A
GND
-
0
31A
X_SD1_DATA0
I/O
VDD_3V3
32A
X_SD1_DATA2
I/O
VDD_3V3
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
43A
44A
45A
X_SD1_CLK
GND
X_CSPI1_SS0
X_CSPI1_SPI_RDY
X_CSPI1_SCLK
GND
X_UART1_TXD
X_UART1_RTS
GND
X_AC97_INT
X_STXD4
X_SRXD4
GND
O
O
O
O
O
O
I/O
O
I
-
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
-
46A
X_GPIO2_7
I/O
VDD_3V3
47A
X_GPIO1_1
I/O
VDD_3V3
48A
X_WKUP
I
VDD_3V3
49A
50A
GND
X_BOOT0
I
VDD_3V3
14
USB-OTG Power switch output open
drain
USB-OTG over current input signal
Ground 0V
USB VBUS Voltage
USB transceiver cable interface, DUSB transceiver cable interface, D+
USB on the go transceiver cable ID
resistor connection
Ground 0V
SD/MMC Data line both in 1-bit and
4-bit mode
SD/MMC Data line both in 1-bit and
4-bit mode
SD/MMC Clock for MMC/SD/SDIO
Ground 0V
SPI 1 Chip select 0
SPI 1 SPI data ready in Master mode
SPI 1 clock
Ground 0V
Serial transmit signal UART 1
Request to send UART 1
Ground 0V
AC'97 Interrupt Input
AC'97 Transmit Output
AC'97 Receive Input
Ground 0V
GPIO0 / IRQ0 (µC port GPIO2_7 at
T7)
GPIO2 / IRQ 2/ PWM (µC port
GPIO1_1 at L16)
Wakeup Interrupt Input (µC port
GPIO2_12 at U6; PMIC port 'Power
On 2')
Ground 0V
Boot-Mode Input 0
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Pin Description
Pin Row X2B
SL
Power
Power
Power
VDD_3V3
Power
Pin #
1B
2B
3B
4B
5B
6B
Signal
VDD_3V3_IN
VDD_3V3_IN
VDD_3V3_IN
GND
VDD_3V3_IN
VBAT
I/O
O
-
7B
X_RESET_PER
-
VDD_3V3
Active low Reset output
8B
9B
10B
11B
12B
13B
GND
X_TXOUT1+
X_TXOUT1X_TXOUT3+
X_TXOUT3GND
O
O
O
O
-
LVDS
LVDS
LVDS
LVDS
-
14B
X_RXIN+
O
LVDS
15B
X_RXIN-
O
LVDS
16B
17B
18B
X_LOCK
X_I2C3_SDA
GND
O
I/O
-
VDD_3V3
VDD_3V3
-
19B
X_ETH_LINK
O
VDD_3V3
20B
X_ETH_RX+
I (O) ETH
21B
X_ETH_RX-
I (O) ETH
22B
GND
-
-
23B
X_USB_ PWR2
O
VDD_3V3
24B
X_USB_OC2
I
VDD_3V3
25B
GND
-
-
26B
X_Suspend_to_RAM
OC
VDD_3V3
27B
X_USB_DM2
I/O
USB
Ground 0V
LVDS Chanel 1 positive Output
LVDS Chanel 1 negative Output
LVDS Chanel 3 positive Output
LVDS Chanel 3 negative Output
Ground 0V
LVDS Receive positive Input for
Camera
LVDS Receive negative Input for
Camera
Lock Output for Camera Interface
I2C Data
Ground 0V
Ethernet Speed Indicator (Open
Drain)
Receive positive input (normal)
Transmit positive output (reversed)
Receive negative input (normal)
Transmit negative output (reversed)
Ground 0V
USB-HOST Power switch output
open drain
USB-HOST over current input
signal
Ground 0V
Suspend to RAM Open Collector
Output (µC port GPIO2_29 at V2)
USB HOST transceiver cable
interface, D-
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Description
3.3V Primary Voltage Supply Input
3.3V Primary Voltage Supply Input
3.3V Primary Voltage Supply Input
Ground 0V
VCC Logic Output
Standby Voltage Input
15
phyCARD-M [PCA-A-M1-xxx]
28B
X_USB_DP2
I/O
USB
29B
X_Power_off
OC
VDD_3V3
30B
GND
-
-
31B
X_SD1_DATA1
I/O
VDD_3V3
32B
X_SD1_DATA3
I/O
VDD_3V3
33B
X_SD1_CMD
O
VDD_3V3
34B
35B
36B
37B
38B
39B
40B
41B
42B
43B
GND
X_CSPI1_SS1
X_CSPI1_MOSI
X_CSPI1_MISO
GND
X_UART1_RXD
X_UART1_CTS
GND
X_SCK4
X_STXFS4
O
I/O
I/O
I
I
I
O
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
VDD_3V3
USB HOST transceiver cable
interface, D+
Power Off Open Collector Output
(µC port GPIO3_10 at H3)
Ground 0V
SD/MMC Data line both in 1-bit
and 4-bit mode
SD/MMC Data line both in 1-bit
and 4-bit mode
SD/MMC
Command
for
MMC/SD/SDIO
Ground 0V
SPI 1 Chip select 1
SPI 1 Master data out; slave data in
SPI 1 Master data in; slave data out
Ground 0V
Serial data receive signal UART 1
Clear to send UART 1
Ground 0V
AC'97 Clock
AC'97 SYNC
44B
X_AC97_RESET
O
VDD_3V3
AC'97 Reset
45B
GND
-
-
46B
X_SDIO_CD
I
VDD_3V3
47B
GPIO2_23
I/O
VDD_3V3
48B
X_OWIRE
-
VDD_3V3
49B
50B
GND
X_BOOT1
I
VDD_3V3
Ground 0V
SD/MMC
Card
Detect
for
MMC/SD/SDIO
GPIO1 / IRQ1 (µC port GPIO2_23
at V3)
Hardware Introspection Interface
for internal use only
Ground 0V
Boot-Mode Input 1
Table 3:
16
Pin-out of the phyCARD-Connector X2
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Jumpers
3
Jumpers
For configuration purposes, the phyCARD-M has 25 solder jumpers,
some of which have been installed prior to delivery. Figure 5
illustrates the numbering of the solder jumper pads, while Figure 6
and Figure 7 indicate the location of the solder jumpers on the board.
10 solder jumpers are located on the top side of the module (opposite
side of connectors) and 15 solder jumpers are located on the bottom
side of the module (connector side). Table 4 below provides a
functional summary of the solder jumpers which can be changed to
adapt the phyCARD-M to your needs. It shows their default positions,
and possible alternative positions and functions. A detailed description
of each solder jumper can be found in the applicable chapter listed in
the table.
Note:
Jumpers not listed should not be changed as they are installed with
regard to the configuration of the phyCARD-M.
e.g.: J1
Figure 5:
e.g.: J10
Typical jumper pad numbering scheme
If manual jumper modification is required please ensure that the board
as well as surrounding components and sockets remain undamaged
while de-soldering. Overheating the board can cause the solder pads to
loosen, rendering the module inoperable. Carefully heat neighboring
connections in pairs. After a few alternations, components can be
removed with the solder-iron tip. Alternatively, a hot air gun can be
used to heat and loosen the bonds.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
17
phyCARD-M [PCA-A-M1-xxx]
Please pay special attention to the "TYPE" column to ensure you are
using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The
jumpers are either 0805 package or 0402 package with a 1/8W or
better power rating.
J2
J9
Figure 6:
18
Jumper locations (top view)
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Jumpers
J21
J13
J22
J4
J1
J3
Figure 7:
J16
Jumper locations (bottom view)
© PHYTEC Messtechnik GmbH 2010
L-750e_2
19
phyCARD-M [PCA-A-M1-xxx]
The jumpers (J = solder jumper) have the following functions:
Jumper Description
J4, J1,
J3
Type
J4, J1 and J3 define the slave addresses (A0 toA2)
of the serial memory U6 on the I2C2 bus. In the
high-nibble of the address, I2C memory devices
have the slave ID 0xA. The low-nibble is build
from A2, A1, A0, and the R/W bit. .
Chapter
0R
(0402)
7.3.1
all 2+3 A0 = 0, A1 = 1, A2= 0, => 0x4 / 0x5 (W/R) are
selected as the low-nibble of the EEPROM's
address
other please refer to Table 11 to find alternative
settings addresses resulting from other combinations of
jumpers J1, J3, and J4
J16
J16 connects pin 7 of the serial memory at U6 to
0R
GND. On many memory devices pin 7
(0402)
enables/disables the activation of a write protect
function.
It is not guaranteed that the standard serial memory
populating the phyCARD-M will have this write
protection function.
Please refer to the corresponding memory data
sheet for more detailed information.
7.3.2
open EEPROM U6 is write protected
closed EEPROM U6 is not write protected
J2
J2 selects, if the fuse voltage VDD_FUSE is
available only if the primary voltage
VDD_3V3_IN is supplied, or if it is also available
when only VBAT is supplied.
0R
(0402)
1+2 Fuse voltage VDD_FUSE is not available if
VBAT is the only voltage source
2+3 Fuse voltage VDD_Fuse is also available when
VBAT is the only voltage source
20
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Jumpers
Jumper Description
Type
J9 selects, if the 2.775V voltage rail is available
only if the primary voltage VDD_3V3_IN is
supplied, or if it is also available when only
VBAT is supplied.
J9
Chapter
0R
(0805)
1+2 2.775V voltage rail is not available if VBAT is
the only voltage source
2+3 2.775V voltage rail is also available when VBAT
is the only voltage source
J13 allows to attach a programming voltage to the 0R
IC Identification Module (IIM) for programming (0402)
and/or overriding identification and control
information stored in on-chip fuse elements.
J13
7.3.2
open VDD_FUSE not connected
closed Only close Jumper when burning of fuses is
required
J21 selects rising, or falling edge strobe for the
LVDS Deserializer at U5 used for the display
connectivity of the phyCARD-M
J21
10k
(0805)
0
1+2 rising edge strobe used for the LVDS camera
signals
2+3 falling edge strobe used for the LVDS camera
signals
J22 selects rising, or falling edge strobe for the
LVDS Transmitter at U4 used for the display
connectivity of the phyCARD-M.
J22
1+2 falling edge strobe used for the LVDS display
signals
10k
(0805)
0
2+3 rising edge strobe used for the LVDS display
signals
Table 4:
Jumper settings
© PHYTEC Messtechnik GmbH 2010
L-750e_2
21
phyCARD-M [PCA-A-M1-xxx]
22
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Power
4
Power
The phyCARD-M operates off of a single power supply voltage.
The following sections of this chapter discuss the primary power pins
on the phyCARD-Connector X2 in detail.
4.1
Primary System Power (VCC_3V3)
The phyCARD-M operates off of a primary voltage supply with a
nominal value of +3.3V. On-board switching regulators generate the
1.375V, 1.5V, 1.8V, 2.775V, and 3.3V voltage supplies required by
the i.MX35 MCU and on-board components from the primary 3.3V
supplied to the SBC.
For proper operation the phyCARD-M must be supplied with a
voltage source of 3.3V ±5 % with 600 mA load at the VCC pins on
the phyCARD-Connector X2.
VDD_3V3_IN:
X2
1A, 2A, 3A, 1B, 2B, 3B
Connect all +3.3V VCC input pins to your power supply and at least
the matching number of GND pins.
Corresponding GND:
X2 4A, 8A, 13A, 4B, 8B, 13B
Please refer to section 2 for information on additional GND Pins
located at the phyCARD-Connector X2.
Caution:
As a general design rule we recommend connecting all GND pins
neighboring signals which are being used in the application circuitry.
For maximum EMI performance all GND pins should be connected to
a solid ground plane.
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phyCARD-M [PCA-A-M1-xxx]
4.2
Standby Voltage (VBAT)
For applications requiring a standby mode a secondary voltage source
of 3.3V can be attached to the phyCARD-M at pin X2B6. This voltage
source is supplying the core and on-chip peripherals of the i.MX35
(e.g. EMI, PLL, etc.), as well as the SDRAM and the EEPROM at U6
while the primary system power (VCC_3V3) is removed. Applications
not requiring a standby mode can connect the VBAT pin to the
primary system power supply (VCC = 3.3V), or can leave it open.
4.3
On-board Voltage Regulator (U1)
The phyCARD-M provides an on-board switching regulator (U1) to
source the five different voltages (1.375V, 1.5V, 1.8V, 2.775V, and
3.3V) required by the processor and on-board components. Figure 8
presents a graphical depiction of the powering scheme.
The switching regulator has two input voltage rails as can be seen in
Figure 8. 3V3 and 3V3 Backup. 3V3 is supplied only from the
primary voltage input pins VDD_3V3_IN of the phyCARD-M,
whereas 3V3 Backup is supplied from the primary voltage input pins
VDD_3V3_IN and the secondary voltage input pin VBAT. The
following list summarizes the relation between the different voltage
rails and the devices on the phyCARD-M:
External voltages: VCC_3V3 and VBAT (optional)
•
VDD_3V3_IN: 3V3
•
VBAT: 3V3 BACKUP Voltage Regulator
Voltage Regulator, Reset Controller
Internally generated voltages: 1V375, 1V5, 1V8 and 2V775
•
1V375 i.MX35 Core power supply
•
1V5
on-chip PLLs
•
1V8
NVCC_EMI of the i.MX35, DDR2 SDRAM
•
2V775 internal I²C-Bus, I2C EEPROM
24
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Power
3V3 Backup *
DC/DC
1,375V
i.MX35 Core
Converter
1,8V
DC/DC
Converter
3V3 **
NVCC_EMI of the i.MX35
DDR2 SDRAM
2,775V
internal I²C-Bus, I²C EEPROM
LDO
1,5V
On-chip PLLs
LDO
*: supplied from VDD_3V3_IN and VBAT
**: supplied from VDD_3V3_IN
MC13892
Figure 8:
4.4
Power Supply Diagram
Supply Voltage for external Logic
The voltage level of the phyCARD's logic circuitry is VDD_3V3
(3.3V) and equals the supply voltage of the phyCARD-M. Thus
connecting external devices to the phyCARD-M does not require any
special precautions. This means that external devices could be
supplied from the same power source as the phyCARD-M.
Nonetheless we recommend to supply external devices with the
voltage (VCC_Logic) brought out at pins X2A5 and X2B5 of the
phyCARD-Connector and to use level shifters supplied with this
voltage at one of the supply rails if you want to keep your application
compatible to other phyCARDs with a different signal level. This
means that use of level shifters supplied with VCC_Logic allows
converting the signals according to the needs on the custom target
hardware independently from the phyCARD mounted. Alternatively
signals can be connected to an open drain circuitry with a pull-up
resistor attached to VCC_Logic.
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phyCARD-M [PCA-A-M1-xxx]
26
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Power Management
5
Power Management
The phyCARD-M was designed to support applications requiring a
power management. Three pins of the X-Arc bus are designated for
this purpose. X_Power_off and X_Suspend_to_RAM are output pins
which can be used to indicate the power status of the phyCARD-M,
whereas X_WKUP is an input pin to apply a wake up signal to the
phyCARD-M.
All three pins lead to GPIOs of the i.MX. Thus their functionality can
be programmed to your needs. In addition the X_WKUP input is
connected to the PWRON2 input of the voltage regulator to allow
implementing a power management by programming the power
management IC.
The following table shows the location of the power management pins
on the phyCARD-Connector and the corresponding GPIOs of the
i.MX35.
Pin #
Signal
X2A48 X_WKUP
I/O SL
I
VDD_3V3_
BACKUP
Description
Wakeup Interrupt Input
(µC port GPIO2_12 (at
U6) and PMIC PWRON2
input)
Suspend to RAM Open
X2B26 X_Suspend_to_RAM OC VDD_3V3_IN Collector Output
(µC port GPIO2_29 (at
V2))
X2B29 X_Power_off
Table 5:
Power Off Open Collector
OC VDD_3V3_IN Output (µC port
GPIO3_10 (at H3))
Power Management Pins
With the two output signals X_Power_off (pin X2B29) and
X_Suspend_to_RAM (pin X2B26) three different power states can be
defined.
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phyCARD-M [PCA-A-M1-xxx]
Power State
Signal
Power On
Standby
Off
X_Suspend_to_RAM High
Low
X
X_Power_off
High
High
Low
VDD_3V3_IN
On
Off
Off
VBAT
X
On
Off
X=don’t care
Table 6:
Power States
Please refer to the chapter "Power Management" in the phyCARD
Design-In Guide for more information about the implementation of
the power management into your design.
Caution:
According to the specification for the phyCARD family writing
custom
software
to
utilize
pins
X_Power_off
and
X_Suspend_to_RAM requires them to be configured as Open
Collector Output.
Use of the power management features of the PMIC at U1 allows for a
higher granularity in control of the power consumption. To implement
power management with the PMIC it can be programmed via an I2C
interface. The MC13892 can be accessed at I2C address 0x10 / 0x11
(write/read). Please refer to the MC13892 User's Guide for more
information.
As a third option jumpers J2 and J9 allow to switch off devices on the
phyCARD-M, if VBAT is the only supply voltage.
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Power Management
Jumper Description
J2
Type
J2 selects, if the fuse voltage VDD_FUSE is
0R
available only if the primary voltage (0402)
VDD_3V3_IN is supplied, or if it is also
available when only VBAT is supplied.
1+2 Fuse voltage VDD_FUSE is not available if
VBAT is the only voltage source
2+3 Fuse voltage VDD_FUSE is also available when
VBAT is the only voltage source
J9
J9 selects, if the 2.775V voltage rail is available
0R
only if the primary voltage VDD_3V3_IN is (0805)
supplied, or if it is also available when only
VBAT is supplied.
1+2 2.775V voltage rail is not available if VBAT is
the only voltage source
2+3 2.775V voltage rail is also available when
VBAT is the only voltage source
Table 7:
Power management jumpers J2 and J9
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System Configuration and Booting
6
System Configuration and Booting
Although most features of the i.MX35 microcontroller are configured
and/or programmed during the initialization routine, other features,
which impact program execution, must be configured prior to
initialization.
The system start-up configuration includes:
• Boot device select configuration (boot type)
• Memory configuration
• USB PHY configuration, etc.
The i.MX35 processor always begins fetching instruction from the
internal bootstrap ROM, sync flash or CS0 space. The operational
system boot mode of the i.MX35 processor is determined by the
configuration of the two external input pins, BMOD[1:0] during the
reset cycle. The settings of these pins control where the system is boot
from. They are accessible via boot pins X_BOOT[1:0] (X2B50 and
X2A50) of the X-Arc bus. This boot mode information is registered
during the system reset.
The following table shows the different boot modes, which can be
selected by configuring the two boot pins.
The standard phyCARD-M module with 128MB NAND Flash comes
with a boot configuration of ‘0001010001’, so the system will boot
from the 8-bit NAND Flash at CS0.
Note:
To conform to the phyCARD specification, BMOD0 is the inverse of
the input level of X_BOOT0.
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phyCARD-M [PCA-A-M1-xxx]
phyCARD
config pins
X_BOOT[1:0]
00
01
10
11 or
unconnected
Table 8:
Boot Mode Boot Mode/ Boot Details
Selection
Device
BMOD[1:0]
01
Startup
Mode for debug and/or
mode
development
purpose
using
JTAG-capable
development tools.
00
Internal
Boot
11
Serial boot Load and execute code,
loader
via serial devices; e.g.
the ATK Toolkit from
Freescale
10
External
Boot from NAND
(direct)
Flash populated on the
Boot
phyCARD-M
Boot Modes of i.MX35 module
Because of pull-up resistors located on the phyCARD-M the default
boot mode is External Boot which allows to boot from NAND Flash,
if the boot pins X_BOOT[1:0] are left open. In other words, to boot
from NAND Flash no further settings at X_BOOT[1:0] are necessary.
To enter other boot modes a low level must be applied to X_BOOT[0]
(X2A50) and/or X_BOOT[1] (X2B50) according to Table 8.
Additional boot configuration settings are obtained either from
programmable eFuses or by contacts sampled at POR. On the
phyCARD-M the boot configuration is set up by 10k pull-up/ pulldown resistors which are tied to the corresponding CSI-Signals. Table
9 lists the additional configuration settings and the default values.
32
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System Configuration and Booting
Signal Name
eFuse
X_CSI_D8
BT_MEM_CTRL[0]
X_CSI_D9
BT_MEM_CTRL[1]
X_CSI_D10
BT_MEM_TYPE[0]
X_CSI_D11
BT_MEM_TYPE[1]
X_CSI_D12
BT_PAGE_SIZE[0]
X_CSI_D13
BT_PAGE_SIZE[1]
X_CSI_D14
BT_ECC_SEL
X_CSI_D15
BT_USB_SRC[0]
X_CSI_HSYNC BT_USB_SRC[1]
X_CSI_VSYNC BT_BUS_WIDTH
Table 9:
Definition Settings
00 WEIM
Boot
01 NAND Flash
memory
10 ATA HDD
control
11 Expansion Device
type
(SD, MMC…)
BT_MEM_CTRL=01:
00 3 address cycles
01 4 address cycles
Boot
10 5 address cycles
memory
11 6 address cycles
type
BT_MEM_CTRL=other:
See i.MX35 Reference
Manual
00 512 bytes
NAND
01 2Kbytes
Flash
page size 10 4Kbytes
11 Reserved
Defines
0 4-bit ECC
4- or 8-bit 1 8-bit ECC
ECC
00 UTMI PHY
USB
01 ULPI PHY
PHY
selection 10 Serial PHY: ATLAS
11 Serial PHY: ISP1301
BT_MEM_CTRL=01:
0 8 bit
1 16 bit
Bus width
BT_MEM_CTRL=other:
See i.MX35 Reference
Manual
Further Boot Configuration Pins 1
For further information please see the i.MX35 Reference Manual.
1
:
Defaults are in bold blue text
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phyCARD-M [PCA-A-M1-xxx]
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System Memory
7
System Memory
The phyCARD-M provides three types of on-board memory:
• DDR2-SDRAM:
• NAND Flash:
• I²C-EEPROM:
64MByte
(up to 256MByte)
128MByte
(up to 1GByte)
4KB
(up to 32KByte)
The following sections of this chapter detail each memory type used
on the phyCARD-M.
7.1
DDR2-SDRAM (U8 - U11)
The RAM memory of the phyCARD-M in comprised of up to four 16bit wide DDR2-SDRAM chips at U8 - U11. They are connected to the
special SDRAM interface of the i.MX35 processor, configured for 32bit access, and operating at the maximum frequency of 133MHz.
The phyCARD-M can use one, or both of the DDR2-SDRAM banks
on the i.MX35 depending on the SDRAM population density options.
Each RAM bank is comprised of two 16-bit wide DDR2-SDRAM
chips, configured for 32-bit access, and operating at 133MHz. In
lower density configurations, U9 and U11 populate the module and
are accessed via SDRAM memory bank 0 using chip select signal
/CSD0 starting at 0x8000 0000. In higher density configurations, U8
and U10 are also populated and are accessed via SDRAM memory
bank 1 using chip select signal /CSD1 starting at 0x9000 0000.
Typically the DDR2-SDRAM initialization is performed by a boot
loader or operating system following a power-on reset and must not be
changed at a later point by any application code. When writing custom
code independent of an operating system or boot loader, SDRAM
must be initialized by accessing the appropriate SDRAM
configuration registers on the i.MX35 controller. Refer to the i.MX35
Reference Manual for accessing and configuring these registers.
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phyCARD-M [PCA-A-M1-xxx]
7.2
NAND Flash Memory (U13)
Use of Flash as non-volatile memory on the phyCARD-M provides an
easily reprogrammable means of code storage. The following Flash
devices can be used on the phyCARD-M:
Manufacturer
NAND Flash P/N
Samsung
K9F1G08UOC
Table 10:
Density
(MByte)
128
Compatible NAND Flash devices
Additionally, any parts that are footprint (48-TSOP) and functionally
compatible with the NAND Flash devices listed above may also be
used with the phyCARD-M.
These Flash devices are programmable with 3.3 V. No dedicated
programming voltage is required.
As of the printing of this manual these NAND Flash devices generally
have a life expectancy of at least 100,000 erase/program cycles and a
data retention rate of 10 years.
The NAND Flash memory is connected to the NAND Flash Controller
(NFC).
7.3
I²C EEPROM (U6)
The phyCARD-M is populated with an ST 24W32C 1 non-volatile
4KByte EEPROM with an I²C interface at U6. This memory can be
used to store configuration data or other general purpose data. This
device is accessed through I²C port 1 on the i.MX35. The control
registers for I²C port 1 are mapped between addresses 0x43F8 0000
and 0x43F8 3FFF. Please see the i.MX35 Reference Manual for
detailed information on the registers.
1
:
36
See the manufacturer’s data sheet for interfacing and operation.
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System Memory
Three solder jumpers are provided to set the lower address bits: J3, J4
and J5. Refer to section 7.3.1 for details on setting these jumpers.
Write protection to the device is accomplished via jumper J2. Refer to
section 7.3.2 for further details on setting this jumper.
7.3.1
Setting the EEPROM Lower Address Bits (J1, J3, J4)
The 4KB I²C EEPROM populating U6 on the phyCARD-M module
has the capability of configuring the lower address bits A0, A1, and
A2. The four upper address bits of the device are fixed at ‘1010’ (see
ST 24W32C data sheet). The remaining three lower address bits of the
seven bit I²C device address are configurable using jumpers J1, J3 and
J4. J4 sets address bit A0, J1 address bit A1, and J3 address bit A2.
Table 11 below shows the resulting seven bit I²C device address for
the eight possible jumper configurations.
U6 I²C Device Address
1010 010
1010 011
1010 000
1010 001
1010 110
1010 111
1010 100
1010 101
Table 11:
1
:
J3
2+3
2+3
2+3
2+3
1+2
1+2
1+2
1+2
J1
2+3
2+3
1+2
1+2
2+3
2+3
1+2
1+2
J4
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
U6 EEPROM I²C address via J1, J3, and J4 1
Defaults are in bold blue text
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phyCARD-M [PCA-A-M1-xxx]
7.3.2
EEPROM Write Protection Control (J16)
Jumper J16 controls write access to the EEPROM (U6) device.
Closing this jumper allows write access to the device, while removing
this jumper will cause the EEPROM to enter write protect mode,
thereby disabling write access to the device.
The following configurations are possible:
EEPROM Write Protection State J16
Write access allowed
closed
Write protected
open
Table 12:
7.4
EEPROM write protection states via J16 1
Memory Model
There is no special address decoding device on the phyCARD-M,
which means that the memory model is given according to the
memory mapping of the i.MX35. Please refer to the i.MX35 Reference
Manual for more information on the memory mapping.
1
:
38
Defaults are in bold blue text
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SD / MMC Card Interfaces
8
SD / MMC Card Interfaces
The X-Arc bus features an SD / MMC Card interface. On the
phyCARD-M the interface signals extend from the controllers first
Enhanced Secure Digital Host Controller (SDIO1) to the phyCARDConnector. Table 13 shows the location of the different interface
signals on the phyCARD-Connector. The Secure Digital Host
Controller is fully compatible with the SD Memory Card Specification
2.0 and SD I/O Specification 2.0 with 1 and 4 channel(s) and supports
data rates from 25 Mbps to 200 Mbps (refer to the i.MX35 Reference
Manual for more information).
Due to compatibility reasons a card detect signal (X_SDIO_CD) is
added to the SD / MMC Card Interface. This signal connects to port
GPIO3_1 at pin V1 of the i.MX35.
Pin #
Signal
I/O
SL
X2A31 X_SD1_DATA0 I/O
VDD_3V3
X2A32 X_SD1_DATA2 I/O
VDD_3V3
X2A33 X_SD1_CLK
VDD_3V3
O
X2B31 X_SD1_DATA1 I/O
VDD_3V3
X2B32 X_SD1_DATA3 I/O
VDD_3V3
X2B33 X_SD1_CMD
O
VDD_3V3
X2B46 X_SDIO_CD
I
VDD_3V3
Table 13:
Description
SD/MMC Data line both
in 1- and 4-bit mode
SD/MMC Data line both
in 1- and 4-bit mode
SD/MMC Clock for
MMC/SD/SDIO
SD/MMC Data line both
in 1- and 4-bit mode
SD/MMC Data line both
in 1- and 4-bit mode
SD/MMC Command for
MMC/SD/SDIO
SD/MMC Card Detect
for MMC/SD/SDIO
Location of SD/ MMC Card interface signals
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phyCARD-M [PCA-A-M1-xxx]
Note:
The signal level of the SD / MMC card interface is 3.3V. Thus
integration of an SD / MMC card slot on custom target hardware does
not require any special precautions. Nonetheless use of level shifters
supplied with the voltage at pins X2A5 and X2B5 at one of the supply
rails is necessary if you want to keep your application compatible to
other phyCARDs with a different signal level.
Please refer to the chapter "SD / MMC" in the phyCARD Design-In
Guide for more information about connecting an SD / MMC Card slot
to the phyCARD-M.
40
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Serial Interfaces
9
Serial Interfaces
The phyCARD-M provides seven serial interfaces some of which are
equipped with a transceiver to allow direct connection to external
devices:
1.
2.
3.
4.
5.
6.
7.
High speed UART (TTL, derived from UART1 of the i.MX35)
with up to 4.125Mbit/s and hardware flow control (RTS and CTS
signals)
High speed USB OTG interface extend from the i.MX35 USB
OTG interface
Full speed USB HOST interface using the i.MX35's internal USB
Host interface, or optional high speed USB HOST interface
derived from an external USB HOST controller at U16.
Auto-MDIX enabled 10/100 Ethernet PHY supporting the
i.MX35 Ethernet MAC
I2C interface (derived from third I2C port of the i.MX35)
Serial Peripheral Interface (SPI) interface (extended from the first
SPI module of the i.MX35)
Synchronous Serial Interface (SSI) with AC97 support
(originating from the synchronous serial interface of the i.MX35)
The following sections of this chapter detail each of these serial
interfaces and any applicable configuration jumpers.
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phyCARD-M [PCA-A-M1-xxx]
Caution:
The signal level of some of the serial interfaces is VDD_3V3_IN,
which is 3.3V and therefore identical with the voltage level of the
primary supply voltage of the phyCARD-M. Therefore special
precautions are not necessary when connecting to these interfaces.
Nonetheless if you want to keep your application compatible with
other phyCARDs and thus being able to change your application's
processing power, level shifters supplied with the output voltage at
pins X2A5 and X2B5 at one of the supply rails should be used when
connecting these interfaces to external devices. Unlike on the
phyCARD-M the voltage level of interface signals is different from
the primary supply voltage on other phyCARDs. Please pay special
attention to the Signal Level (SL) column in the following tables.
Please refer to the phyCARD Design-In Guide for more information
about using the serial interfaces of the phyCARD-M in customer
applications.
9.1
Universal Asynchronous Interface
The phyCARD-M provides a high speed universal asynchronous
interface with up to 4 Mbit/s and hardware flow control (RTS and
CTS signals). The following table shows the location of the signals on
the phyCARD- Connector.
Pin #
Signal
I/O SL
X2A39 X_UART1_TXD O
VDD_3V3
X2A40 X_UART1_RTS O
VDD_3V3
X2B39 X_UART1_RXD I
VDD_3V3
X2B40 X_UART1_CTS I
VDD_3V3
Table 14:
42
Description
Serial transmit signal
UART 1
Request to send UART 1
Serial data receive signal
UART 1
Clear to send UART 1
Location of the UART signals
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Serial Interfaces
The signals extend from UART1 of the i.MX35 directly to the
phyCARD-Connector without conversion to RS-232 level. External
RS-232 transceivers must be attached by the user if RS-232 levels are
required.
9.2
USB-OTG Interface
The i.MX35 features an USB 2.0 OTG (up to 480 Mbps) controller
with internal high-speed OTG PHY. The signals of the high-speed
OTG PHY extend directly to the phyCARD-Connector X2. An
external USB Standard-A (for USB host), USB Standard-B (for USB
device), or USB mini-AB (for USB OTG) connector is all that is
needed to interface the phyCARD-M USB OTG functionality. The
applicable interface signals can be found on the phyCARD-Connector
as shown in Table 15.
Pin #
Description
USB-OTG Power
X2A23 X_USBOTG_PWR O VDD_3V3 switch output open
drain
USB-OTG over
X2A24 X_USBOTG_OC
I
VDD_3V3
current input signal
X2A26 X_USBPHY1_VBUS I
5V
USB VBUS Voltage
USB transceiver
X2A27 X_USBPHY1_DM
I/O
cable interface, DUSB transceiver
X2A28 X_USBPHY1_DP
I/O
cable interface, D+
USB on the go
X2A29 X_USBPHY1_UID I
transceiver cable ID
resistor connection
Table 15:
Signal
I/O SL
Location of the USB-OTG signals
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phyCARD-M [PCA-A-M1-xxx]
9.3
USB-Host Interface
The i.MX35 has an internal USB 2.0 Host with internal full-speed
PHY. The phyCARD-M is optionally populated with an NXP
ISP1760 High-Speed USB Host controller at U16 to also allow highspeed USB HOST connectivity. Jumpers J18 - J20 and J25 select
either the internal PHY of the i.MX35 or the external USB HOST
controller at U16. They are installed prior to delivery and must not be
changed. An external USB Standard-A (for USB host connector is all
that is needed to interface the phyCARD-M USB Host functionality.
The applicable interface signals (D+/D-/ /PSW/FAULT) can be found
on the phyCARD-Connector.
Pin #
Description
USB-HOST Power
X2B23 X_USB_PRW2 O VDD_3V3
switch output open drain
USB-HOST over current
X2B24 X_USB_OC2
I
VDD_3V3
input signal
USB HOST transceiver
X2B27 X_USB_DM2 I/O
cable interface, DUSB HOST transceiver
X2B28 X_USB_DP2
I/O
cable interface, D+
Table 16:
44
Signal
I/O SL
Location of the USB-Host signals
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Serial Interfaces
9.4
Ethernet Interface
Connection of the phyCARD-M to the world wide web or a local area
network (LAN) is possible using the integrated FEC (Fast Ethernet
Controller) of the i.MX35. The FEC operates with a data transmission
speed of 10 or 100 Mbit/s.
9.4.1
PHY Physical Layer Transceiver (U7)
With a physical layer transceiver mounted at U7 the phyCARD-M has
been designed for use in 10Base-T and 100Base-T networks. The
10/100Base-T interface with its LED signals extends to phyCARDConnector X2.
Pin #
Signal
I/O
X2A19 X_ETH_SPEED O
SL
VDD_3V3
X2A20 X_ETH_TX+
O (I) V DD_3V3
X2A21 X_ETH_TX-
O (I) V DD_3V3
X2B19 X_ETH_LINK
O
X2B20 X_ETH_RX+
I (O) V DD_3V3
X2B21 X_ETH_RX-
I (O) V DD_3V3
Table 17:
V DD_3V3
Description
Ethernet Speed
Indicator (Open Drain)
Transmit positive output
(normal)
Receive positive input
(reversed)
Transmit negative
output (normal)
Receive negative input
(reversed)
Ethernet Speed
Indicator (Open Drain)
Receive positive input
(normal)
Transmit positive output
(reversed)
Receive negative input
(normal)
Transmit negative
output (reversed)
Location of the Ethernet signals
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phyCARD-M [PCA-A-M1-xxx]
The Ethernet PHY provides MII/RMII/SMII interfaces to transmit and
receive data. In addition the PHY also supports HP Auto-MDIX
technology, eliminating the need for the consideration of a direct
connect LAN cable, or a cross-over patch cable. It detects the TX and
RX pins of the connected device and automatically configures the
PHY TX and RX pins accordingly. The Ethernet PHY also features
LinkMD cable diagnostics, which allows detection of common cabling
plant problems such as open and short circuits.
The physical memory area for the Fast Ethernet controller is defined
in Table 18.
Address
0x5003 8000 – 0x5003 81FF
0x5003 8200 – 0x5003 83FF
Table 18:
Function
Control/Status Registers
MIB Block Counters
Fast Ethernet controller memory map
In order to connect the module to an existing 10/100Base-T network
some external circuitry is required. The required 49.9 Ohm +/-1%
termination resistors on the analog signals (ETH_RX±, ETH_TX±)
are already populated on the module. Connection to an external
Ethernet magnetics should be done using very short signal traces. The
TPI+/TPI- and TPO+/TPO- signals should be routed as 100 Ohm
differential pairs. The same applies for the signal lines after the
transformer circuit. The carrier board layout should avoid any other
signal lines crossing the Ethernet signals.
An example for the external circuitry is shown in the phyCARD's
Design Guide.
If you are using the applicable Carrier Board for the phyCARD-M
(part number PBA-A-01), the external circuitry mentioned above is
already integrated on the board (refer to section 17.3.4).
46
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Serial Interfaces
Caution!
Please see the datasheet of the Ethernet PHY as well as the
phyCARD's Design Guide when designing the Ethernet transformer
circuitry.
9.4.2
MAC Address
In a computer network such as a local area network (LAN), the MAC
(Media Access Control) address is a unique computer hardware
number. For a connection to the Internet, a table is used to convert the
assigned IP number to the hardware's MAC address.
In order to guarantee that the MAC address is unique, all addresses are
managed in a central location. PHYTEC has acquired a pool of MAC
addresses. The MAC address of the phyCARD-M is located on the bar
code sticker attached to the module. This number is a 12-digit HEX
value.
9.5
I2C Interface
The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional
serial bus that provides a simple and efficient method for data
exchange among devices. The i.MX35 contains three identical and
independent I2C modules. The interface of the third module is
available on the phyCARD-Connector., whereas the first module
connects to the on-board EEPROM (refer to section 7.3) and the
Power Management IC at U1 (refer to section 5). The following table
lists the I2C port on the phyCARD-Connector:
Pin # Signal
X2A17 X_I2C3_SCL
X2B17 X_I2C3_SDA
Table 19:
I/O SL
O VDD_3V3
I/O VDD_3V3
Description
I2C Clock Output
I2C Data
I2C Interface Signal Location
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phyCARD-M [PCA-A-M1-xxx]
9.6
SPI Interface
The Serial Peripheral Interface (SPI) interface is a six-wire,
bidirectional serial bus that provides a simple and efficient method for
data exchange among devices. The i.MX35 contains two SPI modules.
The interface signals of the first module (CSPI1) are made available
on the phyCARD-Connector. This module is Master/Slave
configurable. Due to the specification of the X-Arc bus, only two of
the three chips-selects are available on the phyCARD-Connector. The
following table lists the SPI signals on the phyCARD-Connector:
Pin # Signal
X2A35 X_CSPI1_SS0
X2B35 X_CSPI1_SS1
I/O SL
Description
O
VDD_3V3 SPI 1 Chip select 0
O
VDD_3V3 SPI 1 Chip select 1
SPI 1 SPI data ready
X2A36 X_CSPI1_SPI_RDY O
VDD_3V3
in Master mode
X2A37 X_CSPI1_SCLK
O
VDD_3V3 SPI 1 clock
SPI 1 Master data
X2B36 X_CSPI1_MOSI
I/O VDD_3V3
out; slave data in
SPI 1 Master data in;
X2B37 X_CSPI1_MISO
I/O VDD_3V3
slave data out
Table 20:
9.7
SPI Interface Signal Location
Synchronous Serial Interface (SSI)
The Synchronous Serial Interface (SSI) interface of the phyCARD-M
is a full-duplex, serial port that allows to communicate with a variety
of serial devices, such as standard codecs, digital signal processors
(DSPs), microprocessors, peripherals, and popular industry audio
codecs that implement the inter-IC sound bus standard (I2S) and Intel
AC'97 standard.
With reference to the X-Arc bus specification, the main purpose of
this interface is to connect to an external codec, such as AC'97. In
AC'97 mode the clock and the frame sync signal are synchronous for
the receive and transmit sections of the i.MX35 SSI module. Thus
48
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Serial Interfaces
only four signals extend from the i.MX35 Digital Audio MUX
(AUDMUX) to the phyCARD-Connector (X_STXD4, X_SRXD4,
X_SCK4, X_STXFS4). X_AC97_INT and X_AC97_RESET are two
additional pins assisting the functionality of this interface.
X_AC97_INT is used as input and output. As output it signals which
codec is supported by the phyCARD. Use of this pin as an input
enables to attach an external interrupt to port GPIO2_3 (at T13).
X_AC97_RESET is connected to port GPIO3_2 (at R5) of the i.MX35
allowing to perform a software reset for the device attached to the
interface. Please also read the phyCARD Design-In Guide for more
information about how to use the AC97 interface.
Pin # Signal
X2A42 X_AC97_INT
X2A43 X_STXD4
X2A44
X2B42
X2B43
X2B44
Table 21:
X_SRXD4
X_SCK4
X_STXFS4
X_AC97_RESET
I/O SL
Description
I/O VDD_3V3 AC97 Interrupt Input
O VDD_3V3 AC97 Transmit
Output
I
VDD_3V3 AC97 Receive Input
I
VDD_3V3 AC97 Clock
O VDD_3V3 AC97 SYNC
O VDD_3V3 AC97 Reset
SSI Interface Signal Location
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phyCARD-M [PCA-A-M1-xxx]
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General Purpose I/Os
10 General Purpose I/Os
The X-Arc bus provides 3 GPIO / IRQ signals. Table 22 shows the
location of the GPIO / IRQ pins on the phyCARD-Connector, as well
as the corresponding ports of the i.MX35.
Pin #
Description
GPIO0 connected to µC
X2A46 X_GPIO2_7 I/O VDD_3V3
port GPIO2_7 (at T7)
GPIO2 connected to µC
X2A47 X_GPIO1_1 I/O VDD_3V3
port GPIO1_1 (at L16)
GPIO1 connected to µC
X2B47 X_GPIO2_23 I/O VDD_3V3
port GPIO2_23 (at V3)
Table 22:
Signal
I/O SL
Location of GPIO and IRQ pins
As can be seen in the table above the voltage level is VDD_3V3,
which is 3.3V and equals the supply voltage of the phyCARD-M.
Thus connecting external devices to the phyCARD-M does not require
any special precautions. This means that external devices could be
supplied from the same power source as the phyCARD-M.
Nonetheless we recommend to supply external devices with the
voltage (VCC_Logic) brought out at pins X2A5 and X2B5 of the
phyCARD-Connector if you want to keep your application compatible
to other phyCARDs with a different signal level (refer to section 4.4).
Alternatively an open drain circuit with a pull-up resistor attached to
VCC_Logic can be connected to the GPIOs of the phyCARD-M.
Please refer to the chapter "GPIOs" in the phyCARD Design-In Guide
for more information about how to integrate the GPIO pins in your
design.
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phyCARD-M [PCA-A-M1-xxx]
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Debug Interfaces
11 Debug Interface (X1)
The phyCARD-M is equipped with a JTAG interface for downloading
program code into the external flash, internal controller RAM or for
debugging programs currently executing. The JTAG interface extends
to a 2.0 mm pitch pin header at X1 on the edge of the module PCB.
Figure 9 and show the position of the debug interface (JTAG
connector X1) on the phyCARD-M module.
20
X1
2
Figure 9:
JTAG interface at X1 (top view)
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phyCARD-M [PCA-A-M1-xxx]
X1
19
1
Figure 10:
JTAG interface at X1 (bottom view)
Pin 1 of the JTAG connector X1 is on the connector side of the
module. Pin 2 of the JTAG connector is on the controller side of the
module.
Note:
The JTAG connector X1 only populates phyCARD-M modules with
order code PCA-A-M1-D. JTAG connector X1 is not populated on
phyCARD modules with order code PCA-A-M1. We recommend
integration of a standard (2 mm pitch) pin header connector in the user
target circuitry to allow easy program updates via the JTAG interface.
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Debug Interfaces
See the following table for details on the JTAG signal pin assignment.
Signal
VSUPPLY
(VDD_3V3)
Pin Row*
A
B
2
1
Signal
VTref (VDD_3V3 via 100
Ohm)
GND
4
3
X_CPU_TRST
GND
GND
GND
GND
GND
6
8
10
12
14
5
7
9
11
13
X_CPU_TDI
X_CPU_TMS
X_CPU_TCK
X_CPU_RTCK
X_CPU_TDO
GND
16
15
X_RESET_MCU
GND
18
17
X_CPU_DE
GND
20
19
J_DBGACK (10k Ohm pulldown)
Table 23:
JTAG connector X1 signal assignment
*Note: Row A is on the controller side of the module and row B is on
the connector side of the module
PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for
connecting the phyCARD-M to a standard emulator. The JTAGEmulator adapter extends the signals of the module's JTAG connector
to a standard ARM connector with 2 mm pin pitch. The JA-002
therefore functions as an adapter for connecting the module's nonARM-compatible JTAG connector X1 to standard Emulator
connectors.
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phyCARD-M [PCA-A-M1-xxx]
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LVDS Display Interface
12 LVDS Display Interface
The phyCARD-M uses a DS90C383B 4-Channel 24-Bit LVDS
Transmitter (U4) to generate LVDS-Signals from the parallel TTL
Display Interface. Thus you can connect a LVDS-Display to the
phyCARD-M. The location of the applicable interface signals
(X_TXOUT1-3+/X_TXOUT1-3-/X_TXCLK+/TXCLK-) can be
found in the table below.
Pin #
X2A9
X2A10
X2A11
X2A12
X2A14
X2A15
X2B9
X2B10
X2B11
X2B12
Table 24:
Signal
X_TXOUT0+
X_TXOUT0X_TXOUT2+
X_TXOUT2X_TXCLKOUT+
X_TXCLKOUTX_TXOUT1+
X_TXOUT1X_TXOUT3+
X_TXOUT3-
I/O
O
O
O
O
O
O
O
O
O
O
SL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Description
LVDS chanel 0 pos. output
LVDS chanel 0 neg. output
LVDS chanel 2 pos. output
LVDS chanel 2 neg. output
LVDS clock pos. output
LVDS clock neg. output
LVDS chanel 1 pos. output
LVDS chanel 1 neg. output
LVDS chanel 3 pos. output
LVDS chanel 3 neg. output
Display Interface Signal Location
To assists the implementation of a power managment the LVDS
Transmitter's PWR_DWN input is connected to GPIO2_24 at pin Y2
of the i.MX35. Therefore the LVDS Transmitter can be turned off by
software.
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phyCARD-M [PCA-A-M1-xxx]
12.1 Signal configuration (J22)
J22 selects rising, or falling edge strobe for the LVDS Transmitter at
U4 used for the display connectivity of the phyCARD-M.
Position Description
1+2
2+3
Table 25:
Type
falling edge strobe used for the LVDS display 10k (0805)
signals
rising edge strobe used for the LVDS
display signals
LVDS signal configuration J22
12.2 LVDS Display Interface pixel mapping
The phyCARD specification defines the pixel mapping of the LVDS
display interface. The pixel mapping equates to the OpenLDI
respectively Intel 24.0 standard. Thus you can connect 18-bit as well
as 24-bit LVDS displays to the phyCARD. Table 26 and Table 27
show the recommended pixel mapping of the LVDS display. For
further information please see the phyCARD Design Guide.
Note:
Make sure that the LVDS display you want to use provides the same
pin mapping as the phyCARD. Normally this is only important for 24bit LVDS displays because due to the organization of the LVDS pixel
mapping all common 18-bit LVDS displays should work.
18-bit LVDS Display
1
2
CLK 1
1
A0
G0
R5
A1
B1
B0
A2
DE
VSYNC
A3
0
0
Table 26:
58
3
0
R4
G5
HSYNC
0
4
0
R3
G4
B5
0
5
0
R2
G3
B4
0
6
1
R1
G2
B3
0
7
1
R0
G1
B2
0
Pixel mapping of 18-bit LVDS display interface
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LVDS Display Interface
24-bit LVDS Display
1
2
CLK 1
1
A0
G2
R7
A1
B3
B2
A2
DE
VSYNC
A3
0
B1
Table 27:
3
0
R6
G7
HSYNC
B0
4
0
R5
G6
B7
G1
5
0
R4
G5
B6
G0
6
1
R3
G4
B5
R1
7
1
R2
G3
B4
R0
Pixel mapping of 24-bit LVDS display interface
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phyCARD-M [PCA-A-M1-xxx]
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LVDS Camera Interface
13 LVDS Camera Interface
The phyCARD-M uses a DS92LV1212A 1-channel 10-Bit LVDS
Random Lock Deserializer (U5) to receive LVDS-Signals from a
LVDS Camera Interface. The LVDS Deserializer converts the LVDS
signal to a 10-bit wide parallel data bus and separate clock which can
be used as inputs for the i.MX35 Camera Sensor Interface. The 10-bit
wide data bus consists of 8 color information bits and 2 sync bits
(HSYNC/VSYNC).
The following table shows the location of the applicable
interface signals (X_CSI_MCLK, X_LOCK, X_RXIN+, X_RXIN-)
on the phyCARD-Connector.
Pin #
Signal
X2A16 X_CSI_MCLK
X2B14 X_RXIN+
X2B15 X_RXINX2B16 X_LOCK
Table 28:
I/O SL
Description
Clock Output for
O VDD_3V3_IN
Camera Interface
LVDS Receive
O LVDS
positive Input for
Camera
LVDS Receive
O LVDS
negative Input for
Camera
Lock Output for
O VDD_3V3_IN
Camera Interface
Camera Interface Signal Location
To assists the implementation of a power managment the
Deserializer's REN input is connected to GPIO2_2 at pin V13 of the
i.MX35. Therefore the LVDS Deserializer can be turned off by
software.
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phyCARD-M [PCA-A-M1-xxx]
13.1 Signal configuration (J21)
J21 selects rising, or falling edge strobe for the LVDS Deserializer at
U5 used for the display connectivity of the phyCARD-M.
Position Description
Type
1+2
rising edge strobe used for the LVDS camera 10k
(0805)
signals
2+3
falling edge strobe used for the LVDS camera
signals
Table 29:
62
LVDS signal configuration J21
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Technical Specifications
14 Technical Specifications
4mm
The physical dimensions of the phyCARD-M are represented in
Figure 11. The module's profile is max. 11,4 mm thick, with a
maximum component height of 5.0 mm on the bottom (connector)
side of the PCB and approximately 5.0 mm on the top
(microcontroller) side. The board itself is approximately 1.4 mm thick.
60mm
52mm
4mm
Figure 11:
52mm
60mm
D2.7mm
phyCARD-M
Physical dimensions
Note:
To facilitate the integration of the phyCARD-M into your design, the
footprint of the phyCARD-M is available for download (see section
16.1).
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phyCARD-M [PCA-A-M1-xxx]
Additional specifications:
Dimensions:
Weight:
Storage temperature:
Operating temperature:
Humidity:
Operating voltage:
Power consumption:
VCC 3.3 V/300mA typical
60 mm x 60 mm
approximately 16 g with all
optional components mounted on
the circuit board
-40°C to +125°C
0°C to +70°C (commercial)
-20°C to +85°C (industrial)
95 % r.F. not condensed
VCC 3.3V
Max. 1.2 watts
Conditions:
VCC = 3.3 V, VBAT = 0 V,
128MB DDR2-RAM,
128MB
NAND Flash, Ethernet, 400 MHz
CPU frequency at 20°C
These specifications describe the standard configuration of the
phyCARD-M as of the printing of this manual.
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Technical Specifications
Connectors on the phyCARD:
Manufacturer
Number of pins per contact rows
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
52885-1074 (receptacle)
Two different heights are offered for the receptacle sockets that
correspond to the connectors populating the underside of the
phyCARD-M. The given connector height indicates the distance
between the two connected PCBs when the module is mounted on the
corresponding carrier board. In order to get the exact spacing, the
maximum component height (2.5 mm) on the bottom side of the
phyCARD must be subtracted.
Component height 6 mm
Manufacturer
Number of pins per contact row
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
55091-1075/1074 (header)
Component height 10 mm
Manufacturer
Number of pins per contact row
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
53553-1079 (header)
Please refer to the corresponding data sheets and mechanical
specifications provided by Molex (www.molex.com).
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phyCARD-M [PCA-A-M1-xxx]
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Component Placement Diagram
15 Component Placement Diagram
J10
C173
X5
U13
R70
R80
C36
R82
U7
C150
C149
RN3
R81
C42
R60
R31
C127
20
R42
C182
C170 C23
U3
R64
R63
TP3
J5
XT3
X1
R84
TP4
U10
C184
R38
R39
R113
R79
C181
TP2
R73
R74
C24
L5
L8
U9
R77
C174
C25
C168
R78
C183
C44
X6
R26
XT4
R61 R32
C128
J17
J11
J12
C48
TP5
C43
R59
R30
C41
R25
J6
J25
C37
C111
L9
C6
R43
TP7
C13
C10
R49 C11
U1
L2
C59
C39
C46
U11
C160
J7
R54
XT1
C159
Q1
C9
R33
C34
D3
L1
J2
X3
R62
C47
C55
D2
2
C14
C12 C141
TP6
Figure 12:
U8
C185
C64
C171
XT2
C169
D4
R5 C153 C30
C19
C29
R117 C172
C5
D1
X4
J9
phyCARD-M component placement (top view)
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67
C217
R119
C3
C1
TP10
68
R51
U2
R52
C17
C82
C70
C50
Q10
C144
R122
TP13
C88
R114
R57
J4
J1
J3
Q6
C122
C71
TP9
TP11
U6
C178
Q3
Q4
R10
C73
R89
C186
C40
Q5
TP16
J16
C72
C74
C175
C187
R9 R34
C148 C142
C91
C22
R96
C194
C110 C33
C31
C196
L4
R50
C2
Q11
R76
R71
R126
C61
RN2
C56
R72
C121
C123
C85
C179
C75
C126
J27
R53
C89
C53
R48
R2
C97
R35
C78
C218
R3
C162
C156
L3
C114
C7
C4
C164
C161
C151
R83
C167 C166 R65
C163 C165
R85
C8
C60
R46
C139
C57
TP1
J22
C118
C147
Q2
C87
TP15
R40
R44
J8
U4
L6
TP14
R37
C54
R1
C45
R124
C138
U15
C96
L7
RN1
R55
C77
J20 J13
C58
C65
C177
C67
C49
J19
X1
C81
R97
J14
J15
C112 C133
J18
U12
Q7
C69
C193
R95
C66
R41
U17
C68
C27 C102
C94
R93
C125
C191
C108
R94
C124 C113
C192
C120
C189
C100
R91
C63
C119
C188
C98
R90
R92
C190 C157
L10
R29
R8
C140
R27
R11 TP12
C103
R14
C35
R16
R18
C210 C20 R36
R20
R22
C146
R24
R115
R116
R58
U14
C145
C135
C83
C84
R47
R6
R28
R7
R12
R13
R15
R17
R19
R21
R23
Figure 13:
R118
C195
C197
R101
C32
R45 R4
C176
C80
C152
J26
R66
R67
R87
J21
R125
Q9
C211
U5
R121 R123
C21 TP8
R102
C201 C208 R108 C26 R107
C95
C180
C93
C203 C216 C206
R106 C207
C158
C90
C130
R100
1B 1A
R120
Q8
C92
XT5
C15 C18
R56 R68
C16
C132 C86
R69 C38
C136 C107 C116 C51
C52
R75 C137
C101
C62 C129
C154
R88
C99 C109 C106
C79 C155
R86
C134
C117 C131
C105 C104
C115
C28 C209 C205
C213
U16
C212
X2
C214
C198
C199
C200
R109 C215 R111 R105
1
R110
R104
R103
R98
R99
C202
19
C204
phyCARD-M [PCA-A-M1-xxx]
C143
C76
R112
phyCARD-M component placement (bottom view)
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Hints for Integrating and Handling
16 Hints for Integrating and Handling the phyCARD-M
16.1 Integrating the phyCARD-M
Besides this hardware manual much information is available to
facilitate the integration of the phyCARD-M into customer
applications.
1.
2.
3.
4.
5.
the design of the stamdard phyBASE Carrier Board can be used
as a reference for any customer application
many answers to common questions can be found at
or
http://www.phytec.de/de/support/faq/faq-phycard-m.html,
http://www.phytec.eu/europe/support/faq/faq-phycard-m.html.
a Design-In Guide can be downloaded from the same web side. It
provides recommendations as to development of customized
Carrier Board target hardware in which the phyCARD-M (and
other phyCARDs) can be deployed.
the link "Carrier Board" within the category Dimensional
Drawing leads to the layout data as shown in . It is available in
different file formats.
different support packages are available to support you in all
stages of your embedded development. Please visite
or
http://www.phytec.de/de/support/support-pakete.html,
http://www.phytec.eu/europe/support/support-packages.html, or
contact our sales team for more details.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
109
110
20mm
107
108
20mm
105
106
100mm
80mm
60mm
52mm
D2.7mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D
101
102
103
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
104
9.19mm
9.2mm
4mm
2mm
2.1mm
10.44mm
10.45mm
D0.9mm
0.635mm
D0.7mm
31.11mm
L-750e_2
© PHYTEC Messtechnik GmbH 2010
70
Footprint of the phyCARD-M
Figure 14:
7.23mm
Ref Des
7.24mm
4mm
60mm
52mm
alle Maße mit Toleranz von +/- 0,1mm
Hints for Integrating and Handling
16.2 Handling the phyCARD-M
• Modifications on the phyCARD Module
Removal of various components, such as the microcontroller and the
standard quartz, is not advisable given the compact nature of the
module. Should this nonetheless be necessary, please ensure that the
board as well as surrounding components and sockets remain
undamaged while de-soldering. Overheating the board can cause the
solder pads to loosen, rendering the module inoperable. Carefully heat
neighboring connections in pairs. After a few alternations,
components can be removed with the solder-iron tip. Alternatively, a
hot air gun can be used to heat and loosen the bonds.
Caution!
If any modifications to the module are performed, regardless of their
nature, the manufacturer guarantee is voided.
• Integrating the phyCARD into a Target Application
Successful integration in user target circuitry greatly depends on the
adherence to the layout design rules for the GND connections of the
phyCARD module. For best results we recommend using a carrier
board design with a full GND layer. It is important to make sure that
the GND pins that have neighboring signals which are used in the
application circuitry are connected. Just for the power supply of the
module at least 8 GND pins that are located right next to the VCC pins
must be connected
Note!
Please refer to the phyCARD Design-In Guide (LAN-051) for
additional information, layout recommendations and example
circuitry.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
72
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
17 The phyCARD-M on the phyBase
PHYTEC phyBASE Boards are fully equipped with all mechanical
and electrical components necessary for the speedy and secure start-up
and subsequent communication to and programming of applicable
PHYTEC Single Board Computer (SBC) modules. phyBASE Boards
are designed for evaluation, testing and prototyping of PHYTEC
Single Board Computers in laboratory environments prior to their use
in customer designed applications.
The phyBASE supports the following features for the phyCARD-M
modules:
• Power supply circuits to supply the modules and the peripheral
devices
• Support of different power modes of appropriate phyCARDs
• Full featured 4 line RS-232 transceiver supporting data rates of up
to 120kbps, hardware handshake and RS-232 connector
• Seven USB-Host interfaces
• USB-OTG interface
• 10/100 Mbps Ethernet interface
• Complete Audio and Touchscreen interface
• LVDS display interface with separate connectors for data lines and
display / backlight supply voltage
• Circuitry to allow dimming of a backlight
• LVDS camera interface with I2C for camera control
• Secure Digital Memory Card / MultiMedia Card Interface
• Two expansion connectors for customer prototyping purposes
featuring one USB, one I2C and one SPI interface, as well as one
GPIO/IRQ at either connector
• DIP-Switch to configure various interface options
• Jumper to configure the boot options for the phyCARD-M module
mounted
• RTC with battery supply/backup
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
17.1 Concept of the phyBASE Board
The phyBASE Carrier Board provides a flexible development
platform enabling quick and easy start-up and subsequent
programming of the phyCARD Single Board Computer module. The
Carrier Board design allows easy connection of additional expansion
boards featuring various functions that support fast and convenient
prototyping and software evaluation. The Carrier Board is compatible
with all phyCARDs.
This modular development platform concept includes the following
components:
•
the phyCARD-M module populated with the i.MX35 processor
and all applicable SBC circuitry such as DDR2 SDRAM, Flash,
PHYs, and transceivers to name a few.
•
the phyBASE which offers all essential components and
connectors for start-up including: a power socket which enables
connection to an external power adapter, interface connectors
such as DB-9, USB and Ethernet allowing for use of the SBC's
interfaces with standard cable.
The following sections contain specific information relevant to the
operation of the phyCARD-M mounted on the phyBASE Carrier
Board.
Note:
Only features of the phyBASE which are supported by the
phyCARD-M are described. Jumper settings and configurations which
are not suitable for the phyCARD-M are not described in the
following chapters.
74
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
17.2 Overview of the phyBASE Peripherals
X6
U23
D39
U9
U8
D38
The phyBASE is depicted in Figure 15. It is equipped with the
components and peripherals listed in Table 30, Table 31, Table 32 and
Table 33. For a more detailed description of each peripheral, refer to
the appropriate chapter listed in the applicable table. Figure 15
highlights the location of each peripheral for easy identification.
U43
U33
U30
U29
U25
U3
X8
Expansion 1
U14
XT1
U6
U31
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
D45
BAT1
S3
U7
MMC / SD card
U5
S1
Reset
S2
ON / OFF
U28
U20
J3
X26
U16
Expansion 2
U1
Figure 15:
U17
X9
X4
U13
J1
AUDIO
CAM
X5
X3 X2 X1
U32
D30
U10
U22
RS232
U11
U2
MIC
OUT
IN
X34
U4
P1
USB Host
X33
U27
9.4mm
D46
U18 U19
J2
U15
U21
D41
U12
USB Host
X7
X32
D37
X27
U26
Ethernet
X10
USB OTG
X29
phyCARD Connector
Front
D40
X28
JP2 JP1
PWR
LVDS
U24
phyBASE Overview of Connectors, LEDs and Buttons
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
17.2.1
Connectors and Pin Header
Table 30 lists all available connectors on the phyBASE. Figure 15
highlights the location of each connector for easy identification.
Reference
Designator
X1
X2
X3
X5
X6
X7
X8A
X9A
X10
X26
X27
X28
X29
X32
X33
X34
P1
Table 30:
76
See
Section
Stereo Microphone input connector
17.3.9
Stereo Line Out connector
17.3.9
Stereo Line In connector
17.3.9
Camera Interface, RJ45
17.3.8
Display data connector
17.3.7.1
Dual USB Host connector
17.3.5
Expansion connector 0
17.3.13
Expansion connector 1
17.3.13
Ethernet connector, RJ45 with speed and 17.3.4
link led
Secure Digital Mem./MultiMedia Card slot 17.3.14
phyCARD-Connector for mounting the 17.3.1
phyCARD-M
Wall adapter input power jack to supply 17.3.2
main board power (+9 - +36 V)
USB On-The-Go connector
17.3.6
Display / Backlight supply voltage 17.3.7.2
connector
USB Host connector
17.3.5
for
CPLD JTAG connector
internal
use only
Serial Interface, DB-9F
17.3.3
Description
phyBASE Connectors and Pin Headers
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
Note:
Even though the signal level of the phyCARD's I2C and SPI interface
is already 3.3 V the interfaces are connected to level shifters on the
phyCARD Carrier Board. This is essential to keep the phyCARD
Carrier Board compatible with all phyCARDs.
Ensure that all module connections are not to exceed their expressed
maximum voltage or current. Maximum signal input values are
indicated in the corresponding controller User's Manual/Data Sheets.
As damage from improper connections varies according to use and
application, it is the user‘s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
17.2.2
Switches
The phyBASE is populated with some switches which are essential for
the operation of the phyCARD-M module on the Carrier Board.
Figure 15 shows the location of the switches and push buttons.
Button
S1
S2
Table 31:
Description
System Reset Button – system reset signal
generation
Power Button – powering on and off main
supply voltages of the Carrier Board
See
Section
17.3.16
17.3.2
phyBASE push buttons descriptions
S1 Issues a system reset signal. Pressing this button will toggle the
nRESET_IN pin (X2A7) of the phyCARD microcontroller LOW,
causing the controller to reset.
S2 Issues a power on/off event. Pressing this button less than 2
seconds will toggle the PWR_KEY pin of the phyBASE CPLD
LOW, causing the CPLD to turn on the supply voltages. Pressing
this button for more than 2 seconds causes the CPLD to turn off
the supply voltages.
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phyCARD-M [PCA-A-M1-xxx]
Additionally a DIP-Switch is available at S3. The following table
gives an overview of the functions of the DIP-switch.
Note:
The following table describes only settings suitable for the
phyCARD-M. Other settings must not be used with the phyCARD-M.
See
Section
Button
Setting
S3_1/
S3_2
Description
Depending on the audio standard supported by
the phyCARD the audio and touch panel signals
are either processed by the Wolfson audio/touch
contrl. at U1 (AC'97) or the Cirrus Logic Audio
CODEC at U17 (HDA) and a dedicated touch
contrl. at U28. Switches 1 and 2 of DIP-Switch
S3 select which device processes the audio and
touch panel signals.
0/0
Auto Detection: based on the high level of the 17.3.9
HDA_SEL/AC_INT signal generated on the
phyCARD the Wolfson audio/touch contrl.
(U1) is selected to process AC'97 compliant
audio signals and the signals from a touch
screen.
Wolfson audio/touch contrl. (U1) is selected to
process AC'97 compliant audio signals and the
signals from a touch screen.
Switches 3 and 4 of DIP-Switch S3 configure the
I2C address for the communication between
CPLD and phyCARD.
0/1
S3_3/
S3_4
0/0
CPLD Address 0x80
Switch 5 of DIP-Switch S3 selects the interface
used for the communication between CPLD and
phyCARD.
0
I2C communication selected
Switch 6 of DIP-Switch S3 turns the SPI
Multiplexer on, or off.
0
SPI multiplexer off
S3_5
S3_6
78
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The phyCARD-M on the phyBASE
S3_7/
S3_8
0/0
0/1
1/x
Table 32:
1
:
Switches 7 and 8 of DIP-Switch S3 map the two
slave select signals of the SPI interface and the
two
GPIO_IRQ
signals
(GIO0_IRQ,
GPIO1_IRQ) to two of the three available
17.3.7.1
connectors.
17.3.11
SS0/GPIO0 -> expansion 0 (X8A),
17.3.12
SS1/GPIO1 -> expansion 1 (X9A)
17.3.13
SS0/GPIO0 -> expansion 0 (X8A),
SS1/GPIO1 -> display data connector (X6)
SS0/GPIO0 -> expansion 1 (X9A),
SS1/GPIO1 -> display data connector (X6)
phyBASE DIP-Switch S3 descriptions 1
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2010
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phyCARD-M [PCA-A-M1-xxx]
17.2.3
LEDs
The phyBASE is populated with numerous LEDs to indicate the status
of the various USB-Host interfaces, as well as the different supply
voltages. Figure 15 shows the location of the LEDs. Their function is
listed in the table below:
See
Section
LED
Color
Description
D16
yellow
USB1 amber led
D17
yellow
USB2 amber led
D18
yellow
USB3 amber led
D19
yellow
USB4 amber led
D20
yellow
USB5 amber led
D21
yellow
USB6 amber led
D22
yellow
USB7 amber led
D23
green
USB1 green led
D24
green
USB2 green led
D25
green
USB3 green led
D26
green
USB4 green led
D27
green
USB5 green led
D28
green
USB6 green led
D29
green
USB7 green led
D30
red
USB HUB global led
D37
green
5V supply voltage for peripherals on the phyBASE
D38
green
supply voltage of the phyCARD
D39
green
3V3 supply voltage for peripherals on the
phyBASE
D40
green
3V3 standby voltage of the phyBASE
D41
green
standby voltage of the phyCARD
D45
yellow
SSI interface compliant with the AC97 standard
D46
green
SSI interface compliant with the HDA standard
Table 33:
80
17.3.5
17.3.2
phyBASE LEDs descriptions
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
Note:
Detailed descriptions of the assembled connectors, jumpers and
switches can be found in the following chapters.
17.2.4
Jumpers
The phyCARD Carrier Board comes pre-configured with 2 removable
jumpers (JP) and 3 solder jumpers (J). The jumpers allow the user
flexibility of configuring a limited number of features for development
constraint purposes. Table 34 below lists the 5 jumpers, their default
positions, and their functions in each position. Figure 16 depicts the
jumper pad numbering scheme for reference when altering jumper
settings on the development board.
Figure 17 provides a detailed view of the phyBase jumpers and their
default settings. In this diagrams a beveled edge indicates the location
of pin 1.
Before making connections to peripheral connectors it is advisable to
consult the applicable section in this manual for setting the associated
jumpers.
e.g.: JP1
Figure 16:
e.g.: J1
e.g.: JP2
Typical jumper numbering scheme
Table 34 provides a comprehensive list of all Carrier Board jumpers.
The table only provides a concise summary of jumper descriptions.
For a detailed description of each jumper see the applicable chapter
listing in the right hand column of the table.
If manual modification of the solder jumpers is required please ensure
that the board as well as surrounding components and sockets remain
undamaged while de-soldering. Overheating the board can cause the
solder pads to loosen, rendering the board inoperable. Carefully heat
neighboring connections in pairs. After a few alternations,
© PHYTEC Messtechnik GmbH 2010
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81
phyCARD-M [PCA-A-M1-xxx]
X6
U23
D39
U9
U8
D38
components can be removed with the solder-iron tip. Alternatively, a
hot air gun can be used to heat and loosen the bonds.
U43
U33
U30
U29
U25
U3
X8
Expansion 1
U14
Figure 17:
BAT1
U17
X9
S3
U7
MMC / SD card
U5
S1
Reset
S2
U28
ON / OFF
J3
X26
U16
Expansion 2
J1
X4
U13
U20
MIC
OUT
IN
X34
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
D45
U31
U32
U1
X3 X2 X1
AUDIO
CAM
X5
U2
D30
U10
U11
U22
RS232
U6
XT1
U4
P1
USB Host
X33
U27
9.4mm
D46
U18 U19
J2
U15
U21
D41
U12
USB Host
X7
X32
D37
X27
U26
Ethernet
X10
USB OTG
X29
phyCARD Connector
Front
D40
X28
JP2 JP1
PWR
LVDS
U24
phyBASE jumper locations
The following conventions were used in the Jumper column of the
jumper table (Table 34)
• J = solder jumper
• JP = removable jumper
82
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
Jumper
Setting
See
Section
Description
Jumper JP1 selects the boot device of the
phyCARD-M
open
External boot, FLASH enabled as Boot
device 7
1+2
Serial Bootloader1
3+4
Internal Bootloader1
1+2,
3+4
Startup mode1
JP1
17.3.3
Jumper JP2 connects the input voltage to
connector X32 as supply voltage for a backlight.
JP2
open
VCC12V Backlight disabled
closed
VCC12V Backlight connected to power supply.
Only 12V DC power supplies allowed
17.3.7.2
Jumper J1 selects the function of the AC97
interrupt
J1
1+2
Pendown signal of the Audio/Touch controller
at U1 is connected to AC97 interrupt
2+3
GPIO2_IRQ output of the Audio/Touch
controller at U1 connected to AC97 interrupt
17.3.7.3
Jumper J2 configures the I2C address of the LED
dimmer at U21
J2
closed
17.3.7.2
I C device address of LED dimmer set to 0xC0 17.3.10
open
I2C device address of LED dimmer set to 0xC2
2
Jumper J3 configures the I2C address of the touch
screen controller at U28
J3
Table 34:
7
:
:
8
2
1+2
I C device address set to 0x88
2+3
I2C device address set to 0x82
17.3.7.3
17.3.10
phyBASE jumper descriptions 8
please see section 6 for more information on the different boot modes
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2010
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83
phyCARD-M [PCA-A-M1-xxx]
17.3 Functional Components on the phyBASE Board
This section describes the functional components of the phyBASE
Carrier Board supporting the phyCARD-M. Each subsection details a
particular connector/interface and associated jumpers for configuring
that interface.
17.3.1
phyCARD-M SBC Connectivity (X27)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
ON / OFF
X27
D30
1
Reset
S1
U4
BAT1
U18 U19
U29
XT1
D39
B
D37
X34
50
U25
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
A
phyCARD Connector
S2
U30
U21
U33
J2
LVDS
U17
J3
U9
U32
U16
U28
U43
D46
U7
MMC / SD card
Figure 18:
X32
X6
JP2 JP1
phyCARD-M SBC Connectivity to the Carrier Board
Connector X27 on the Carrier Board provides the phyCARD Single
Board Computer connectivity. The connector is keyed for proper
insertion of the SBC. Figure 18 above shows the location of connector
X27, along with the pin numbering scheme as described in section 2.
84
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
17.3.2
Power Supply (X28)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U3
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
S3
X26
phyCARD Connector
U4
BAT1
U5
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 19:
X6
JP2 JP1
Power adapter
Caution:
Do not use a laboratory adapter to supply power to the Carrier Board!
Power spikes during power-on could destroy the phyCARD module
mounted on the Carrier Board! Do not change modules or jumper
settings while the Carrier Board is supplied with power!
Permissible input voltage at X28: +9 - +36 V DC unregulated.
The required current load capacity of the power supply depends on the
specific configuration of the phyCARD mounted on the Carrier Board
as well as whether an optional expansion board is connected to the
Carrier Board. An adapter with a minimum supply of 2.0 A is
recommended.
© PHYTEC Messtechnik GmbH 2010
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85
phyCARD-M [PCA-A-M1-xxx]
Polarity:
+9 - 36 VDC
≥ 2000 mA
-- +
Center Hole
2.5 mm
5.0 mm
GND
Figure 20:
Connecting the Supply Voltage at X28
No jumper configuration is required in order to supply power to the
phyCARD module!
The phyBASE is assembled with a few power LEDs whose functions
are described in the following table:
LEDs
D37
Color
green
D38
green
D39
green
D40
green
D41
green
Table 35:
Description
VCC5V - 5V supply voltage for peripherals on
the phyBASE
VCC_PHYCARD - supply voltage of the
phyCARD
VCC3V3 - 3V3 supply voltage for peripherals
on the phyBASE
VCC3V3STBY - 3V3 standby voltage of the
phyBASE
VSTBY - standby voltage of the phyCARD
LEDs assembled on the Carrier Board
Note:
For powering up the phyCARD the following actions have to be done:
1. Plug in the power supply connector
» All power LEDs should light up and the phyCARD puts
serial output to serial line 0 at P1.
2.
For powering down the phyCARD-M button S2 should be
pressed for a minimum time of 2000 ms.
3.
Press button S2 for a maximum time of 1000 ms.
» All power LEDs should light up and the phyCARD puts
serial output to serial line 0 at P1.
86
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The phyCARD-M on the phyBASE
Three different power states are possible RUN, OFF and SUSPEND.
•
•
•
During RUN all supply voltages except VSTBY are on. This
means that the phyCARD-M is supplied by VCC_PHYCARD.
In OFF state all supply voltages are turned off. Only the standby
voltage (VCC3V3STBY) of the phyBASE itself is still available
to supply the PLD, the RTC and to provide a high-level voltage
for the Reset and Power switch.
In SUSPEND mode only the standby voltage VSTBY for the
phyCARD-M and the standby voltage (VCC3V3STBY) of the
phyBASE itself are generated. This means the phyCARD-M is
supplied only by VSTBY.
The RUN and OFF state can be entered using the power button S2 as
described in the gray box above. It is also possible to enter OFF state
with the help of the phyCARD's X_Power_off signal at pin X2A29B
of the phyCARD-Connector (GPIO3_10 at H3 of the i.MX35). To
enter OFF state signal X_Power_off must be active (low).
SUSPEND state can be entered using signal X_Suspend_to_RAM at
pin X2A26B of the phyCARD-Connector (GPIO2_29 at V2 of the
i.MX35). X_Suspend_to_RAM must be active (low) for at least
500ms.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
87
phyCARD-M [PCA-A-M1-xxx]
17.3.3
RS-232 Connectivity (P1)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 21:
X6
JP2 JP1
RS-232 connection interface at connector P1
Connector P1 is a DB9 sub-connector and provides a connection
interface to UART1 of the i.MX35. The TTL level signals from the
phyCARD-M are converted to RS-232 level signals. As defined in the
specification of the X-Arc bus the serial interface allows for a 5-wire
connection including the signals RTS and CTS for hardware flow
control. Figure 22 below shows the signal mapping of the RS-232
level signals at connector P1.
The RS-232 interface is hard-wired and no jumpers must be
configured for proper operation.
88
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
1
6
2
7
3
8
4
9
5
Figure 22:
TxD-RS232
RTS-RS232
RxD-RS232
CTS-RS232
Pin 5:
GND
RS-232 connector P1 signal mapping
Ethernet Connectivity (X10)
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.4
Pin 2:
Pin 7:
Pin 3:
Pin 8:
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
U29
U19
XT1
X34
U23
D40
U24
U25
U21
J2
U7
X32
MMC / SD card
Figure 23:
D37
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Ethernet interface at connector X10
The Ethernet interface of the phyCARD is accessible at an RJ45
connector (X10) on the Carrier Board. Due to its characteristics this
interface is hard-wired and can not be configured via jumpers. The
LEDs for LINK (green) and SPEED (yellow) indication are integrated
in the connector.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
89
phyCARD-M [PCA-A-M1-xxx]
17.3.5
USB Host Connectivity (X6, X7, X8, X9, X33)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
USB Host
RS232
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 24:
X6
JP2 JP1
Components supporting the USB host interface
The USB host interface of the phyCARD is accessible via the USB
hub controller U4 on the Carrier Board. The controller supports
control of input USB devices such keyboard, mouse or USB key. The
USB hub has 7 downstream facing ports. Three ports extend to
standard USB connectors at X7 (dual USB A). Two more ports
connect to 9 pin header row X33. These interfaces are compliant with
USB revision 2.0. The remaining ports are accessible at the display
data connector X6 and the expansion connectors X8A and X9A. These
three interfaces provide only the data lines D+ and D-. They do not
feature a supply line Vbus.
90
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
LEDs D16 to D30 signal use of the USB host interfaces. Table 33
shows the assignment of the LEDs to the different USB ports.
Table 36 shows the distribution of the seven downstream facing ports
to the different connectors, whereas Table 37 shows the Pin-out of
USB host connector X33.
USB hub port #
USB1 / USB 5
USB2
USB3
USB4
USB6
USB7
Table 36:
Connector Type
9 pin header row (see table
X33
below)
40 pin FCC (pins 16 (D+) and
X6
17 (D-))
20 pin header row (pins 19 (D-)
X8
and 20 (D+))
20 pin header row (pins 19 (D-)
X9
and 20 (D+))
X7A (bottom) USB A
X7B (top)
USB A
Distribution of the USB hub's (U4) ports
Pin number
1
3
5
2
4
6
7, 8
9,10
Table 37:
Connector
Signal name
USB5_VBUS
USB5_DUSB5_D+
USB1_VBUS
USB1_DUSB1_D+
GND
NC
Description
USB5 Power Supply
USB5 Data USB5 Data +
USB1 Power Supply
USB1 Data USB1 Data +
Ground
Not connected
Universal USB pin header X33 signal description
© PHYTEC Messtechnik GmbH 2010
L-750e_2
91
phyCARD-M [PCA-A-M1-xxx]
17.3.6
USB OTG Connectivity (X29)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 25:
X6
JP2 JP1
USB OTG interface at connector X29
The USB OTG interface of the phyCARD is accessible at connector
X29 (USB Mini AB) on the Carrier Board. This interface is compliant
with USB revision 2.0.
No jumper settings are necessary for using the USB OTG port.
The phyCARD supports the On-The-Go feature. The Universal Serial
Bus On-The-Go is a device capable to initiate the session, control the
connection and exchange Host/Peripheral roles between each other.
92
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-M on the phyBASE
17.3.7
Display / Touch Connectivity (X6, X32)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 26:
X6
JP2 JP1
Universal LVDS interface at connector X6
The various performance classes of the phyCARD family allow to
attach a large number of different displays varying in resolution,
signal level, type of the backlight, Pin-out, etc. In order not to limit the
range of displays connectable to the phyCARD, the phyBASE has no
special display connector suitable only for a small number of displays.
The new concept intends the use of an adapter board (e.g. phyBASE
LCD interface LCD-014) to attach a special display, or display family
to the phyCARD. Two universal connectors provide the connectivity
for the display adapter. They allow easy adaption also to any customer
display. The display data connector at X6 combines various interface
signals like LVDS, USB, I2C, etc. required to hook up a display. The
display power connector at X32 provides all supply voltages needed to
supply the display and a backlight.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
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phyCARD-M [PCA-A-M1-xxx]
17.3.7.1 Display Data Connector (X6)
The display data connector at X6 (40 pin FCC connector 0,5mm pitch)
combines various interface signals.
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12
13
Signal name
Description
SPI1_SCLK
SPI1_MISO
SPI1_MOSI
SPI1_SS_DISP
DISP_IRQ
VCC3V3
I2C_SCL
I2C_SDA
GND
LS_BRIGHT
VCC3V3
/PWR_KEY
/DISP_ENA
14
PHYWIRE
15
16
17
18
19
20
21
22
23
GND
USB2_D+
USB2_DGND
TXOUT0TXOUT0+
GND
TXOUT1TXOUT1+
SPI 1 clock
SPI 1 Master data in; slave data out
SPI 1 Master data out; slave data in
SPI 1 Chip select display
Display interrupt input
Power supply display
I2C Clock Signal
I2C Data Signal
Ground
PWM brightness Output
Power Supply Display
Power on/off Button
Display enable signal
Hardware Introspection Interface
for internal use only
Ground
USB2 data + 9
USB2 data -1
Ground
LVDS data channel 0 negative output
LVDS data channel 0 positive output
Ground
LVDS data channel 1 negative output
LVDS data channel 1 positive output
9
:
94
LEDs D17 and D24 signal use of the USB interface
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Table 38:
GND
TXOUT2TXOUT2+
GND
TXOUT3TXOUT3+
GND
TXCLKOUTTXCLKOUT+
GND
TP_X+
TP_XTP_Y+
TP_YTP_WP
GND
LS_ANA
Ground
LVDS data channel 2 negative output
LVDS data channel 2 positive output
Ground
LVDS data channel 3 negative output
LVDS data channel 3 positive output
Ground
LVDS clock channel negativ output
LVDS clock channel positive output
Ground
Touch
Touch
Touch
Touch
Touch
Ground
Light sensor Analog Input
Display data connector signal description
The connection of the SPI interface and the display interrupt input to
the X-Arc bus is shared with the SPI interfaces and the interrupt inputs
on the expansion connectors X8A and X9A. Because of that these
signals have to be mapped to the display data connector by
configuring switches 7 and 8 of DIP-Switch S3. Table 39 shows the
required settings.
The default setting does not connect the SPI interface and the
GPIO/Interrupt pin of the X-Arc bus to the display data connector.
© PHYTEC Messtechnik GmbH 2010
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95
phyCARD-M [PCA-A-M1-xxx]
Button Setting Description
SS0/GPIO0_IRQ 10 -> expansion 0 (X8A),
S3_7/ 0/0
SS1/GPIO1_IRQ1 -> expansion 1 (X9A)
S3_8
SS0/GPIO0_IRQ1 -> expansion 0 (X8A),
0/1
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> expansion 1 (X9A),
1/x
SS1/GPIO1_IRQ1 -> display data connector (X6)
Table 39:
SPI and GPIO connector selection
The Light sensor Analog Input at pin 40 extends to an A/D converter
which is connected to the I2C bus at address 0xC8 (write) and 0XC9
(read).
17.3.7.2 Display Power Connector (X32)
The display power connector X32 (AMP microMatch 8-188275-2)
provides all supply voltages needed to supply the display and a
backlight.
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
Table 40:
10
Signal name
GND
VCC3V3
GND
VCC5V
GND
VCC5V
GND
VCC5V
GND
LS_BRIGHT
VCC12V_BL
VCC12V_BL
Description
Ground
3,3V power supply display
Ground
5V power supply display
Ground
5V power supply display
Ground
5V power supply display
Ground
PWM brightness output
12V Backlight power supply
12V Backlight power supply
LVDS power connector X32 signal description
: GPIO0_IRQ ≙ GPIO2_7 (at T7) and GPIO1_IRQ ≙ GPIO2_23 (at V3) of the i.MX35
96
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
The PWM signal at pin 10 can be used to control the brightness of a
display's backlight. It is generated by an LED dimmer. The LED
dimmer is connected to the I2C bus at address 11 0xC0 (write) and
0xC1 (read).
To make VCC12V_BL available at X32 jumper JP2 must be closed.
Caution:
There is no protective circuitry for the backlight. Close jumper JP2
only if a 12 V power supply is connected to X28 as primary supply for
the phyBASE.
17.3.7.3 Touch Screen Connectivity
As many smaller applications need a touch screen as user interface,
provisions are made to connect 4- or 5- wire resistive touch screens to
the display data connector X6 (pins 34 - 38, refer to Table 38). Two
touch screen controllers are available on the phyCARD Carrier Board.
The Wolfson WM9712L audio/touch codec at U1 allows connecting
4- and 5-wire touch panels, whereas the STMPE811 touch panel
controller at U28 is suitable for 4-wire touch panels only. Because of
the dual functionality of the Wolfson audio / touch controller the
choice which controller is chosen to handle the signals from the touch
screen is pegged to the audio standard supported by the phyCARD.
For phyCARDs supporting the AC'97 standard the Wolfson
WM9712L audio/touch controller processes the touch panel signals.
For phyCARDs delivering HDA compliant audio signals the dedicated
touch panel controller at U28 (STMPE811) must be selected.
Switches 1 and 2 of DIP-Switch S3 select which controller is used to
process the touch panel signals. The different configurations are
shown in Table 41.
11
:
Default address. Jumper J2 allows to select a 0xC2 (write) and 0xC3 (read) alternatively
(refer to Table 34).
© PHYTEC Messtechnik GmbH 2010
L-750e_2
97
phyCARD-M [PCA-A-M1-xxx]
Button Setting
S3_1/
S3_2
0/0
0/1
Table 41:
Description
Depending on the audio standard supported by the
phyCARD the audio and touch panel signals are either
processed by the Wolfson audio/touch contrl. at U1
(AC'97) or the Cirrus Logic Audio CODEC at U17
(HDA) and a dedicated touch contrl. at U28.
Switches 1 and 2 of DIP-Switch S3 select which device
processes the audio and touch panel signals.
Auto Detection: based on the high level of the
HDA_SEL/AC_INT signal generated on the
phyCARD the Wolfson audio/touch contrl. (U1) is
selected to process AC'97 compliant audio signals
and the signals from a touch screen.
Wolfson audio/touch contrl. (U1) is selected to process
AC'97 compliant audio signals and the signals from a
touch screen.
Selection of the touch screen controller
As the phyCARD-M features an AC'97 compliant audio interface the
Wolfson WM9712L audio/touch codec must be chosen. The touch
screen data is then available at the AC'97 interface. An interrupt or the
pendown signal of the WM9712L, selected by jumper J1 (refer to
section 17.2.4), is connected to the AC'97 interrupt pin
(HAD_SEL/AC_INT, pin X2A42). The default configuration selects
the pendown signal to be attached to pin X2A42 of the phyCARDConnector.
98
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
17.3.8
Camera Interface (X5)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
USB Host
RS232
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
U9
U32
U16
ON / OFF
X27
D39
D30
Reset
S1
U4
BAT1
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
U30
U21
U33
J2
LVDS
S2
phyCARD Connector
U28
U43
D46
U7
X32
MMC / SD card
Figure 27:
X6
JP2 JP1
Camera interface at connectors X5
The phyCARD-M has an optional camera interface. This interface
extends from the phyCARD-Connector to the RJ45 socket (X5) on the
Carrier Board. The table below shows the Pin-out of connector X5:
Pin #
1
2
3
4
5
6
7
8
Table 42:
Signal Name
RXIN+
RXINRX_CLKI2C_SDA
I2C_SCL
RXCLK+
VCC_CAM
GND
Description
LVDS Input+
LVDS InputLVDS ClockI2C Data
I2C Clock
LVDS Clock+
Power supply camera (3.3V)
Ground
PHYTEC camera connector X5
© PHYTEC Messtechnik GmbH 2010
L-750e_2
99
phyCARD-M [PCA-A-M1-xxx]
17.3.9
Audio Interface (X1,X2,X3)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U3
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
S3
X26
phyCARD Connector
U4
BAT1
U5
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 28:
X6
JP2 JP1
Audio interface at connectors X1,X2,X3
Depending on the audio standard supported by the phyCARD the
AC'97/HDA interface on the X-Arc bus connects either to a Wolfson
WM9712L audio / touch controller (U1) or a Cirrus Logic CS4207
(U17) Audio CODEC on the Carrier Board. The Wolfson audio /
touch controller processes AC'97 compliant signals, while signals
according to the HDA standard are handled by the Cirrus Logic
CS4207 Audio CODEC.
Switches 1 and 2 of DIP-Switch S3 select which codec is used to
process the audio signals. Table 43 shows the different options.
100
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
Button Setting
S3_1/ 0/0
S3_2
0/1
Table 43:
Description
Auto Detection: based on the high level of the
HDA_SEL/AC_INT signal generated on the
phyCARD the Wolfson audio/touch contrl.
(U1) is selected to process AC'97 compliant
audio signals and the signals from a touch
screen.
Wolfson audio/touch contrl. (U1) is selected to
process AC'97 compliant audio signals and the
signals from a touch screen.
Selection of the audio codec
Audio devices can be connected to 3,5mm audio jacks at X1, X2, and
X3.
Audio Outputs:
X2 – Line Output - Line_OUTL/Line_OUTR
Audio Inputs:
X1- Microphone Inputs - MIC1/MIC2
X3 - Line Input - Line_INL/Line_INR
Please refer to the audio codec’s reference manual for additional
information regarding the special interface specification.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
101
phyCARD-M [PCA-A-M1-xxx]
17.3.10 I2C Connectivity
The I2C interface of the X-Arc bus is available at different connectors
on the phyBASE. The following table provides a list of the connectors
and pins with I2C connectivity.
Connector
Camera interface X5
Display data connector X6
Expansion connector 1 X8A
Expansion connector 2 X9A
Table 44:
Location
pin 4 (I2C_SDA); pin 5 (I2C_SCL)
pin 8 (I2C_SDA); pin 7 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
I2C connectivity
To avoid any conflicts when connecting external I2C devices to the
phyBASE the addresses of the on-board I2C devices must be
considered. Some of the addresses can be configured by jumper. Table
45 lists the addresses already in use. The table shows only the default
address. Please refer to section 17.2.4 for alternative address settings.
Device
LED dimmer (U21)
RTC (U3)
A/D converter (U22)
Touch screen controller
(U28)
CPLD (U25)
Table 45:
102
Address used (write / read)
0xC0 / 0xC1
0xA2 / 0xA3
0xC8 / 0xC9
0x88 / 0x89
Jumper
J2
0x80 / 0x81
S3_3, S3_4
J3
I2C addresses in use
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
17.3.11 SPI Connectivity
The SPI interface of the X-Arc bus is available at the expansion
connectors X8A and X9A as well as at the display data connector X6
(refer to sections 17.3.7.1 and 17.3.13 to see the Pin-out). Due to the
X-Arc bus specification only two slave select signals are available.
Because of that the CPLD maps the SPI interface to two of the
connectors depending on the configuration of switches 7 and 8 of
DIP-Switch S3. The table below shows the possible configurations.
Button Setting Description
SS0/GPIO0_IRQ 12 -> expansion 0 (X8A),
S3_7/ 0/0
SS1/GPIO1_IRQ1 -> expansion 1 (X9A)
S3_8
SS0/GPIO0_IRQ1 -> expansion 0 (X8A),
0/1
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> expansion 1 (X9A),
1/x
SS1/GPIO1_IRQ1 -> display data connector (X6)
Table 46:
SPI connector selection
17.3.12 User programmable GPIOs
Two (GPIO0_IRQ and GPIO1_IRQ) of the three GPIO / Interrupt
signals available at the X-Arc bus are freely available. They are
mapped to the expansion connectors X8A and X9A (pin 16), or to the
display data connector X6 (pin 5) depending in the configuration at
DIP-Switch S3 (see Table 46). The third GPIO / Interrupt signal
(GPIO2_IRQ 13) is used to connect the interrupt output of the touch
screen controller at U28 to the phyCARD-M.
12
13
: GPIO0_IRQ ≙ GPIO2_7 (at T7) and GPIO1_IRQ ≙ GPIO2_23 (at V3) of the i.MX35
: GPIO2 ≙ GPIO1_1 at pin L16 of the i.MX35
© PHYTEC Messtechnik GmbH 2010
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103
phyCARD-M [PCA-A-M1-xxx]
17.3.13 Expansion connectors (X8A, X9A)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
USB Host
RS232
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 29:
X6
JP2 JP1
Expansion connector X8A, X9A
The expansion connectors X8A and X9A provide an easy way to add
other functions and features to the phyBASE. Standard interfaces such
as USB, SPI and I2C as well as different supply voltages and one
GPIO are available at the pin header rows.
As can be seen in Figure 29 the location of the connectors allows to
expand the functionality without expanding the physical dimensions.
Mounting wholes can be used to screw the additional PCBs to the
phyBASE.
The expansion connectors share the SPI interface and the GPIOs of
the X-Arc bus with the display data connector X6. Therefore switches
7 and 8 of DIP-Switch S3 must be configured to map the signals to the
desired connector.
104
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
Button
S3_7/
S3_8
Setting
Description
0/0
SS0/GPIO0_IRQ 14 -> expansion 0 (X8A),
SS1/GPIO1_IRQ1 -> expansion 1 (X9A)
SS0/GPIO0_IRQ1 -> expansion 0 (X8A),
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> expansion 1 (X9A),
SS1/GPIO1_IRQ1 -> display data connector (X6)
0/1
1/x
Table 47:
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal Name
VCC5V
VCC5V
VCC3V3
VCC3V3
GND
GND
I2C_SDA
I2C_SCL
PHYWIRE
GND
SPI_SS_SLOT0
SPI_SS_SLOT1
SPI1_MOSI
SPI1_SCLK
SPI1_MISO
/SPI1_RDY
SLOT0_IRQ
SLOT1_IRQ
GND
GND
USB3_DUSB4_DUSB3_D+
USB4_D+
Table 48:
14
SPI and GPIO connector selection
Description
5V power supply
5V power supply
3,3V power supply
3,3V power supply
Ground
Ground
I2C Data
I2C Clock
Hardware Introspection Interf. For internal use only
Ground
X8A SPI chip select expansion port 0
X9A SPI chip select expansion port 1
SPI master output/slave input
SPI clock output
SPI master input/slave output
SPI data ready input master mode only
X8A Interrupt input expansion port 0
X9A Interrupt input expansion port 1
Ground
Ground
X8A USB3 Data DX9A USB4 Data DX8A USB3 Data D+
X9A USB4 Data D+
PHYTEC expansion connector X8A, X9A
: GPIO0_IRQ ≙ GPIO2_7 (at T7) and GPIO1_IRQ ≙ GPIO2_23 (at V3) of the i.MX35
© PHYTEC Messtechnik GmbH 2010
L-750e_2
105
phyCARD-M [PCA-A-M1-xxx]
17.3.14 Secure Digital Memory Card/ MultiMedia Card (X26)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U3
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
S3
X26
phyCARD Connector
U4
BAT1
U5
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 30:
X6
JP2 JP1
SD / MM Card interface at connector X26
The phyCARD Carrier Board provides a standard SDHC card slot at
X26 for connection to SD/MMC interface cards. It allows easy and
convenient connection to peripheral devices like SD- and MMC cards.
Power to the SD interface is supplied by sticking the appropriate card
into the SD/MMC slot. The card slot X26 connects to the
phyCARD-M via a level shifter to ensure the correct voltage for the
SD/MMC cards.
106
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
17.3.15 Boot Mode Selection (JP1)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
USB Host
RS232
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
X6
JP2 JP1
1 2
3 4
Figure 31:
Boot Mode Selection Jumper JP1
The boot mode jumper JP1 is provided to configure the boot mode of
the phyCARD-M after a reset.
By default the boot mode jumper is open, configuring the
phyCARD-M for booting from the Flash device. Closing jumper JP1
results in start of the on-chip boot strap software of the i.MX35.
Please refer to the phyCARD-M Quick Start Manual as well as the
i.MX35 Reference Manual for Information on how to use the boot
strap mode.
© PHYTEC Messtechnik GmbH 2010
L-750e_2
107
phyCARD-M [PCA-A-M1-xxx]
Jumper Setting
JP1
Description
Jumper JP1 selects the boot device of the phyCARD-M
FLASH enabled as Boot device 15
Serial Bootloader1
Internal Bootloader1
Startup Mode1
open
1+2
3+4
1+2
3+4
Figure 32:
Boot Mode Selection Jumper JP1
17.3.16 System Reset Button (S1)
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 33:
X6
JP2 JP1
System Reset Button S1
The phyCARD Carrier Board is equipped with a system reset button at
S1. Pressing the button will not only reset the phyCARD mounted on
the phyBASE, but also the peripheral devices, such as the USB Hub,
etc.
15
108
please see section 6 for more information on the different boot modes
© PHYTEC Messtechnik GmbH 2010
L-750e_2
The phyCARD-M on the phyBASE
17.3.17 RTC at U3
Front
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
X5
USB Host
RS232
PWR
X33
U2
CAM
Ethernet
D38
U13
U6
U27
U1
U8
U12
U22
U14
X4
USB Host
D45
U11
U10
X9
U20
X10
USB OTG
AUDIO
J1
X28
X29
X7
X8
Expansion 2
U26
Expansion 1
U31
D41
U17
J3
ON / OFF
X27
D39
D30
Reset
U18 U19
U29
XT1
X34
U25
D37
U23
D40
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
U5
phyCARD Connector
U4
BAT1
U30
U21
U33
J2
LVDS
S2
S1
U9
U32
U16
U28
U43
D46
U7
X32
MMC / SD card
Figure 34:
X6
JP2 JP1
The RTC at U3 with the battery connector BAT1
For real-time or time-driven applications, the phyBASE is equipped
with an RTC-8564 Real-Time Clock at U3. This RTC device provides
the following features:
• Serial input/output bus (I2C), address 0xA2(write)/0xA3(read)
• Power consumption
Bus active (400 kHz): < 1 mA
Bus inactive, CLKOUT inactive:
= 275 nA
• Clock function with four year calendar
• Century bit for year 2000-compliance
• Universal timer with alarm and overflow indication
• 24-hour format
• Automatic word address incrementing
• Programmable alarm, timer and interrupt functions
© PHYTEC Messtechnik GmbH 2010
L-750e_2
109
phyCARD-M [PCA-A-M1-xxx]
The Real-Time Clock is programmed via the I2C bus
(address 0xA2 / 0xA3). Since the phyCARD-M is equipped with an
internal I2C controller, the I2C protocol is processed very effectively
without extensive processor action (refer also to section 9.5)
The Real-Time Clock also provides an interrupt output that extends to
the Wakeup signal at X27A48 16. An interrupt occurs in the event of a
clock alarm, timer alarm, timer overflow and event counter alarm. It
has to be cleared by software. With the interrupt function, the
Real-Time Clock can be utilized in various applications.
If the RTC interrupt is to be used as software interrupt via a
corresponding interrupt input of the processor.
Note:
After connection of the supply voltage the Real-Time Clock generates
no interrupt. The RTC must be first initialized (see RTC Data Sheet
for more information).
Use of a coin cell at BAT1 allows to buffer the RTC.
17.3.18 PLD at U25
The phyBASE is equipped with a Lattice LC4256V PLD at U25. This
PLD device provides the following features:
• Power management function (section 17.3.2)
• Signal mapping for sound devices WM9712L and AD1986A
(section 17.3.9)
• Signal mapping SPI chip select and interrupt to the expansion or
display connectors (sections 17.3.11 and 17.3.12)
• Touch Signal mapping to WM9712L or STMP811 (section
17.3.7.3)
16
: connected to GPIO2_12 (at U6) of the i.MX35 on the phyCARD-M
110
© PHYTEC Messtechnik GmbH 2010
L-750e_2
© PHYTEC Messtechnik GmbH 2010
X26
BAT1
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
D30
U10
U22
L-750e_2
X34
XT1
U6
RS232
U4
U14
X8
U25
U3
U29
Expansion 1
172mm
185mm
USB Host
U27
X33
U12
U21
U19
S3
D46
J2
USB Host
X7
U18
MMC / SD card
U5
S1
U17
U32
Reset
U16
U31
D45
U2
S2
J3
Expansion 2
X9
X4
CAM
X5
P1
9.4mm
ON / OFF
U28
U20
U1
J1
AUDIO
X3 X2 X1
U15
3mm
6.5mm
3mm
Figure 35:
X29
D41
U43
U33
U30
USB OTG
X32
X27
U26
D40
D37
X10
Ethernet
phyCARD Connector
MIC
OUT
IN
PWR
JP2 JP1
X28
X6
LVDS
Front
U23
D39
U9
U8
D38
D3.2mm
124mm
130mm
6.5mm
The phyCARD-M on the phyBASE
17.3.19 Carrier Board Physical Dimensions
U24
U11
U13
U7
Carrier Board Physical Dimensions
Please contact us if a more detailed dimensioned drawing is needed to
integrate the phyBASE into a customer application.
111
phyCARD-M [PCA-A-M1-xxx]
18 Revision History
Date
Version
numbers
01-07-2009 Manual
L-750e_0
10-06-2010 Manual
L-750e_1
19-11-2010 Manual
L-750e_2
112
Changes in this manual
First draft, Preliminary documentation.
Describes the phyCARD-M with
phyBASE- Baseboard.
Final version matching phyCARD-M's
PCB-No. 1328.1 and 1333.1 for the
phyBASE
New version matching phyCARD-M's
PCB-No. 1328.2 and 1333.2 for the
phyBASE
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Index
Index
Features ................................. 2, 73
FEC ........................................... 45
1
100Base-T................................. 45
10Base-T................................... 45
1V3............................................ 24
1V5............................................ 24
1V8............................................ 24
2
G
General Purpose I/Os ................ 51
GND Connection ...................... 71
H
Humidity ................................... 64
2V775........................................ 24
3
I
Audio CODEC........................ 100
I²C EEPROM ............................ 36
I2C Interface .............................. 47
I2C Memory............................... 20
I2C2 Bus .................................... 20
IC Identification Module........... 21
B
J
Block Diagram............................ 4
Booting...................................... 31
Bootstrap................................... 32
DDR2 SDRAM......................... 35
Debug Interface......................... 53
Dimensions ............................... 64
Display Interface....................... 57
J1.........................................20, 37
J13............................................. 21
J16.......................................20, 38
J2...................................20, 28, 29
J21.......................................21, 62
J22.......................................21, 58
J3.........................................20, 37
J4.........................................20, 37
J9...................................21, 28, 29
JA-002....................................... 55
JTAG Interface.......................... 53
JTAG-Emulator Adapter........... 55
E
L
EEPROM ............................ 35, 36
EEPROM Write Protection....... 38
EMC .......................................... xi
Emulator.................................... 55
LAN .......................................... 47
LINK LED ................................ 89
LVDS
Camera Signals ................21, 62
Display Signals ................21, 58
3V3............................................ 24
A
C
Camera Interface....................... 61
D
F
Fast Ethernet Controller............ 45
© PHYTEC Messtechnik GmbH 2010
L-750e_2
113
phyCARD-M [PCA-A-M1-xxx]
M
MAC ......................................... 47
MAC Address ........................... 47
N
NAND Flash ....................... 35, 36
O
Operating Temperature............. 64
Operating Voltage..................... 64
P
PHY .......................................... 45
phyBASE
Connectors............................. 76
LEDs...................................... 80
P1........................................... 88
Peripherals ............................. 75
Pin Header ............................. 76
Switches................................. 77
X10 ........................................ 89
X27 ........................................ 84
X28 ........................................ 85
phyCARD-Connector ........... 9, 11
Physical Dimensions ................ 63
Physical Layer Transceiver ...... 45
Pin Description ........................... 9
Pin-out ...................................... 16
PLD......................................... 110
Power Consumption ................. 64
Power Management .................. 27
Power Supply.............................. 7
Programming Voltage .............. 21
R
RS-232 Level............................ 43
RTC ........................................ 109
RTC Interrupt ......................... 110
S
SD / MMC Card Interfaces....... 39
114
SDRAM .................................... 35
Serial Interfaces ........................ 41
SMT Connector .......................... 9
SPEED LED ............................. 89
SPI Interface ............................. 48
SSI Interface ............................. 48
Standby Voltage........................ 24
Storage Temperature................. 64
Supply Voltage ......................... 23
System Configuration ............... 31
System Memory........................ 35
System Power ........................... 23
T
Technical Specifications........... 63
U
U10 ........................................... 35
U11 ........................................... 35
U13 ........................................... 36
U16 ........................................... 44
U4 ....................................... 21, 58
U5 ....................................... 21, 62
U6 ....................................... 20, 36
U7 ............................................. 45
U8 ............................................. 35
U9 ............................................. 35
UART ....................................... 42
USB
Host Controller ...................... 44
OTG Interface........................ 43
USB 2.0............................... 90, 92
USB Device .............................. 43
USB Host .................................. 43
USB OTG ................................. 43
V
VBAT ....................................... 24
VCC_3V3 ................................. 23
VCC_Logic............................... 25
Voltage Output.......................... 25
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Index
Voltage Regulator ..................... 24
X
W
X1.............................................. 53
X29............................................ 92
Weight....................................... 64
WM9712L................... 97, 98, 100
© PHYTEC Messtechnik GmbH 2010
L-750e_2
115
phyCARD-M [PCA-A-M1-xxx]
116
© PHYTEC Messtechnik GmbH 2010
L-750e_2
Suggestions for Improvement
Document:
phyCARD-M
Document number: L-750e_2, September 2010
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© PHYTEC MesstechnikGmbH 2010
L-750e_2
page
Published by
© PHYTEC Messtechnik GmbH 2010
Ordering No. L-750e_2
Printed in Germany

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