Maxim MAX7318AUG+ (73-865-26)

Maxim MAX7318AUG+ (73-865-26)
KIT
ATION
EVALU
E
L
B
AVAILA
19-3381; Rev 3; 12/07
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Features
The MAX7318 2-wire-interfaced expander provides 16bit parallel input/output (I/O) port expansion for SMBus™
and I2C applications. The MAX7318 consists of input
port registers, output port registers, polarity inversion
registers, configuration registers, and an I2C-compatible
serial interface logic compatible with SMBus. The system master can invert the MAX7318 input data by writing
to the active-high polarity inversion register.
Any of the 16 I/O ports can be configured as an input or
output. A power-on reset (POR) initializes the 16 I/Os
as inputs. Three address select pins configure one of
64 slave ID addresses.
♦ 400kbps I2C-Compatible Serial Interface
The MAX7318 supports hot insertion. All port pins, the
INT output, SDA, SCL, and the slave address inputs
AD0–2 remain high impedance in power-down (V+ =
0V) with up to 6V asserted upon them.
The MAX7318 is available in 24-pin SO, SSOP, TSSOP,
and thin QFN packages and is specified over the -40°C
to +125°C automotive temperature range.
For applications requiring an SMBus timeout function,
refer to the MAX7311 data sheet.
♦ Low Standby Current (5.4µA typ)
Applications
Servers
RAID Systems
Industrial Control
Medical Equipment
PLCs
Instrumentation and Test Measurement
♦ 2V to 5.5V Operation
♦ 5.5V Overvoltage-Tolerant I/Os
♦ Supports Hot Insertion
♦ 16 I/O Pins that Default to Inputs on Power-Up
♦ 100kΩ Pullup on Each I/O
♦ Open-Drain Interrupt Output (INT)
♦ Noise Filter on SCL/SDA Inputs
♦ 64 Slave ID Addresses Available
♦ Polarity Inversion
♦ 4mm ✕ 4mm, 0.8mm Thin QFN Package
♦ -40°C to +125°C Operation
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX7318AWG -40°C to +125°C 24 Wide SO
—
MAX7318AAG
-40°C to +125°C 24 SSOP
—
MAX7318ATG
-40°C to +125°C
MAX7318AUG
-40°C to +125°C 24 TSSOP
24 Thin QFN
(4mm ✕ 4mm)
T2444-4
—
SMBus is a trademark of Intel Corp.
INT 1
I/O11
16
I/O13
17
I/O12
I/O15
18
I/O14
TOP VIEW
AD0
Pin Configurations
15
14
13
24 V+
AD1 2
SCL 19
12 I/O10
SDA 20
11 I/O9
23 SDA
AD2 3
22 SCL
V+ 21
I/O0 4
GND
8
I/O7
AD2 24
7
I/O6
19 I/O14
16 I/O11
I/O6 10
15 I/O10
I/O7 11
14 I/O9
GND 12
13 I/O8
3
4
5
6
I/O5
17 I/O12
I/O5 9
2
I/O4
I/O4 8
1
I/O3
18 I/O13
I/O2
I/O3 7
9
AD1 23
20 I/O15
I/O1
I/O2 6
MAX7318
MAX7318ATG
INT 22
I/O0
I/O1 5
10 I/O8
21 AD0
THIN QFN
TSSOP/SSOP/SO
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7318
General Description
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGS
V+ to GND ................................................................-0.3V to +6V
I/O0–I/O15 as Inputs ....................................(GND - 0.3V) to +6V
SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V
Maximum V+ Current......................................................+250mA
Maximum GND Current ...................................................-250mA
DC Input Current on I/O0–I/O15 .......................................±20mA
DC Output Current on I/O0–I/O15 ....................................±80mA
Continuous Power Dissipation (TA = +70°C)
24-Pin Wide SO (derate 11.8mW/°C above +70°C) ....941mW
24-Pin SSOP (derate 8.0mW/°C above +70°C) ...........640mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW
24-Pin Thin QFN (derate 20.8mW/°C above +70°C) .1667mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Supply Voltage
V+
Supply Current
I+
Standby Current
Power-On Reset Voltage
ISTBY
CONDITIONS
MIN
TYP
2.0
All I/Os unloaded,
fSCL = 400kHz
All I/Os unloaded,
fSCL = 0
MAX
UNITS
5.5
V
V+ = 2V
24
V+ = 3.3V
45
62
V+ = 5.5V
83
124
V+ = 2V
4.8
12.1
V+ = 3.3V
5.4
14.4
V+ = 5.5V
6.4
19.4
1.4
1.7
V
0.3 x V+
V
0.4
V
+1
µA
VPOR
36
µA
µA
SCL, SDA
Input-Voltage Low
VIL
Input-Voltage High
VIH
Low-Level Output Voltage
VOL
Leakage Current
0.7 x V+
V
ISINK = 6mA
IL
-1
Input Capacitance
10
pF
I/O_
Input-Voltage Low
VIL
Input-Voltage High
VIH
0.8
1.8
Input Leakage Current
TA = -40°C to +85°C; includes internal
pullup current, VIO = V+
Internal Pullup Current
TA = -40°C to +85°C, VIO = 0
Low-Level Output Current
ISINK
34
V+ = 2V, VOL = 0.5V
8.5
17
V+ = 3.3V, VOL = 0.5V
17
32
V+ = 5V, VOL = 0.5V
High Output Current
ISOURCE
V+ = 3.3V, VOH = 2.4V
V
V
1
µA
100
µA
mA
43
29
V+ = 5V, VOH = 4.5V
41
mA
31
AD0, AD1, AD2
Input-Voltage Low
VIL
Input-Voltage High
VIH
2
0.3 x V+
0.7 x V+
_______________________________________________________________________________________
V
V
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Leakage Current
MIN
TYP
-1
Input Capacitance
MAX
UNITS
+1
µA
4
pF
INT
Low-Level Output Current
IOL
VOL = 0.4V
6
mA
AC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
Figure 2
1.3
µs
Hold Time (Repeated) START
Condition
tHD,STA
Figure 2
0.6
µs
Repeated START Condition
Setup Time
tSU,STA
Figure 2
0.6
µs
STOP Condition Setup Time
tSU,STO
Figure 2
0.6
Data Hold Time
tHD,DAT
Figure 2 (Note 2)
Data Setup Time
tSU,DAT
Figure 2
100
ns
SCL Low Period
tLOW
Figure 2
1.3
µs
SCL High Period
tHIGH
Figure 2
0.7
SDA Fall Time
tF
Figure 2 (Notes 3, 4)
Pulse Width of Spike Suppressed
tSP
(Note 5)
tPV
Figure 7
µs
0.9
µs
µs
V+ < 3.3V
500
V+ ≥ 3.3V
250
50
ns
ns
PORT TIMING
Output Data Valid
3
µs
Input Data Setup Time
27
µs
Input Data Hold Time
0
µs
INTERRUPT TIMING
Interrupt Valid
tIV
Figure 9
30.5
µs
Interrupt Reset
tIR
Figure 9
2
µs
Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL
signal) to bridge the undefined region SCL’s falling edge.
Note 3: CB = total capacitance of one bus line in pF.
Note 4: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tF.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
_______________________________________________________________________________________
3
MAX7318
DC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
60
50
V+ = 3.3V
40
30
20
V+ = 2V
V+ = 5V
8
V+ = 3.3V
6
4
V+ = 2V
70
60
50
40
30
20
2
10
0
0
-25
0
25
50
75
100
125
-50
-25
50
MAX7318 toc04
V+ = 2V
TA = -40°C
50
75
100
V+ = 3.3V
50
8
6
4
2
0
0.2
0.3
0.4
0.5
TA = +25°C
25
20
TA = +125°C
20
TA = +125°C
15
10
5
5
0
0
0.1
0.2
0.3
0.4
0.5
0
0.6
0.1
0.2
0.3
0.4
VOL (V)
I/O OUTPUT LOW VOLTAGE
vs. TEMPERATURE
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
V+ = 5V, ISINK = 10mA
V+ = 2V
TA = -40°C
20
50
MAX7318 toc08
MAX7318 toc07
25
300
V+ = 2V, ISINK = 10mA
150
V+ = 2V, ISINK = 1mA
V+ = 5V, ISINK = 1mA
10
25
25
20
TA = +125°C
10
5
0
0
0
TA = +25°C
30
15
5
0
-25
0.5
35
15
TA = +125°C
100
TA = -40°C
40
ISOURCE (mA)
ISOURCE (mA)
200
V+ = 3.3V
45
TA = +25°C
250
-50
25
VOL (V)
350
50
TA = +25°C
VOL (V)
400
5.5
30
10
0.6
5.0
TA = -40°C
35
30
0
0.1
4.5
40
TA = -40°C
15
0
4.0
V+ = 5V
45
ISINK (mA)
TA = +125°C
3.5
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
40
ISINK (mA)
TA = +25°C
3.0
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
35
16
14
12
10
2.5
SUPPLY VOLTAGE (V)
45
18
2.0
125
MAX7318 toc09
24
22
20
25
TEMPERATURE (°C)
TEMPERATURE (°C)
I/O SINK CURRENT
vs. OUTPUT LOW VOLTAGE
0
MAX7318 toc05
-50
MAX7318 toc06
0
ISINK (mA)
MAX7318 toc03
80
10
50
75
TEMPERATURE (°C)
4
fSCL = 400kHz
ALL I/Os UNLOADED
90
SUPPLY CURRENT (μA)
V+ = 5V
70
SUPPLY CURRENT (μA)
SUPPLY CURRENT (μA)
80
SCL = V+
ALL I/Os UNLOADED
10
100
MAX7318 toc02
fSCL = 400kHz
ALL I/Os UNLOADED
90
12
MAX7318 toc01
100
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
VOL (mV)
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
100
125
0
0.1
0.2
0.3
0.4
V+ - VOH (V)
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
V+ - VOH (V)
_______________________________________________________________________________________
0.5
0.6
0.7
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
I/O SOURCE CURRENT
vs. OUTPUT HIGH VOLTAGE
TA = -40°C
40
MAX7318 toc11
V+ = 5V
45
I/O HIGH VOLTAGE vs. TEMPERATURE
500
MAX7318 toc10
50
400
V+ = 2V, ISOURCE = 10mA
V+ - VOH (V)
ISOURCE (mA)
35
TA = +25°C
30
25
20
300
200
TA = +125°C
15
100
10
5
V+ = 5V, ISOURCE = 10mA
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
V+ - VOH (V)
Pin Description
PIN
TSSOP/
SSOP/SO
THIN
QFN
NAME
1
22
INT
Interrupt Output (Open Drain)
2
23
AD1
Address Input 1
3
24
AD2
4–11
1–8
I/O0–I/O7
GND
FUNCTION
Address Input 2
Input/Output Port 1
12
9
13–20
10–17
Supply Ground
21
18
AD0
Address Input 0
22
19
SCL
Serial Clock Line
23
20
SDA
Serial Data Line
24
21
V+
Supply Voltage. Bypass with a 0.047µF capacitor to GND.
—
—
EP
Exposed Pad on Package Underside. Connect to GND.
I/O8–I/O15 Input/Output Port 2
_______________________________________________________________________________________
5
MAX7318
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
AD0
INPUT/OUTPUT
PORT 1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
INPUT/OUTPUT
PORT 2
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
8 BIT
AD1
WRITE PULSE
AD2
READ PULSE
SCL
SMBus
CONTROL
INPUT
FILTER
SDA
8 BIT
N
WRITE PULSE
READ PULSE
V+
INT
POWER-ON
RESET
MAX7318
GND
Figure 1. Block Diagram
SDA
tBUF
tSU,STA
tSU,DAT
tHD,STA
tLOW
tSU,STO
tHD,DAT
SCL
tHIGH
tHD,STA
tR
tF
REPEATED START CONDITION
START CONDITION
STOP CONDITION
START CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Detailed Description
Serial Interface
The MAX7318 general-purpose input/output (GPIO)
peripheral provides up to 16 I/O ports, controlled
through an I 2 C-compatible serial interface. The
MAX7318 consists of input port registers, output port
registers, polarity inversion registers, and configuration
registers. Upon power-on, all I/O lines are set as inputs.
Three slave ID address select pins, AD0, AD1, and
AD2, choose one of 64 slave ID addresses, including
the eight addresses supported by the Phillips PCA9555.
Table 1 is the register address table. Tables 2–5 show
detailed register information.
The MAX7318 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the
MAX7318, and generates the SCL clock that synchronizes the data transfer (Figure 2).
6
Serial Addressing
_______________________________________________________________________________________
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
MAX7318
SDA
S
P
START
CONDITION
STOP
CONDITION
SCL
Figure 3. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 5. Acknowledge
Each transmission consists of a START condition sent by
a master, followed by the MAX7318 7-bit slave address
plus R/W bit, a register address byte, 1 or more data
bytes, and finally a STOP condition (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
START and STOP Conditions
Acknowledge
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When
the master is transmitting to the MAX7318, the MAX7318
_______________________________________________________________________________________
7
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
generates the acknowledge bit since the MAX7318 is
the recipient. When the MAX7318 is transmitting to the
master, the master generates the acknowledge bit.
Slave address pins AD2, AD1, and AD0 choose 1 of 64
slave ID addresses (Table 7).
Slave Address
The command byte is the first byte to follow the 8-bit
device slave address during a write transmission
(Table 1, Figure 7). The command byte is used to determine which of the following registers are written or read.
Data Bus Transaction
The MAX7318 has a 7-bit-long slave address (Figure 6).
The 8th bit following the 7-bit slave address is the R/W
bit. Set this bit low for a write command and high for a
read command.
Writing to Port Registers
Transmit data to the MAX7318 by sending the device
slave address and setting the LSB to a logic zero. The
command byte is sent after the address and determines which registers receive the data following the
command byte (Figure 7).
PROGRAMMABLE
SDA
A6
A5
A4
A3
A2
A1
A0
MSB
R/W
ACK
LSB
SDA
Figure 6. Slave Address
Table 1. Command-Byte Register
COMMAND BYTE
ADDRESS (hex)
FUNCTION
POWER-UP
DEFAULT
PROTOCOL
0x00
Input port 1
Read byte
XXXX XXXX
0x01
Input port 2
Read byte
XXXX XXXX
0x02
Output port 1
Read/write byte
1111 1111
0x03
Output port 2
Read/write byte
1111 1111
0x04
Port 1 polarity inversion
Read/write byte
0000 0000
0x05
Port 2 polarity inversion
Read/write byte
0000 0000
0x06
Port 1 configuration
Read/write byte
1111 1111
0x07
Port 2 configuration
Read/write byte
1111 1111
0xFF
Factory reserved. (Do not write to this register.)
SCL
1
2
3
4
5
6
7
8
S
SLAVE ADDRESS
R/W
START
CONDITION
—
9
COMMAND BYTE
SDA
—
A
0
0
ACKNOWLEDGE
FROM SLAVE
0
0
0
0
PORT 1 DATA
1
0 A
7
6
ACKNOWLEDGE
FROM SLAVE
5
4
3
PORT 2 DATA
2
1
0 A
7
6
ACKNOWLEDGE
FROM SLAVE
5
4
3
2
1
0
A
ACKNOWLEDGE
FROM SLAVE
WRITE TO PORT
DATA OUT PORT 1
tPV
READ FROM PORT 2
tPV
Figure 7. Writes to Output Registers Through Write-Byte Protocol
8
_______________________________________________________________________________________
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Reading Port Registers
To read the device data, the bus master must first send
the MAX7318 address with the R/W bit set to zero, followed by the command byte, which determines which
register is accessed. After a restart, the bus master
must then send the MAX7318 address with the R/W bit
set to 1. Data from the register defined by the command byte is then sent from the MAX7318 to the master
(Figures 8, 9).
ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS
S
COMMAND BYTE
0 A
SLAVE ADDRESS
A S
R/W
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
MSB
1 A
DATA
LSB
DATA FROM LOWER OR
UPPER BYTE OF REGISTER
MSB
A
DATA
LSB
NA P
0
P
ACKNOWLEDGE
FROM SLAVE
R/W
ACKNOWLEDGE
FROM SLAVE
MASTER TRANSMITTER BECOMES
MASTER RECEIVER AND SLAVE
RECEIVER BECOMES SLAVE TRANSMITTER
TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.
Figure 8. Read from Register
SCL
1
S
2
3
4
5
6
SLAVE ADDRESS
7
8
1
9
A
7
PORT 1 DATA
0
A
7
PORT 2 DATA
0
A
7
PORT 1 DATA
0
A
7
PORT 2 DATA
1
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MASTER
NONACKNOWLEDGE
FROM MASTER
READ FROM PORT 1
DATA INTO PORT 1
READ FROM PORT 2
DATA INTO PORT 2
INT
tIV
tIR
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE
STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS
VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.
Figure 9. Read from Input Registers
_______________________________________________________________________________________
9
MAX7318
The MAX7318’s eight registers are configured to operate as four register pairs: input ports, output ports,
polarity inversion ports, and configuration ports. After
sending 1 byte of data to one register, the next byte is
sent to the other register in the pair. For example, if the
first byte of data is sent to output port 2, then the next
byte of data is stored in output port 1. An unlimited
number of data bytes can be sent in one write transmission. This allows each 8-bit register to be updated independently of the other registers.
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Input/Output Port
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read transmission, but the final byte received must not be
acknowledged by the bus master.
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input with
a nominal 100kΩ pullup to V+. All inputs are overvoltage
protected to 5.5V, independent of supply voltage. When
a port is configured as an output, either Q1 or Q2 is on,
depending on the state of the output port register. When
V+ powers up, an internal power-on reset sets all registers to their respective defaults (Table 1).
Interrupt (INT)
The open-drain interrupt output, INT, activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an output does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused by
port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Input Port Registers
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
OUTPUT PORT
REGISTER DATA
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
CONFIGURATION
REGISTER
SET
D
Q
VDD
Q1
100kΩ
I/O PIN
Q
CLR
DATA FROM
SHIFT REGISTER
WRITE PULSE
SET
D
Q
Q
CLR
OUTPUT PORT
REGISTER
Q2
GND
INPUT PORT
REGISTER
SET
Q
D
INPUT PORT
REGISTER DATA
READ PULSE
Q
CLR
TO INT
POWER-ON
RESET
DATA FROM
SHIFT REGISTER
WRITE POLARITY
PULSE
SET
D
Q
POLARITY
REGISTER
DATA
Q
CLR
POLARITY INVERSION
REGISTER
Figure 10. Simplified Schematic of I/Os
10
______________________________________________________________________________________
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
MAX7318
Table 2. Registers 0x00, 0x01—Input Port Registers
BIT
I7
I6
I5
I4
I3
I2
I1
I0
I15
I14
I13
I12
I11
I10
I9
I8
Table 3. Registers 0x02, 0x03—Output Port Registers
BIT
Power-up default
O7
O6
O5
O4
O3
O2
O1
O0
O15
O14
O13
O12
O11
O10
O9
O8
1
1
1
1
1
1
1
1
Table 4. Registers 0x04, 0x05—Polarity Inversion Registers
BIT
Power-up default
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
0
0
0
0
0
0
0
0
Table 5. Registers 0x06, 0x07—Configuration Registers
BIT
Power-up default
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
1
1
1
1
1
1
1
Output Port Registers
The output port registers (Table 3) set the outgoing
logic levels of the I/Os defined as outputs by the
respective configuration register. Reads from the output
port registers reflect the value that is in the flip-flop controlling the output selection, not the actual I/O value.
Standby
The MAX7318 goes into standby when the I2C bus is
idle. Standby supply current is typically 5.4µA.
Applications Information
Hot Insertion
Polarity Inversion Registers
The polarity inversion registers (Table 4) enable polarity
inversion of pins defined as inputs by the respective
port configuration registers. Set the bit in the polarity
inversion register to invert the corresponding port pin’s
polarity. Clear the bit in the polarity inversion register to
retain the corresponding port pin’s original polarity.
The I/O ports I/O0–I/O15, interrupt output INT, and serial
interface SDA, SCL, AD0–2 remain high impedance with
up to 6V asserted on them when the MAX7318 is powered down (V+ = 0V). The MAX7318 can therefore be
used in hot-swap applications. Note that each I/O’s
100kΩ pullup effectively becomes a 100kΩ pulldown
when the MAX7318 is powered down.
Configuration Registers
The configuration registers (Table 5) configure the
directions of the I/O pins. Set the bit in the respective
configuration register to enable the corresponding port
as an input. Clear the bit in the configuration register to
enable the corresponding port as an output.
The MAX7318 operates from a supply voltage of 2V to
5.5V. Bypass the power supply to GND with a 0.047µF
capacitor as close to the device as possible. For the
QFN version, connect the exposed pad to GND.
Power-Supply Consideration
______________________________________________________________________________________
11
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Table 6. MAX7318 Address Map
12
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
ADDRESS (hex)
GND
SCL
GND
0
0
1
0
0
0
0
0x20
GND
SCL
V+
0
0
1
0
0
0
1
0x22
GND
SDA
GND
0
0
1
0
0
1
0
0x24
GND
SDA
V+
0
0
1
0
0
1
1
0x26
V+
SCL
GND
0
0
1
0
1
0
0
0x28
V+
SCL
V+
0
0
1
0
1
0
1
0x2A
V+
SDA
GND
0
0
1
0
1
1
0
0x2C
V+
SDA
V+
0
0
1
0
1
1
1
0x2E
GND
SCL
SCL
0
0
1
1
0
0
0
0x30
GND
SCL
SDA
0
0
1
1
0
0
1
0x32
GND
SDA
SCL
0
0
1
1
0
1
0
0x34
GND
SDA
SDA
0
0
1
1
0
1
1
0x36
V+
SCL
SCL
0
0
1
1
1
0
0
0x38
V+
SCL
SDA
0
0
1
1
1
0
1
0x3A
V+
SDA
SCL
0
0
1
1
1
1
0
0x3C
V+
SDA
SDA
0
0
1
1
1
1
1
0x3E
GND
GND
GND
0
1
0
0
0
0
0
0x40
GND
GND
V+
0
1
0
0
0
0
1
0x42
GND
V+
GND
0
1
0
0
0
1
0
0x44
GND
V+
V+
0
1
0
0
0
1
1
0x46
V+
GND
GND
0
1
0
0
1
0
0
0x48
V+
GND
V+
0
1
0
0
1
0
1
0x4A
V+
V+
GND
0
1
0
0
1
1
0
0x4C
V+
V+
V+
0
1
0
0
1
1
1
0x4E
GND
GND
SCL
0
1
0
1
0
0
0
0x50
GND
GND
SDA
0
1
0
1
0
0
1
0x52
GND
V+
SCL
0
1
0
1
0
1
0
0x54
GND
V+
SDA
0
1
0
1
0
1
1
0x56
V+
GND
SCL
0
1
0
1
1
0
0
0x58
V+
GND
SDA
0
1
0
1
1
0
1
0x5A
V+
V+
SCL
0
1
0
1
1
1
0
0x5C
V+
V+
SDA
0
1
0
1
1
1
1
0x5E
______________________________________________________________________________________
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
AD2
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
ADDRESS (hex)
SCL
SCL
GND
1
0
1
0
0
0
0
0xA0
SCL
SCL
V+
1
0
1
0
0
0
1
0xA2
SCL
SDA
GND
1
0
1
0
0
1
0
0xA4
SCL
SDA
V+
1
0
1
0
0
1
1
0xA6
SDA
SCL
GND
1
0
1
0
1
0
0
0xA8
SDA
SCL
V+
1
0
1
0
1
0
1
0xAA
SDA
SDA
GND
1
0
1
0
1
1
0
0xAC
SDA
SDA
V+
1
0
1
0
1
1
1
0xAE
SCL
SCL
SCL
1
0
1
1
0
0
0
0xB0
SCL
SCL
SDA
1
0
1
1
0
0
1
0xB2
SCL
SDA
SCL
1
0
1
1
0
1
0
0xB4
0xB6
SCL
SDA
SDA
1
0
1
1
0
1
1
SDA
SCL
SCL
1
0
1
1
1
0
0
0xB8
SDA
SCL
SDA
1
0
1
1
1
0
1
0xBA
SDA
SDA
SCL
1
0
1
1
1
1
0
0xBC
SDA
SDA
SDA
1
0
1
1
1
1
1
0xBE
SCL
GND
GND
1
1
0
0
0
0
0
0xC0
SCL
GND
V+
1
1
0
0
0
0
1
0xC2
SCL
V+
GND
1
1
0
0
0
1
0
0xC4
0xC6
SCL
V+
V+
1
1
0
0
0
1
1
SDA
GND
GND
1
1
0
0
1
0
0
0xC8
SDA
GND
V+
1
1
0
0
1
0
1
0xCA
SDA
V+
GND
1
1
0
0
1
1
0
0xCC
SDA
V+
V+
1
1
0
0
1
1
1
0xCE
SCL
GND
SCL
1
1
0
1
0
0
0
0xD0
SCL
GND
SDA
1
1
0
1
0
0
1
0xD2
SCL
V+
SCL
1
1
0
1
0
1
0
0xD4
SCL
V+
SDA
1
1
0
1
0
1
1
0xD6
SDA
GND
SCL
1
1
0
1
1
0
0
0xD8
SDA
GND
SDA
1
1
0
1
1
0
1
0xDA
SDA
V+
SCL
1
1
0
1
1
1
0
0xDC
SDA
V+
SDA
1
1
0
1
1
1
1
0xDE
Chip Information
TRANSISTOR COUNT: 12,994
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX7318
Table 6. MAX7318 Address Map (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
N
E
DIM
A
A1
B
C
e
E
H
L
H
MAX
MIN
0.104
0.093
0.012
0.004
0.019
0.014
0.013
0.009
0.050
0.299
0.291
0.394
0.419
0.050
0.016
SOICW.EPS
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
MILLIMETERS
MIN
2.35
0.10
0.35
0.23
MAX
2.65
0.30
0.49
0.32
1.27
7.40
7.60
10.00
10.65
0.40
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
D
D
D
A
B
e
FRONT VIEW
MIN
0.398
0.447
0.496
0.598
0.697
MAX
0.413
0.463
0.512
0.614
0.713
MILLIMETERS
MIN
10.10
11.35
12.60
15.20
17.70
MAX
10.50
11.75
13.00
15.60
18.10
N MS013
16
AA
18
AB
20 AC
24 AD
28 AE
C
0∞-8∞
A1
L
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .300" SOIC
APPROVAL
DOCUMENT CONTROL NO.
21-0042
14
______________________________________________________________________________________
REV.
B
1
1
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
SSOP.EPS
2
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
0.09
0.20
0.004 0.008
SEE VARIATIONS
D
E
e
0.205
0.212
0.0256 BSC
5.20
INCHES
D
D
D
D
D
5.38
MILLIMETERS
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
A1
L
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
1
______________________________________________________________________________________
15
MAX7318
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
16
______________________________________________________________________________________
I
1
1
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
24L QFN THIN.EPS
______________________________________________________________________________________
17
MAX7318
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
18
______________________________________________________________________________________
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
REVISION
NUMBER
REVISION
DATE
0
8/04
Initial release
—
1
—
—
—
2
—
—
—
3
12/07
DESCRIPTION
Corrected error in General Description; various style edits; updated TSSOP and
TQFN package outlines.
PAGES
CHANGED
1, 15, 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX7318
Revision History
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