RL78/G1A Datasheet

RL78/G1A Datasheet
Datasheet
Specifications in this document are tentative and subject to change.
RL78/G1A
R01DS0151EJ0100
Rev.1.00
2013.09.25
RENESAS MCU
Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and
0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz
1.
1.1
<R>
OUTLINE
Features
Ultra-Low Power Technology
• 1.6 V to 3.6 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.57 µA
• Snooze: 0.7 mA (UART), 0.6 mA (ADC)
• Operating: 66 µA/MHz
16-bit RL78 CPU Core
• Delivers 41 DMIPS at maximum operating frequency
of 32 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 16 KB to 64 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
• Data Flash with background operation
• Data flash size: 4 KB
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 3.6 V
RAM
• 2 KB to 4 KB size options
• Supports operands or instructions
• Back-up retention in all modes
<R>
High-speed On-chip Oscillator
• 32 MHz with +/− 1% accuracy over voltage (1.8 V to
3.6 V) and temperature (−20 °C to +85 °C)
• Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1
MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
R01DS0151EJ0100 Rev.1.00
2013.09.25
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
• Up to 6 x I2C master
2
• Up to 1 x I C multi-master
• Up to 6 x CSI/SPI (7-, 8-bit)
• Up to 3 x UART (7-, 8-, 9-bit)
• Up to 1 x LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 28 channels, 12-bit resolution, 3.375 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/ frequency detection
• ADC self-test
General Purpose I/O
• 3.6 V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
• Extended: −40 °C to +105 °C
Package Type and Pin Count
From 3 mm x 3 mm to 10 mm x 10 mm
QFP: 48, 64
QFN: 32, 48
LGA: 25
BGA: 64
Page 1 of 123
RL78/G1A
1. OUTLINE
{ ROM, RAM capacities
Flash ROM
Data flash
RAM
Note
RL78/G1A
25 pins
32 pins
48 pins
64 pins
R5F10E8E
R5F10EBE
R5F10EGE
R5F10ELE
64 KB
4 KB
4 KB
48 KB
4 KB
3 KB
R5F10E8D
R5F10EBD
R5F10EGD
R5F10ELD
32 KB
4 KB
2 KB
R5F10E8C
R5F10EBC
R5F10EGC
R5F10ELC
16 KB
4 KB
2 KB
R5F10E8A
R5F10EBA
R5F10EGA
−
Note
This is about 3 KB when the self-programming function and data flash function are used.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 2 of 123
RL78/G1A
1.2
1. OUTLINE
List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A
Part No. R 5 F 1 0 E L C A x x x F B # V 0
Packing
#U0 : Tray (HWQFN, VFBGA, WFLGA)
#V0 : Tray (LFQFP)
#W0 : Embossed Tape (HWQFN, VFBGA, WFLGA)
#X0 : Embossed Tape (LFQFP)
Package type:
BG : VFBGA, 0.40 mm pitch
FB : LFQFP, 0.50 mm pitch
LA : WFLGA, 0.50 mm pitch
NA : HWQFN, 0.50 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications : TA = −40˚C to 85˚C
G : Industrial applications : TA = −40˚C to 105˚C
ROM capacity:
A
C
D
E
:
:
:
:
16 KB
32 KB
48 KB
64 KB
Pin count:
8 :
B:
G:
L :
25-pin
32-pin
48-pin
64-pin
RL78/G1A group
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Caution The part number above is valid as of when this manual was issued. For the latest part number,
see the web page of the target product on the Renesas Electronics website.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 3 of 123
RL78/G1A
1. OUTLINE
<R>
Table 1-1.
Pin count
25 pins
Package
25-pin plastic WFLGA
List of Ordering Part Numbers
Note 1
Fields of Application
A
(3 × 3 mm, 0.5 mm pitch)
Ordering Part Number
R5F10E8AALA#U0, R5F10E8CALA#U0,
R5F10E8DALA#U0, R5F10E8EALA#U0,
R5F10E8AALA#W0, R5F10E8CALA#W0,
R5F10E8DALA#W0, R5F10E8EALA#W0
Note 2
G
R5F10E8AGLA#U0, R5F10E8CGLA#U0,
R5F10E8DGLA#U0, R5F10E8EGLA#U0,
R5F10E8AGLA#W0, R5F10E8CGLA#W0,
R5F10E8DGLA#W0, R5F10E8EGLA#W0
32 pins
32-pin plastic HWQFN
A
(5 × 5 mm, 0.5 mm pitch)
R5F10EBAANA#U0, R5F10EBCANA#U0,
R5F10EBDANA#U0, R5F10EBEANA#U0,
R5F10EBAANA#W0, R5F10EBCANA#W0,
R5F10EBDANA#W0, R5F10EBEANA#W0
G
R5F10EBAGNA#U0, R5F10EBCGNA#U0,
R5F10EBDGNA#U0, R5F10EBEGNA#U0,
R5F10EBAGNA#W0, R5F10EBCGNA#W0,
R5F10EBDGNA#W0, R5F10EBEGNA#W0
48 pins
48-pin plastic LFQFP
A
(7 × 7 mm, 0.5 mm pitch)
R5F10EGAAFB#V0, R5F10EGCAFB#V0,
R5F10EGDAFB#V0, R5F10EGEAFB#V0,
R5F10EGAAFB#X0, R5F10EGCAFB#X0,
R5F10EGDAFB#X0, R5F10EGEAFB#X0
G
R5F10EBAGNA#V0, R5F10EBCGNA#V0,
R5F10EBDGNA#V0, R5F10EBEGNA#V0,
R5F10EBAGNA#X0, R5F10EBCGNA#X0,
R5F10EBDGNA#X0, R5F10EBEGNA#X0
48-pin plastic HWQFN
A
(7 × 7 mm, 0.5 mm pitch)
R5F10EGAANA#U0, R5F10EGCANA#U0,
R5F10EGDANA#U0, R5F10EGEANA#U0,
R5F10EGAANA#W0, R5F10EGCANA#W0,
R5F10EGDANA#W0, R5F10EGEANA#W0
G
R5F10EGAGNA#U0, R5F10EGCGNA#U0,
R5F10EGDGNA#U0, R5F10EGEGNA#U0,
R5F10EGAGNA#W0, R5F10EGCGNA#W0,
R5F10EGDGNA#W0, R5F10EGEGNA#W0
64 pins
64-pin plastic LFQFP
(10 × 10 mm, 0.5 mm
pitch)
A
R5F10ELCAFB#V0, R5F10ELDAFB#V0, R5F10ELEAFB#V0,
R5F10ELCAFB#X0, R5F10ELDAFB#X0, R5F10ELEAFB#X0
G
R5F10ELCGFB#V0, R5F10ELDGFB#V0,
R5F10ELEGFB#V0,
R5F10ELCGFB#X0, R5F10ELDGFB#X0, R5F10ELEGFB#X0
64-pin plastic VFBGA
A
(4 × 4 mm, 0.4 mm pitch)
R5F10ELCABG#U0, R5F10ELDABG#U0,
R5F10ELEABG#U0, R5F10ELCABG#W0,
R5F10ELDABG#W0, R5F10ELEABG#W0
Note 2
G
R5F10ELCGBG#U0, R5F10ELDGBG#U0,
R5F10ELEGBG#U0, R5F10ELCGBG#W0,
R5F10ELDGBG#W0, R5F10ELEGBG#W0
Notes 1.
2.
Caution
For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G1A.
In planning
The part number above is valid as of when this manual was issued. For the latest part number,
see the web page of the target product on the Renesas Electronics website.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 4 of 123
RL78/G1A
1.3
1.3.1
1. OUTLINE
Pin Configuration (Top View)
25-pin products
• 25-pin plastic WFLGA (3 × 3 mm, 0.50 mm pitch)
Bottom View
Top View
5
4
3
2
1
A
B
C
D
E
E
A
B
RESET
5
4
P122/X2/
EXCLK
P137/INTP0
P121/X1
VDD
3
REGC
VSS
P60/SCLA0
P61/SDAA0
1
A
B
B
A
C
D
E
P03/ANI16/
RxD1/TO00/
(KR1)
P23/ANI3/
(KR3)
AVSS
P02/ANI17/
TxD1/TI00/
(KR0)
P22/ANI2/
(KR2)
AVDD
P21/ANI1/
AVREFM
P11/ANI20/
SI00/SDA00/
RxD0/
TOOLRxD
P51/ANI25/
SO11/INTP2
P10/ANI18/
SCK00/SCL00
P12/ANI21/
SO00/TxD0/
TOOLTxD
P20/ANI0/
AVREFP
P30/ANI27/
SCK11/SCL11/
INTP3
2
C
INDEX MARK
INDEX MARK
P40/TOOL0
D
P31/ANI29/TI03/
TO03/PCLBUZ0
/INTP4
C
D
5
4
P50/ANI26/
SI11/SDA11
INTP1
3
2
1
E
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 5 of 123
RL78/G1A
1.3.2
1. OUTLINE
32-pin products
AVSS
AVDD
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)
• 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)
exposed die pad
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
INDEX MARK
P51/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P30/ANI27/SCK11/SCL11/INTP3
P70/ANI28/KR0
P31/ANI29/TI03/TO03/PCLBUZ0/INTP4
P62
P61/SDAA0
P60/SCLA0
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P24/ANI4/(KR5)
P23/ANI3/(KR4)
P22/ANI2/(KR3)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P03/ANI16/RxD1/TO00/(KR2)
P02/ANI17/TxD1/TI00/(KR1)
P120/ANI19/(KR0)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
<R>
3. It is recommended to connect an exposed die pad to Vss.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 6 of 123
RL78/G1A
1.3.3
1. OUTLINE
48-pin products
P140/PCLBUZ0/INTP6
P02/ANI17/TxD1/TI00/(KR0)
P03/ANI16/RxD1/TO00/(KR1)
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/(KR2)
P23/ANI3/(KR3)
P24/ANI4/(KR4)
P25/ANI5/(KR5)
P26/ANI6
P27/ANI7
• 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
AVSS
AVDD
P150/ANI8
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)
P16/TI01/TO01/INTP5
P51/ANI25/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P60/SCLA0
P61/SDAA0
P62
P63
P31/ANI29/TI03/TO03/INTP4
P75/SCK01/SCL01/INTP9/KR5
P74/SI01/SDA01/INTP8/KR4
P73/SO01/KR3
P72/SO21/KR2
P71/SI21/SDA21/KR1
P70/ANI28/SCK21/SCL21/KR0
P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ
P120/ANI19
P41/ANI30/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 7 of 123
RL78/G1A
1. OUTLINE
P140/PCLBUZ0/INTP6
P02/ANI17/TxD1/TI00/(KR0)
P03/ANI16/RxD1/TO00/(KR1)
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/(KR2)
P23/ANI3/(KR3)
P24/ANI4/(KR4)
P25/ANI5/(KR5)
P26/ANI6
P27/ANI7
• 48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
AVSS
AVDD
P150/ANI8
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)
P16/TI01/TO01/INTP5
P51/ANI25/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
P60/SCLA0
P61/SDAA0
P62
P63
P31/ANI29/TI03/TO03/INTP4
P75/SCK01/SCL01/INTP9/KR5
P74/SI01/SDA01/INTP8/KR4
P73/SO01/KR3
P72/SO21/KR2
P71/SI21/SDA21/KR1
P70/ANI28/SCK21/SCL21/KR0
P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ
P120/ANI19
P41/ANI30/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 8 of 123
RL78/G1A
1.3.4
1. OUTLINE
64-pin products
AVSS
AVDD
P150/ANI8
P151/ANI9/(KR6)
P152/ANI10/(KR7)
P153/ANI11/(KR8)
P154/ANI12/(KR9)
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/(KR5)
P16/TI01/TO01/INTP5
P51/ANI25/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
• 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6/(KR9)
P25/ANI5/(KR8)
P24/ANI4/(KR7)
P23/ANI3/(KR6)
P22/ANI2/(KR5)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10/(KR4)
P03/ANI16/SI10/SDA10/RxD1/(KR3)
P02/ANI17/SO10/TxD1/(KR2)
P01/TO00/(KR1)
P00/TI00/(KR0)
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI19
P43
P42/TI04/TO04
P41/ANI30/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
1 2 3 4 5
P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ
P05/TI05/TO05/KR8
P06/TI06/TO06/KR9
P70/ANI28/SCK21/SCL21/KR0
P71/SI21/SDA21/KR1
P72/SO21/KR2
P73/SO01/KR3
P74/SI01/SDA01/INTP8/KR4
P75/SCK01/SCL01/INTP9/KR5
P76/INTP10/KR6
P77/INTP11/KR7
P31/ANI29/TI03/TO03/INTP4
P63
P62
P61/SDAA0
P60/SCLA0
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 9 of 123
RL78/G1A
1. OUTLINE
• 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch)
Top View
Bottom View
8
7
6
5
4
3
2
1
A
B
C D E
F
G H
H
G
F
E D
C
B A
Index mark
Pin No.
Name
Pin No.
Name
Pin No.
Name
Pin No.
Name
A1
P05/TI05/TO05/KR8
C1
P51/ANI25/SO11
/INTP2
E1
P153/ANI11/(KR8)
G1
AVDD
A2
P30/ANI27/SCK11
/SCL11/INTP3
/RTC1HZ
C2
P71/SI21/SDA21/KR1
E2
P154/ANI12/(KR9)
G2
P25/ANI5/(KR8)
A3
P70/ANI28/SCK21
/SCL21/KR0
C3
P74/SI01/SDA01
/INTP8/KR4
E3
P10/ANI18/SCK00
/SCL00/(KR0)
G3
P24/ANI4/(KR7)
A4
P75/SCK01/SCL01
/INTP9/KR5
C4
P16/TI01/TO01/INTP5 E4
P11/ANI20/SI00
/SDA00/RxD0
/TOOLRxD/(KR1)
G4
P22/ANI2/(KR5)
A5
P77/INTP11/KR7
C5
P15/ANI24/SCK20
/SCL20/(KR5)
E5
P03/ANI16/SI10
/SDA10/RxD1/(KR3)
G5
P130
A6
P61/SDAA0
C6
P63
E6
P41/ANI30/TI07/TO07 G6
P02/ANI17/SO10/TxD1
/(KR2)
A7
P60/SCLA0
C7
VSS
E7
RESET
G7
P00/TI00/(KR0)
A8
EVDD0
C8
P121/X1
E8
P137/INTP0
G8
P124/XT2/EXCLKS
B1
P50/ANI26 /SI11
/SDA11/INTP1
D1
P13/ANI22/SO20
/TxD2/(KR3)
F1
P150/ANI8
H1
AVSS
B2
P72/SO21/KR2
D2
P06/TI06/TO06/KR9
F2
P151/ANI9/(KR6)
H2
P27/ANI7
B3
P73/SO01/KR3
D3
P12/ANI21/SO00
F3
/TxD0/TOOLTxD/(KR2)
P152/ANI10/(KR7)
H3
P26/ANI6/(KR9)
B4
P76/INTP10/KR6
D4
P14/ANI23/SI20/
SDA20/RxD2/(KR4)
F4
P21/ANI1/AVREFM
H4
P23/ANI3/(KR6)
B5
P31/ANI29/TI03/TO03 D5
/INTP4
P42/TI04/TO04
F5
P04/SCK10/SCL10
/(KR4)
H5
P20/ANI0/AVREFP
B6
P62
D6
P40/TOOL0
F6
P43
H6
P141/PCLBUZ1/INTP7
B7
VDD
D7
REGC
F7
P01/TO00/(KR1)
H7
P140/PCLBUZ0/INTP6
B8
EVSS0
D8
P122/X2/EXCLK
F8
P123/XT1
H8
P120/ANI19
Cautions 1.
2.
3.
Remarks 1.
2.
Make EVSS0 pin the same potential as VSS pin.
Make VDD pin the potential that is higher than EVDD0 pin.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
For pin identification, see 1.4
Pin Identification.
When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3.
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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2013.09.25
Page 10 of 123
RL78/G1A
1.4
1. OUTLINE
Pin Identification
ANI0 to ANI12,
PCLBUZ0, PCLBUZ1:
Programmable clock output/buzzer
ANI16 to ANI30:
Analog input
AVDD:
Analog power supply
REGC:
Regulator capacitance
AVSS:
Analog ground
RESET:
Reset
AVREFM:
A/D converter reference
RTC1HZ:
Real-time clock correction clock
output
potential (− side) input
AVREFP:
(1 Hz) output
A/D converter reference
RxD0 to RxD2:
potential (+ side) input
SCK00, SCK01, SCK10,
EVDD0:
Power supply for port
SCK11, SCK20, SCK21: Serial clock input/output
EVSS0:
Ground for port
SCLA0, SCL00, SCL01,
EXCLK:
External clock input (main
SCL10, SCL11, SCL20,
system clock)
SCL21:
External clock input
SDAA0, SDA00, SDA01,
(subsystem clock)
SDA10, SDA11, SDA20,
EXCLKS:
INTP0 to INTP11: Interrupt Request from
SDA21:
Receive data
Serial clock output
Serial data input/output
External
SI00, SI01, SI10, SI11,
KR0 to KR9:
Key return
SI20, SI21:
P00 to P06:
Port 0
SO00, SO01, SO10,
P10 to P16:
Port 1
SO11, SO20, SO21:
P20 to P27:
Port 2
TI00, TI01, TI03 to TI07: Timer input
P30, P31:
Port 3
TO00, TO01,
P40 to P43:
Port 4
TO03 to TO07:
Timer output
P50, P51:
Port 5
TOOL0:
Data input/output for tool
P60 to P63:
Port 6
TOOLRxD, TOOLTxD:
Data input/output for external device
P70 to P77:
Port 7
TxD0 to TxD2:
Transmit data
P120 to P124:
Port 12
VDD:
Power supply
P130, P137:
Port 13
VSS:
Ground
P140, P141:
Port 14
X1, X2:
Crystal oscillator (main system clock)
P150 to P154:
Port 15
XT1, XT2:
Crystal oscillator (subsystem clock)
R01DS0151EJ0100 Rev.1.00
2013.09.25
Serial data input
Serial data output
Page 11 of 123
RL78/G1A
1.5
1. OUTLINE
Block Diagram
1.5.1
25-pin products
TI00/P02
TO00/P03
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P02, P03
ch0
PORT 1
3
P10 to P12
PORT 2
4
P20 to P23
PORT 3
2
P30, P31
ch1
ch2
ch3
TI03/TO03/P31
PORT 4
P40
ch4
ch5
ch6
ch7
PORT 5
2
P50, P51
PORT 6
2
P60, P61
PORT 12
2
P121, P122
PORT 13
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
INTERVAL
TIMER
RL78
CPU
CORE
CODE FLASH MEMORY
(KEY RETURN)
P137
(KR0/P02, KR1/P03,
KR2/P22, KR3/P23)
(4)
ANI0/P20 to
ANI3/P23
4
DATA FLASH MEMORY
ANI16/P03, ANI17/P02,
ANI18/P10, ANI20/P11,
ANI21/P12, ANI25/P51,
ANI26/P50, ANI27/P30,
ANI29/P31
9
A/D CONVERTER
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
AVREFP/P20
AVREFM/P21
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
AVDD
VSS TOOLRxD/P11,
AVSS TOOLTxD/P12
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
IIC11
BCD
ADJUSTMENT
RESET
X1/P121
ON-CHIP
PCLBUZ0/P31
CLOCK OUTPUT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
HIGH-SPEED
BUZZER OUTPUT
SCL11/P30
SDA11/P50
POR/LVD
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
X2/EXCLK/P122
OSCILLATOR
VOLTAGE
REGULATOR
REGC
CRC
INTP0/P137
INTP1/P50
INTERRUPT
CONTROL
INTP2/P51
2
Remark
INTP3/P30,
INTP4/P31
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 12 of 123
RL78/G1A
<R>
1.5.2
1. OUTLINE
32-pin products
TI00/P02
TO00/P03
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P02, P03
ch0
PORT 1
6
P10 to P15
PORT 2
5
P20 to P24
PORT 3
2
P30, P31
ch1
ch2
TI03/TO03/P31
ch3
PORT 4
P40
ch4
PORT 5
2
P50, P51
ch6
PORT 6
3
P60 to P62
ch7
PORT 7
ch5
RxD2/P14
WINDOW
WATCHDOG
TIMER
PORT 12
P70
P120
P121, P122
2
PORT 13
LOW-SPEED
ON-CHIP
OSCILLATOR
INTERVAL
TIMER
CODE FLASH MEMORY
RL78
CPU
CORE
REAL-TIME
CLOCK
UART0
RxD1/P03
TxD1/P02
UART1
A/D CONVERTER
SCK00/P10
SI00/P11
SO00/P12
CSI00
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
TOOL0/P40
ON-CHIP DEBUG
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
LINSEL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SCK20/P15
SI20/P14
SO20/P13
CSI20
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
IIC20
Remark
POR/LVD
CONTROL
VSS, TOOLRxD/P11,
AVSS TOOLTxD/P12
2
RxD2/P14
TxD2/P13
13
UART2
KR0/P70
(KR0/P10 to KR5/P15)
(KR0/P120, KR1/P02, KR2/P03,
KR3/P22 to KR5/P24)
ANI0/P20 to
ANI4/P24
ANI16/P01, ANI17/P00, ANI18/P10,
ANI19/P120 to ANI24/P15, ANI26/P50,
ANI27/P30, ANI28/P70, ANI29/P31
AVREFP/P20
AVREFM/P21
RESET CONTROL
VDD,
AVDD
SCK11/P30
SI11/P50
SO11/P51
POWER ON RESET/
VOLTAGE
DETECTOR
RAM
1(6)
5
DATA FLASH MEMORY
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
KEY RETURN
P137
PCLBUZ0/P31,
PCLBUZ1/P15
CRC
SYSTEM
CONTROL
RESET
X1/P121
HIGH-SPEED
ON-CHIP
OSCILLATOR
X2/EXCLK/P122
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
BCD
ADJUSTMENT
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 13 of 123
RL78/G1A
<R>
1.5.3
1. OUTLINE
48-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P02, P03
TI00/P02
TO00/P03
ch0
PORT 1
7
P10 to P16
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
6
ch2
TI03/TO03/P31
ch3
ch4
ch5
ch6
TI07/TO07/P41
RxD2/P14
ch7
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 12
INTERVAL
TIMER
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10
SI00/P11
SO00/P12
SCK01/P75
SI01/P74
SO01/P73
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL11/P30
SDA11/P50
IIC11
SCL20/P15
SDA20/P14
SCL21/P70
SDA21/P71
Remark
P140
PORT 15
P150
9
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
VDD,
AVDD
ANI0/P20 to ANI7/P2, ANI8/P150
15
VSS, TOOLRxD/P11,
AVSS TOOLTxD/P12
6(6)
UART2
LINSEL
CSI20
CSI21
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
TOOL0/P40
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
DIRECT MEMORY
ACCESS CONTROL
PCLBUZ0/P140,
PCLBUZ1/P15
KR0/P70 to KR5/P75
(KR0/P10 to KR5/P15)
(KR0/P02, KR1/P03, KR2/P22 to KR5/P25)
RESET CONTROL
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CRC
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
INTP6/P140
IIC20
IIC21
ANI16/P03, ANI17/P02, ANI18/P147,
ANI19/P120, ANI20/P11 to ANI24/P15,
ANI25, P51, ANI26/P50, P30/ANI27,
ANI28/P70, ANI29/P31, ANI30/P41
POR/LVD
CONTROL
ON-CHIP DEBUG
SERIAL ARRAY
UNIT1 (2ch)
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
PORT 14
AVREFP/P20
AVREFM/P21
CSI01
SCL00/P10
SDA00/P11
P121 to P124
P130
P137
A/D CONVERTER
RAM
CSI11
4
PORT 13
DATA FLASH MEMORY
CSI00
SCK11/P30
SI11/P50
SO11/P51
RxD2/P14
TxD2/P13
CODE FLASH MEMORY
RL78
CPU
CORE
P70 to P75
P120
BCD
ADJUSTMENT
2
INTP8/P74,
INTP9/P75
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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2013.09.25
Page 14 of 123
RL78/G1A
1.5.4
1. OUTLINE
64-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
7
P00 to P06
TI00/P00
TO00/P01
ch0
PORT 1
7
P10 to P16
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
4
P40 to P43
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
8
ch2
TI03/TO03/P31
ch3
TI04/TO04/P42
ch4
TI05/TO05/P05
ch5
TI06/TO06/P06
ch6
TI07/TO07/P41
RxD2/P14
ch7
PORT 12
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
P70 to P77
P120
4
P121 to P124
P130
P137
PORT 13
INTERVAL
TIMER
REAL-TIME
CLOCK
PORT 14
2
P140, P141
PORT 15
5
P150 to P154
13
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P12
UART0
RxD1/P03
TxD1/P02
UART1
SCK00/P10
SI00/P11
SO00/P12
SCK01/P75
SI01/P74
SO01/P73
A/D CONVERTER
DATA FLASH MEMORY
KEY RETURN
CSI00
POWER ON RESET/
VOLTAGE
DETECTOR
CSI01
SCK10/P04
SI10/P03
SO10/P02
CSI10
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P75
SDA01/P74
IIC01
IIC10
SCL11/P30
SDA11/P50
IIC11
RESET CONTROL
VDD, VSS, TOOLRxD/P11,
EVDD0, EVSS0, TOOLTxD/P12
AVDD AVSS
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SDAA0/P61
SERIAL
INTERFACE IICA0
XT1/P123
OSCILLATOR
XT2/EXCLKS/P124
SCLA0/P60
VOLTAGE
REGULATOR
REGC
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
UART2
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
LINSEL
CSI20
DIRECT MEMORY
ACCESS CONTROL
PCLBUZ0/P140,
PCLBUZ1/P141
RxD2/P14
INTP0/P137
CRC
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTERRUPT
CONTROL
INTP5/P16
2
INTP6/P140,
INTP7/P141
2
INTP8/P74,
INTP9/P75
2
INTP10/P76,
INTP11/P77
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
Remark
TOOL0/P40
ON-CHIP DEBUG
2
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
POR/LVD
CONTROL
RAM
SERIAL ARRAY
UNIT1 (2ch)
TxD2/P13
KR0/P70 to KR7/P77, KR8/P05, KR9/P06
10 (10) (KR0/P00 to KR4/P04, KR5/P22 to KR9/P26)
(KR0/P10 to KR5/P15, KR6/P151 to KR9/P154)
ON-CHIP
SCL10/P04
SDA10/P03
RxD2/P14
15
CODE FLASH MEMORY
RL78
CPU
CORE
ANI0/P20 to ANI7/P27,
ANI8/P150 to ANI12/P154
ANI16/P03, ANI17/P02, ANI18/P10,
ANI19/P120, ANI20/P11 to ANI24/P15,
ANI25//P51, ANI26/P50, ANI27/P30,
ANI28/P70ANI29/P31, ANI30/P41
AVREFP/P20
AVREFM/P21
BCD
ADJUSTMENT
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 15 of 123
RL78/G1A
1.6
1. OUTLINE
Outline of Functions
(1/2)
Item
Code flash memory (KB)
Data flash memory (KB)
25-pin
32-pin
48-pin
64-pin
R5F10E8x
R5F10EBx
R5F10EGx
R5F10ELx
16 to 64
16 to 64
16 to 64
32 to 64
4
4
Note1
RAM (KB)
2 to 4
2 to 4
4
Note1
2 to 4
4
Note1
2 to 4
Note1
Address space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator
HS (High-speed main) mode
: 1 to 32 MHz (VDD = 2.7 to 3.6 V),
HS (High-speed main) mode
: 1 to 16 MHz (VDD = 2.4 to 3.6 V),
LS (Low-speed main) mode
: 1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (Low-voltage main) mode
: 1 to 4 MHz (VDD = 1.6 to 3.6 V)
−
Subsystem clock
XT1 (crystal) oscillation, external subsystem
clock input (EXCLKS) 32.768 kHz (TYP.)
Low-speed on-chip oscillator
15 kHz (TYP.)
General-purpose register
(8-bit register × 8) × 4 bank
Minimum instruction execution time
0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz
operation)
−
•
•
•
•
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
<R>
CMOS I/O
19
26
42
56
14
(N-ch O.D. I/O [VDD
withstand voltage]: 6)
20
(N-ch O.D. I/O [VDD
withstand voltage]: 9)
32
(N-ch O.D. I/O [VDD
withstand voltage]: 11)
46
(N-ch O.D. I/O [VDD
withstand voltage]: 12)
3
3
5
5
CMOS input
Timer
CMOS output
−
−
1
1
N-ch open-drain I/O
(6 V tolerance)
2
3
4
4
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
Note 2
1 channel
12-bit interval timer (IT)
Timer output
1 channel
2 channels (PWM outputs: 1
RTC output
Notes 1.
−
Note 3
)
4 channels
Note 3
)
(PWM outputs: 3
7 channels
Note 3
(PWM outputs: 6
)
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash
function are used.
<R>
2.
Only the constant-period interrupt function when the low-speed on-chip oscillator clock (fIL) is
3.
The number of PWM outputs varies depending on the setting of channels in use (the number of
selected.
masters and slaves).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 16 of 123
RL78/G1A
1. OUTLINE
(2/2)
Item
25-pin
R5F10E8x
32-pin
R5F10EBx
48-pin
R5F10EGx
64-pin
R5F10ELx
1
2
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,
2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,
2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz,
4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/12-bit resolution A/D converter
13 channels
18 channels
Serial interface
[25-pin products]
24 channels
28 channels
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
[32-pin products]
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART (UART supporting LIN-bus): 1 channel
[48-pin products]
2
• CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
• CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
2
• CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[64-pin products]
2
•
•
•
2
I C bus
2
CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
CSI: 2 channels/simplified I C: 2 channels/UART: 1 channel
2
CSI: 2 channels/simplified I C: 2 channels/UART (UART supporting LIN-bus): 1 channel
1 channel
1 channel
1 channel
Multiplier and
divider/multiply-accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
sources
External
24
27
6
Key interrupt
0 ch (4 ch)
6
Note 1
Note 1
1 ch (6 ch)
1 channel
27
27
10
13
6 ch
10 ch
Reset
•
•
•
•
•
•
•
Power-on-reset circuit
• Power-on-reset:
1.51 V (TYP.)
• Power-down-reset: 1.50 V (TYP.)
Voltage detector
•
•
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 3.6 V
Operating ambient temperature
TA = −40 to +85°C (A: Consumer application), TA = −40 to +105°C (G: Industrial application)
Notes 1.
2.
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Note 2
Internal reset by illegal instruction execution
Internal reset by RAM parity error
Internal reset by illegal-memory access
Rising edge :
Falling edge :
1.67 V to 3.14 V (12 stages)
1.63 V to 3.06 V (12 stages)
Can be used by the Peripheral I/O redirection register (PIOR).
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or
on-chip debug emulator.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
This chapter describes the following electrical specifications.
Target products
TA = −40 to +85°C
A: Consumer applications
R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA
R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA
R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB
R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA
R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB
R5F10ELCABG, R5F10ELDABG, R5F10ELEABG
G: Industrial applications
When TA = −40 to +105°C products is used in the range of TA = −40
to +85°C
R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA
R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB
R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA
R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for
development and evaluation.
Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. With products not provided with an EVDD0 or EVSS0 pin, replace EVDD0 with VDD, or replace
EVSS0 with VSS.
3. The pins mounted depend on the product.
See 1.3.1 25-pin products to 1.3.4 64-pin
products.
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2.1
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter
Symbols
Supply voltage
Conditions
VDD
Ratings
Unit
−0.5 to +6.5
V
EVDD0
−0.5 to +6.5
V
AVDD
−0.5 to +4.6
V
−0.3 to AVDD +0.3
Note 3
AVREFP
EVSS0
−0.5 to +0.3
AVSS
−0.5 to +0.3
V
V
−0.3 to AVDD +0.3
AVREFM
V
Note 3
V
and AVREFM ≤ AVREFP
REGC pin input voltage
VIREGC
−0.3 to +2.8
REGC
V
and −0.3 to VDD +0.3
Input voltage
VI1
−0.3 to EVDD0 +0.3
P00 to P06, P10 to P16, P30, P31, P40 to P43,
and −0.3 to VDD +0.3
P50, P51, P70 to P77, P120, P140, P141
Output voltage
V
Note 2
−0.3 to +6.5
VI2
P60 to P63 (N-ch open-drain)
VI3
P121 to P124, P137, EXCLK, EXCLKS, RESET
VI4
P20 to P27, P150 to P154
−0.3 to AVDD +0.3
P00 to P06, P10 to P16, P30, P31, P40 to P43,
−0.3 to EVDD0 +0.3
VO1
Note 1
−0.3 to VDD +0.3
V
Note 2
V
Note 2
V
Note 2
V
Note 2
V
P50, P51, P60 to P63, P70 to P77, P120, P130,
P140, P141
Analog input voltage
VO2
P20 to P27, P150 to P154
VAI1
ANI16 to ANI30
−0.3 to AVDD +0.3
−0.3 to EVDD0 +0.3
and −0.3 to AVREF(+) +0.3
VAI2
−0.3 to AVDD +0.3
ANI0 to ANI12
and −0.3 to AVREF(+) +0.3
Notes 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
V
Notes 2, 4
V
Notes 2, 4
This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Must be 4.6 V or lower.
4. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2.
AVREF(+): + side reference voltage of the A/D converter.
3.
VSS: Reference voltage
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P00 to P06, P10 to P16, P30, P31,
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.1
mA
−1.3
mA
40
mA
70
mA
100
mA
0.4
mA
P40 to P43, P50, P51, P70 to P77,
P120, P130, P140, P141
Total of all pins
P00 to P04, P40 to P43, P120,
−170 mA
P130, P140, P141
P05, P06, P10 to P16, P30, P31,
P50, P51, P70 to P77,
IOH2
Per pin
P20 to P27, P150 to P154
Total of all pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P16, P30, P31,
P40 to P43, P50, P51, P60 to P63,
P70 to P77, P120, P130, P140,
P141
Total of all pins
P00 to P04, P40 to P43, P120,
170 mA
P130, P140, P141
P05, P06, P10 to P16, P30, P31,
P50, P51, P60 to P63, P70 to P77
IOL2
Per pin
P20 to P27, P150 to P154
TA
In normal operation mode
Total of all pins
Operating ambient
temperature
6.4
mA
−40 to +85
°C
−65 to +150
°C
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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2.2
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Oscillator Characteristics
2.2.1
X1, XT1 oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
X1 clock oscillation
Resonator
Conditions
Ceramic resonator/crystal resonator
Note
frequency (fX)
XT1 clock oscillation
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
35
kHz
Crystal resonator
32
32.768
Note
frequency (fX)
Note Indicates only permissible oscillator frequency ranges. See AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
<R>
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register
and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
2.2.2
On-chip oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
clock frequency
Parameters
Conditions
fIH
MIN.
TYP.
MAX.
Unit
1
32
MHz
Notes 1, 2
High-speed on-chip oscillator
−20 to +85 °C
1.8 V ≤ VDD ≤ 3.6 V
−1.0
+1.0
%
1.6 V ≤ VDD < 1.8 V
−5.0
+5.0
%
−40 to −20 °C
1.8 V ≤ VDD ≤ 3.6 V
−1.5
+1.5
%
1.6 V ≤ VDD < 1.8 V
−5.5
+5.5
%
clock frequency accuracy
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
−15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. See AC Characteristics for instruction execution
time.
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2.3
2.3.1
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
DC Characteristics
Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
Conditions
Notes 1.
(1/5)
TYP.
MAX.
−10.0
Unit
Per pin for P00 to P06, P10 to P16,
P30, P31, P40 to P43, P50, P51,
P70 to P77, P120, P130, P140, P141
1.6 V ≤ EVDD0 ≤ 3.6 V
Total of P00 to P04, P40 to P43, P120,
P130, P140, P141
Note 3
(When duty ≤ 70%
)
2.7 V ≤ EVDD0 ≤ 3.6 V
−10.0
mA
Note 2
mA
1.8 V ≤ EVDD0 < 2.7 V
−5.0
mA
1.6 V ≤ EVDD0 < 1.8 V
−2.5
mA
2.7 V ≤ EVDD0 ≤ 3.6 V
−19.0
mA
1.8 V ≤ EVDD0 < 2.7 V
−10.0
mA
1.6 V ≤ EVDD0 < 1.8 V
−5.0
mA
Total of all pins
Note 3
)
(When duty ≤ 70%
1.6 V ≤ EVDD0 ≤ 3.6 V
−29.0
mA
Per pin for P20 to P27, P150 to P154
1.6 V ≤ AVDD ≤ 3.6 V
Total of all pins
Note 3
)
(When duty ≤ 70%
1.6 V ≤ AVDD ≤ 3.6 V
Total of P05, P06, P10 to P16, P30,
P31, P50, P51, P70 to P77,
Note 3
(When duty ≤ 70%
)
IOH2
MIN.
−0.1
Note 2
−1.3
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
VDD pins to an output pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain
mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
MIN.
TYP.
Per pin for P00 to P06, P10 to P16,
P30, P31, P40 to P43, P50, P51,
P70 to P77, P120, P130, P140, P141
20.0
Per pin for P60 to P63
15.0
Note 2
Total of P05, P06, P10 to P16, P30,
P31, P50, P51, P60 to P63,
P70 to P77
Note 3
)
(When duty ≤ 70%
mA
mA
mA
9.0
mA
4.5
mA
2.7 V ≤ EVDD0 ≤ 3.6 V
35.0
mA
1.8 V ≤ EVDD0 < 2.7 V
20.0
mA
1.6 V ≤ EVDD0 < 1.8 V
10.0
mA
50.0
mA
Per pin for P20 to P27, P150 to P154
Total of all pins
Note 3
)
(When duty ≤ 70%
Unit
15.0
Total of all pins
Note 3
)
(When duty ≤ 70%
Notes 1.
MAX.
Note 2
Total of P00 to P04, P40 to P43, P120, 2.7 V ≤ EVDD0 ≤ 3.6 V
P130, P140, P141
1.8 V ≤ EVDD0 < 2.7 V
Note 3
(When duty ≤ 70%
)
1.6 V ≤ EVDD0 < 1.8 V
IOL2
(2/5)
0.4
1.6 V ≤ AVDD ≤ 3.6 V
Note 2
5.2
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS0 and VSS pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can can be
calculated with the following expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P00 to P06, P10 to P16, P30, P31,
MIN.
Normal input buffer
(3/5)
TYP.
MAX.
Unit
0.8EVDD0
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
P40 to P43, P50, P51, P70 to P77,
high
P120, P140, P141
VIH2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P16, P43
3.3 V ≤ EVDD0 ≤ 3.6 V
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
VIH3
P20 to P27, P150 to P154
0.7AVDD
AVDD
V
VIH4
P60 to P63
0.7EVDD0
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
Normal input buffer
0
0.2EVDD0
V
P01, P03, P04, P10, P11,
TTL input buffer
0
0.5
V
P13 to P16, P43
3.3 V ≤ EVDD0 ≤ 3.6 V
0
0.32
V
Input voltage, low VIL1
P00 to P06, P10 to P16, P30, P31,
P40 to P43, P50, P51, P70 to P77,
P120, P140, P141
VIL2
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
VIL3
P20 to P27, P150 to P154
0
0.3AVDD
V
VIL4
P60 to P63
0
0.3EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 is EVDD0,
even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P00 to P06, P10 to P16, P30, P31,
2.7 V ≤ EVDD0 ≤ 3.6 V,
P40 to P43, P50, P51, P70 to P77,
IOH1 = −2.0 mA
P120, P130, P140, P141
1.8 V ≤ EVDD0 ≤ 3.6 V,
IOH1 = −1.5 mA
1.6 V ≤ EVDD0 ≤ 3.6 V,
IOH1 = −1.0 mA
VOH2
P20 to P27, P150 to P154
1.6 V ≤ AVDD ≤ 3.6 V,
IOH2 = −100 μA
Output voltage,
VOL1
low
P00 to P06, P10 to P16, P30, P31,
2.7 V ≤ EVDD0 ≤ 3.6 V,
P40 to P43, P50, P51, P70 to P77,
IOL1 = 3.0 mA
P120, P130, P140, P141
2.7 V ≤ EVDD0 ≤ 3.6 V,
TYP.
(4/5)
MAX.
Unit
EVDD0 −
V
0.6
EVDD0 −
V
0.5
EVDD0 −
V
0.5
AVDD −
V
0.5
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL1 = 1.5 mA
1.8 V ≤ EVDD0 ≤ 3.6 V,
IOL1 = 0.6 mA
1.6 V ≤ EVDD0 < 1.8 V,
IOL1 = 0.3 mA
VOL2
P20 to P27, P150 to P154
1.6 V ≤ AVDD ≤ 3.6 V,
IOL2 = 400 μA
VOL3
P60 to P63
2.7 V ≤ EVDD0 ≤ 3.6 V,
IOL3 = 3.0 mA
1.8 V ≤ EVDD0 ≤ 3.6 V,
IOL3 = 2.0 mA
1.6 V ≤ EVDD0 < 1.8 V,
IOL3 = 1.0 mA
Caution
P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain
mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Input leakage
ILIH1
Conditions
P00 to P06, P10 to P16, P30,
MIN.
(5/5)
TYP.
MAX.
Unit
VI = EVDD0
1
μA
1
μA
1
μA
10
μA
P31, P40 to P43, P50, P51,
current, high
P60 to P63, P70 to P77, P120,
P140, P141
ILIH2
P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIH4
P20 to P27, P150 to P154
VI = AVDD
1
μA
ILIL1
P00 to P06, P10 to P16,
VI = EVSS0
−1
μA
−1
μA
−1
μA
−10
μA
−1
μA
100
kΩ
P30, P31, P40 to P43,
current, low
P50, P51, P60 to P67,
P70 to P77, P120, P140, P141
ILIL2
P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
ILIL4
P20 to P27, P150 to P154
VI = AVSS
RU
P00 to P06, P10 to P16, P30,
VI = EVSS0, In input port
10
20
P31, P40 to P43, P50, P51,
resistance
P70 to P77, P120, P140, P141
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2.3.2
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply
Note 1
current
IDD1
(1/3)
Conditions
Operating
mode
HS (high-speed
Note 5
main) mode
MIN.
Note 3
fIH = 32 MHz
2.1
Normal
operation
VDD = 3.0 V
4.6
7.0
mA
Note 3
Normal
operation
VDD = 3.0 V
3.7
5.5
mA
Note 3
Normal
operation
VDD = 3.0 V
2.7
4.0
mA
Note 3
Normal
operation
VDD = 3.0 V
1.2
1.8
mA
VDD = 2.0 V
1.2
1.8
Note 3
Normal
operation
VDD = 3.0 V
1.2
1.7
VDD = 2.0 V
1.2
1.7
Normal
operation
Square
wave input
3.0
4.6
Resonator
connection
3.2
4.8
Square
wave input
1.9
2.7
Resonator
connection
1.9
2.7
Square
wave input
1.1
1.7
Resonator
connection
1.1
1.7
Square
wave input
1.1
1.7
Resonator
connection
1.1
1.7
Square
wave input
4.1
4.9
Resonator
connection
4.2
5.0
Square
wave input
4.2
4.9
Resonator
connection
4.3
5.0
Square
wave input
4.3
5.5
Resonator
connection
4.4
5.6
Square
wave input
4.5
6.3
Resonator
connection
4.6
6.4
Square
wave input
4.8
7.7
Resonator
connection
4.9
7.8
fIH = 8 MHz
LV (Low-voltage fIH = 4 MHz
Note 5
main) mode
Note 2
fMX = 20 MHz
VDD = 3.0 V
,
Note 2
fMX = 10 MHz
VDD = 3.0 V
LS (low-speed
Note 5
main) mode
,
Note 2
fMX = 8 MHz
VDD = 3.0 V
,
fSUB = 32.768 kHz
TA = −40°C
fSUB = 32.768 kHz
TA = +25°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +70°C
fSUB = 32.768 kHz
TA = +85°C
Normal
operation
Normal
operation
,
Note 2
fMX = 8 MHz
VDD = 2.0 V
Subsystem
clock mode
Unit
VDD = 3.0 V
fIH = 16 MHz
HS (high-speed
Note 5
main) mode
MAX.
Basic
operation
fIH = 24 MHz
LS (low-speed
Note 5
main) mode
TYP.
Normal
operation
Note 4
Note 4
Note 4
Note 4
Note 4
Normal
operation
Normal
operation
Normal
operation
Normal
operation
Normal
operation
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
(Notes and Remarks are listed on the next page.)
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RL78/G1A
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0.
The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, on-chip pull-up/pull-down resistors, and data flash rewriting.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low
power consumption oscillation (AMPHS1 = 1). Not including the current flowing into the RTC, 12-bit
interval timer and watchdog timer
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode:
VDD = 2.7 V to 3.6 [email protected] MHz to 32 MHz
VDD = 2.4 V to 3.6 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
VDD = 1.8 V to 3.6 [email protected] MHz to 8 MHz
LV (Low-voltage main) mode: VDD = 1.6 V to 3.6 [email protected] MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0151EJ0100 Rev.1.00
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RL78/G1A
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply
IDD2
current
Note 2
Note 1
HALT
HS (high-speed
mode
Note 7
main) mode
MIN.
main) mode
VDD = 3.0 V
0.54
1.63
mA
VDD = 3.0 V
0.44
1.28
mA
Note 4
VDD = 3.0 V
0.40
1.00
mA
VDD = 3.0 V
270
530
μA
VDD = 2.0 V
270
530
VDD = 3.0 V
435
640
VDD = 2.0 V
435
640
Square wave input
0.28
1.00
Resonator connection
0.45
1.17
Square wave input
0.19
0.60
Resonator connection
0.26
0.67
Square wave input
95
330
Resonator connection
145
380
Square wave input
95
330
Note 4
fIH = 8 MHz
Note 4
fIH = 4 MHz
Note 7
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
LS (low-speed
main) mode
Note 7
Note 3
fMX = 8 MHz
,
VDD = 3.0 V
Note 3
fMX = 8 MHz
,
VDD = 2.0 V
Resonator connection
145
380
Square wave input
0.25
0.57
Resonator connection
0.44
0.76
fSUB = 32.768 kHz
Square wave input
0.30
0.57
TA = +25°C
Resonator connection
0.49
0.76
fSUB = 32.768 kHz
Square wave input
0.38
1.17
TA = +50°C
Note 5
Subsystem clock fSUB = 32.768 kHz
mode
TA = −40°C
Note 5
Note 5
Resonator connection
0.57
1.36
Note 5
Square wave input
0.52
1.97
Resonator connection
0.71
2.16
fSUB = 32.768 kHz
Note 5
Square wave input
0.97
3.37
TA = +85°C
Resonator connection
1.16
3.56
TA = −40°C
0.16
0.50
TA = +25°C
0.23
0.50
TA = +50°C
0.34
1.10
TA = +70°C
0.46
1.90
TA = +85°C
0.75
3.30
fSUB = 32.768 kHz
TA = +70°C
IDD3
STOP
mode
μA
Note 7
HS (high-speed
main) mode
Unit
Note 7
LV (Low-voltage
main) mode
MAX.
Note 4
fIH = 24 MHz
LS (low-speed
TYP.
Note 4
fIH = 32 MHz
fIH = 16 MHz
Note 6
(2/3)
Conditions
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA
Note 8
(Notes and Remarks are listed on the next page.)
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RL78/G1A
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0.
The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, on-chip pull-up/pull-down resistors, and data flash rewriting.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1).
Including the current flowing into the RTC.
However, not including the current flowing into the 12-bit interval timer, and watchdog timer.
6. When subsystem clock is stopped. Not including the current flowing into the RTC, 12-bit interval timer,
watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 3.6 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD < 3.6 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 3.6 [email protected] MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
<R>
Parameter
Low-speed on-chip
Symbol
(3/3)
Conditions
MIN.
Note 1
IFIL
TYP.
MAX.
Unit
0.20
μA
0.02
μA
0.02
μA
μA
oscillator operating
current
RTC operating
IRTC
Notes 1, 2, 3
current
12-bit interval timer
IIT
Notes 1, 2, 4
operating current
Watchdog timer
Notes 1, 2, 5
fIL = 15 kHz
0.22
Notes 6, 7
AVDD = 3.0 V, When conversion at maximum speed
420
720
μA
14.0
25.0
μA
14.0
25.0
μA
25.0
μA
IWDT
operating current
A/D converter
operating current
IADC
AVREF(+) current
IAVREF
Note 8
Note 7
AVDD = 3.0 V, ADREFP1 = 0, ADREFP0 = 0
Note 10
AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1
Note 1
ADREFP1 = 1, ADREFP0 = 0
14.0
VDD = 3.0 V
75.0
μA
VDD = 3.0 V
75.0
μA
Notes 1, 11
0.08
μA
Notes 1, 12
2.5
12.2
mA
Notes 1, 13
2.5
12.2
mA
A/D converter
reference voltage
current
IADREF
Temperature
sensor operating
current
ITMP
LVD operating
ILVD
Notes 1, 9
Note 1
current
BGO operating
IBGO
current
Self-programming
IFSP
operating current
SNOOZE operating
ISNOZ
current
A/D converter
operation
(AVDD = 3.0 V)
Notes 1
The mode is performed
0.50
0.60
mA
During A/D conversion
Note 1
0.60
0.75
mA
During A/D conversion
Note 7
420
720
μA
0.70
0.84
mA
CSI/UART operation
Note 1
(Notes and Remarks are listed on the next page.)
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Notes 1. Current flowing to VDD.
<R>
2. When high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed
on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of
the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
ocsillator and the XT1 oscillator).
The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and IWDT
when the watchdog timer is in operation.
6. Current flowing only to the A/D converter.
The supply current of the RL78 microcontrollers is the sum of
IDD1 or IDD2 and IADC, IAVREF, IADREF when the A/D converter operates in an operation mode or the HALT
mode.
7. Current flowing to the AVDD.
8. Current flowing from the reference voltage source of A/D converter.
9. Operation current flowing to the internal reference voltage.
10. Current flowing to the AVREFP.
11. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
12. Current flowing only during data flash rewrite.
13. Current flowing only during self programming.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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RL78/G1A
2.4
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
AC Characteristics
(TA = −40 to +85°C, AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Instruction cycle (minimum TCY
instruction execution time)
Conditions
Main system
clock (fMAIN)
operation
μs
μs
LV (low-voltage 1.6 V ≤ VDD ≤ 3.6 V
main) mode
0.25
1
μs
1.8 V ≤ VDD ≤ 3.6 V
28.5
31.3
μs
1
μs
HS (high-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
1
μs
0.125
1
μs
LV (low-voltage 1.6 V ≤ VDD ≤ 3.6 V
main) mode
0.25
1
μs
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
2.7 V ≤ VDD ≤ 3.6 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1.6 V ≤ VDD < 1.8 V
tTIH, tTIL
TO00, TO01, TO03 to
TO07 output frequency
fTO
fPCL
tINTH, tINTL
Key interrupt input
high-level width, low-level
width
tKR
RESET low-level width
tRSL
ns
μs
Note
ns
2.7 V ≤ EVDD0 ≤ 3.6 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
1.8 V ≤ EVDD0 ≤ 3.6 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LV (low-voltage main)
mode
1.6 V ≤ EVDD0 ≤ 3.6 V
2
MHz
HS (high-speed main)
mode
2.7 V ≤ EVDD0 ≤ 3.6 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
1.8 V ≤ EVDD0 ≤ 3.6 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
1.8 V ≤ EVDD0 ≤ 3.6 V
4
MHz
2
MHz
HS (high-speed main)
mode
LS (low-speed main)
mode
Interrupt input high-level
width, low-level width
120
13.7
1/fMCK+10
LS (low-speed main)
mode
PCLBUZ0, PCLBUZ1
output frequency
30.5
1.8 V ≤ VDD ≤ 3.6 V
tEXHS, tEXLS
TI00, TI01, TI03 to TI07
input high-level width,
low-level width
μs
1
fEXS
External system clock input tEXH, tEXL
high-level width, low-level
width
Unit
1
1
LS (low-speed
main) mode
fEX
MAX.
0.125
Subsystem clock (fSUB)
operation
External system clock
frequency
TYP.
1.8 V ≤ VDD ≤ 3.6 V
LS (low-speed
main) mode
In the self
programming
mode
MIN.
HS (high-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
LV (low-voltage main)
mode
1.6 V ≤ EVDD0 < 1.8 V
INTP0
1.6 V ≤ VDD ≤ 3.6 V
1
μs
INTP1 to INTP11
1.6 V ≤ EVDD0 ≤ 3.6 V
1
μs
KR0 to KR9
1.8 V ≤ EVDD0 ≤ 3.6 V,
1.8 V ≤ AVDD0 ≤ 3.6 V
250
ns
1.6 V ≤ EVDD0 < 1.8 V,
1.6 V ≤ AVDD0 < 1.8 V
1
μs
10
μs
(Note and Remark are listed on the next page.)
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Note The following conditions are required for low-voltage interface when EVDD0 < VDD.
1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer clock select register 0 (TPS0) and timer mode
register 0n (TMR0n). n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
<R>
10
1.0
Cycle time TCY [μs]
When the high-speed on-chip oscillator
clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
4.0
2.4 2.7 3.6
5.0
6.0
Supply voltage VDD [V]
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
TCY vs VDD (LS (low-speed main) mode)
<R>
10
When the high-speed on-chip oscillator
clock is selected
Cycle time TCY [μs]
1.0
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
3.6
5.0 5.5 6.0
Supply voltage VDD [V]
TCY vs VDD (LV (low-voltage main) mode)
<R>
Cycle time TCY [μs]
10
1.0
When the high-speed on-chip oscillator
clock is selected
During self programming
When high-speed system clock is selected
0.25
0.1
0.01
0
1.0
2.0
1.6 1.8
3.0
4.0
3.6
5.0
6.0
Supply voltage VDD [V]
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/fEX
tEXL
tEXH
0.7 VDD MIN.
EXCLK
0.3 VDD MAX.
TI/TO Timing
tTIH
tTIL
TI00, TI01, TI03 to TI07
1/fTO
TO00, TO01, TO03 to TO07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR9
RESET Input Timing
tRSL
RESET
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RL78/G1A
2.5
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
<R>
2.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
Note 4
Transfer rate
2.4 V ≤ EVDD ≤ 3.6 V
Theoretical value of the
Note 1
LS
MAX.
fMCK/6
Note 5
5.3
MIN.
Note 2
LV
MAX.
MIN.
Note 3
Unit
MAX.
fMCK/6
fMCK/6
bps
1.3
0.6
Mbps
fMCK/6
fMCK/6
bps
1.3
0.6
Mbps
fMCK/6
fMCK/6
bps
0.6
Mbps
fMCK/6
bps
0.6
Mbps
maximum transfer rate
Note 6
fMCK = fCLK
1.8 V ≤ EVDD ≤ 3.6 V
Theoretical value of the
fMCK/6
Note 5
5.3
maximum transfer rate
Note 6
fMCK = fCLK
1.7 V ≤ EVDD ≤ 3.6 V
Theoretical value of the
fMCK/6
Note 5
5.3
1.3
Note 5
maximum transfer rate
Note 6
fMCK = fCLK
1.6 V ≤ EVDD ≤ 3.6 V
Theoretical value of the
−
−
fMCK/6
Note 5
1.3
maximum transfer rate
Note 6
fMCK = fCLK
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode is 4800 bps.
5. The following conditions are required for low-voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps
6. fCLK in each operating mode is as below.
HS (high-speed main) mode: fCLK = 32 MHz
LS (low-speed main) mode:
fCLK = 8 MHz
LV (low-voltage main) mode: fCLK = 4 MHz
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User device
RL78 microcontroller
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY1
2.7 V ≤ EVDD ≤ 3.6 V
SCKp high-/low-level width
tKH1,
2.7 V ≤ EVDD ≤ 3.6 V
tKCY1 ≥ 2/fCLK
tKL1
Note 4
SIp setup time (to SCKp↑)
Note 4
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to
SOp output
Note 1
MAX.
LS
Note 2
MIN.
MAX.
LV
MIN.
Note 3
Unit
MAX.
83.3
250
500
ns
tKCY1/2
tKCY1/2
tKCY1/2
ns
−10
−50
−50
tSIK1
2.7 V ≤ EVDD ≤ 3.6 V
33
110
110
ns
tKSI1
2.7 V ≤ EVDD ≤ 3.6 V
10
10
10
ns
tKSO1
Note 6
C = 20 pF
10
10
10
ns
Note 5
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY2
tKH2,
width
tKL2
SIp hold time
tKSI2
Note 4
250
500
1000
ns
1.8 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK
500
500
1000
ns
1.7 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK
1000
1000
1000
ns
2.7 V ≤ EVDD0 ≤ 3.6 V
1000
1000
ns
tKCY2/2
tKCY2/2
ns
−18
−50
−50
tKCY2/2
tKCY2/2
tKCY2/2
−38
−50
−50
tKCY2/2
tKCY2/2
tKCY2/2
−50
−50
−50
tKCY2/2
tKCY2/2
tKCY2/2
−100
−100
−100
−
tKCY2/2
tKCY2/2
−100
−100
ns
ns
ns
ns
44
110
110
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
75
110
110
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
110
110
110
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
220
220
220
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
220
220
ns
1.7 V ≤ EVDD ≤ 3.6 V
19
19
19
ns
−
19
19
ns
Delay time from SCKp↓
1.7 V ≤ EVDD ≤ 3.6 V
tKSO2
−
tKCY2/2
2.7 V ≤ EVDD0 ≤ 3.6 V
1.6 V ≤ EVDD ≤ 3.6 V
Note 5
MAX.
2.4 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK
(from SCKp↑)
to SOp output
MIN.
Unit
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
tSIK2
MAX.
Note 3
1000
1.7 V ≤ EVDD0 ≤ 3.6 V
Note 4
MIN.
LV
500
1.8 V ≤ EVDD0 ≤ 3.6 V
(to SCKp↑)
MAX.
Note 2
125
2.4 V ≤ EVDD0 ≤ 3.6 V
SIp setup time
LS
2.7 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK
1.6 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK
SCKp high-/low-level
Note 1
1.6 V ≤ EVDD ≤ 3.6 V
Note6
25
25
25
ns
Note6
−
25
25
ns
C = 30 pF
C = 30 pF
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
Note 4
SCKp high-/low-level
width
SIp setup time
Note 5
(to SCKp↑)
SIp hold time
Note 5
(from SCKp↑)
Delay time from SCKp↓
Note 6
to SOp output
tKCY2
tKH2,
tKL2
tSIK2
tKSI2
tKSO2
2.7 V ≤ EVDD0 ≤ 3.6 V
Note 1
LS
MAX.
MIN.
Note 2
MAX.
LV
MIN.
Note 3
Unit
MAX.
16 MHz < fMCK
8/fMCK
−
−
ns
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
6/fMCK
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
6/fMCK
and
500ns
6/fMCK
and
500ns
6/fMCK
and
500ns
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
6/fMCK
and
750ns
6/fMCK
and
750ns
6/fMCK
and
750ns
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
6/fMCK
and
1500ns
6/fMCK
and
1500ns
6/fMCK
and
1500ns
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
6/fMCK
and
1500ns
6/fMCK
and
1500ns
ns
2.7 V ≤ EVDD ≤ 3.6 V
tKCY2/2
−8
tKCY2/2
−8
tKCY2/2
−8
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
tKCY2/2
−18
tKCY2/2
−18
tKCY2/2
−18
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
tKCY2/2
−66
tKCY2/2
−66
tKCY2/2
−66
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
tKCY2/2
−66
tKCY2/2
−66
ns
2.7 V ≤ EVDD0 ≤ 3.6 V
1/fMCK
+20
1/fMCK
+30
1/fMCK
+30
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
1/fMCK
+30
1/fMCK
+30
1/fMCK
+30
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
1/fMCK
+40
1/fMCK
+40
1/fMCK
+40
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
1/fMCK
+40
1/fMCK
+40
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
1/fMCK
+31
1/fMCK
+31
1/fMCK
+31
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
1/fMCK+
250
1/fMCK+
250
1/fMCK+
250
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
1/fMCK+
250
1/fMCK+
250
ns
Note 7
C = 30 pF
2.7 V ≤ EVDD0 ≤ 3.6 V
2/fMCK
+44
2/fMCK
+110
2/fMCK
+110
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
2/fMCK
+75
2/fMCK
+110
2/fMCK
+110
ns
1.8 V ≤ EVDD0 ≤ 3.6 V
2/fMCK
+110
2/fMCK
+110
2/fMCK
+110
ns
1.7 V ≤ EVDD0 ≤ 3.6 V
2/fMCK
+220
2/fMCK
+220
2/fMCK
+220
ns
1.6 V ≤ EVDD0 ≤ 3.6 V
−
2/fMCK
+220
2/fMCK
+220
ns
(Note, Caution and Remark are listed on the next page.)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to
3),
g: PIM number (g = 0, 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78
microcontroller
SIp
SO
SOp
SI
User device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 11, 20, 21)
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
2
(5) During communication at same potential (simplified I C mode) (1/2)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCLr clock frequency
fSCL
2.7 V ≤ EVDD0 ≤ 3.6 V,
Note 1
LS
MAX.
MIN.
Note 4
1000
Note 2
LV
MAX.
MIN.
Note 3
Unit
MAX.
400
Note 4
400
Note 4
kHz
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 3.6 V,
400
Note 4
400
Note 4
400
Note 4
kHz
300
Note 4
300
Note 4
300
Note 4
kHz
250
Note 4
250
Note 4
250
Note 4
kHz
250
Note 4
250
Note 4
kHz
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
−
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 3.6 V,
475
1150
1150
ns
1150
1150
1150
ns
1550
1550
1550
ns
1850
1850
1850
ns
−
1850
1850
ns
475
1150
1150
ns
1150
1150
1150
ns
1550
1550
1550
ns
1850
1850
1850
ns
−
1850
1850
ns
1/fMCK +
1/fMCK +
1/fMCK +
ns
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Data setup time (reception)
tSU:DAT
2.7 V ≤ EVDD0 ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
85
Note 5
1.8 V ≤ EVDD ≤ 3.6 V,
1/fMCK +
Cb = 100 pF, Rb = 3 kΩ
145
Note 5
145
Note 5
1/fMCK +
145
Note 5
145
Note 5
1/fMCK +
145
1.8 V ≤ EVDD0 < 2.7 V,
1/fMCK+
Cb = 100 pF, Rb = 5 kΩ
230
230
230
1.7 V ≤ EVDD < 1.8 V,
1/fMCK +
1/fMCK +
1/fMCK +
Cb = 100 pF, Rb = 5 kΩ
290
Note 5
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Note 5
−
1/fMCK+
Note 5
290
Note 5
1/fMCK +
290
Note 5
ns
Note 5
1/fMCK+
ns
Note 5
290
1/fMCK +
290
ns
Note 5
ns
Note 5
(Notes, Caution and Remarks are listed on the next page.)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2
(5) During communication at same potential (simplified I C mode) (2/2)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Data hold time (transmission)
tHD:DAT
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
2.7 V ≤ EVDD0 ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
1.8 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0
405
0
405
0
405
ns
1.7 V ≤ EVDD0 ≤ 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
0
405
0
405
0
405
ns
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
−
−
0
405
0
405
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be fCLK/4 or lower.
5. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 25- to 48-pin
products)/EVDD tolerance (When 64-pin products)) mode for the SDAr pin and the normal output
mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
2
Simplified I C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
RL78
microcontroller
User device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD : DAT
Remarks 1.
2.
3.
tSU : DAT
Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1), h: POM number (h = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number, mn = 00 to 03, 10, 11)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate
Reception
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 4
fMCK/6
fMCK/6
fMCK/6
bps
5.3
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Theoretical value of the
5.3
1.3
0.6
Mbps
maximum transfer rate
Note 6
Theoretical value of the
maximum transfer rate
Note 7
fMCK = fCLK
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5
Note 7
fMCK = fCLK
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode is 4800 bps.
5. Use it with EVDD0≥Vb.
6. The following conditions are required for low-voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
7. fCLK in each operating mode is as below.
HS (high-speed main) mode:
LS (low-speed main) mode:
fCLK = 32 MHz
fCLK = 8 MHz
LV (low-voltage main) mode: fCLK = 4 MHz
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the TxDq pin by using
<R>
port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter Symbol
Conditions
HS
Note 1
LS
Note 2
LV
Note 3
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transmission 2.7 V ≤ EVDD0 ≤ 3.6 V,
Transfer
2.3 V ≤ Vb ≤ 2.7 V
rate
Note 4
Note 4
Note 4
bps
Theoretical value of the
1.2
1.2
1.2
Mbps
maximum transfer rate
Note 5
Note 5
Note 5
Note 7
Note 7
Note 7
bps
0.43
0.43
0.43
Mbps
Note 8
Note 8
Note 8
Cb = 50 pF, Rb = 2.7 kΩ,
Vb = 2.3 V
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 6
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
Notes 1.
HS is condition of HS (high-speed main) mode.
2.
LS is condition of LS (low-speed main) mode.
3.
LV is condition of LV (low-voltage main) mode.
4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 ≤ 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1
2.0
Vb )} × 3
[bps]
1
− {−Cb × Rb × ln
Transfer rate × 2
2.0
(1 − Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
5.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. See Note 4 above to calculate the maximum transfer rate under conditions of the customer.
6.
Use it with EVDD0 ≥ Vb.
7.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1
1.5
Vb )} × 3
[bps]
1.5
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. See Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the TxDq pin by using
<R>
port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
Rx
TxDq
User device
RL78
microcontroller
Tx
RxDq
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
tKCY1
2.7 V ≤ EVDD0 ≤ 3.6 V,
tKCY1 ≥ 2/fCLK
Note 1
LS
MAX.
300
Note 2
MIN.
LV
MAX.
Note 3
MIN.
Unit
MAX.
1150
1150
ns
tKCY1/2 −
tKCY1/2 −
ns
120
120
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 −
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 −
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
tSIK1
Note 4
SIp hold time
tKSI1
Note 4
(from SCKp↑)
tKSO1
Note 4
50
121
479
479
ns
10
10
10
ns
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
130
130
130
ns
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
tSIK1
Note 5
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
33
110
110
ns
10
10
10
ns
Cb = 20 pF, Rb = 2.7 kΩ
(to SCKp↓)
SIp hold time
tKSI1
Note 5
(from SCKp↓)
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
tKSO1
Note 5
Notes 1.
tKCY1/2 −
50
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
tKCY1/2 −
10
Cb = 20 pF, Rb = 2.7 kΩ
(to SCKp↑)
SOp output
120
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
10
10
10
ns
Cb = 20 pF, Rb = 2.7 kΩ
HS is condition of HS (high-speed main) mode.
2.
LS is condition of LS (low-speed main) mode.
3.
LV is condition of LV (low-voltage main) mode.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
5.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp pin and SCKp
<R>
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
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2.
(8) Communication at different potential (1.8V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
Note 1
MIN.
SCKp cycle time
tKCY1
2.7 V ≤ EVDD0 ≤ 3.6 V,
MAX.
LS
Note 2
MIN.
MAX.
LV
Note 3
MIN.
Unit
MAX.
tKCY1 ≥ 4/fCLK
500
1150
1150
ns
tKCY1 ≥ 4/fCLK
1150
1150
1150
ns
tKCY1/2 −
tKCY1/2 −
tKCY1/2 −
ns
170
170
170
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 4
,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width tKH1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
, tKCY1/2 −
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY1/2 −
tKCY1/2 −
458
458
458
tKCY1/2 −
tKCY1/2 −
tKCY1/2 −
18
50
50
tKCY1/2 −
tKCY1/2 −
50
50
Note 4
, tKCY1/2 −
Note 4
Cb = 30 pF, Rb = 5.5 kΩ
50
ns
ns
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Use it with EVDD0 ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp pin and SCKp
<R>
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10, 20), m: Unit number , n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3. CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SIp setup time
Note 4
(to SCKp↑)
SIp hold time
Note 4
(from SCKp↑)
tSIK1
tKSI1
SIp hold time
Note 5
(from SCKp↓)
tSIK1
tKSI1
MAX.
LV
MIN.
Unit
Note 3
MAX.
479
479
ns
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
, 479
479
479
ns
19
19
19
ns
19
19
19
ns
Note 6
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Note 6
,
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Note 6
,
195
195
195
ns
483
483
483
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44
110
110
ns
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
, 110
110
110
ns
19
19
19
ns
19
19
19
ns
Note 6
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to tKSO1
Note 5
SOp output
MIN.
Note 2
177
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
Note 5
(to SCKp↓)
MAX.
LS
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to tKSO1
Note 4
SOp output
Note 1
Note 6
,
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Note 6
,
25
25
25
ns
25
25
25
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
5. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. Use it with EVDD0 ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp pin and SCKp
<R>
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Rb
Vb
Rb
SCKp
RL78
microcontroller
Remarks 1.
SCK
SIp
SO
SOp
SI
User device
Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2.
p: CSI number (p = 00, 10, 20), m: Unit number , n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3.
CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
Remarks 1. p: CSI number (p = 00, 10, 20), m: Unit number, n: Channel number (m = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
2. CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCKp cycle time
Note 4
tKCY2
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
tKH2,
tKL2
tSIK2
tKSI2
Delay time from SCKp↓
Note 7
to SOp output
tKSO2
MAX.
LV
MIN.
Note 3
Unit
MAX.
−
−
ns
20 MHz < fMCK ≤ 24 MHz
16/fMCK
−
−
ns
16 MHz < fMCK ≤ 20 MHz
14/fMCK
−
−
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
−
−
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
−
ns
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
10/fMCK
ns
24 MHz < fMCK
48/fMCK
−
−
ns
20 MHz < fMCK ≤ 24 MHz
36/fMCK
−
−
ns
16 MHz < fMCK ≤ 20 MHz
32/fMCK
−
−
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
−
−
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
−
ns
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
10/fMCK
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2
− 18
tKCY2/2
− 50
tKCY2/2
− 50
ns
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2
− 50
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
Note 5
SIp hold time
Note 6
(from SCKp↑)
MIN.
Note 2
20/fMCK
Note 5
SIp setup time
Note 6
(to SCKp↑)
MAX.
LS
24 MHz < fMCK
1.8 V ≤ EVDD0 < 3.3 V,
Note 5
1.6 V ≤ Vb ≤ 2.0 V
SCKp high-/low-level
width
Note 1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 5
Cb = 30 pF, Rb = 5.5 kΩ
,
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
5. Use it with EVDD0 ≥ Vb.
6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
7. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (When 25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp
<R>
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78
microcontroller
Remarks 1.
SCK
SIp
SO
SOp
SI
User device
Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2.
p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 02, 10))
4.
CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
SOp
Output data
Remarks 1. p: CSI number (p = 00, 10, 20), m: Unit number, n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
2. CSI01, CSI11, and CSI21 cannot communicate at different potential.
Use other CSI for
communication at different potential.
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
SCLr clock frequency
fSCL
2.7 V ≤ EVDD0 ≤ 3.6 V,
Note 1
LS
MAX.
MIN.
LV
MAX.
MIN.
Note 3
Unit
MAX.
300
Note 4
300
Note 4
300
Note 4
300
Note 4
300
Note 4
300
1000
Note 4
Note 2
Note 4
kHz
Note 4
kHz
Note 4
kHz
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
400
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
300
Note 5
,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 3.6 V,
475
1550
1550
ns
1150
1550
1550
ns
1550
1550
1550
ns
200
610
610
ns
600
610
610
ns
610
610
610
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5
,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5
,
Cb = 100 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the next page.)
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2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
HS
MIN.
Data setup time (reception)
tSU:DAT
Data hold time (transmission)
tHD:DAT
Note 1
MAX.
LS
MIN.
Note 2
MAX.
LV
MIN.
Note 3
Unit
MAX.
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
Note 6
135
1/fMCK +
Note 6
190
1/fMCK +
Note 6
190
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK +
Note 6
190
1/fMCK +
Note 6
190
1/fMCK +
Note 6
190
ns
1.8 V ≤ EVDD0 < 3.3 V,
Note 5
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK +
Note 6
190
1/fMCK +
Note 6
190
1/fMCK +
Note 6
190
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ EVDD0 < 3.3 V,
Note 5
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 100 pF, Rb = 5.5 kΩ
0
405
0
405
0
405
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be fCLK/4 or lower.
5. Use it with EVDD0 ≥ Vb.
6. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 25- to 48-pin
products)/EVDD tolerance (When 64-pin products)) mode for the SDAr pin and the N-ch open drain
output (VDD tolerance (When 25- to 48-pin products)/EVDD tolerance (When 64-pin products))
<R>
mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 58 of 123
RL78/G1A
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
2
Simplified I C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDA
SDAr
RL78
microcontroller
User device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD : DAT
Remarks 1.
tSU : DAT
Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2.
r: IIC number (r = 00, 10, 20), g: PIM, POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02, 10)
4.
IIC01, IIC11, and IIC21 cannot communicate at different potential. Use IIC00, IIC10, or IIC20 for
communication at different potential.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 59 of 123
RL78/G1A
2.5.2
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Serial interface IICA
2
(1) I C standard mode
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
Standard Mode
HS
SCLA0 clock frequency
fSCL
Setup time of restart condition
Hold time
Note 5
tSU:STA
tHD:STA
Hold time when SCLA0 = “L”
tLOW
Hold time when SCLA0 = “H”
tHIGH
Data setup time (reception)
tSU:DAT
Note 6
Data hold time (transmission)
Setup time of stop condition
Bus-free time
tHD:DAT
tSU:STO
tBUF
Note 2
LS
Note 1
Note 3
Unit
LV
Note 4
MIN.
MAX.
MIN.
MIN.
MAX.
MIN.
2.7 V ≤ EVDD0 ≤ 3.6 V
0
100
0
100
0
100
1.8 V ≤ EVDD0 ≤ 3.6 V
0
100
0
100
0
100
1.7 V ≤ EVDD0 ≤ 3.6 V
0
100
0
100
0
100
100
0
100
1.6 V ≤ EVDD0 ≤ 3.6 V
−
0
2.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.8 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.7
4.7
2.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.8 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.0
4.0
2.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.8 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.7
4.7
2.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.8 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
kHz
μs
μs
μs
μs
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.0
4.0
2.7 V ≤ EVDD0 ≤ 3.6 V
250
250
250
1.8 V ≤ EVDD0 ≤ 3.6 V
250
250
250
1.7 V ≤ EVDD0 ≤ 3.6 V
250
250
250
1.6 V ≤ EVDD0 ≤ 3.6 V
−
250
250
2.7 V ≤ EVDD0 ≤ 3.6 V
0
3.45
0
3.45
0
3.45
1.8 V ≤ EVDD0 ≤ 3.6 V
0
3.45
0
3.45
0
3.45
1.7 V ≤ EVDD0 ≤ 3.6 V
0
3.45
0
3.45
0
3.45
1.6 V ≤ EVDD0 ≤ 3.6 V
−
−
0
3.45
0
3.45
2.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.8 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.7 V ≤ EVDD0 ≤ 3.6 V
4.0
4.0
4.0
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.0
4.0
2.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.8 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.7 V ≤ EVDD0 ≤ 3.6 V
4.7
4.7
4.7
1.6 V ≤ EVDD0 ≤ 3.6 V
−
4.7
4.7
ns
μs
μs
μs
(Note and Remark are listed on the next page.)
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 60 of 123
RL78/G1A
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
(2) I2C fast mode, fast mode plus
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Note 7
Conditions
Fast Mode
Fast Mode
Unit
Note 8
Plus
HS
SCLA0 clock frequency
Setup time of restart
Note 5
Hold time when SCLA0
MAX.
MIN.
2.7 V ≤ EVDD0 ≤ 3.6 V
0
400
0
400
0
400
0
1000
1.8 V ≤ EVDD0 ≤ 3.6 V
0
400
0
400
0
400
−
tSU:STA
2.7 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
1.8 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
−
tHD:STA
2.7 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
0.26
1.8 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
−
2.7 V ≤ EVDD0 ≤ 3.6 V
1.3
1.3
1.3
0.5
1.8 V ≤ EVDD0 ≤ 3.6 V
1.3
1.3
1.3
−
2.7 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
0.26
1.8 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
−
2.7 V ≤ EVDD0 ≤ 3.6 V
100
100
100
50
1.8 V ≤ EVDD0 ≤ 3.6 V
100
2.7 V ≤ EVDD0 ≤ 3.6 V
0
0.9
0
0.9
0
0.9
0
1.8 V ≤ EVDD0 ≤ 3.6 V
0
0.9
0
0.9
0
0.9
−
2.7 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
0.26
1.8 V ≤ EVDD0 ≤ 3.6 V
0.6
0.6
0.6
−
2.7 V ≤ EVDD0 ≤ 3.6 V
1.3
1.3
1.3
0.5
1.8 V ≤ EVDD0 ≤ 3.6 V
1.3
1.3
1.3
−
fSCL
tLOW
tHIGH
tHD:DAT
Note 6
tSU:STO
condition
Notes 1.
Note 2
MIN.
(transmission)
Bus-free time
HS
MAX.
tSU:DAT
Setup time of stop
Note 4
MIN.
(reception)
Data hold time
LV
MIN.
= “H”
Data setup time
Note 3
MAX.
= “L”
Hold time when SCLA0
LS
MIN.
condition
Hold time
Note 2
tBUF
100
kHz
μs
0.26
μs
μs
μs
ns
−
100
450
μs
μs
μs
In normal mode, use it with fCLK ≥ 1 MHz, 1.6 V ≤ EVDD ≤ 3.6 V.
2.
HS is condition of HS (high-speed main) mode.
3.
LS is condition of LS (low-speed main) mode.
4.
5.
LV is condition of LV (low-voltage main) mode.
The first clock pulse is generated after this period when the start/restart condition is detected.
6.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
7.
In fast mode, use it with fCLK ≥ 3.5 MHz, 1.8 V ≤ EVDD ≤ 3.6 V.
8.
In fast mode plus, use it with fCLK ≥ 10 MHz, 2.7 V ≤ EVDD ≤ 3.6 V.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
R01DS0151EJ0100 Rev.1.00
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Page 61 of 123
RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tBUF
Stop
condition
Start
condition
R01DS0151EJ0100 Rev.1.00
2013.09.25
Restart
condition
Stop
condition
Page 62 of 123
RL78/G1A
2.6
2.6.1
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Analog Characteristics
A/D converter characteristics
Division of A/D Converter Characteristics
Reference voltag Reference voltage (+) = AVREFP
Reference voltage (−) = AVREFM
Reference voltage (+) = AVDD
Reference voltage (+) = Internal
Reference voltage (−) = AVSS
refrence voltage
Reference voltage (−) = AVSS
Input channel
High-accuracy channel; ANI0 to
See 2.6.1 (1)
ANI12
See 2.6.1 (2)
See 2.6.1 (3)
See 2.6.1 (6)
(input buffer power supply: AVDD)
Standard channel; ANI16 to ANI30
See 2.6.1 (4)
See 2.6.1 (5)
See 2.6.1 (4)
See 2.6.1 (5)
(input buffer power supply: VDD or
EVDD0)
Temperature sensor, internal
−
reference voltage output
<R>
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI2 to ANI12
(TA = −40 to +85°C, 2.7 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (−) = AVREFM = 0 V, HALT mode)
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
MAX.
Unit
12
bit
±1.7
±3.3
LSB
RES
Notes 1, 2, 3
Overall error
Conversion time
Notes 1, 2, 3
Zero-scale error
Full-scale error
Notes 1, 2, 3
Integral linearity error
Notes 1, 2, 3
Differential linearity error
Notes 1, 2, 3
Analog input voltage
AINL
12-bit resolution
μs
tCONV
ADTYP = 0, 12-bit resolution
EZS
12-bit resolution
±1.3
±3.2
LSB
EFS
12-bit resolution
±0.7
±2.9
LSB
ILE
12-bit resolution
±1.0
±1.4
LSB
DLE
12-bit resolution
±1.2
LSB
AVREFP
V
VAIN
3.375
±0.9
0
Notes 1. TYP. Value is the average value at AVDD = AVREFP = 3 V and TA = 25°C. MAX. value is the average
value ±3σ at normalized distribution.
2. These values are the results of characteristic evaluation and are not checked for shipment.
3. Excludes quantization error (±1/2 LSB).
Cautions 1. Route the wiring so that noise will not be superimposed on each power line and ground line,
and insert a capacitor to suppress noise.
In addition, separate the reference voltage line of AVREFP from the other power lines to keep it
free from the influences of noise.
2. During A/D conversion, keep a pulse, such as a digital signal, that abruptly changes its level
from being input to or output from the pins adjacent to the converter pins and P20 to P27 and
P150 to P154.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 63 of 123
RL78/G1A
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI2 to ANI12
(TA = −40 to +85°C, 1.6 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
RES
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
MIN.
8
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Note 3
Overall error
AINL
Conversion time
tCONV
Note 3
Zero-scale error
Full-scale error
EZS
Note 3
Integral linearity error
EFS
Note 3
Differential linearity error
Analog input voltage
Notes 1.
2.
3.
Note 3
ILE
DLE
TYP.
8
MAX.
Unit
12
bit
10
8
Note 1
Note 2
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
3.375
ADTYP = 0,
Note 1
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
6.75
ADTYP = 0,
Note 2
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
13.5
ADTYP = 1,
8-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
2.5625
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
5.125
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
10.25
12-bit resolution
12-bit resolution
μs
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.0
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.0
VAIN
0
LSB
AVREFP
LSB
LSB
LSB
LSB
V
Cannot be used for lower 2 bit of ADCR register
Cannot be used for lower 4 bit of ADCR register
Excludes quantization error (±1/2 LSB).
R01DS0151EJ0100 Rev.1.00
2013.09.25
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RL78/G1A
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(3) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM
= 0), target for conversion: ANI0 to ANI12
(TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference
voltage (−) = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
1.8 V ≤ AVDD ≤ 3.6 V
MIN.
8
Overall error
AINL
Conversion time
tCONV
MAX.
Unit
12
bit
Note 1
8
1.6 V ≤ AVDD ≤ 3.6 V
Note 3
TYP.
10
8
Note 2
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±7.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
ADTYP = 0,
2.4 V ≤ AVDD ≤ 3.6 V
3.375
1.8 V ≤ AVDD ≤ 3.6 V
6.75
1.6 V ≤ AVDD ≤ 3.6 V
13.5
ADTYP = 1,
2.4 V ≤ AVDD ≤ 3.6 V
2.5625
8-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
5.125
1.6 V ≤ AVDD ≤ 3.6 V
10.25
LSB
±3.0
μs
12-bit resolution
ADTYP = 0,
10-bit resolution
Note 1
ADTYP = 0,
8-bit resolution
Note 3
Zero-scale error
Full-scale error
EZS
Note 3
Integral linearity error
EFS
Note 3
Differential linearity error
<R> Analog input voltage
Notes 1.
2.
3.
Note 3
ILE
DLE
Note 2
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
VAIN
0
AVDD
LSB
LSB
LSB
LSB
V
Cannot be used for lower 2 bit of ADCR register
Cannot be used for lower 4 bit of ADCR register
Excludes quantization error (±1/2 LSB).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 65 of 123
RL78/G1A
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(4) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI16 to ANI30, interanal reference voltage,
temperature sensor output voltage
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0
V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
RES
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
MIN.
8
8
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Note 3
Overall error
AINL
Conversion time
tCONV
Note 3
Zero-scale error
Full-scale error
EZS
Note 3
Integral linearity error
EFS
Note 3
Differential linearity error
Analog input voltage
Notes 1.
2.
3.
4.
Note 3
ILE
DLE
TYP.
MAX.
Unit
12
bit
10
8
Note 1
Note 2
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±7.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±3.0
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
4.125
ADTYP = 0,
Note 1
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
9.5
ADTYP = 0,
Note 2
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
57.5
ADTYP = 1,
8-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
3.3125
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
7.875
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
54.25
μs
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±3.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
VAIN
LSB
LSB
LSB
LSB
LSB
±1.5
0
AVREFP
and EVDD0
Note 4
Interanal reference voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VBGR
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VTMPS25
Note 4
V
V
V
Cannot be used for lower 2 bit of ADCR register
Cannot be used for lower 4 bit of ADCR register
Excludes quantization error (±1/2 LSB).
See 2.6.2 Temperature sensor, internal reference voltage output characteristics.
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RL78/G1A
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(5) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM
= 0), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output
voltage
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD0 ≤ 3.6 V, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0 V,
Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
1.8 V ≤ AVDD ≤ 3.6 V
MIN.
8
8
1.6 V ≤ AVDD ≤ 3.6 V
Note 3
Overall error
AINL
Conversion time
tCONV
TYP.
MAX.
Unit
12
bit
10
Note 1
Note 2
8
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±6.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.5
ADTYP = 0,
2.4 V ≤ AVDD ≤ 3.6 V
4.125
1.8 V ≤ AVDD ≤ 3.6 V
9.5
1.6 V ≤ AVDD ≤ 3.6 V
57.5
ADTYP = 1,
2.4 V ≤ AVDD ≤ 3.6 V
3.3125
8-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
7.875
1.6 V ≤ AVDD ≤ 3.6 V
54.25
LSB
μs
12-bit resolution
ADTYP = 0,
10-bit resolution
Note 1
ADTYP = 0,
8-bit resolution
Note 3
Zero-scale error
Full-scale error
EZS
Note 3
Integral linearity error
EFS
Note 3
Differential linearity error
Analog input voltage
Note 3
ILE
DLE
Note 2
μs
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.0
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.0
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
VAIN
LSB
LSB
LSB
LSB
±2.0
AVDD and
0
V
EVDD0
Notes 1.
2.
3.
4.
Note 4
Interanal reference voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VBGR
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VTMPS25
Note 4
V
V
Cannot be used for lower 2 bit of ADCR register
Cannot be used for lower 4 bit of ADCR register
Excludes quantization error (±1/2 LSB).
See 2.6.2 Temperature sensor, internal reference voltage output characteristics.
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RL78/G1A
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
(6) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference
voltage (−) = AVSS (ADREFM = 0), target ANI pin: ANI0 to ANI12, ANI16 to ANI30
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD ≤ VDD, 1.6 V ≤ AVDD ≤ VDD, VSS = EVSS0 = 0 V, AVSS = 0 V,
Reference voltage (+) = Internal reference voltage, Reference voltage (−) = AVSS = 0 V, HS (high-speed main)
mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
TYP.
MAX.
8
Unit
bit
μs
tCONV
8-bit resolution
EZS
8-bit resolution
ILE
8-bit resolution
±2.0
LSB
DLE
8-bit resolution
±2.5
LSB
Reference voltage (+)
AVREF(+)
= Internal reference voltage (VBGR)
1.5
V
Analog input voltage
VAIN
VBGR
V
MAX.
Unit
Note
Zero-scale error
Integral linearity error
Note
Differential linearity error
Note
2.6.2
Note
16
±4.0
1.38
1.45
0
LSB
Excludes quantization error (±1/2 LSB).
Temperature sensor, internal reference voltage output characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor output voltage that
TYP.
1.05
1.38
1.45
V
1.5
V
−3.6
mV/°C
depends on the temperature
Operation stabilization wait time
2.6.3
tAMP
μs
10
POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Minimum pulse width
Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.47
1.51
1.55
V
VPDR
Power supply fall time
1.46
1.50
1.54
V
TPW
μs
300
This is the time required for the POR circuit to execute a reset when VDD falls below VPDR. When the
microcontroller enters STOP mode or if the main system clock (fMAIN) has been stopped by setting bit 0
(HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required
for the POR circuit to execute a reset before VDD rises to VPOR after having fallen below 0.7 V.
TPW
Power supply voltage (VDD)
VPOR
VPOR or 0.7 V
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RL78/G1A
2.6.4
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVD2
voltage
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Conditions
Power supply rise time
MIN.
TYP.
MAX.
Unit
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
tLW
Caution
μs
300
Detection delay time
300
Set the detection voltage (VLVD) to be within the operating voltage range.
μs
The operating voltage
range depends on the setting of the user option byte (000C2H/010C2H). The following shows
the operating voltage range.
HS (high-speed main) mode: VDD = 2.7 to 3.6 [email protected] MHz to 32 MHz
VDD = 2.4 to 3.6 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
VDD = 1.8 to 3.6 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: VDD = 1.6 to 3.6 [email protected] MHz to 4 MHz
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RL78/G1A
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Interrupt & reset
VLVD13
mode
VLVD12
Conditions
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0
VLVD11
LVIS1, LVIS0 = 0, 1
VLVD4
VLVD11
LVIS1, LVIS0 = 0, 0
LVIS1, LVIS0 = 1, 0
VLVD9
LVIS1, LVIS0 = 0, 1
VLVD2
VLVD8
LVIS1, LVIS0 = 0, 0
LVIS1, LVIS0 = 1, 0
VLVD6
VLVD5
LVIS1, LVIS0 = 0, 1
VLVD3
Caution
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
Unit
1.60
1.63
1.66
V
1.74
1.77
1.81
V
Falling interrupt voltage
1.73
1.77
V
Rising release reset voltage
1.84
1.88
1.91
V
Falling interrupt voltage
1.80
1.84
1.87
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
1.80
1.84
1.87
V
Rising release reset voltage
1.94
1.98
2.02
V
Falling interrupt voltage
1.90
1.94
1.98
V
Rising release reset voltage
2.05
2.09
2.13
V
Falling interrupt voltage
2.00
2.04
2.08
V
Rising release reset voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
Rising release reset voltage
2.56
2.61
2.66
V
Falling interrupt voltage
2.50
2.55
2.60
V
Rising release reset voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
2.70
2.75
2.81
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVD4
MAX.
1.70
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
VLVD7
TYP.
Rising release reset voltage
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
VLVD10
MIN.
Set the detection voltage (VLVD) to be within the operating voltage range.
The operating voltage
range depends on the setting of the user option byte (000C2H/010C2H). The following shows
the operating voltage range.
HS (high-speed main) mode: VDD = 2.7 to 3.6 [email protected] MHz to 32 MHz
VDD = 2.4 to 3.6 [email protected] MHz to 16 MHz
LS (low-speed main) mode:
VDD = 1.8 to 3.6 [email protected] MHz to 8 MHz
LV (low-voltage main) mode: VDD = 1.6 to 3.6 [email protected] MHz to 4 MHz
2.6.5
Supply voltage rise slope characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Supply voltage rise
Symbol
Conditions
MIN.
SVDD
TYP.
MAX.
Unit
54
V/ms
Caution Be sure to maintain the internal reset state until VDD reaches the operating voltage range specified
in 2.4
AC Characteristics, by using the LVD circuit or external reset pin.
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RL78/G1A
2.7
<R>
2.
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Data retention supply voltage
Conditions
MIN.
VDDDR
1.46
TYP.
Note
MAX.
Unit
3.6
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data hold mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(inerrupt request)
<R>
2.8
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
CPU/peripheral hardware clock
Conditions
fCLK
1.8 V ≤ VDD ≤ 3.6 V
Cerwr
Retained for 20 years
MIN.
TYP.
1
MAX.
Unit
32
MHz
frequency
Notes 1, 2
Number of code flash rewrites
Notes 1, 2
Number of data flash rewrites
Retained for 1 years
Retained for 5 years
Retained for 20 years
Note 3
TA = 85°C
1,000
Note 3
TA = 25°C
1,000,000
Note 3
100,000
Note 3
10,000
TA = 85°C
TA = 85°C
Times
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
2.9
Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Transfer rate
R01DS0151EJ0100 Rev.1.00
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Symbol
Conditions
During flash memory programming
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 71 of 123
RL78/G1A
2.10
ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C)
2.
Timing Specs for Switching Flash Memory Programming Modes
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
How long from when an external reset
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
POR and LVD reset must end before the
tSUINIT
external reset ends.
ends until the initial communication
settings are specified
How long from when the TOOL0 pin is
POR and LVD reset must end before the
tSU
10
μs
1
ms
external reset ends.
placed at the low level until a external
reset ends
<R> How long the TOOL0 pin must be kept at
POR and LVD reset must end before the
tHD
external reset ends.
the low level after an external reset ends
(except flash firmware processing time)
<1>
<2>
<3>
<4>
RESET
723 μs + tHD
process time
<R>
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The pins reset ends (POR and LVD reset must end before the external reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
<R>
tSU:
How long from when the TOOL0 pin is placed at the low level until a external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external resets end (except flash
firmware processing time)
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RL78/G1A
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
3. ELECTRICAL SPECIFICATIONS
(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
This chapter describes the following electrical specifications.
Target products
G: Industrial applications
TA = −40 to +105°C
R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA
R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB
R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA
R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB
Cautions 1. The RL78/G1A has an on-chip debug function, which is provided for development and
evaluation.
Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may
be exceeded when this function is used, and product reliability therefore cannot be
guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip
debug function is used.
2. With products not provided with an EVDD0 or EVSS0 pin, replace EVDD0 with VDD, or replace
EVSS0 with VSS.
3. The pins mounted depend on the product.
See 1.3.1 25-pin products to 1.3.4 64-pin
products.
4. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C
to +105°C. Derating is the systematic reduction of load for the sake of improved reliability.
Remark
When RL78/G1A is used in the range of TA = −40 to +85°C, see 2.
ELECTRICAL
SPECIFICATIONS (TA = −40 to +85°C).
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3.1
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter
Symbols
Supply voltage
Conditions
VDD
Ratings
Unit
−0.5 to +6.5
V
EVDD0
−0.5 to +6.5
V
AVDD
−0.5 to +4.6
V
−0.3 to AVDD +0.3
Note 3
AVREFP
EVSS0
−0.5 to +0.3
AVSS
−0.5 to +0.3
V
V
−0.3 to AVDD +0.3
AVREFM
V
Note 3
V
and AVREFM ≤ AVREFP
REGC pin input voltage
VIREGC
−0.3 to +2.8
REGC
V
and −0.3 to VDD +0.3
Input voltage
VI1
−0.3 to EVDD0 +0.3
P00 to P06, P10 to P16, P30, P31, P40 to P43,
and −0.3 to VDD +0.3
P50, P51, P70 to P77, P120, P140, P141
Output voltage
V
Note 2
−0.3 to +6.5
VI2
P60 to P63 (N-ch open-drain)
VI3
P121 to P124, P137, EXCLK, EXCLKS, RESET
VI4
P20 to P27, P150 to P154
−0.3 to AVDD +0.3
P00 to P06, P10 to P16, P30, P31, P40 to P43,
−0.3 to EVDD0 +0.3
VO1
Note 1
−0.3 to VDD +0.3
V
Note 2
V
Note 2
V
Note 2
V
Note 2
V
P50, P51, P60 to P63, P70 to P77, P120, P130,
P140, P141
Analog input voltage
VO2
P20 to P27, P150 to P154
VAI1
ANI16 to ANI30
−0.3 to AVDD +0.3
−0.3 to EVDD0 +0.3
and −0.3 to AVREF(+) +0.3
VAI2
−0.3 to AVDD +0.3
ANI0 to ANI12
and −0.3 to AVREF(+) +0.3
Notes 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
V
Notes 2, 4
V
Notes 2, 4
This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Must be 4.6 V or lower.
4. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2.
AVREF(+): + side reference voltage of the A/D converter.
3.
VSS: Reference voltage
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P00 to P06, P10 to P16, P30, P31,
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.1
mA
−1.3
mA
40
mA
70
mA
100
mA
0.4
mA
P40 to P43, P50, P51, P70 to P77,
P120, P130, P140, P141
Total of all pins
P00 to P04, P40 to P43, P120,
−170 mA
P130, P140, P141
P05, P06, P10 to P16, P30, P31,
P50, P51, P70 to P77,
IOH2
Per pin
P20 to P27, P150 to P154
Total of all pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P16, P30, P31,
P40 to P43, P50, P51, P60 to P63,
P70 to P77, P120, P130, P140,
P141
Total of all pins
P00 to P04, P40 to P43, P120,
170 mA
P130, P140, P141
P05, P06, P10 to P16, P30, P31,
P50, P51, P60 to P63, P70 to P77
IOL2
Per pin
P20 to P27, P150 to P154
TA
In normal operation mode
Total of all pins
Operating ambient
temperature
6.4
mA
−40 to +105
°C
−65 to +150
°C
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3.2
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Oscillator Characteristics
3.2.1
X1, XT1 oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
X1 clock oscillation
Resonator
Conditions
Ceramic resonator/crystal resonator
Note
frequency (fX)
XT1 clock oscillation
MIN.
TYP.
MAX.
Unit
MHz
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
2.4 V ≤ VDD < 2.7 V
1.0
16.0
Crystal resonator
32
32.768
35
kHz
Note
frequency (fX)
Note Indicates only permissible oscillator frequency ranges. See AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register
and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
3.2.2
On-chip oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
oscillation frequency
Conditions
fIH
MIN.
TYP.
MAX.
Unit
1
32
MHz
Notes 1, 2
High-speed on-chip oscillator
+85 to +105 °C
2.4 V ≤ VDD ≤ 3.6 V
−2
+2
%
oscillation frequency accuracy
−20 to +85 °C
2.4 V ≤ VDD ≤ 3.6 V
−1
+1
%
−40 to −20 °C
2.4 V ≤ VDD ≤ 3.6 V
−1.5
+1.5
%
Low-speed on-chip oscillator
fIL
15
kHz
oscillation frequency
Low-speed on-chip oscillator
−15
+15
%
oscillation frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. See AC Characteristics for instruction execution
time.
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3.3
3.3.1
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
DC Characteristics
Pin characteristics
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
Conditions
Notes 1.
(1/5)
TYP.
MAX.
−3.0
Unit
Per pin for P00 to P06, P10 to P16,
P30, P31, P40 to P43, P50, P51,
P70 to P77, P120, P130, P140, P141
2.4 V ≤ EVDD0 ≤ 3.6 V
Total of P00 to P04, P40 to P43, P120,
P130, P140, P141
Note 3
(When duty ≤ 70%
)
2.7 V ≤ EVDD0 ≤ 3.6 V
−10.0
mA
2.4 V ≤ EVDD0 < 2.7 V
−5.0
mA
2.7 V ≤ EVDD0 ≤ 3.6 V
−19.0
mA
2.4 V ≤ EVDD0 < 2.7 V
−10.0
mA
Total of all pins
Note 3
)
(When duty ≤ 70%
2.4 V ≤ EVDD0 ≤ 3.6 V
−29.0
mA
Per pin for P20 to P27, P150 to P154
2.4 V ≤ AVDD ≤ 3.6 V
Total of all pins
Note 3
)
(When duty ≤ 70%
2.4 V ≤ AVDD ≤ 3.6 V
Total of P05, P06, P10 to P16, P30,
P31, P50, P51, P70 to P77,
Note 3
(When duty ≤ 70%
)
IOH2
MIN.
−0.1
Note 2
Note 2
−1.3
mA
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
VDD pins to an output pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain
mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
MIN.
TYP.
Per pin for P60 to P63
15.0
Note 2
mA
mA
15.0
mA
9.0
mA
2.7 V ≤ EVDD0 ≤ 3.6 V
35.0
mA
2.4 V ≤ EVDD0 < 2.7 V
20.0
mA
50.0
mA
Total of all pins
Note 3
)
(When duty ≤ 70%
Per pin for P20 to P27, P150 to P154
Total of all pins
Note 3
)
(When duty ≤ 70%
Unit
Note 2
8.5
Total of P05, P06, P10 to P16, P30,
P31, P50, P51, P60 to P63,
P70 to P77
Note 3
)
(When duty ≤ 70%
Notes 1.
MAX.
Per pin for P00 to P06, P10 to P16,
P30, P31, P40 to P43, P50, P51,
P70 to P77, P120, P130, P140, P141
Total of P00 to P04, P40 to P43, P120, 2.7 V ≤ EVDD0 ≤ 3.6 V
P130, P140, P141
2.4 V ≤ EVDD0 < 2.7 V
Note 3
(When duty ≤ 70%
)
IOL2
(2/5)
0.4
2.4 V ≤ AVDD ≤ 3.6 V
Note 2
5.2
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS0 and VSS pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the dury factor > 70% the duty ratio can can be
calculated with the following expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P00 to P06, P10 to P16, P30, P31,
MIN.
Normal input buffer
TYP.
(3/5)
MAX.
Unit
0.8EVDD0
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
P40 to P43, P50, P51, P70 to P77,
high
P120, P140, P141
VIH2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P16, P43
3.3 V ≤ EVDD0 ≤ 3.6 V
TTL input buffer
2.4 V ≤ EVDD0 < 3.3 V
VIH3
P20 to P27, P150 to P154
0.7AVDD
AVDD
V
VIH4
P60 to P63
0.7EVDD0
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
Normal input buffer
0
0.2EVDD0
V
P01, P03, P04, P10, P11,
TTL input buffer
0
0.5
V
P13 to P16, P43
3.3 V ≤ EVDD0 ≤ 3.6 V
0
0.32
V
Input voltage, low VIL1
P00 to P06, P10 to P16, P30, P31,
P40 to P43, P50, P51, P70 to P77,
P120, P140, P141
VIL2
TTL input buffer
2.4 V ≤ EVDD0 < 3.3 V
VIL3
P20 to P27, P150 to P154
0
0.3AVDD
V
VIL4
P60 to P63
0
0.3EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 is EVDD0,
even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P00 to P06, P10 to P16, P30, P31,
2.7 V ≤ EVDD0 ≤ 3.6 V,
P40 to P43, P50, P51, P70 to P77,
IOH1 = −2.0 mA
P120, P130, P140, P141
2.4 V ≤ EVDD0 ≤ 3.6 V,
IOH1 = −1.5 mA
VOH2
P20 to P27, P150 to P154
2.4 V ≤ AVDD ≤ 3.6 V,
IOH2 = −100 μA
Output voltage,
VOL1
low
P00 to P06, P10 to P16, P30, P31,
2.7 V ≤ EVDD0 ≤ 3.6 V,
P40 to P43, P50, P51, P70 to P77,
IOL1 = 3.0 mA
P120, P130, P140, P141
2.7 V ≤ EVDD0 ≤ 3.6 V,
TYP.
(4/5)
MAX.
Unit
EVDD0 −
V
0.6
EVDD0 −
V
0.5
AVDD −
V
0.5
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL1 = 1.5 mA
2.4 V ≤ EVDD0 ≤ 3.6 V,
IOL1 = 0.6 mA
VOL2
P20 to P27, P150 to P154
2.4 V ≤ AVDD ≤ 3.6 V,
IOL2 = 400 μA
VOL3
P60 to P63
2.7 V ≤ EVDD0 ≤ 3.6 V,
IOL3 = 3.0 mA
2.4 V ≤ EVDD0 ≤ 3.6 V,
IOL3 = 2.0 mA
Caution
P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain
mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Input leakage
ILIH1
Conditions
P00 to P06, P10 to P16, P30,
MIN.
TYP.
(5/5)
MAX.
Unit
VI = EVDD0
1
μA
1
μA
1
μA
10
μA
P31, P40 to P43, P50, P51,
current, high
P60 to P63, P70 to P77, P120,
P140, P141
ILIH2
P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIH4
P20 to P27, P150 to P154
VI = AVDD
1
μA
ILIL1
P00 to P06, P10 to P16,
VI = EVSS0
−1
μA
−1
μA
−1
μA
−10
μA
−1
μA
100
kΩ
P30, P31, P40 to P43,
current, low
P50, P51, P60 to P67,
P70 to P77, P120, P140, P141
ILIL2
P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
ILIL4
P20 to P27, P150 to P154
VI = AVSS
RU
P00 to P06, P10 to P16, P30,
VI = EVSS0, In input port
10
20
P31, P40 to P43, P50, P51,
resistance
P70 to P77, P120, P140, P141
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3.
3.3.2
Supply current characteristics
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply
current
IDD1
Note 1
(1/3)
Conditions
Operating
mode
HS (high-speed
Note 5
main) mode
MIN.
Note 3
fIH = 32 MHz
Unit
VDD = 3.0 V
2.1
Normal
operation
VDD = 3.0 V
4.6
7.5
mA
Note 3
Normal
operation
VDD = 3.0 V
3.7
5.8
mA
Note 3
Normal
operation
VDD = 3.0 V
2.7
4.2
mA
Normal
operation
Square
wave input
3.0
4.9
mA
Resonator
connection
3.2
5.0
Square
wave input
1.9
2.9
Resonator
connection
1.9
2.9
Square
wave input
4.1
4.9
Resonator
connection
4.2
5.0
Square
wave input
4.2
4.9
Resonator
connection
4.3
5.0
Square
wave input
4.3
5.5
Resonator
connection
4.4
5.6
Square
wave input
4.5
6.3
Resonator
connection
4.6
6.4
Square
wave input
4.8
7.7
Resonator
connection
4.9
7.8
Square
wave input
6.9
19.7
Resonator
connection
7.0
19.8
fIH = 16 MHz
Note 2
fMX = 20 MHz
VDD = 3.0 V
,
Note 2
fMX = 10 MHz
VDD = 3.0 V
Subsystem
clock mode
MAX.
Basic
operation
fIH = 24 MHz
HS (high-speed
Note 5
main) mode
TYP.
,
fSUB = 32.768 kHz
TA = −40°C
fSUB = 32.768 kHz
TA = +25°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +70°C
fSUB = 32.768 kHz
TA = +85°C
fSUB = 32.768 kHz
TA = +105°C
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Normal
operation
Normal
operation
Normal
operation
Normal
operation
Normal
operation
Normal
operation
Normal
operation
mA
mA
μA
μA
μA
μA
μA
μA
(Notes and Remarks are listed on the next page.)
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0.
The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, on-chip pull-up/pull-down resistors, and data flash rewriting.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When setting ultra-low
power consumption oscillation (AMPHS1 = 1). Not including the current flowing into the RTC, 12-bit
interval timer and watchdog timer
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode:
VDD = 2.7 V to 3.6 [email protected] MHz to 32 MHz
VDD = 2.4 V to 3.6 [email protected] MHz to 16 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Supply
IDD2
current
Note 2
Note 1
(2/3)
Conditions
HALT
HS (high-speed
mode
Note 7
main) mode
MIN.
Note 7
VDD = 3.0 V
0.54
2.90
mA
VDD = 3.0 V
0.44
2.30
mA
Note 4
VDD = 3.0 V
0.40
1.70
mA
Square wave input
0.28
1.90
mA
Resonator connection
0.45
2.00
Square wave input
0.19
1.02
Resonator connection
0.26
1.10
Square wave input
0.25
0.57
Resonator connection
0.44
0.76
fSUB = 32.768 kHz
Square wave input
0.30
0.57
TA = +25°C
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
Note 5
Subsystem clock fSUB = 32.768 kHz
mode
TA = −40°C
Note 5
Resonator connection
0.49
0.76
fSUB = 32.768 kHz
Square wave input
0.38
1.17
TA = +50°C
Resonator connection
0.57
1.36
fSUB = 32.768 kHz
Square wave input
0.52
1.97
TA = +70°C
Resonator connection
0.71
2.16
fSUB = 32.768 kHz
Square wave input
0.97
3.37
TA = +85°C
Resonator connection
1.16
3.56
Square wave input
3.01
15.37
Note 5
Note 5
Note 5
Note 5
fSUB = 32.768 kHz
TA = +105°C
Resonator connection
Note 6
IDD3
STOP
mode
Unit
Note 4
fIH = 16 MHz
main) mode
MAX.
Note 4
fIH = 32 MHz
fIH = 24 MHz
HS (high-speed
TYP.
3.20
15.56
TA = −40°C
0.16
0.50
TA = +25°C
0.23
0.50
TA = +50°C
0.34
1.10
TA = +70°C
0.46
1.90
TA = +85°C
0.75
3.30
TA = +105°C
2.94
15.30
mA
μA
μA
μA
μA
μA
μA
μA
Note 8
(Notes and Remarks are listed on the next page.)
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0.
The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, on-chip pull-up/pull-down resistors, and data flash rewriting.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1).
Including the current flowing into the RTC.
However, not including the current flowing into the 12-bit interval timer, and watchdog timer.
6. When subsystem clock is stopped. Not including the current flowing into the RTC, 12-bit interval timer,
watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 [email protected] MHz to 32 MHz
2.4 V ≤ VDD ≤ 3.6 [email protected] MHz to 16 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Low-speed on-chip
Symbol
(3/3)
Conditions
MIN.
Note 1
IFIL
TYP.
MAX.
Unit
0.20
μA
0.02
μA
0.02
μA
μA
oscillator operating
current
RTC operating
IRTC
Notes 1, 2, 3
current
12-bit interval timer
IIT
Notes 1, 2, 4
operating current
Watchdog timer
Notes 1, 2, 5
fIL = 15 kHz
0.22
Notes 6, 7
AVDD = 3.0 V, When conversion at maximum speed
420
720
μA
14.0
25.0
μA
14.0
25.0
μA
25.0
μA
IWDT
operating current
A/D converter
operating current
IADC
AVREF(+) current
IAVREF
Note 8
Note 7
AVDD = 3.0 V, ADREFP1 = 0, ADREFP0 = 0
Note 10
AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1
Note 1
ADREFP1 = 1, ADREFP0 = 0
14.0
VDD = 3.0 V
75.0
μA
VDD = 3.0 V
75.0
μA
Notes 1, 11
0.08
μA
Notes 1, 12
2.5
12.2
mA
Notes 1, 13
2.5
12.2
mA
A/D converter
reference voltage
current
IADREF
Temperature
sensor operating
current
ITMPS
LVD operating
ILVD
Notes 1, 9
Note 1
current
BGO operating
IBGO
current
Self-programming
IFSP
operating current
SNOOZE operating
ISNOZ
current
A/D converter
operation
(AVDD = 3.0 V)
Notes 1
The mode is performed
0.50
1.10
mA
During A/D conversion
Note 1
0.60
1.34
mA
During A/D conversion
Note 7
420
720
μA
0.70
1.54
mA
CSI/UART operation
Note 1
(Notes and Remarks are listed on the next page.)
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Notes 1. Current flowing to VDD.
2. When high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed
on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of
the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
ocsillator and the XT1 oscillator).
The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and IWDT
when the watchdog timer is in operation.
6. Current flowing only to the A/D converter.
The supply current of the RL78 microcontrollers is the sum of
IDD1 or IDD2 and IADC, IAVREF, IADREF when the A/D converter operates in an operation mode or the HALT
mode.
7. Current flowing to the AVDD.
8. Current flowing from the reference voltage source of A/D converter.
9. Operation current flowing to the internal reference voltage.
10. Current flowing to the AVREFP.
11. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of
IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
12. Current flowing only during data flash rewrite.
13. Current flowing only during self programming.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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3.4
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
AC Characteristics
(TA = −40 to +105°C, AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Items
Symbol
Instruction cycle (minimum TCY
instruction execution time)
Conditions
Main system
clock (fMAIN)
operation
2.4 V ≤ VDD ≤ 3.6 V
Subsystem clock (fSUB)
operation
In the self
programming
mode
External system clock
frequency
fEX
MIN.
TYP.
HS (high-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
28.5
HS (high-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
30.5
MAX.
Unit
1
μs
1
μs
31.3
μs
1
μs
1
μs
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
32
35
kHz
fEXS
External system clock input tEXH, tEXL
2.7 V ≤ VDD ≤ 3.6 V
high-level width, low-level
2.4 V ≤ VDD < 2.7 V
width
tEXHS, tEXLS
24
ns
30
ns
μs
13.7
TI00, TI01, TI03 to TI07
input high-level width,
low-level width
tTIH, tTIL
TO00, TO01, TO03 to
TO07 output frequency
fTO
HS (high-speed main)
mode
PCLBUZ0, PCLBUZ1
output frequency
fPCL
HS (high-speed main)
mode
Interrupt input high-level
width, low-level width
tINTH, tINTL
INTP0
2.4 V ≤ VDD ≤ 3.6 V
Key interrupt input
high-level width, low-level
width
tKR
RESET low-level width
tRSL
Note
1/fMCK+10
ns
2.7 V ≤ EVDD0 ≤ 3.6 V
8
MHz
2.4 V ≤ EVDD0 < 2.7 V
4
MHz
2.7 V ≤ EVDD0 ≤ 3.6 V
8
MHz
2.4 V ≤ EVDD0 < 2.7 V
4
MHz
1
μs
INTP1 to INTP11
2.4 V ≤ EVDD0 ≤ 3.6 V
1
μs
KR0 to KR9
2.4 V ≤ EVDD0 ≤ 3.6 V,
2.4 V ≤ AVDD0 ≤ 3.6 V
250
ns
10
μs
Note The following conditions are required for low-voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MIN. 125 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer clock select register 0 (TPS0) and timer mode
register 0n (TMR0n). n: Channel number (n = 0 to 7))
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [μs]
When the high-speed on-chip oscillator
clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
4.0
2.4 2.7 3.6
5.0
6.0
Supply voltage VDD [V]
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/fEX
tEXL
tEXH
0.7 VDD MIN.
EXCLK
0.3 VDD MAX.
TI/TO Timing
tTIH
tTIL
TI00, TI01, TI03 to TI07
1/fTO
TO00, TO01, TO03 to TO07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR9
RESET Input Timing
tRSL
RESET
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3.5
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
3.5.1
VIL/VOL
Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
Note 1
Transfer rate
MAX.
Unit
fMCK/12
bps
Theoretical value of the
2.6
Note 2
Mbps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps.
2. The following conditions are required for low-voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User device
RL78 microcontroller
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
SCKp high-/low-level width
Note 1
SIp setup time (to SCKp↑)
Note 1
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to
SOp output
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V ≤ EVDD0 ≤ 3.6 V
tKCY1 ≥ 4/fCLK
250
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
tKCY1 ≥ 4/fCLK
500
ns
tKH1,
2.7 V ≤ EVDD0 ≤ 3.6 V
tKCY1/2 − 36
ns
tKL1
2.4 V ≤ EVDD0 ≤ 3.6 V
tKCY1/2 − 76
ns
tSIK1
2.7 V ≤ EVDD0 ≤ 3.6 V
66
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
113
ns
38
ns
tKSI1
tKSO1
C = 30 p
Note 3
50
ns
Note 2
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1)
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
SCKp cycle time
Note 1
Symbol
tKCY2
Conditions
2.7 V ≤ EVDD0 ≤ 3.6 V
MIN.
TYP.
MAX.
Unit
16 MHz < fMCK
16/fMCK
ns
fMCK ≤ 16 MHz
12/fMCK
ns
12/fMCK and
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
1000
SCKp high-/low-level width
SIp setup time
tKH2,
2.7 V ≤ EVDD0 ≤ 3.6 V
tKCY2/2−14
ns
tKL2
2.4 V ≤ EVDD0 ≤ 3.6 V
tKCY2/2−16
ns
tSIK2
2.7 V ≤ EVDD0 ≤ 3.6 V
1/fMCK + 40
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
1/fMCK + 60
ns
2.7 V ≤ EVDD0 ≤ 3.6 V
1/fMCK+62
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
1/fMCK+62
ns
Note 2
(to SCKp↑)
SIp hold time
tKSI2
Note 2
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
tKSO2
Note 4
C = 30 pF
Note 3
2.7 V ≤ EVDD0 ≤ 3.6 V
2/fMCK+66
ns
2.4 V ≤ EVDD0 ≤ 3.6 V
2/fMCK+113
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to
3),
g: PIM number (g = 0, 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11))
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78
microcontroller
SIp
SO
SOp
SI
User device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 11, 20, 21)
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
2
(4) During communication at same potential (simplified I C mode)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.7 V ≤ EVDD0 ≤ 3.6 V,
MAX.
Unit
Note 1
kHz
Note 1
kHz
400
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 3.6 V,
100
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 3.6 V,
1200
ns
4600
ns
1200
ns
4600
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
1/fMCK +
ns
Cb = 50 pF, Rb = 2.7 kΩ
220
2.4 V ≤ EVDD ≤ 3.6 V,
1/fMCK +
Cb = 100 pF, Rb = 3 kΩ
580
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
Data setup time (reception)
Data hold time (transmission)
tSU:DAT
tHD:DAT
2.7 V ≤ EVDD0 ≤ 3.6 V,
Note 2
ns
Note 2
0
770
ns
0
1420
ns
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
Notes 1. The value must also be fCLK/4 or lower.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 25- to 48-pin
products)/EVDD tolerance (When 64-pin products)) mode for the SDAr pin and the normal output
mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
2
Simplified I C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
RL78
microcontroller
User device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD : DAT
Remarks 1.
2.
3.
tSU : DAT
Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1), h: POM number (h = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number, mn = 00 to 03, 10, 11)
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Note 1
Transfer rate
Conditions
Reception
MIN.
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
TYP.
MAX.
Unit
fMCK/12
bps
2.6
Mbps
fMCK/12
bps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
2.6
Note 2
Mbps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps.
2. The following conditions are required for low-voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(2/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Transfer
Symbol
Conditions
Transmission
TYP.
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
rate
MIN.
Theoretical value of the maximum
MAX.
Unit
Note 1
bps
1.2
Note 2
Mbps
transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
2.4 V ≤ EVDD0 < 3.3 V,
Note 3
1.6 V ≤ Vb ≤ 2.0 V
Note 4
Theoretical value of the maximum
0.43
bps
Mbps
transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 ≤ 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1
2.0
Vb )} × 3
[bps]
1
− {−Cb × Rb × ln
Transfer rate × 2
2.0
(1 − Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1
1.5
Vb )} × 3
[bps]
1
1.5
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
Rx
TxDq
User device
RL78
microcontroller
Tx
RxDq
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
2.7 V ≤ EVDD0 ≤ 3.6 V,
MIN.
TYP.
MAX.
Unit
tKCY1 ≥ 4/fCLK
1000
ns
tKCY1 ≥ 4/fCLK
2300
ns
tKCY1/2 − 340
ns
tKCY1/2 − 916
ns
tKCY1/2 − 36
ns
tKCY1/2 − 100
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp pin and SCKp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 10, 20), m: Unit number , n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3. CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
tSIK1
SIp setup time
Note 1
(to SCKp↑)
tKSI1
SIp hold time
Note 1
(from SCKp↑)
Delay time from SCKp↓ to
Note 1
SOp output
tKSO1
tSIK1
SIp setup time
Note 2
(to SCKp↓)
tKSI1
SIp hold time
Note 2
(from SCKp↓)
Delay time from SCKp↑ to
Note 2
SOp output
tKSO1
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
354
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
958
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
390
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
966
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
88
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
220
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
50
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
50
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp pin and SCKp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Rb
Vb
Rb
SCK
SCKp
RL78
microcontroller
Remarks 1.
SIp
SO
SOp
SI
User device
Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2.
p: CSI number (p = 00, 10, 20), m: Unit number , n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3.
CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
Remarks 1. p: CSI number (p = 00, 10, 20), m: Unit number, n: Channel number (m = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
2. CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
SCKp cycle time
Note 1
SCKp high-/low-level width
Symbol
tKCY2
tKH2,
tKL2
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V ≤ EVDD0 ≤ 3.6 V,
24 MHz < fMCK
40/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
20 MHz < fMCK ≤ 24 MHz
32/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ EVDD0 < 3.3 V,
24 MHz < fMCK
96/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 − 36
ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2 −
ns
100
SIp setup time
tSIK2
Note 2
(to SCKp↑)
SIp hold time
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
ns
1/fMCK + 40
1/fMCK + 60
1/fMCK + 62
tKSI2
ns
Note 2
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
tKSO2
Note 3
2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
ns
428
2/fMCK +
ns
1146
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp↓“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (When 25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for the SOp
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH
and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78
microcontroller
Remarks 1.
SCK
SIp
SO
SOp
SI
User device
Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2.
p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 02, 10))
4.
CSI01, CSI11, and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
SOp
Output data
Remarks 1. p: CSI number (p = 00, 10, 20), m: Unit number, n: Channel number (mn = 00, 02, 10),
g: PIM and POM number (g = 0, 1)
2. CSI01, CSI11, and CSI21 cannot communicate at different potential.
Use other CSI for
communication at different potential.
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3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
2
(8) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.7 V ≤ EVDD0 ≤ 3.6 V,
MAX.
Unit
Note 1
kHz
100
Note 1
kHz
100
Note 1
kHz
400
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 3.6 V,
1200
ns
4600
ns
4650
ns
500
ns
2400
ns
1830
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the next page.)
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
2
(8) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (2/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Data setup time (reception)
Symbol
tSU:DAT
Data hold time (transmission)
tHD:DAT
Conditions
MIN.
MAX.
Unit
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
Note 2
340
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK +
Note 2
760
ns
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK +
Note 2
570
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
1420
ns
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
0
1215
ns
Notes 1. The value must also be fCLK/4 or lower.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 25- to 48-pin
products)/EVDD tolerance (When 64-pin products)) mode for the SDAr pin and the N-ch open drain
output (VDD tolerance (When 25- to 48-pin products)/EVDD tolerance (When 64-pin products))
mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
2
Simplified I C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDA
SDAr
RL78
microcontroller
User device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD : DAT
Remarks 1.
tSU : DAT
Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2.
r: IIC number (r = 00, 10, 20), g: PIM, POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02, 10)
4.
IIC01, IIC11, and IIC21 cannot communicate at different potential. Use IIC00, IIC10, or IIC20 for
communication at different potential.
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3.5.2
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
3.
Serial interface IICA
2
(1) I C standard mode, fast mode
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
Standard
Conditions
Fast Mode
Unit
Mode
MIN.
SCLA0 clock frequency
fSCL
Setup time of restart condition
Hold time
Note 1
Fast mode: fCLK ≥ 3.5 MHz
2.4 V ≤ EVDD0 ≤ 3.6 V
Normal mode: fCLK ≥ 1 MHz
2.4 V ≤ EVDD0 ≤ 3.6 V
0
MAX.
MIN.
MAX.
0
400
100
kHz
kHz
tSU:STA
4.7
0.6
μs
tHD:STA
4.0
0.6
μs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
μs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
μs
tSU:DAT
250
100
ns
Data hold time (transmission)
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
μs
Bus-free time
tBUF
4.7
1.3
μs
Data setup time (reception)
Note 2
Notes 1.
2.
3.45
0
0.9
μs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode:
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tBUF
Stop
condition
Start
condition
R01DS0151EJ0100 Rev.1.00
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Restart
condition
Stop
condition
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3.6
3.6.1
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Analog Characteristics
A/D converter characteristics
Division of A/D Converter Characteristics
Reference voltag Reference voltage (+) = AVREFP
Reference voltage (−) = AVREFM
Reference voltage (+) = AVDD
Reference voltage (+) = Internal
Reference voltage (−) = AVSS
refrence voltage
Reference voltage (−) = AVSS
Input channel
High-accuracy channel; ANI0 to
See 3.6.1 (1)
See 3.6.1 (2)
See 3.6.1 (3)
See 3.6.1 (4)
See 3.6.1 (3)
See 3.6.1 (4)
See 3.6.1 (5)
ANI12
(input buffer power supply: AVDD)
Standard channel; ANI16 to ANI30
(input buffer power supply: VDD or
EVDD0)
Temperature sensor, internal
−
reference voltage output
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI2 to ANI12
(TA = −40 to +105°C, 2.4 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
RES
Overall error
AINL
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Note
MIN.
8.
TYP.
MAX.
Unit
12.
bit
±6.0
LSB
μs
3.375
12-bit resolution
Note
Zero-scale error
Full-scale error
Note
Integral linearity error
Differential linearity
error
Note
EZS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
LSB
EFS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
LSB
ILE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
LSB
DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
LSB
AVREFP
V
Note
Analog input voltage
VAIN
0
Note Excludes quantization error (±1/2 LSB).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 110 of 123
RL78/G1A
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(2) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM
= 0), target for conversion: ANI0 to ANI12
(TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD,
Reference voltage (−) = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
Overall error
AINL
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
2.4 V ≤ AVDD ≤ 3.6 V
Note
MIN.
8
TYP.
MAX.
Unit
12
bit
±7.5
LSB
μs
3.375
12-bit resolution
Note
Zero-scale error
Full-scale error
Note
Integral linearity error
Note
Differential linearity error
Analog input voltage
Note
EZS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
LSB
EFS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
LSB
ILE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.0
LSB
DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.0
LSB
AVDD
V
VAIN
0
Note Excludes quantization error (±1/2 LSB).
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 111 of 123
RL78/G1A
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(3) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI16 to ANI30, interanal reference voltage,
temperature sensor output voltage
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 2.4 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS =
0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Note 1
Overall error
AINL
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
MIN.
TYP.
8
MAX.
Unit
12
bit
±7.0
LSB
μs
4.125
12-bit resolution
Note 1
Zero-scale error
Full-scale error
Note 1
Integral linearity error
Note 1
Differential linearity error
Analog input voltage
Note 1
EZS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
LSB
EFS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
LSB
ILE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±3.0
LSB
DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
LSB
AVREFP
V
VAIN
0.
and EVDD0
Interanal reference voltage
VBGR
Note 2
V
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
Temperature sensor output voltage
Note 2
VTMPS25
V
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
Notes 1.
2.
Excludes quantization error (±1/2 LSB).
See 3.6.2 Temperature sensor, internal reference voltage output characteristics.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 112 of 123
RL78/G1A
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(4) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM
= 0), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output
voltage
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD0 ≤ 3.6 V, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0 V,
Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
Note 1
Overall error
AINL
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
2.4 V ≤ AVDD ≤ 3.6 V
MIN.
TYP.
8
MAX.
Unit
12
bit
±8.5
LSB
μs
4.125
12-bit resolution
Note 1
Zero-scale error
Full-scale error
Note 1
Integral linearity error
Note 1
Differential linearity error
Analog input voltage
Note 1
EZS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
LSB
EFS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
LSB
ILE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.5
LSB
DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.5
LSB
AVDD and
V
VAIN
0
EVDD0
Notes 1.
2.
Note 2
Interanal reference voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VBGR
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode)
VTMPS25
Note 2
V
V
Excludes quantization error (±1/2 LSB).
See 3.6.2 Temperature sensor, internal reference voltage output characteristics.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 113 of 123
RL78/G1A
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
(5) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference
voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI0 to ANI12, ANI16 to ANI30
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD ≤ VDD, 2.4 V ≤ AVDD ≤ VDD, VSS = EVSS0 = 0 V, AVSS = 0 V,
Reference voltage (+) = Internal reference voltage, Reference voltage (−) = AVSS = 0 V, HS (high-speed main)
mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
TYP.
MAX.
8
Unit
bit
μs
tCONV
8-bit resolution
EZS
8-bit resolution
±4.0
LSB
ILE
8-bit resolution
±2.0
LSB
DLE
8-bit resolution
±2.5
LSB
Reference voltage (+)
AVREF(+)
= Internal reference voltage (VBGR)
1.50
V
Analog input voltage
VAIN
VBGR
V
MAX.
Unit
Note
Zero-scale error
Integral linearity error
Note
Differential linearity error
Note
3.6.2
Note
16.0
1.38
1.45
0
Excludes quantization error (±1/2 LSB).
Temperature sensor, internal reference voltage output characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor output voltage that
TYP.
1.05
1.38
1.45
V
1.5
V
−3.6
mV/°C
depends on the temperature
Operation stabilization wait time
3.6.3
tAMP
μs
10
POR circuit characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Minimum pulse width
Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.45
1.51
1.57
V
VPDR
Power supply fall time
1.44
1.50
1.56
V
TPW
μs
300
This is the time required for the POR circuit to execute a reset when VDD falls below VPDR. When the
microcontroller enters STOP mode or if the main system clock (fMAIN) has been stopped by setting bit 0
(HIOSTOP) and bit 7 (MSTOP) of the clock operation status control register (CSC), this is the time required
for the POR circuit to execute a reset before VDD rises to VPOR after having fallen below 0.7 V.
TPW
Power supply voltage (VDD)
VPOR
VPOR or 0.7 V
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 114 of 123
RL78/G1A
3.6.4
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Detection
Symbol
Supply voltage level
VLVD2
Power supply rise time
voltage
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
3.01
3.13
3.25
V
Power supply fall time
2.94
3.06
3.18
V
Power supply rise time
2.90
3.02
3.14
V
Power supply fall time
2.85
2.96
3.07
V
Power supply rise time
2.81
2.92
3.03
V
Power supply fall time
2.75
2.86
2.97
V
Power supply rise time
2.70
2.81
2.92
V
Power supply fall time
2.64
2.75
2.86
V
Power supply rise time
2.61
2.71
2.81
V
Power supply fall time
2.55
2.65
2.75
V
Power supply rise time
2.51
2.61
2.71
V
Power supply fall time
2.45
2.55
2.65
V
tLW
μs
300
Detection delay time
Remark
300
μs
VLVD (n−1) > VLVDn: n = 3 to 7
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +105°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Interrupt & reset
VLVD5
mode
VLVD4
Conditions
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising release reset voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVD3
Caution
MIN.
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
Set the detection voltage (VLVD) to be within the operating voltage range.
The operating voltage
range depends on the setting of the user option byte (000C2H/010C2H). The following shows
the operating voltage range.
HS (high-speed main) mode: VDD = 2.7 to 3.6 [email protected] MHz to 32 MHz
VDD = 2.4 to 3.6 [email protected] MHz to 16 MHz
3.6.5
Supply voltage rise slope characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Supply voltage rise
Symbol
Conditions
MIN.
SVDD
TYP.
MAX.
Unit
54
V/ms
Caution Be sure to maintain the internal reset state until VDD reaches the operating voltage range specified
in 3.4
AC Characteristics, by using the LVD circuit or external reset pin.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 115 of 123
RL78/G1A
3.7
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Symbol
Data retention supply voltage
Conditions
MIN.
VDDDR
1.44
TYP.
Note
MAX.
Unit
3.6
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data hold mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(inerrupt request)
3.8
Flash Memory Programming Characteristics
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
CPU/peripheral hardware clock
Conditions
MIN.
fCLK
2.4 V ≤ VDD ≤ 3.6 V
Cerwr
Retained for 20 years
TA = 85°C
Retained for 1 years
TA = 25°C
Retained for 5 years
TA = 85°C
100,000
Retained for 20 years
TA = 85°C
10,000
TYP.
1
MAX.
Unit
32
MHz
frequency
Notes 1, 2, 3
Number of code flash rewrites
Notes 1, 2, 3
Number of data flash rewrites
1,000
Times
1,000,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
3.9
Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Transfer rate
R01DS0151EJ0100 Rev.1.00
2013.09.25
Symbol
Conditions
During flash memory programming
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 116 of 123
RL78/G1A
3.10
3.
ELECTRICAL SPECIFICATIONS(G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C)
Timing Specs for Switching Flash Memory Programming Modes
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter
Symbol
How long from when an external reset
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
POR and LVD reset must end before the
tSUINIT
external reset ends.
ends until the initial communication
settings are specified
How long from when the TOOL0 pin is
POR and LVD reset must end before the
tSU
10
μs
1
ms
external reset ends.
placed at the low level until a external
reset ends
How long the TOOL0 pin must be kept at
POR and LVD reset must end before the
tHD
external reset ends.
the low level after an external reset ends
(except flash firmware processing time)
<1>
<2>
<3>
<4>
RESET
723 μs + tHD
process time
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The pins reset ends (POR and LVD reset must end before the external reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external resets end (except flash
firmware processing time)
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 117 of 123
RL78/G1A
4. PACKAGE DRAWINGS
4. PACKAGE
4.1
DRAWINGS
25-pin products
R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA25-3x3-0.50
PWLG0025KA-A
P25FC-50-2N2-2
0.01
21x b
w S A
S AB
M
A
ZD
D
x
e
ZE
5
4
B
3 2.27
E
2
C
1
E
w S B
INDEX MARK
y1
S
D
C
B
A
D
2.27
INDEX MARK
A
S
(UNIT:mm)
y
S
DETAIL OF C PART
DETAIL OF D PART
R0.17±0.05
0.43±0.05
R0.12±0.05 0.33±0.05
0.50±0.05
0.365±0.05
b
(LAND PAD)
0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.365±0.05
ITEM
D
DIMENSIONS
3.00±0.10
E
3.00±0.10
w
0.20
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.50
ZE
0.50
R0.165±0.05
0.50±0.05
0.33±0.05
R0.215±0.05
0.43±0.05
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 118 of 123
RL78/G1A
4.2
4. PACKAGE DRAWINGS
32-pin products
R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA
R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA
JEITA Package code
P-HWQFN32-5x5-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0032KB-A
P32K8-50-3B4-5
0.06
D
17
24
DETAIL OF A PART
16
25
E
A
9
32
A1
C2
8
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
8
9
32
Dimension in Millimeters
Min
Nom
Max
D
4.95
5.00
5.05
E
4.95
5.00
5.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
ZE
16
25
17
24
ZD
e
b
x
M
0.25
0.30
0.50
0.30
0.40
0.50
x
0.05
y
0.05
ZD
0.75
ZE
0.75
c2
0.15
0.20
D2
3.50
E2
3.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 119 of 123
RL78/G1A
4.3
4. PACKAGE DRAWINGS
48-pin products
R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB
R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP48-7x7-0.50
PLQP0048KF-A
P48GA-50-8EU-1
0.16
HD
D
detail of lead end
36
25
37
A3
24
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
13
48
12
1
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
7.00±0.20
E
7.00±0.20
HD
9.00±0.20
HE
9.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
0.75
ZE
0.75
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 120 of 123
RL78/G1A
4. PACKAGE DRAWINGS
R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA
R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA
JEITA Package code
P-HWQFN48-7x7-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0040KB-A
48PJN-A
P40K8-50-5B4-6
0.13
D
25
36
DETAIL OF A PART
24
37
E
A
A1
13
48
C2
12
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
12
1
13
48
Dimension in Millimeters
Min
Nom
Max
D
6.95
7.00
7.05
E
6.95
7.00
7.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
ZE
37
24
36
25
ZD
e
b
x
M
0.25
0.30
0.50
0.30
0.40
0.50
x
0.05
y
0.05
ZD
0.75
ZE
0.75
c2
0.15
0.20
D2
5.50
E2
5.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 121 of 123
RL78/G1A
4.4
4. PACKAGE DRAWINGS
64-pin products
R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB
R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP64-10x10-0.50
PLQP0064KF-A
P64GB-50-UEU-2
0.35
HD
D
detail of lead end
48
33
49
A3
32
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 122 of 123
RL78/G1A
4. PACKAGE DRAWINGS
R5F10ELCABG, R5F10ELDABG, R5F10ELEABG
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-VFBGA64-4x4-0.40
PVBG0064LA-A
P64F1-40-AA2-2
0.03
w
D
S A
ZE
ZD
A
8
7
6
B
5
4
E
3
2
1
H G F E D C B A
INDEX MARK
w
S B
(UNIT:mm)
A
y1
A2
S
S
y
e
S
b
x
M
A1
S A B
INDEX MARK
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.15
4.00±0.10
A
0.89±0.10
A1
0.20± 0.05
A2
0.69
e
0.40
b
0.25 ± 0.05
x
0.05
y
0.08
y1
0.20
ZD
0.60
ZE
0.60
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0151EJ0100 Rev.1.00
2013.09.25
Page 123 of 123
Revision History
Rev.
0.01
1.00
Date
Dec 26, 2011
Sep 25, 2013
RL78/G1A Data Sheet
Description
Summary
Page
p.1
p.4
p.6
p.13
p.14
p.16
p.21
pp.31,
32
pp.34,35
p.37
First Edition issued
Modification of 1.1 Features
Modification of Table 1-1. List of Ordering Part Numbers
Modification of Remark 3 to 1.3.2 32-pin products.
Modification of 1.5.2 32-pin products.
Modification of 1.5.3 48-pin products.
Modification of 1.6 Outline of Functions
Modification of 2.2.1 X1, XT1 oscillator characteristics
Modification of Note 1 in 2.3.2 Supply current characteristics
Modification of Minimum Instruction Execution Time during Main System Clock
Operation
Modification of AC Timing Test Points in 2.5 Peripheral Functions
Characteristics
pp.46 to
p.58
Modification of Caution to 2.5.1 Serial array unit.
pp.63 to
p.68
p.71
Modification of 2.6.1 A/D converter characteristics
p.71
p.72
Modification of 2.7 Data Memory STOP Mode Low Supply Voltage Data
Retention Characteristics
Modification of 2.8 Flash Memory Programming Characteristics
Modification of 2.10 Timing Specs for Switching Flash Memory Programming
Modes
pp.73 to
p.117
Addition of 3 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL
APPLICATIONS TA = −40 to +105°C)
pp.118
to p.123
Modification of 4. PACKAGE DRAWINGS
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
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