NXP PCA6416A Low-voltage translating 16-bit I²C-bus/SMBus I/O expander Data Sheet

PCA6416A

Low-voltage translating 16-bit I

2

C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers

Rev. 2. — 10 January 2013 Product data sheet

The PCA6416A is a 16-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I 2 C-bus interface.

NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCA6416A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required.

Its wide V

DD

range of 1.65 V to 5.5 V on the dual power rail allows seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.

There are two supply voltages for PCA6416A: V

DD(I2C-bus)

and V

DD(P)

. V

DD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the V

DD(P)

provides the supply for core circuits and Port P. The bidirectional voltage level translation in the PCA6416A is provided through V

DD(I2C-bus)

.

V

DD(I2C-bus)

should be connected to the V

DD

of the external SCL/SDA lines. This indicates the V

DD

level of the I 2 C-bus to the PCA6416A. The voltage level on Port P of the

PCA6416A is determined by the V

DD(P)

.

The PCA6416A register set consists of four pairs of 8-bit Configuration, Input, Output, and

Polarity Inversion registers.

At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates.

The system master can reset the PCA6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I 2 C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The PCA6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.

NXP Semiconductors

PCA6416A

Low-voltage translating 16-bit I 2 C-bus/SMBus I/O expander

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I 2 C-bus. Thus, the PCA6416A can remain a simple slave device.

The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I 2 C-bus address and allow up to two devices to share the same I 2 C-bus or SMBus.

2. Features and benefits

 I 2 C-bus to parallel port expander

 Operating power supply voltage range of 1.65 V to 5.5 V

 Allows bidirectional voltage-level translation and GPIO expansion between:

 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P



 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P

 Low standby current consumption:

 1.5

A typical at 5 V V

DD

 1.0

A typical at 3.3 V V

DD

 Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs

 V hys

= 0.18 V (typical) at 1.8 V

 V hys


 V hys


 V hys

= 0.5 V (typical) at 5 V

 5 V tolerant I/O ports

 Active LOW reset input (RESET)

 Open-drain active LOW interrupt output (INT)

 400 kHz Fast-mode I 2 C-bus

 Input/Output Configuration register

 Polarity Inversion register

 Internal power-on reset

 Power-up with all channels configured as inputs

 No glitch on power-up

 Noise filter on SCL/SDA inputs

 Latched outputs with 25 mA drive maximum capability for directly driving LEDs

 Latch-up performance exceeds 100 mA per JESD 78, Class II

 ESD protection exceeds JESD 22

 2000 V Human-Body Model (A114-A)

 1000 V Charged-Device Model (C101)

 Packages offered: TSSOP24, HWQFN24, VFBGA24

PCA6416A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 10 January 2013

© NXP B.V. 2013. All rights reserved.

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PCA6416A


Table 1.

Ordering information

Type number Topside marking

Package

Name Description

PCA6416AEV

PCA6416AHF

416A

416A

VFBGA24 plastic very thin fine-pitch ball grid array package; 24 balls; body 3

 3  0.85 mm

HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4

 4  0.75 mm

PCA6416APW PCA6416A TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm

Version

SOT1199-1

SOT994-1

SOT355-1

3.1 Ordering options

Table 2.

Ordering options

Type number Orderable part number

PCA6416AEV PCA6416AEVJ

PCA6416AHF PCA6416AHF,128

PCA6416APW PCA6416APW,118

Package

VFBGA24

HWQFN24

TSSOP24

Packing method Minimum order quantity

Reel pack, SMD,

13-inch

6000

6000 Reel pack, SMD,

13-inch, turned

Reel pack, SMD,

13-inch

2500

Temperature

T amb

=

40 C to +85 C

T amb

=

40 C to +85 C

T amb

=

40 C to +85 C

PCA6416A

INT

ADDR

SCL

SDA

LP FILTER

INTERRUPT

LOGIC

INPUT

FILTER

I

2

C-BUS

CONTROL

SHIFT

REGISTER

16 BITS

I/O

PORT

P0_0 to P0_7

P1_0 to P1_7

V

DD(I2C-bus)

V

DD(P)

RESET

V

SS

POWER-ON

RESET

All I/Os are set to inputs at reset.

Fig 1.

Block diagram (positive logic) write pulse read pulse

002aaf537

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5.1 Pinning

INT

V

DD(I2C-bus)

RESET

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

V

SS

9

10

11

12

7

8

5

6

3

4

1

2

Fig 2.

PCA6416APW

002aaf535

24

23

22

21

20

19

18

17

V

DD(P)

SDA

SCL

ADDR

P1_7

P1_6

P1_5

P1_4

16

15

14

13

P1_3

P1_2

P1_1

P1_0

Pin configuration for TSSOP24 terminal 1 index area

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

3

4

5

6

1

2

PCA6416AHF

18

17

16

15

14

13

ADDR

P1_7

P1_6

P1_5

P1_4

P1_3

002aaf536

Transparent top view

The exposed center pad, if used, must be connected only as a secondary ground or must be left electrically open.

Fig 3.

Pin configuration for HWQFN24 ball A1 index area

1

PCA6416AEV

2 3 4 5

A

Fig 4.

B

C

D

E

Transparent top view

002aaf786

Pin configuration for VFBGA24

A

1 2

P0_0 RESET

3

INT

4

SDA

5

SCL

B P0_2

C P0_3 P0_4

V

DD(I2C-bus)

V

DD(P)

ADDR

P0_1 P1_7 P1_6

D P0_5 P0_7

E P0_6 V

SS

P1_2

P1_0

P1_4 P1_5

P1_1 P1_3

002aah370

An empty cell indicates no ball is populated at that grid point.

Fig 5.

Ball mapping for VFBGA24

(transparent top view)

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PCA6416A


5.2 Pin description

Table 3.

Pin description

Symbol Pin

TSSOP24 HWQFN24 VFBGA24

INT 1 22 A3

Description

V

DD(I2C-bus)

RESET

V

SS

P1_0

[2]

P1_1

[2]

P1_2

[2]

P1_3

[2]

P1_4

[2]

P1_5

[2]

P1_6

[2]

P1_7

[2]

ADDR

P0_0

[1]

P0_1

[1]

P0_2

[1]

P0_3

[1]

P0_4

[1]

P0_5

[1]

P0_6

[1]

P0_7

[1]

SCL

SDA

V

DD(P)

2

3

16

17

18

19

12

13

14

15

20

21

22

23

24

8

9

10

11

6

7

4

5

23

24

7

8

5

6

3

4

1

2

9

10

11

12

13

14

15

16

17

18

19

20

21

B3

A2

A1

C3

B1

C1

C2

D1

E1

D2

E2

E3

E4

D3

E5

D4

D5

C5

C4

B5

A5

A4

B4

Interrupt output. Connect to V

DD(I2C-bus)

or V

DD(P)

through a pull-up resistor.

Supply voltage of I 2 C-bus. Connect directly to the V

DD

of the external

I 2 C master. Provides voltage-level translation.

Active LOW reset input. Connect to V

DD(I2C-bus)

through a pull-up resistor if no active connection is used.

Port 0 input/output 0.








Ground.









Address input. Connect directly to V

DD(P)

or ground.

Serial clock bus. Connect to V

DD(I2C-bus)


Serial data bus. Connect to V

DD(I2C-bus)


Supply voltage of PCA6416A for Port P.

[1] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input.

[2] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input.

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PCA6416A


Table 4 shows how to set up V

DD

levels for the necessary voltage translation between the

I 2 C-bus and the PCA6416A.

2.5 V

3.3 V

3.3 V

3.3 V

3.3 V

5 V

5 V

5 V

5 V

Table 4.

Voltage translation

V

DD(I2C-bus)

(SDA and SCL of I 2 C master) V

DD(P)

(Port P)

1.8 V 1.8 V

1.8 V

1.8 V

2.5 V

3.3 V

1.8 V

2.5 V

2.5 V

2.5 V

5 V

1.8 V

2.5 V

3.3 V

5 V

1.8 V

2.5 V

3.3 V

5 V

1.8 V

2.5 V

3.3 V

5 V

Refer to

Figure 1 “Block diagram (positive logic)” .

7.1 Device address

The address of the PCA6416A is shown in

Figure 6 .

Fig 6.

PCA6416A address

0 1 slave address

0 0 0 0

AD

DR

R/W fixed hardware selectable

002aah045

ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW

(logic 0) to assign one of the two possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.


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PCA6416A


7.2 Interface definition

Table 5.

Interface definition

Byte

7 (MSB)

I 2 C-bus slave address

I/O data bus

L

P0.7

P1.7

Bit

6 5 4 3 2 1

H L L L L ADDR

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

0 (LSB)

R/W

P0.0

P1.0

7.3 Pointer register and command byte

Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCA6416A. The lower three bits of this data byte state the operation (read or write) and the internal registers (Input,

Output, Polarity Inversion, or Configuration) that will be affected. This register is write only.

Once a new command has been sent, the register that was last addressed continues to be accessed by reads until a new command byte is sent.

B7 B6 B5 B4 B3 B2 B1 B0

002aaf540

Fig 7.

Pointer register bits

0

0

0

0

0

Table 6.

Command byte

Pointer register bits

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

1

0

1

1

0

1

1

0

1

0

1

[1] Undefined.

Command byte

00h

01h

02h

03h

04h

05h

06h

07h

Register Protocol Power-up default

Input port 0

Input port 1

Output port 0 read byte read byte read/write byte

xxxx xxxx [1]

xxxx xxxx

1111 1111

Output port 1 read/write byte 1111 1111

Polarity Inversion port 0 read/write byte 0000 0000

Polarity Inversion port 1 read/write byte 0000 0000

Configuration port 0 read/write byte 1111 1111

Configuration port 1 read/write byte 1111 1111

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7.4 Register descriptions

7.4.1 Input port registers (00h, 01h)

The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect.

The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in

Section 8.2

.

Table 7.

Input port 0 register (address 00h)

Bit

Symbol

Default

7

I0.7

X

6

I0.6

X

5

I0.5

X

4

I0.4

X

3

I0.3

X

2

I0.2

X

1

I0.1

X

0

I0.0

X

Table 8.

Input port 1 register (address 01h)

Bit

Symbol

Default

7

I1.7

X

6

I1.6

X

5

I1.5

X

4

I1.4

X

3

I1.3

X

2

I1.2

X

1

I1.1

X

0

I1.0

X

7.4.2 Output port registers (02h, 03h)

The Output port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that was written to these registers, not the actual pin value. A register pair write is described in

Section 8.1

and a register pair read is described in Section 8.2

.

Table 9.

Output port 0 register (address 02h)

Bit

Symbol

Default

7

O0.7

1

6

O0.6

1

5

O0.5

1

4

O0.4

1

3

O0.3

1

2

O0.2

1

1

O0.1

1

0

O0.0

1

Table 10.

Output port 1 register (address 03h)

Bit

Symbol

Default

7

O1.7

1

6

O1.6

1

5

O1.5

1

4

O1.4

1

3

O1.3

1

2

O1.2

1

1

O1.1

1

0

O1.0

1

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PCA6416A


7.4.3 Polarity inversion registers (04h, 05h)

The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair write is described in

Section 8.1

and a register pair read is described in

Section 8.2

.

Table 11.

Polarity inversion port 0 register (address 04h)

Bit 7 6 5 4 3

Symbol

Default

N0.7

0

N0.6

0

N0.5

0

N0.4

0

N0.3

0

2

N0.2

0

1

N0.1

0

0

N0.0

0

Table 12.

Polarity inversion port 1 register (address 05h)

Bit 7 6 5 4 3

Symbol

Default

N1.7

0

N1.6

0

N1.5

0

N1.4

0

N1.3

0

2

N1.2

0

1

N1.1

0

0

N1.0

0

7.4.4 Configuration registers (06h, 07h)

The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin

is enabled as an output. A register pair write is described in Section 8.1

and a register pair

read is described in Section 8.2

.

Table 13.

Configuration port 0 register (address 06h)

Bit 7 6 5 4

Symbol

Default

C0.7

1

C0.6

1

C0.5

1

C0.4

1

3

C0.3

1

2

C0.2

1

1

C0.1

1

0

C0.0

1

Table 14.

Configuration port 1 register (address 07h)

Bit 7 6 5 4

Symbol

Default

C1.7

1

C1.6

1

C1.5

1

C1.4

1

3

C1.3

1

2

C1.2

1

1

C1.1

1

0

C1.0

1

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PCA6416A


7.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V

DD(P)

to a maximum of

5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and either V

DD(P)

or V

SS

. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

data from shift register data from shift register write configuration pulse write pulse configuration register

D Q

FF

CK Q

D Q

FF

CK output port register

Q1

Q2 output port register data

V

DD(P) read pulse input port register

D Q

FF

CK

ESD protection diode

P0_0 to P0_7

P1_0 to P1_7

V

SS input port register data to INT data from shift register write polarity pulse polarity inversion register

D

CK

FF

Q polarity inversion register data

002aaf538

On power-up or reset, all registers return to default values.

Fig 8.

Simplified schematic of P0_0 to P1_7

7.6 Power-on reset

When power (from 0 V) is applied to V

DD(P)

, an internal power-on reset holds the

PCA6416A in a reset condition until V

DD(P)

has reached V

POR

. At that time, the reset condition is released and the PCA6416A registers and I 2 C-bus/SMBus state machine initializes to their default states. After that, V

DD(P)

must be lowered to below V

POR

and

back up to the operating voltage for a power-reset cycle. See Section 9.2 “Power-on reset requirements”

.

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PCA6416A


7.7 Reset input (RESET)

The RESET input can be asserted to initialize the system while keeping the V

DD(P)

at its operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of t w(rst)

. The PCA6416A registers and I 2 C-bus/SMBus state machine are changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor to V

DD(I2C-bus)

if no active connection is used.

7.8 Interrupt output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.

After time t v(INT)

, the signal INT is valid. The interrupt is reset when data on the port changes back to the original value or when data is read from the port that generated the interrupt (see

Figure 12 ). Resetting occurs in the Read mode at the acknowledge (ACK)

or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after resetting is detected and is transmitted as INT.

A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to V

DD(P)

or

V

DD(I2C-bus)

depending on the application. INT should be connected to the voltage source of the device that requires the interrupt information.

PCA6416A


The PCA6416A is an I 2 C-bus slave device. Data is exchanged between the master and

PCA6416A through write and read commands using I 2 C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Write commands

Data is transmitted to the PCA6416A by sending the device address and setting the Least

Significant Bit (LSB) to a logic 0 (see

Figure 6 for device address). The command byte is

sent after the address and determines which register receives the data that follows the command byte.

The eight registers within the PCA6416A are configured to operate as four register pairs.

The four pairs are input ports, output ports, polarity inversion and configuration registers.

After sending data to one register, the next data byte is sent to the other register in the pair

(see Figure 9

and

Figure 10

). For example, if the first byte is sent to Output Port 1

(register 3), the next byte is stored in Output Port 0 (register 2).

There is no limit on the number of data bytes sent in one write transmission. In this way, the host can continuously update a register pair independently of the other registers or the host can simply update a single register.


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SCL 1 2 3 4 5 6 7 8 9

STOP condition slave address command byte

SDA S 0 1 0 0 0 0

AD

DR

0 A 0 0 0 0 0 0 1 0 A 0.7

START condition R/W acknowledge from slave acknowledge from slave data to port 0

DATA 0 write to port t v(Q)

0.0 A 1.7

acknowledge from slave data to port 1

DATA 1 data out from port 0 DATA 0 VALID t v(Q)

1.0

A P acknowledge from slave data out from port 1 DATA 1 VALID

002aaf556

Fig 9.

Write to Output port register

SCL 1 2 3 4 5 6 7 8 9

STOP condition slave address command byte data to register

SDA S 0 1 0 0 0 0

START condition

AD

DR

0

R/W

A 0 0 0 0 0 1/0 1/0 1/0 A acknowledge from slave

MSB acknowledge from slave

DATA 0 data to register

A

LSB MSB acknowledge from slave

DATA 1 A P

LSB acknowledge from slave

002aaf557

Fig 10. Write to device registers


PCA6416A


8.2 Read commands

To read data from the PCA6416A, the bus master must first send the PCA6416A address with the least significant bit set to a logic 0 (see

Figure 6 for device address).

The command byte is sent after the address and determines which register is to be accessed.

After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte is sent by the PCA6416A

(see Figure 11

and Figure 12

). Data is clocked into the register on the rising edge of the

ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data.

After a subsequent restart, the command byte contains the value of the next register to be read in the pair. For example, if Input Port 1 was read last before the restart, the register that is read after the restart is the Input Port 0.

slave address command byte

SDA S 0 1 0 0 0 0 AD

DR

0 A 0 0 0 0 0 1/0 1/0 1/0 A

(cont.)

(cont.)

START condition

S 0

R/W acknowledge from slave acknowledge from slave slave address

1 0 0 0 0 AD 1 A

MSB data from lower or upper byte of register

LSB

DATA (first byte) A

MSB data from upper or lower byte of register

DATA (last byte)

LSB

NA P

(repeated)

START condition

R/W acknowledge from slave acknowledge from master no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter

STOP condition

002aaf558

Fig 11. Read from device registers

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Rev. 2 — 10 January 2013


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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx data into port 0 data into port 1

INT t v(INT) t rst(INT)

SCL 1 2 3 4 5 6 7 8

R/W

9 slave address I0.x

I1.x

SDA S 0 1 0 0 0 0

AD

DR

1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0

START condition acknowledge from slave acknowledge from master acknowledge from master read from port 0

STOP condition

I0.x

I1.x

7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P acknowledge from master

non acknowledge from master read from port 1

002aah131

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to ‘00’ (read input port register).

This figure eliminates the command byte transfer and a restart between the initial slave address call and actual data transfer from P port (see

Figure 11 ).

Fig 12. Read input port register, scenario 1

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx data into port 0 DATA 00 t h(D)

DATA 10

DATA 01 data into port 1

INT t v(INT)

SCL 1 2 3 4 5 6 7 8

R/W

9 slave address

SDA S 0 1 0 0 0 0

AD

DR

1 A

START condition acknowledge from slave read from port 0 read from port 1 t rst(INT)

I0.x

DATA 00 acknowledge from master

A t h(D)

DATA 02 t su(D)

DATA 11

I1.x


DATA 03 t su(D)

I0.x


A

DATA 12

I1.x

DATA 12

STOP condition

1 P

non acknowledge from master

002aah132

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to ‘00’ (read input port register).

This figure eliminates the command byte transfer and a restart between the initial slave address call and actual data transfer from P port (see

Figure 11 ).

Fig 13. Read input port register, scenario 2


PCA6416A


V

DD(I2C-bus)

V

DD(P)

V

DD(I2C-bus)

= 1.8 V

10 kΩ 10 kΩ 10 kΩ 10 kΩ

V

DD

MASTER

CONTROLLER

SCL

SDA

INT

RESET

V

SS

10 kΩ (× 7)

V

DD(I2C-bus)

V

DD(P)

ADDR

V

SS

P0_0

P0_1

SCL

SDA

INT

RESET

PCA9614A

P1_0

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

ALARM

(1)

SUBSYSTEM 1

(e.g., alarm system)

A enable controlled switch

B

KEYPAD

002aaf594

Device address configured as 0100 000x for this example.

P0_0 and P0_2 through P1_0 are configured as inputs.

P0_1 and P1_1 through P1_7 are configured as outputs.

(1) External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed. If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an output in the P port is configured as an open-drain output, external pull-up resistors are required.

Fig 14. Typical application

9.1 Minimizing I

DD

when the I/Os are used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V

DD(P)

through a

resistor as shown in Figure 14

. Since the LED acts as a diode, when the LED is off the I/O

V

I

is about 1.2 V less than V

DD(P)

. The supply current, I

DD(P)

, increases as V

I

becomes lower than V

DD(P)

.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V

DD(P)

when the LED is

off. Figure 15 shows a high value resistor in parallel with the LED. Figure 16 shows V

DD(P) less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O

V

I

at or above V

DD(P)

and prevents additional supply current consumption when the LED is off.

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PCA6416A


3.3 V 5 V

V

DD

V

DD(P)

Pn

LED

100 kΩ V

DD(P)

Pn

LED

002aah278

Fig 15. High value resistor in parallel with the LED

002aah279

Fig 16. Device supplied by a lower voltage

9.2 Power-on reset requirements

In the event of a glitch or data corruption, PCA6416A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in

Figure 17 and Figure 18 .

V

DD(P) ramp-up ramp-down re-ramp-up t d(rst) time

(dV/dt) r

(dV/dt) f time to re-ramp when V

DD(P)

drops below 0.2 V or to V

SS

(dV/dt) r

002aag960

Fig 17. V

DD(P)

is lowered below 0.2 V or to 0 V and then ramped up to V

DD(P)

V

DD(P) ramp-down ramp-up t d(rst)

V

I

drops below POR levels

(dV/dt) f

(dV/dt) r time time to re-ramp when V

DD(P)

drops to V

POR(min)

− 50 mV

002aag961

Fig 18. V

DD(P)

is lowered below the POR threshold, then ramped back up to V

DD(P)

Table 15 specifies the performance of the power-on reset feature for PCA6416A for both

types of power-on reset.

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Rev. 2 — 10 January 2013


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PCA6416A


Table 15.

Recommended supply sequencing and ramp rates

T amb

= 25



C (unless otherwise noted). Not tested; specified by design.

Symbol Parameter Condition

(dV/dt) f

(dV/dt) r t d(rst) fall rate of change of voltage rise rate of change of voltage reset delay time glitch supply voltage difference

Figure 17

Figure 17

Figure 17 ; re-ramp time when

V

DD(P) drops below 0.2 V or to V

SS

Figure 18 ; re-ramp time when

V

DD(P)

drops to V

POR(min)

 50 mV

Figure 19

V

DD(gl) t w(gl)VDD

V

POR(trip) supply voltage glitch pulse width power-on reset trip voltage

Figure 19

falling V

DD(P) rising V

DD(P)

[1]

-

[2]

-

0.7

-

Min

0.1

0.1

1

1

-

-

-

-

-

-

-

-

Typ

-

1.0

-

10

1.4

Max Unit

2000 ms

-

2000 ms

s

[1] Level that V

DD(P)

can glitch down to with a ramp rate at 0.4

s/V, but not cause a functional disruption when t w(gl)VDD

< 1

s.

[2] Glitch width that will not cause a functional disruption when

V

DD(gl)

= 0.5

 V

DD(P)

.

s

V

s

V

V

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (t w(gl)VDD

) and glitch height (

V

DD(gl)

) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 19 and Table 15 provide more information on

how to measure these specifications.

V

DD(P)

∆V

DD(gl) t w(gl)VDD time

002aag962

Fig 19. Glitch width and glitch height

V

POR

is critical to the power-on reset. V

POR

is the voltage level at which the reset condition is released and all the registers and the I 2 C-bus/SMBus state machine are initialized to their default states. The value of V

POR

differs based on the V

DD

being lowered to or from

0 V.

Figure 20 and Table 15 provide more details on this specification.

V

DD(P)

V

POR

(rising V

DD(P)

)

V

POR

(falling V

DD(P)

) time

POR time

002aag963

PCA6416A


Fig 20. Power-on reset voltage (V

POR

)


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PCA6416A


10. Limiting values

Table 16.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Conditions

V

O

I

IK

I

OK

I

IOK

Symbol

V

DD(I2C-bus)

I 2 C-bus supply voltage

V

V

I

DD(P)

Parameter supply voltage port P input voltage output voltage input clamping current output clamping current input/output clamping current

I

I

I

I

I

OL

OH

DD

DD(P)

DD(I2C-bus)

T stg

T j(max)

LOW-level output current

HIGH-level output current supply current supply current port P

I 2 C-bus supply current storage temperature maximum junction temperature

ADDR, RESET, SCL; V

I

< 0 V

INT; V

O

< 0 V

P port; V

O

< 0 V or V

O

> V

DD(P)

SDA; V

O

< 0 V or V

O

> V

DD(I2C-bus) continuous; P port; V

O

= 0 V to V

DD(P) continuous; SDA, INT; V

O

V

DD(I2C-bus)

= 0 V to continuous; P port; V

O

= 0 V to V

DD(P) continuous through V

SS continuous through V

DD(P) continuous through V

DD(I2C-bus)

[1]

[1]

-

-

-

-

-

-

-

-

-

-

-

Min

0.5

0.5

0.5

0.5

65

Max

+6.5

+6.5

+6.5

+6.5

20

20

20

20

50

25

25

200

160

10

+150

125

[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

mA mA mA mA

C

C

V mA mA mA

V

V

Unit

V mA mA mA

11. Recommended operating conditions

Table 17.

Operating conditions

Symbol

V

DD(I2C-bus)

V

DD(P)

V

IH

Parameter

I 2 C-bus supply voltage supply voltage port P

HIGH-level input voltage

Conditions

V

IL

I

OH

I

OL

T amb

LOW-level input voltage

HIGH-level output current

LOW-level output current ambient temperature

SCL, SDA, RESET

ADDR, P1_7 to P0_0

SCL, SDA, RESET

ADDR, P1_7 to P0_0

P1_7 to P0_0

P1_7 to P0_0 operating in free air

Min

1.65

-

1.65

0.7

 V

DD(I2C-bus)

0.7

 V

DD(P)

0.5

0.5

-

40

Max

5.5

5.5

5.5

5.5

0.3

 V

DD(I2C-bus)

0.3

 V

DD(P)

10

25

+85

V

V

V mA mA

C

V

V

Unit

V

PCA6416A



Rev. 2 — 10 January 2013


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PCA6416A


12. Thermal characteristics

Table 18.

Thermal characteristics

Symbol

Z th(j-a)

Parameter Conditions transient thermal impedance from junction to ambient TSSOP24 package

HWQFN24 package

VFBGA24 package

[1] The package thermal impedance is calculated in accordance with JESD 51-7.

13. Static characteristics

Table 19.

Static characteristics

T amb

=



40



C to +85



C; V

DD(I2C-bus)

= 1.65 V to 5.5 V; unless otherwise specified.

I

Symbol

V

V

V

V

IK

POR

OH

OL

Parameter input clamping voltage power-on reset voltage

Conditions

I

I

=

18 mA

V

I

= V

DD(P)

or V

SS

; I

O

= 0 mA

HIGH-level output voltage P port

I

OH

=

8 mA; V

DD(P)

= 1.65 V

I

OH

=

10 mA; V

DD(P)

= 1.65 V

I

OH

=

8 mA; V

DD(P)

= 2.3 V

I

OH

=

10 mA; V

DD(P)

= 2.3 V

I

OH

=

8 mA; V

DD(P)

= 3.0 V

I

OH

=

10 mA; V

DD(P)

= 3.0 V

I

OH

=

8 mA; V

DD(P)

= 4.5 V

I

OH

=

10 mA; V

DD(P)

= 4.5 V

LOW-level output voltage P port; I

OL

= 8 mA

V

DD(P)

= 1.65 V

V

DD(P)

= 2.3 V

OL

V

DD(P)

= 3 V

V

DD(P)

= 4.5 V

LOW-level output current V

OL

= 0.4 V; V

DD(P)

= 1.65 V to 5.5 V

SDA

INT

P port

V

OL

= 0.5 V; V

DD(P)

= 1.65 V

V

OL

= 0.7 V; V

DD(P)

= 1.65 V

V

OL

= 0.5 V; V

DD(P)

= 2.3 V

V

OL

= 0.7 V; V

DD(P)

= 2.3 V

V

OL

= 0.5 V; V

DD(P)

= 3.0 V

V

OL

= 0.7 V; V

DD(P)

= 3.0 V

V

OL

= 0.5 V; V

DD(P)

= 4.5 V

V

OL

= 0.7 V; V

DD(P)

= 4.5 V

[2]

-

[2]

-

[2]

-

[2]

-

[2]

1.2

[2]

1.1

[2]

1.8

[2]

1.7

[2]

2.6

[2]

2.5

[2]

4.1

[2]

4.0

-

-

-

-

-

-

-

-

[3]

3

[3]

3

[3]

8

[3]

10

[3]

8

[3]

10

[3]

8

[3]

10

[3]

8

[3]

10

Max

[1]

88

[1]

66

[1]

171

Unit

K/W

K/W

K/W

-

Min Typ

[1]

1.2

-

1.1

-

Max Unit

V

1.4

V

-

-

-

-

-

15

[4]

-

-

-

-

-

-

-

-

-

-

13

14

19

17

24

10

13

10

-

-

-

-

-

-

-

-

0.45

V

0.25

V

0.25

V

0.2

V mA mA mA mA mA mA mA mA

V

V

V

V

V

V

V

V mA mA

PCA6416A



Rev. 2 — 10 January 2013


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PCA6416A


Table 19.

Static characteristics …continued

T amb

=



40



C to +85



C; V

DD(I2C-bus)

= 1.65 V to 5.5 V; unless otherwise specified.

Symbol Parameter Conditions

I

I

I

IH

I

IL

I

DD

I

DD

C i

C io input current

HIGH-level input current

LOW-level input current supply current additional quiescent supply current input capacitance input/output capacitance

V

DD(P)

= 1.65 V to 5.5 V

SCL, SDA, RESET; V

I

= V

DD(I2C-bus)

or V

SS

ADDR; V

I

= V

DD(P)

or V

SS

P port; V

I

= V

DD(P)

; V

DD(P)

= 1.65 V to 5.5 V

P port; V

I

= V

SS

; V

DD(P)

= 1.65 V to 5.5 V

I

DD(I2C-bus)

+ I

DD(P)

;

SDA, P port, ADDR, RESET;

V

I

V

I on SDA and RESET = V on P port and ADDR = V

DD(I2C-bus)

DD(P)

;

or V

I

O

= 0 mA; I/O = inputs; f

SCL

= 400 kHz

SS

;

V

DD(P)

= 3.6 V to 5.5 V

V

DD(P)

= 2.3 V to 3.6 V

V

DD(P)

= 1.65 V to 2.3 V

I

DD(I2C-bus)

+ I

DD(P)

;

SCL, SDA, P port, ADDR, RESET;

V

I on SCL, SDA and RESET = V

DD(I2C-bus)

or V

SS

;

V

I

on P port and ADDR = V

DD(P)

;

I

O

= 0 mA; I/O = inputs; f

SCL

= 0 kHz

V

DD(P)

= 3.6 V to 5.5 V

V

DD(P)

= 2.3 V to 3.6 V

V

DD(P)

= 1.65 V to 2.3 V

Active mode; I

DD(I2C-bus)

+ I

DD(P)

;

P port, ADDR, RESET;

V

I on RESET = V

DD(I2C-bus)

;

V

I

on P port and ADDR = V

DD(P)

; f

I

O

= 0 mA; I/O = inputs;

SCL

= 400 kHz, continuous register read

V

DD(P)

= 3.6 V to 5.5 V

V

DD(P)

= 2.3 V to 3.6 V

V

DD(P)

= 1.65 V to 2.3 V

SCL, SDA, RESET; one input at V

DD(I2C-bus)

 0.6 V, other inputs at V

DD(I2C-bus)

or V

SS

;

V

DD(P)

= 1.65 V to 5.5 V

P port, ADDR; one input at V

DD(P)

 0.6 V, other inputs at V

DD(P)

or V

SS

;

V

DD(P)

= 1.65 V to 5.5 V

V

I

= V

DD(I2C-bus)

or V

SS

; V

DD(P)

= 1.65 V to 5.5 V

V

I/O

= V

DD(I2C-bus)

or V

SS

; V

DD(P)

= 1.65 V to 5.5 V

V

I/O

= V

DD(P)

or V

SS

; V

DD(P)

= 1.65 V to 5.5 V

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Min Typ [1] Max Unit

-

60

40

-

20

-

-

-

-

10

6.5

4

1.5

1

0.5

6

7

7.5

25

15

9

1

1

1

1

7

3.2

1.7

125

A

75

A

45

25

A

A

80

7

8

8.5

pF pF pF

A

A

A

A

A

A

A

A

A

A

A

[1] For I

DD

, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V V

DD typical values are at V

DD(P)

= V

DD(I2C-bus)

= 3.3 V and T amb

= 25

C.

) and T amb

= 25

C. Except for I

DD

, the

[2] The total current sourced by all I/Os must be limited to 160 mA.

[3] Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.

[4] Typical value for T amb

= 25

C. V

OL

= 0.4 V and V

DD

= 3.3 V. Typical value for V

DD

< 2.5 V, V

OL

= 0.6 V.

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Rev. 2 — 10 January 2013


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PCA6416A


13.1 Typical characteristics

002aag973

I

DD

(μA)

20

16

12

V

DD(P)

= 5.5 V

5.0 V

3.6 V

3.3 V

2.5 V

2.3 V

8

4

0

−40 −15 10

V

DD(P)

= 1.8 V

1.65 V

35 60

T amb

85

(°C)

I

DD

= I

DD(I2C-bus)

+ I

DD(P)

Fig 21. Supply current versus ambient temperature

I

DD

(μA)

20

16

12

8

4

0

1.5

T amb

= 25

C

I

DD

= I

DD(I2C-bus)

+ I

DD(P)

Fig 23. Supply current versus supply voltage

2.5

3.5

002aag974

1400

I

DD(stb)

(nA)

1000

800

600

400

200

0

−40 −15

V

DD(P)

= 5.5 V

5.0 V

3.6 V

3.3 V

2.5 V

2.3 V

1.8 V

1.65 V

10 35 60

T

85 amb

(°C)

Fig 22. Standby supply current versus ambient temperature

002aag975

4.5

V

DD(P)

(V)

5.5

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PCA6416A


T amb

= −40 °C

25 °C

85 °C

002aaf578

T amb

= −40 °C

25 °C

85 °C

002aaf579

I sink

(mA)

35

30

25

20

15

10

5

0

0

I sink

(mA)

35

30

25

20

15

10

5

0

0 0.1

0.2

V

OL

(V)

0.3

0.1

0.2

V

OL

(V)

0.3

a. V

DD(P)

= 1.65 V b. V

DD(P)

= 1.8 V

T amb

= −40 °C

25 °C

85 °C

002aaf580

60

I sink

(mA)

40

20

T amb

= −40 °C

25 °C

85 °C

002aaf581

I sink

(mA)

50

40

30

20

10

0

0 0.1

0.2

V

OL

(V)

0.3

0

0 0.1

0.2

V

OL

(V)

0.3

c. V

DD(P)

= 2.5 V d. V

DD(P)

= 3.3 V

T amb

= −40 °C

25 °C

85 °C

002aaf582

I sink

(mA)

70

60

50

40

30

20

10

0

0 0.1

0.2

V

OL

(V)

0.3

e. V

DD(P)

= 5.0 V

Fig 24. I/O sink current versus LOW-level output voltage

I sink

(mA)

70

60

50

40

30

20

10

0

0 f. V

DD(P)

0.1

= 5.5 V

T amb

= −40 °C

25 °C

85 °C

002aaf583

0.2

V

OL

(V)

0.3

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30

I source

(mA)

20

10

0

0

T amb

= −40 °C

25 °C

85 °C a. V

DD(P)

= 1.65 V

60

I source

(mA)

40

T amb

= −40 °C

25 °C

85 °C

20

0

0

0.2

0.2

c. V

DD(P)

= 2.5 V

90

I source

(mA)

60

T amb

= −40 °C

25 °C

85 °C

002aaf561

0.4

V

DD(P)

− V

OH

0.6

(V)

002aaf563

0.4

V

DD(P)

− V

OH

0.6

(V)

002aaf565

T amb

= −40 °C

25 °C

85 °C

002aaf562

I source

35

(mA)

30

25

20

15

10

5

0

0 0.2

0.4

V

DD(P)

− V

OH

0.6

(V) b. V

DD(P)

= 1.8 V

T amb

= −40 °C

25 °C

85 °C

002aaf564

I source

70

(mA)

60

50

40

30

20

10

0

0 0.2

d. V

DD(P)

= 3.3 V

90

I source

(mA)

60

T amb

= −40 °C

25 °C

85 °C

0.4

V

DD(P)

− V

OH

0.6

(V)

002aaf566

30 30

0

0 0.2

0.4

V

DD(P)

− V

OH

0.6

(V) e. V

DD(P)

= 5.0 V

Fig 25. I/O source current versus HIGH-level output voltage

0

0 0.2

f. V

DD(P)

= 5.5 V

0.4

V

DD(P)

− V

OH

0.6

(V)

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002aah056

V

OL

(mV)

120

100

80

60

(1)

(2)

40

20

0

−40

(3)

−15

(4)

10 35 60 85

T amb

(°C)

(1) V

DD(P)

= 1.8 V; I sink

= 10 mA

(2) V

DD(P)

= 5 V; I sink

= 10 mA

(3) V

DD(P)

= 1.8 V; I sink

= 1 mA

(4) V

DD(P)

= 5 V; I sink

= 1 mA

Fig 26. LOW-level output voltage versus temperature

200

V

DD(P)

− V

OH

(mV)

160

120

80

V

DD(P)

= 1.8 V

5 V

40

0

−40 −15 10

I source

=

10 mA

35

002aah057

60

T

85 amb

(°C)

Fig 27. I/O high voltage versus temperature

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14. Dynamic characteristics

Table 20.

I 2 C-bus interface timing requirements

Over recommended operating free air temperature range, unless otherwise specified. See

Figure 29 .

Symbol Parameter Conditions Standard-mode

I 2 C-bus

Fast-mode I 2 C-bus Unit

Min Max Min Max f

SCL t

HIGH t

LOW t

SP

SCL clock frequency

HIGH period of the SCL clock

LOW period of the SCL clock pulse width of spikes that must be suppressed by the input filter data set-up time

0

4

4.7

0

100

-

-

50

0

0.6

1.3

0

400 kHz

-

s

-

s

50 ns t t t r t f t

SU;DAT t

HD;DAT

BUF

SU;STA data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals bus free time between a STOP and

START condition set-up time for a repeated START condition

250

0

-

-

4.7

4.7

-

-

1000

300

-

-

100

0

20

(V

DD

20



/ 5.5 V)

1.3

0.6

ns

ns

300 ns

300 ns

-

-

s

s t t t t

HD;STA

SU;STO

VD;DAT

VD;ACK hold time (repeated) START condition set-up time for STOP condition data valid time data valid acknowledge time

SCL LOW to

SDA output valid

ACK signal from

SCL LOW to

SDA (out) LOW

4

4

-

-

-

-

3.45

3.45

0.6

0.6

-

-

-

-

s

s

0.9

s

0.9

s

Table 21.

Reset timing requirements

Over recommended operating free air temperature range, unless otherwise specified. See

Figure 31 .


I 2 C-bus

Min Max

Fast-mode

I 2 C-bus

Min Max t w(rst) t rec(rst) t rst reset pulse width reset recovery time reset time

[1]

30

200

600

-

-

-

30

200

600

-

-

-

[1] Minimum time for SDA to become HIGH or minimum time to wait before doing a START.

Unit ns ns ns

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Table 22.

Switching characteristics

Over recommended operating free air temperature range; C

L



100 pF; unless otherwise specified. See Figure 30

.


I 2 C-bus

Fast-mode

I 2 C-bus

Min Max Min t v(INT) t rst(INT) t v(Q) t su(D) t h(D) valid time on pin INT reset time on pin INT data output valid time data input set-up time data input hold time from P port to INT from SCL to INT from SCL to P port from P port to SCL from P port to SCL

-

0

-

-

300

1

1

400

-

-

-

0

-

-

300

Max

1

1

s

s

400 ns

ns

-

Unit ns

15. Parameter measurement information

DUT

V

DD(I2C-bus)

RL = 1 kΩ

SDA

CL = 50 pF

002aag977 a. SDA load configuration

STOP condition

(P)

START condition

(S)

Address

Bit 7

(MSB) two bytes for read Input port register

(1)

Address

Bit 1

R/W

Bit 0

(LSB)

ACK

(A)

Data

Bit 7

(MSB)

Data

Bit 0

(LSB)

STOP condition

(P)

002aag952 b. Transaction format t

LOW t

HIGH t

SP

SCL

SDA t

BUF t r t f t

VD;DAT t f(o) t

VD;ACK t

SU;STA

0.7 × V

DD(I2C-bus)

0.3 × V

DD(I2C-bus) t

SU;STO

0.7 × V

DD(I2C-bus)

0.3 × V

DD(I2C-bus) t f t

HD;STA t r t

SU;DAT t

HD;DAT t

VD;ACK repeat START condition

STOP condition c. Voltage waveforms

C

L

includes probe and jig capacitance.

All inputs are supplied by generators having the following characteristics: PRR

 10 MHz; Z o

= 50

; t r

/t f

 30 ns.

All parameters and waveforms are not applicable to all devices.

Byte 1 = I

2

C-bus address; Byte 2, byte 3 = P port data.

(1) See

Figure 12

.

Fig 28. I 2 C-bus interface load circuit and voltage waveforms

002aag978

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DUT

V

DD(I2C-bus)

RL = 4.7 kΩ

INT

CL = 100 pF

002aag979 a. Interrupt load configuration

START condition slave address

R/W acknowledge from slave

8 bits (one data byte) from port

SDA S 0 1 0 0 0 0

AD

DR

1 A DATA 1 acknowledge from slave no acknowledge from master data from port

STOP condition

A DATA 2 1 P

SCL 1 2 3 4 5 6 7 8 9 t rst(INT) t rst(INT)

B

B

INT data into port t v(INT)

A

A

ADDRESS DATA 1 t su(D)

DATA 2

INT 0.5 × V

DD(I2C-bus)

SCL R/W A

0.7 × V

DD(I2C-bus)

0.3 × V

DD(I2C-bus) t v(INT) t rst(INT)

Pn 0.5 × V

DD(P)

INT 0.5 × V

DD(I2C-bus)

View A - A View B - B

002aag980 b. Voltage waveforms

C

L



 10 MHz; Z o

= 50

; t r

/t f

 30 ns.


Fig 29. Interrupt load circuit and voltage waveforms

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DUT

Pn 500 Ω

CL = 50 pF 500 Ω

2 × V

DD(P)

002aag981 a. P port load configuration

SCL P0 A P7

0.7 × V

DD(I2C-bus)

0.3 × V

DD(I2C-bus)

SDA t v(Q)

Pn unstable data last stable bit

002aag982 b. Write mode (R/W = 0)

SCL P0 t su(D)

A t h(D)

P7

0.7 × V

DD(I2C-bus)

0.3 × V

DD(I2C-bus)

Pn 0.5 × V

DD(P)

002aag983 c. Read mode (R/W = 1)

C

L


t v(Q)

is measured from 0.7

 V

DD(I2C-bus)

on SCL to 50 % I/O (Pn) output.


 10 MHz; Z o

= 50

; t r

/t f

 30 ns.

The outputs are measured one at a time, with one transition per measurement.


Fig 30. P port load circuit and voltage waveforms

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DUT

V

DD(I2C-bus)

RL = 1 kΩ

SDA

CL = 50 pF

002aag977 a. SDA load configuration

SCL

START

DUT

Pn 500 Ω

CL = 50 pF 500 Ω

2 × V

DD(P)

002aag981 b. P port load configuration

ACK or read cycle

SDA

0.3 × V

DD(I2C-bus) t rst

RESET t rec(rst) t w(rst)

0.5 × V

DD(I2C-bus) t rec(rst) t rst

Pn 0.5 × V

DD(P) c. RESET timing

C

L



 10 MHz; Z o

= 50

; t r

/t f

 30 ns.

The outputs are measured one at a time, with one transition per measurement.

I/Os are configured as inputs.


Fig 31. Reset load circuits and voltage waveforms

002aag984

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16. Package outline

HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.75 mm SOT994-1

B A D terminal 1 index area

E A

A

1 c detail X

L

6

7 e e

1

1/2 e b

12

∅ v M

∅ w M

C

C

A B

13 e y

1

C

C y

E h

1/2 e e

2 terminal 1 index area

1

24 19

18

X

D h

0 2.5

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

(1) max

A

1 b c D

(1)

D h mm 0.8

0.05

0.00

0.30

0.18

0.2

4.1

3.9

2.25

1.95

E

(1)

4.1

3.9

E h

2.25

1.95

e

0.5

e

1

2.5

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE

VERSION

SOT994-1

IEC

- - -

REFERENCES

JEDEC JEITA

MO-220 - - e

2

2.5

5 mm

L

0.5

0.3

v w y y

1

0.1

0.05

0.05

0.1

EUROPEAN

PROJECTION

ISSUE DATE

07-02-07

07-03-03

Fig 32. Package outline SOT994-1 (HWQFN24)

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TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

24

Z y

1 pin 1 index e

D c

E A

X v M A H

E

13 b p

12 w

M

A

2

A

1

L

L p detail X

Q

θ

A

0 2.5

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 1.1

0.15

0.05

0.95

0.80

0.25

0.30

0.19

0.2

0.1

D

(1)

7.9

7.7

E

(2)

4.5

4.3

e

0.65

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

IEC

REFERENCES

JEDEC JEITA

SOT355-1 MO-153

H

E

6.6

6.2

5 mm

L

1

L p

0.75

0.50

Q

0.4

0.3

v w y

0.2

0.13

0.1

Z

(1)

0.5

0.2

θ

8 o

0 o

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

03-02-19

Fig 33. Package outline SOT355-1 (TSSOP24)

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VFBGA24: plastic very thin fine-pitch ball grid array package;

24 balls; body 3 x 3 x 0.85 mm SOT1199-1

D B A ball A1 index area

E A

A

2

A

1 detail X e e

1 b

Ø v

Ø w

C

C

A B ball A1 index area

C

B

A

E

D

1 2 3 4 5 e e

2

0

Dimensions mm

Unit A A

1

A

2 max nom min

1.00

0.85

0.75

0.25

0.20

0.15

0.75

0.65

0.60

b

0.35

0.30

0.25

D

3.1

3.0

2.9

E

3.1

3.0

2.9

e

0.5

e

1

2 e

2

2

1 scale v

0.15

w

0.05

y

2 mm

0.08

y

1

0.1

Outline version

SOT1199-1

IEC JEDEC

References

JEITA

- - -

Fig 34. Package outline SOT1199-1 (VFBGA24)

PCA6416A



Rev. 2 — 10 January 2013 y

1

C

European projection

C y

X sot1199-1_po

Issue date

11-02-16

12-03-13


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17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

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17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 35 ) than a SnPb process, thus reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 23 and 24

Table 23.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm 3 )

< 350

 350

< 2.5

 2.5

235

220

220

220

Table 24.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm 3 )

< 350 350 to 2000

< 1.6

1.6 to 2.5

> 2.5

260

260

250

260

250

245

> 2000

260

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 35 .

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Low-voltage translating 16-bit I 2 C-bus/SMBus I/O expander temperature maximum peak temperature

= MSL limit, damage level minimum peak temperature

= minimum soldering temperature peak

temperature time

001aac844

MSL: Moisture Sensitivity Level

Fig 35. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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18. Soldering: PCB footprints

Footprint information for reflow soldering of TSSOP24 package SOT355-1

Hx

Gx

P2

(0.125) (0.125)

Hy Gy

C

D2 (4x) P1 D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

By Ay solder land occupied area

DIMENSIONS in mm

P1 P2 Ay By C D1 D2 Gx Gy Hx

0.650

0.750

7.200

4.500

1.350

0.400

0.600

8.200

5.300

8.600

Hy

7.450

Fig 36. PCB footprint for SOT355-1 (TSSOP24); reflow soldering

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Footprint information for reflow soldering of HVQFN24 package SOT994-1

P

Hx

Gx

D

C

0.025

0.025

(0.105) nSPx

SPx

SPy

Hy Gy SLy By Ay nSPy

SPx tot

SLx

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy

2 2

Dimensions in mm

P Ax Ay Bx By C D SLx SLy SPx tot SPy tot

1.200

0.500

Issue date

5.000

5.000

3.200

3.200

07-09-24

09-06-15

0.900

0.240

2.100

2.100

1.200

Fig 37. PCB footprint for SOT994-1 (HWQFN24); reflow soldering

SPx SPy Gx Gy Hx Hy

0.450

0.450

4.300

4.300

5.250

5.250

sot994-1_fr

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19. Abbreviations

Table 25.

Abbreviations

Acronym

ESD

Description

ElectroStatic Discharge

FET

GPIO

I 2 C-bus

I/O

Field-Effect Transistor

General Purpose Input/Output

Inter-Integrated Circuit bus

Input/Output

LED

LSB

MSB

NACK

PCB

POR

PRR

SMBus

Light-Emitting Diode

Least Significant Bit

Most Significant Bit

Not ACKnowledge

Printed-Circuit Board

Power-On Reset

Pulse Repetition Rate

System Management Bus

20. Revision history

Table 26.

Revision history

Document ID

PCA6416A v.2

Modifications:

PCA6416A v.1

Release date Data sheet status Change notice Supersedes

20130110 Product data sheet PCA6416A v.1

•

Updated

Table 1 “Ordering information” : added “Topside marking” column

•

Updated

Table 2 “Ordering options” : added columns “Orderable part number”, “Packing method” and “Minimum order quantity”; topside marking column is moved to Table 1

•

Figure 3 “Pin configuration for HWQFN24” : corrected type number from “PCA9416AHF”

to “PCA6416AHF”

20120911 Product data sheet -

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21. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

21.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

21.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

PCA6416A


Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.


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PCA6416A


Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I

2

C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

PCA6416A



Rev. 2 — 10 January 2013


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PCA6416A


23. Contents

7.5

7.6

7.8

8

8.1

8.2

9

1

2

3

3.1

4

5

5.1

5.2

6

7

7.1

7.2

7.3

7.4

7.4.1

7.4.2

7.4.3

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 6

Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface definition . . . . . . . . . . . . . . . . . . . . . . 7

Pointer register and command byte . . . . . . . . . 7

Register descriptions . . . . . . . . . . . . . . . . . . . . 8

Input port registers (00h, 01h) . . . . . . . . . . . . . 8

Output port registers (02h, 03h) . . . . . . . . . . . . 8

Polarity inversion registers (04h, 05h) . . . . . . . 9

I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 11

Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11

Write commands. . . . . . . . . . . . . . . . . . . . . . . 11

Read commands . . . . . . . . . . . . . . . . . . . . . . 13

Application design-in information . . . . . . . . . 16

15

16

17

17.1

17.2

17.3

17.4

18

19

9.2

10

11

12

13

13.1

14

to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . 16

Power-on reset requirements . . . . . . . . . . . . . 17

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

Recommended operating conditions. . . . . . . 19

Thermal characteristics . . . . . . . . . . . . . . . . . 20

Static characteristics . . . . . . . . . . . . . . . . . . . . 20

Typical characteristics . . . . . . . . . . . . . . . . . . 22

Dynamic characteristics . . . . . . . . . . . . . . . . . 26

Parameter measurement information . . . . . . 27

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31

Soldering of SMD packages . . . . . . . . . . . . . . 34

Introduction to soldering . . . . . . . . . . . . . . . . . 34

Wave and reflow soldering . . . . . . . . . . . . . . . 34

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 35

Soldering: PCB footprints. . . . . . . . . . . . . . . . 37

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20

21

21.1

21.2

21.3

21.4

22

23

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

Legal information . . . . . . . . . . . . . . . . . . . . . . 40

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Contact information . . . . . . . . . . . . . . . . . . . . 41

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2013.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 10 January 2013

Document identifier: PCA6416A

NXP PCA6416A Low-voltage translating 16-bit I²C-bus/SMBus I/O expander Data Sheet

Assistant Bot

Low-voltage translating 16-bit I

C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers

Rev. 2. — 10 January 2013 Product data sheet

2. Features and benefits

7.4.1 Input port registers (00h, 01h)

7.4.2 Output port registers (02h, 03h)

7.4.3 Polarity inversion registers (04h, 05h)

7.4.4 Configuration registers (06h, 07h)

10. Limiting values

11. Recommended operating conditions

12. Thermal characteristics

13. Static characteristics

14. Dynamic characteristics

15. Parameter measurement information

16. Package outline

17. Soldering of SMD packages

18. Soldering: PCB footprints

19. Abbreviations

20. Revision history

21. Legal information

22. Contact information

23. Contents

Key Features

Frequently Answers and Questions

What is the voltage range supported by this expander?

What is the purpose of the interrupt output?

How can I configure the I/O pins as inputs or outputs?

What is the default configuration of the I/O pins on power-up?

How can I reset the PCA6416A to its default state?

Related manuals

NXP PCA6416A Low-voltage translating 16-bit I²C-bus/SMBus I/O expander Data Sheet

Assistant Bot

Low-voltage translating 16-bit I

C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers

Rev. 2. — 10 January 2013 Product data sheet

2. Features and benefits

7.4.1 Input port registers (00h, 01h)

7.4.2 Output port registers (02h, 03h)

7.4.3 Polarity inversion registers (04h, 05h)

7.4.4 Configuration registers (06h, 07h)

10. Limiting values

11. Recommended operating conditions

12. Thermal characteristics

13. Static characteristics

14. Dynamic characteristics

15. Parameter measurement information

16. Package outline

17. Soldering of SMD packages

18. Soldering: PCB footprints

19. Abbreviations

20. Revision history

21. Legal information

22. Contact information

23. Contents

Key Features

Frequently Answers and Questions

What is the voltage range supported by this expander?

What is the purpose of the interrupt output?

How can I configure the I/O pins as inputs or outputs?

What is the default configuration of the I/O pins on power-up?

How can I reset the PCA6416A to its default state?

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