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12v-2inv
B E C
SSB TRANSCEIVER "FORTY2" board 1
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
J1-1
29/12/2006 18:40:36 C:/Program Files/EAGLE-4.09r2/projects/perso/forty2-1.brd
10,0v
C75
100n
C73
100n
R28
+
C65
100n
C76
47µ
H5-1
D10
1N4148
220
D11
10v
R27
330
1
3
2
2
IC13
78L05
H5-2
IC14
78M05
C66
C62
100p
15t-5/10
D8
11EQS04
C67
3p3
3
6
100n
7
2,0v
H11-2
3,2v
4
Out
MC12080
Out VCO
H3-2
R29
820
5
C70
180p
C68
1n
1,42v
A
H3-1
15µ
Gnd
8
C77
100n
C72
2n2
L13
IC10
In
C
R26
330
C64
33p
3
Vdd
1
R25
100k
T37-6
H11-1
C74
C71
470p
5,0v
+
R52
1k
C100
+
Vcc
TL071
Gnd
4
+
IC11
Out
D12
1N4148
C93
2
R47
56k
R45
56k
3
14
15
R48
56k
R46
56k
11
4
R
R44
560
MC145170-2
OscIn
2
C98 15n
R49
47k
Vdd Data
IC9
V
LD
16
Fin
OscOut
R43 1M
1
C80
56p
CLK
Gnd ENB
12
R40
10k
R35
470
1
7
2
6
3
4
2k2
Q8
2SA933
5
R38 10k
R36 1k
6
D13
Led
C96
56p
12MHz
C95
47p
7
CA5
10p
R39 10k
P8
10k
H1-1
4MHz
5
R41
C81
56p
X11
C82
100n
X12
C99
220n
C78
47µ
R33
10k
R42
10k
10n
47µ
C97 15n
47k
R34
10k
8
R37 1k
9
C83
RA2
RA1
RA3
RA0
RA4
Osc1
CLR
Osc2
16F84
220n 7
6
C94
47µ
R50
C101
R51
1k
5,0v
Vss
RB0
RB1
IC8
C102
1µ
2
+
C103
1µ
D9
11EQS04
1
100p
C63
33p
L12
CA4
5p
R53
12k
C69
100n
Q7
2SK937
RB2
RB3
Vdd
RB7
RB6
RB5
RB4
H1-2
Contrast
18
H1-3
17
H1-4
16
15
14
R31 10k
13
C79
100n
12
11
R30
15
R32 10k
H1-5
10
H1-6
H1-7
100n
C84
H1-8
H1-9
2SA933
2SK937
DTC114
C85
100n
B C E
D G S
16
15
8
3 2 1
H2-5
H2-4
2
STR
Data
Gnd Q1
3
Q2
Q3
Q4
5
6
7
Q10
Q11
Q12
3
CLK
4094
IC12
OE
4
Q5
14
Q13
Q6
13
Q14
Q7
12
Q8
11
Q15
H6-1
1
C86
SSB TRANSCEIVER "FORTY2" board 2 (a)
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
H7-1
1
Vdd
Q9
Q9...Q15=DTC114
H1-10
H2-3
H2-2
H2-1
100n
47p
2
C87
82p
C88
C89
C90
C91
C92
120p
+ 15p
150p
220p
390p
680p
C
Internal loudspeaker
Volume
3
8
4
C111
5
680n
A'
C105
100n
IC15
78L06
R54
1
C106
10k
680n
5,33v
3
R57
100
C107
H10-2
H10-3
R58
IC17
6
2
220µ
C116
LM380
2
3
10 4
11 5
12 7
C109
D15
H8-1
1n
1N60
100n
C'
+
3,0v
C108
P9
H9-1
C112
1µ
470k
C115
4µ7
1
H13-1
H13-2
H13-3
100n
330n
D14
1N60
SSB TRANSCEIVER "FORTY2" board 2 (b)
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
C117
8
C110
1
100n
R56
10k
14
6
10k
R55
10k
10n
H12-1
H10-1
MAX293
7
2
100n
IC16
100n
H12-2
+
C104
H4-1
C114
+
H4-2
C113
R59
10
29/12/2006 18:39:40 C:/Program Files/EAGLE-4.09r2/projects/perso/forty2-2.brd
K2-4
C124
STEP
Pb1
ATTN
100n
SETUP
C123
RIT
Pb2
100n
FILTER
K2-5
K2-1
Encoder
K2-2
K2-3
K1-1
K1-3
2
3
4
5
K1-4
6
7
8
9
10
K1-5
K1-6
K1-7
K1-8
K1-9
K1-10
11
12
13
14
15
16
3
Gnd
Ow
Vdd
VO
RS
R/W
EN
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
L-
S1
7.050.0 RIT ATT
K1-2
1
L+
2w
S2
S3
S4
S5
S6
S7
S8
S9
S9+
18
17
16
15
14
13
12
11
10
8
9
1
2
3
4
LM3914
5
6
7
S3
C120
100n
R60
3k3
LCD 1x16
K4-1
SSB TRANSCEIVER "FORTY2" board 3
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
2
IC19
Bargraph 10 led
IC18
IC20
78M05
5w
+
C119
100n
+
C118
100µ
C121
47µ
1
K3-1
C122
100n
K3-2
29/12/2006 18:36:14 C:/Program Files/EAGLE-4.09r2/projects/perso/forty2-3.brd
Audio 4 to 32 ohms
1
2
3
Board 2 (Synthe + Audio)
H13
H1
K1
H2
K2
H11
K3
H9
K4
LCD Display
S'Meter Bargraph
Board 3 (Front)
Encoder
Step/Attn
Rit/Filter/Setup
Internal LS
1
H10
H12
Volume
2
3
H3
H4
H5
H6
H7
J3
J4
J5
J6
J7
Pot1
10kB
H8
J8
Alim.
On/Off
1
2
J2
J10
Board 1 (Tx + Rx)
Antenna
1
2
J1
J9
Micro/PTT
3
2
1
C125
1n
SSB TRANSCEIVER "FORTY2" connect
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
Préamplificateur BF
CAG
IC3
Haut parleur
Amplificateur BF
Filtre actif BF
IC17
IC16
Mélangeur à gain
Amplificateur FI
IC2
Filtre à quartz 4,9152 MHz
Mélangeur à gain
Q2
Filtre passe-bande 7 MHz
IC1
Q1
Atténuateur
BFO
4,9152 MHz
Antenne
S'mètre à bargraphe
IC18
IC19
IC8
IC12
µcontrôleur
IC9
IC10
IC11
Synthétiseur
Rx
Display
Tx
Indicateur de puissance
Commande filtre BF
LCD 1x16
Commandes du µcontrôleur
4,9152 MHz
OL
Q4 Q5 Q6
IC5
Micro
Préampli - compresseur
IC6
Modulateur équilibré
5W
IC7
Filtre à quartz 4,915 MHz
Mélangeur à gain
Amplificateur HF
Filtre passe-bas 7 MHz
SSB TRANSCEIVER "FORTY2"
(C) Luc Pistorius F6BQU
(C) Jean-Marc Eveille F5RDH
LM380
2.5W Audio Power Amplifier
General Description
The LM380 is a power audio amplifier for consumer applications. In order to hold system cost to a minimum, gain is
internally fixed at 34 dB. A unique input stage allows ground
referenced input signals. The output automatically selfcenters to one-half the supply voltage.
The output is short circuit proof with internal thermal limiting.
The package outline is standard dual-in-line. The LM380N
uses a copper lead frame. The center three pins on either
side comprise a heat sink. This makes the device easy to
use in standard PC layouts.
Uses include simple phonograph amplifiers, intercoms, line
drivers, teaching machine outputs, alarms, ultrasonic drivers, TV sound systems, AM-FM radio, small servo drivers,
power converters, etc.
Connection Diagrams
A selected part for more power on higher supply voltages is
available as the LM384. For more information see AN-69.
Features
Wide supply voltage range: 10V-22V
Low quiescent power drain: 0.13W (VS= 18V)
Voltage gain fixed at 50
High peak current capability: 1.3A
Input referenced to GND
High input impedance: 150kΩ
Low distortion
Quiescent output voltage is at one-half of the supply
voltage
n Standard dual-in-line package
n
n
n
n
n
n
n
n
(Dual-In-Line Packages, Top View)
00697702
00697701
Order Number LM380N
See NS Package Number N14A
© 2004 National Semiconductor Corporation
DS006977
Order Number LM380N-8
See NS Package Number N08E
www.national.com
LM380 2.5W Audio Power Amplifier
August 2000
LM380
Block and Schematic Diagrams
LM380N
LM380N-8
00697704
00697703
00697705
www.national.com
2
Operating Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
+150˚C
Lead Temperature (Soldering, 10 sec.)
+260˚C
ESD rating to be determined
Supply Voltage
22V
Thermal Resistance
Peak Current
1.3A
θJC (14-Pin DIP)
Package Dissipation 14-Pin DIP (Note
7)
0˚C to +70˚C
30˚C/W
θJC (8-Pin DIP)
37˚C/W
8.3W
θJA (14-Pin DIP)
79˚C/W
Package Dissipation 8-Pin DIP (Note 7)
1.67W
107˚C/W
± 0.5V
θJA (8-Pin DIP)
Input Voltage
Storage Temperature
−65˚C to
+150˚C
Electrical Characteristics (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
50
60
V/V
POUT(RMS)
Output Power
AV
Gain
VOUT
Output Voltage Swing
ZIN
Input Resistance
THD
Total Harmonic Distortion
(Notes 5, 6)
0.2
%
PSRR
Power Supply Rejection Ratio
(Note 3)
38
dB
VS
Supply Voltage
BW
Bandwidth
IQ
Quiescent Supply Current
VOUTQ
Quiescent Output Voltage
IBIAS
Bias Current
ISC
Short Circuit Current
RL = 8Ω, THD = 3% (Notes 4, 5)
2.5
40
RL = 8Ω
W
14
Vp-p
150k
Ω
10
POUT = 2W, RL = 8Ω
V
7
25
mA
9.0
10
100k
8
Inputs Floating
22
Hz
V
100
nA
1.3
A
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: VS = 18V and TA = 25˚C unless otherwise specified.
Note 3: Rejection ratio referred to the output with CBYPASS = 5 µF.
Note 4: With device Pins 3, 4, 5, 10, 11, 12 soldered into a 1/16" epoxy glass board with 2 ounce copper foil with a minimum surface of 6 square inches.
Note 5: CBYPASS = 0.47 µfd on Pin 1.
Note 6: The maximum junction temperature of the LM380 is 150˚C.
Note 7: The package is to be derated at 15˚C/W junction to heat sink pins for 14-pin pkg; 75˚C/W for 8-pin.
3
www.national.com
LM380
Absolute Maximum Ratings (Note 1)
LM380
Heat Sink Dimensions
00697706
Staver Heat Sink #V-7
Staver Company
41 Saxon Ave.
P.O. Drawer H
Bayshore, NY 11706
Tel: (516) 666-8000
Copper Wings
2 Required
Soldered to
Pins 3, 4, 5,
10, 11, 12
Thickness 0.04
Inches
Typical Performance Characteristics
Maximum Device Dissipation vs
Ambient Temperature
Device Dissipation vs Output
Power — 4Ω Load
00697713
00697712
www.national.com
4
LM380
Typical Performance Characteristics
(Continued)
Device Dissipation vs Output
Power — 8Ω Load
Device Dissipation vs Output
Power — 16Ω Load
00697715
00697714
Power Supply Current vs
Supply Voltage
Total Harmonic Distortion
vs Frequency
00697716
00697717
Output Voltage Gain and
Phase vs Frequency
Total Harmonic Distortion
vs Output Power
00697718
00697719
5
www.national.com
LM380
Typical Performance Characteristics
(Continued)
Device Dissipation vs
Output Power
Supply Decoupling vs
Frequency
00697720
00697721
Typical Applications
Phono Amplifier
00697708
Bridge Amplifier
00697709
www.national.com
6
LM380
Typical Applications
(Continued)
Intercom
00697710
Phase Shift Oscillator
00697711
7
www.national.com
LM380
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number LM380N-8
NS Package Number N08E
Molded Dual-In-Line Package (N)
Order Number LM380N
NS Package Number N14A
www.national.com
8
LM380 2.5W Audio Power Amplifier
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned
Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
Email: [email protected]
Tel: 1-800-272-9959
www.national.com
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Support Center
Email: [email protected]
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: [email protected]
Tel: 81-3-5639-7560
LM386
Low Voltage Audio Power Amplifier
General Description
Features
The LM386 is a power amplifier designed for use in low voltage consumer applications. The gain is internally set to 20 to
keep external part count low, but the addition of an external
resistor and capacitor between pins 1 and 8 will increase the
gain to any value from 20 to 200.
The inputs are ground referenced while the output automatically biases to one-half the supply voltage. The quiescent
power drain is only 24 milliwatts when operating from a 6 volt
supply, making the LM386 ideal for battery operation.
n
n
n
n
n
n
n
n
Battery operation
Minimum external parts
Wide supply voltage range: 4V–12V or 5V–18V
Low quiescent current drain: 4mA
Voltage gains from 20 to 200
Ground referenced input
Self-centering output quiescent voltage
Low distortion: 0.2% (AV = 20, VS = 6V, RL = 8Ω, PO =
125mW, f = 1kHz)
n Available in 8 pin MSOP package
Applications
n
n
n
n
n
n
n
n
AM-FM radio amplifiers
Portable tape player amplifiers
Intercoms
TV sound systems
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters
Equivalent Schematic and Connection Diagrams
Small Outline,
Molded Mini Small Outline,
and Dual-In-Line Packages
DS006976-2
DS006976-1
© 2000 National Semiconductor Corporation
DS006976
Top View
Order Number LM386M-1,
LM386MM-1, LM386N-1,
LM386N-3 or LM386N-4
See NS Package Number
M08A, MUA08A or N08E
www.national.com
LM386 Low Voltage Audio Power Amplifier
August 2000
LM386
Absolute Maximum Ratings (Note 2)
Dual-In-Line Package
Soldering (10 sec)
+260˚C
Small Outline Package
(SOIC and MSOP)
Vapor Phase (60 sec)
+215˚C
Infrared (15 sec)
+220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
Thermal Resistance
37˚C/W
θJC (DIP)
107˚C/W
θJA (DIP)
35˚C/W
θJC (SO Package)
172˚C/W
θJA (SO Package)
210˚C/W
θJA (MSOP)
56˚C/W
θJC (MSOP)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
(LM386N-1, -3, LM386M-1)
Supply Voltage (LM386N-4)
Package Dissipation (Note 3)
(LM386N)
(LM386M)
(LM386MM-1)
Input Voltage
Storage Temperature
Operating Temperature
Junction Temperature
Soldering Information
15V
22V
1.25W
0.73W
0.595W
± 0.4V
−65˚C to +150˚C
0˚C to +70˚C
+150˚C
Electrical Characteristics (Notes 1, 2)
TA = 25˚C
Parameter
Conditions
Min
Typ
Max
Units
12
V
Operating Supply Voltage (VS)
LM386N-1, -3, LM386M-1, LM386MM-1
4
LM386N-4
Quiescent Current (IQ)
5
VS = 6V, VIN = 0
4
18
V
8
mA
Output Power (POUT)
LM386N-1, LM386M-1, LM386MM-1
VS = 6V, RL = 8Ω, THD = 10%
250
325
LM386N-3
VS = 9V, RL = 8Ω, THD = 10%
500
700
mW
LM386N-4
VS = 16V, RL = 32Ω, THD = 10%
700
1000
mW
Voltage Gain (AV)
VS = 6V, f = 1 kHz
26
dB
mW
10 µF from Pin 1 to 8
46
dB
Bandwidth (BW)
VS = 6V, Pins 1 and 8 Open
300
kHz
Total Harmonic Distortion (THD)
VS = 6V, RL = 8Ω, POUT = 125 mW
0.2
%
50
dB
50
kΩ
250
nA
f = 1 kHz, Pins 1 and 8 Open
Power Supply Rejection Ratio (PSRR)
VS = 6V, f = 1 kHz, CBYPASS = 10 µF
Pins 1 and 8 Open, Referred to Output
Input Resistance (RIN)
Input Bias Current (IBIAS)
VS = 6V, Pins 2 and 3 Open
Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is
given, however, the typical value is a good indication of device performance.
Note 3: For operation in ambient temperatures above 25˚C, the device must be derated based on a 150˚C maximum junction temperature and 1) a thermal resistance of 107˚C/W junction to ambient for the dual-in-line package and 2) a thermal resistance of 170˚C/W for the small outline package.
www.national.com
2
LM386
Application Hints
GAIN CONTROL
INPUT BIASING
To make the LM386 a more versatile amplifier, two pins (1
and 8) are provided for gain control. With pins 1 and 8 open
the 1.35 kΩ resistor sets the gain at 20 (26 dB). If a capacitor
is put from pin 1 to 8, bypassing the 1.35 kΩ resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 1 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series
RC from pin 1 to 5 (paralleling the internal 15 kΩ resistor).
For 6 dB effective bass boost: R . 15 kΩ, the lowest value
for good stable operation is R = 10 kΩ if pin 8 is open. If pins
1 and 8 are bypassed then R as low as 2 kΩ can be used.
This restriction is because the amplifier is only compensated
for closed-loop gains greater than 9.
The schematic shows that both inputs are biased to ground
with a 50 kΩ resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the LM386
is higher than 250 kΩ it will contribute very little additional
offset (about 2.5 mV at the input, 50 mV at the output). If the
dc source resistance is less than 10 kΩ, then shorting the
unused input to ground will keep the offset low (about 2.5 mV
at the input, 50 mV at the output). For dc source resistances
between these values we can eliminate excess offset by putting a resistor from the unused input to ground, equal in
value to the dc source resistance. Of course all offset problems are eliminated if the input is capacitively coupled.
When using the LM386 with higher gains (bypassing the
1.35 kΩ resistor between pins 1 and 8) it is necessary to bypass the unused input, preventing degradation of gain and
possible instabilities. This is done with a 0.1 µF capacitor or
a short to ground depending on the dc source resistance on
the driven input.
3
www.national.com
LM386
Typical Performance Characteristics
Quiescent Supply Current
vs Supply Voltage
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency
Peak-to-Peak Output Voltage
Swing vs Supply Voltage
DS006976-5
DS006976-13
DS006976-12
Voltage Gain vs Frequency
Distortion vs Frequency
DS006976-15
DS006976-14
Device Dissipation vs Output
Power — 4Ω Load
Device Dissipation vs Output
Power — 8Ω Load
DS006976-17
www.national.com
Distortion vs Output Power
DS006976-18
4
DS006976-16
Device Dissipation vs Output
Power — 16Ω Load
DS006976-19
LM386
Typical Applications
Amplifier with Gain = 20
Minimum Parts
Amplifier with Gain = 200
DS006976-4
DS006976-3
Amplifier with Gain = 50
Low Distortion Power Wienbridge Oscillator
DS006976-6
DS006976-7
Amplifier with Bass Boost
Square Wave Oscillator
DS006976-8
DS006976-9
5
www.national.com
LM386
Typical Applications
(Continued)
Frequency Response with Bass Boost
DS006976-10
AM Radio Power Amplifier
DS006976-11
Note 4: Twist Supply lead and supply ground very tightly.
Note 5: Twist speaker lead and ground very tightly.
Note 6: Ferrite bead in Ferroxcube K5-001-001/3B with 3 turns of wire.
Note 7: R1C1 band limits input signals.
Note 8: All components must be spaced very closely to IC.
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6
LM386
Physical Dimensions
inches (millimeters) unless otherwise noted
SO Package (M)
Order Number LM386M-1
NS Package Number M08A
7
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LM386
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead (0.118” Wide) Molded Mini Small Outline Package
Order Number LM386MM-1
NS Package Number MUA08A
www.national.com
8
LM386 Low Voltage Audio Power Amplifier
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Dual-In-Line Package (N)
Order Number LM386N-1, LM386N-3 or LM386N-4
NS Package Number N08E
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Copyright © 2011, Texas Instruments Incorporated
LM3914
Dot/Bar Display Driver
General Description
The LM3914 is a monolithic integrated circuit that senses
analog voltage levels and drives 10 LEDs, providing a linear
analog display. A single pin changes the display from a moving dot to a bar graph. Current drive to the LEDs is regulated
and programmable, eliminating the need for resistors. This
feature is one that allows operation of the whole system from
less than 3V.
The circuit contains its own adjustable reference and accurate 10-step voltage divider. The low-bias-current input
buffer accepts signals down to ground, or V−, yet needs no
protection against inputs of 35V above or below ground. The
buffer drives 10 individual comparators referenced to the
precision divider. Indication non-linearity can thus be held
typically to 1⁄2%, even over a wide temperature range.
Versatility was designed into the LM3914 so that controller,
visual alarm, and expanded scale functions are easily added
on to the display system. The circuit can drive LEDs of many
colors, or low-current incandescent lamps. Many LM3914s
can be “chained” to form displays of 20 to over 100 segments. Both ends of the voltage divider are externally available so that 2 drivers can be made into a zero-center meter.
The LM3914 is very easy to apply as an analog meter circuit.
A 1.2V full-scale meter requires only 1 resistor and a single
3V to 15V supply in addition to the 10 display LEDs. If the 1
resistor is a pot, it becomes the LED brightness control. The
simplified block diagram illustrates this extremely simple external circuitry.
When in the dot mode, there is a small amount of overlap or
“fade” (about 1 mV) between segments. This assures that at
no time will all LEDs be “OFF”, and thus any ambiguous display is avoided. Various novel displays are possible.
© 2000 National Semiconductor Corporation
DS007970
Much of the display flexibility derives from the fact that all
outputs are individual, DC regulated currents. Various effects
can be achieved by modulating these currents. The individual outputs can drive a transistor as well as a LED at the
same time, so controller functions including “staging” control
can be performed. The LM3914 can also act as a programmer, or sequencer.
The LM3914 is rated for operation from 0˚C to +70˚C. The
LM3914N-1 is available in an 18-lead molded (N) package.
The following typical application illustrates adjusting of the
reference to a desired value, and proper grounding for accurate operation, and avoiding oscillations.
Features
Drives LEDs, LCDs or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 100 steps
Internal voltage reference from 1.2V to 12V
Operates with single supply of less than 3V
Inputs operate down to ground
Output current programmable from 2 mA to 30 mA
No multiplex switching or interaction between outputs
Input withstands ± 35V without damage or false outputs
LED driver outputs are current regulated,
open-collectors
n Outputs can interface with TTL or CMOS logic
n The internal 10-step divider is floating and can be
referenced to a wide range of voltages
n
n
n
n
n
n
n
n
n
n
www.national.com
LM3914 Dot/Bar Display Driver
January 2000
LM3914
Typical Applications
0V to 5V Bar Graph Meter
DS007970-1
Note: Grounding method is typical of all uses. The 2.2 µF tantalum or 10 µF aluminum electrolytic capacitor is needed if leads to the LED supply are 6" or
longer.
www.national.com
2
Reference Load Current
10 mA
Storage Temperature Range
−55˚C to +150˚C
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260˚C
Plastic Chip Carrier Package
Vapor Phase (60 seconds)
215˚C
Infrared (15 seconds)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation (Note 6)
Molded DIP (N)
Supply Voltage
Voltage on Output Drivers
Input Signal Overvoltage (Note 4)
Divider Voltage
1365 mW
25V
25V
± 35V
−100 mV to V+
Electrical Characteristics (Notes 2, 4)
Parameter
Conditions (Note 2)
Min
Typ
Max
Units
3
10
mV
3
15
mV
COMPARATOR
Gain (∆ILED/∆VIN)
0V ≤ VRLO = VRHI ≤ 12V,
ILED = 1 mA
0V ≤ VRLO = VRHI ≤ 12V,
ILED = 1 mA
IL(REF) = 2 mA, ILED = 10 mA
Input Bias Current (at Pin 5)
0V ≤ VIN ≤ V+ − 1.5V
Input Signal Overvoltage
No Change in Display
Offset Voltage, Buffer and First
Comparator
Offset Voltage, Buffer and Any Other
Comparator
3
8
25
−35
mA/mV
100
nA
35
V
VOLTAGE-DIVIDER
Divider Resistance
Total, Pin 6 to 4
Accuracy
(Note 3)
8
12
17
kΩ
0.5
2
%
1.28
1.34
V
VOLTAGE REFERENCE
Output Voltage
0.1 mA ≤ IL(REF) ≤ 4 mA,
V+ = VLED = 5V
Line Regulation
3V ≤ V+ ≤ 18V
0.01
0.03
%/V
Load Regulation
0.1 mA ≤ IL(REF) ≤ 4 mA,
V+ = VLED = 5V
0.4
2
%
Output Voltage Change with
Temperature
0˚C ≤ TA ≤ +70˚C, IL(REF) = 1 mA,
V+ = 5V
1.2
%
1
Adjust Pin Current
75
120
µA
mA
OUTPUT DRIVERS
LED Current
LED Current Difference (Between
Largest and Smallest LED Currents)
LED Current Regulation
Dropout Voltage
Saturation Voltage
V+ = VLED = 5V, IL(REF) = 1 mA
ILED = 2 mA
VLED = 5V
7
ILED = 20 mA
ILED = 2 mA
ILED = 20 mA
2V ≤ VLED ≤ 17V
ILED(ON) = 20 mA, VLED = 5V,
∆ILED = 2 mA
ILED = 2.0 mA, IL(REF) = 0.4 mA
Output Leakage, Each Collector
(Bar Mode) (Note 5)
Output Leakage
(Dot Mode)
(Note 5)
13
0.4
1.2
3
0.1
0.25
1
3
0.15
Pins 10–18
Pin 1
10
0.12
60
mA
mA
1.5
V
0.4
V
0.1
10
µA
0.1
10
µA
150
450
µA
2.4
4.2
mA
6.1
9.2
mA
SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)
V+ = 5V,
IL(REF) = 0.2 mA
V+ = 20V,
IL(REF) = 1.0 mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is
given, however, the typical value is a good indication of device performance.
3
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LM3914
Absolute Maximum Ratings (Note 1)
LM3914
Electrical Characteristics (Notes 2, 4)
(Continued)
Note 2: Unless otherwise stated, all specifications apply with the following conditions:
3 VDC ≤ V+ ≤ 20 VDC
VREF, VRHI, VRLO ≤ (V+ − 1.5V)
3 VDC ≤ VLED ≤ V+
0V ≤ VIN ≤ V+ − 1.5V
−0.015V ≤ VRLO ≤ 12 VDC
TA = +25˚C, IL(REF) = 0.2 mA, VLED = 3.0V, pin 9 connected to pin 3 (Bar Mode).
−0.015V ≤ VRHI ≤ 12 VDC
For higher power dissipations, pulse testing is used.
Note 3: Accuracy is measured referred to +10.000 VDC at pin 6, with 0.000 VDC at pin 4. At lower full-scale voltages, buffer and comparator offset voltage may add
significant error.
Note 4: Pin 5 input current must be limited to ± 3 mA. The addition of a 39k resistor in series with pin 5 allows ± 100V signals without damage.
Note 5: Bar mode results when pin 9 is within 20 mV of V+. Dot mode results when pin 9 is pulled at least 200 mV below V+ or left open circuit. LED No. 10 (pin
10 output current) is disabled if pin 9 is pulled 0.9V or more below VLED.
Note 6: The maximum junction temperature of the LM3914 is 100˚C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance is 55˚C/W for the molded DIP (N package).
LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLED) as
measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Line Regulation: The average change in reference output
voltage over the specified range of supply voltage (V+).
Load Regulation: The change in reference output voltage
(VREF) over the specified range of load current (IL(REF)).
Offset Voltage: The differential input voltage which must be
applied to each comparator to bias the output in the linear region. Most significant error when the voltage across the internal voltage divider is small. Specified and tested with pin
6 voltage (VRHI) equal to pin 4 voltage (VRLO).
Definition of Terms
Accuracy: The difference between the observed threshold
voltage and the ideal threshold voltage for each comparator.
Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over
comparator offset voltage.
Adjust Pin Current: Current flowing out of the reference adjust pin when the reference amplifier is in the linear region.
Comparator Gain: The ratio of the change in output current
(ILED) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.
Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.
Typical Performance Characteristics
Supply Current vs
Temperature
Operating Input Bias
Current vs Temperature
DS007970-2
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Reference Voltage vs
Temperature
DS007970-20
4
DS007970-21
Reference Adjust Pin
Current vs Temperature
LM3914
Typical Performance Characteristics
(Continued)
LED Current-Regulation
Dropout
DS007970-22
LED Driver Saturation
Voltage
DS007970-23
DS007970-24
Input Current Beyond
Signal Range (Pin 5)
LED Current vs
Reference Loading
LED Driver Current
Regulation
DS007970-25
DS007970-26
Total Divider Resistance
vs Temperature
Common-Mode Limits
DS007970-27
Output Characteristics
DS007970-29
DS007970-30
DS007970-28
5
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LM3914
Block Diagram
(Showing Simplest Application)
DS007970-3
www.national.com
6
MODE PIN USE
The simplifed LM3914 block diagram is to give the general
idea of the circuit’s operation. A high input impedance buffer
operates with signals from ground to 12V, and is protected
against reverse and overvoltage signals. The signal is then
applied to a series of 10 comparators; each of which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
125 mV that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are 1.5V below V+ and no less than V−. If an expanded scale
meter display is desired, the total divider voltage can be as
little as 200 mV. Expanded-scale meter displays are more
accurate and the segments light uniformly only if bar mode is
used. At 50 mV or more per step, dot mode is usable.
Pin 9, the Mode Select input controls chaining of multiple
LM3914s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).
Dot Display, Single LM3914 Driver: Leave the Mode Select
pin open circuit.
Dot Display, 20 or More LEDs: Connect pin 9 of the first
driver in the series (i.e., the one with the lowest input voltage
comparison points) to pin 1 of the next higher LM3914 driver.
Continue connecting pin 9 of lower input drivers to pin 1 of
higher input drivers for 30, 40, or more LED displays. The
last LM3914 driver in the chain will have pin 9 wired to pin 11.
All previous drivers should have a 20k resistor in parallel with
LED No. 9 (pin 11 to VLED).
INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current I1 then flows through the output set resistor
R2 giving an output voltage of:
Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.
Block Diagram of Mode Pin Description
DS007970-4
Since the 120 µA current (max) from the adjust terminal represents an error term, the reference was designed to minimize changes of this current with V+ and load changes.
DS007970-5
*High for bar
DOT OR BAR MODE SELECTION
The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ − 100 mV). The chip is in bar mode when
pin 9 is above this level; otherwise it’s in dot mode. The comparator is designed so that pin 9 can be left open circuit for
dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20 mV
below V+ for bar mode and more than 200 mV below V+ (or
open circuit) for dot mode. In most applications, pin 9 is either open (dot mode) or tied to V+ (bar mode). In bar mode,
pin 9 should be connected directly to pin 3. Large currents
drawn from the power supply (LED current, for example)
should not share this path so that large IR drops are avoided.
CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the external current and voltage-setting divider should be included
in calculating LED drive current. The ability to modulate LED
brightness with time, or in proportion to input voltage and
other signals can lead to a number of novel displays or ways
of indicating input overvoltages, alarms, etc.
DOT MODE CARRY
In order for the display to make sense when multiple
LM3914s are cascaded in dot mode, special circuitry has
been included to shut off LED No. 10 of the first device when
7
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LM3914
Functional Description
LM3914
Mode Pin Functional Description
LEDs OFF) is 1.6 mA (2.5 mA max). However, any reference
loading adds 4 times that current drain to the V+ (pin 3) supply input. For example, an LM3914 with a 1 mA reference pin
load (1.3k), would supply almost 10 mA to every LED while
drawing only 10 mA from its V+ pin supply. At full-scale, the
IC is typically drawing less than 10% of the current supplied
to the display.
(Continued)
LED No. 1 of the second device comes on. The connection
for cascading in dot mode has already been described and is
depicted below.
As long as the input signal voltage is below the threshold of
the second LM3914, LED No. 11 is off. Pin 9 of LM3914
No. 1 thus sees effectively an open circuit so the chip is in
dot mode. As soon as the input voltage reaches the threshold of LED No. 11, pin 9 of LM3914 No. 1 is pulled an LED
drop (1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2, extinguishing LED No. 10.
VLED is sensed via the 20k resistor connected to pin 11. The
very small current (less than 100 µA) that is diverted from
LED No. 9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 µA
flowing through LED No. 11 even if the input voltage rises
high enough to extinguish the LED. This ensures that pin 9 of
LM3914 No. 1 is held low enough to force LED No. 10 off
when any higher LED is illuminated. While 100 µA does not
normally produce significant LED illumination, it may be noticeable when using high-efficiency LEDs in a dark environment. If this is bothersome, the simple cure is to shunt LED
No. 11 with a 10k resistor. The 1V IR drop is more than the
900 mV worst case required to hold off LED No. 10 yet small
enough that LED No. 11 does not conduct significantly.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the next.
Under rapidly changing signal conditions, this cuts down
high frequency noise and often an annoying flicker. An “overlap” is built in so that at no time between segments are all
LEDs completely OFF in the dot mode. Generally 1 LED
fades in while the other fades out over a mV or more of
range (Note 3). The change may be much more rapid between LED No. 10 of one device and LED No. 1 of a second
device “chained” to the first.
The LM3914 features individually current regulated LED
driver transistors. Further internal circuitry detects when any
driver transistor goes into saturation, and prevents other circuitry from drawing excess current. This results in the ability
of the LM3914 to drive and regulate LEDs powered from a
pulsating DC power source, i.e., largely unfiltered. (Due to
possible oscillations at low voltages a nominal bypass capacitor consisting of a 2.2 µF solid tantalum connected from
the pulsating LED supply to pin 2 of the LM3914 is recommended.) This ability to operate with low or fluctuating voltages also allows the display driver to interface with logic circuitry, opto-coupled solid-state relays, and low-current
incandescent lamps.
OTHER DEVICE CHARACTERISTICS
The LM3914 is relatively low-powered itself, and since any
number of LEDs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
Cascading LM3914s in Dot Mode
DS007970-6
www.national.com
8
LM3914
Typical Applications
Zero-Center Meter, 20-Segment
DS007970-7
9
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LM3914
Typical Applications
(Continued)
Expanded Scale Meter, Dot or Bar
DS007970-8
*This application illustrates that the LED supply needs practically no filtering
Calibration: With a precision meter between pins 4 and 6 adjust R1 for voltage VD of 1.20V. Apply 4.94V to pin 5, and adjust R4 until LED No. 5 just lights.
The adjustments are non-interacting.
Application Example:
Grading 5V Regulators
Highest No.
LED on
Color
VOUT(MIN)
10
Red
5.54
9
Red
5.42
8
Yellow
5.30
7
Green
5.18
6
Green
5.06
5V
5
Green
4.94
4
Green
4.82
3
Yellow
4.7
2
Red
4.58
1
Red
4.46
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10
LM3914
Typical Applications
(Continued)
“Exclamation Point” Display
DS007970-9
LEDs light up as illustrated with the upper lit LED indicating the actual input voltage. The display appears to increase resolution and provides an analog
indication of overrange.
Indicator and Alarm, Full-Scale Changes Display from Dot to Bar
DS007970-10
*The input to the Dot-Bar Switch may be taken from cathodes of other LEDs. Display will change to bar as soon as the LED so selected begins to light.
11
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LM3914
Typical Applications
(Continued)
Bar Display with Alarm Flasher
DS007970-11
Full-scale causes the full bar display to flash. If the junction of R1 and C1 is connected to a different LED cathode, the display will flash when that LED lights,
and at any higher input signal.
Adding Hysteresis (Single Supply, Bar Mode Only)
DS007970-12
Hysteresis is 0.5 mV to 1 mV
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12
LM3914
Typical Applications
(Continued)
Operating with a High Voltage Supply (Dot Mode Only)
DS007970-13
The LED currents are approximately 10 mA, and the LM3914 outputs operate in saturation for minimum dissipation.
*This point is partially regulated and decreases in voltage with temperature. Voltage requirements of the LM3914 also decrease with temperature.
13
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LM3914
Typical Applications
(Continued)
20-Segment Meter with Mode Switch
DS007970-14
*The exact wiring arrangement of this schematic shows the need for Mode Select (pin 9) to sense the V+ voltage exactly as it appears on pin 3.
Programs LEDs to 10 mA
tively high value resistors. These high-impedance ends
should be bypassed to pin 2 with at least a 0.001 µF capacitor, or up to 0.1 µF in noisy environments.
Power dissipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEDs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.5Ω resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 µF solid tantalum capacitor to
pin 2 of the LM3914.
Turning OFF of most of the internal current sources is accomplished by pulling positive on the reference with a current source or resistance supplying 100 µA or so. Alternately,
the input signal can be gated OFF with a transistor switch.
Other special features and applications characteristics will
be illustrated in the following applications schematics. Notes
have been added in many cases, attempting to cover any
special procedures or unusual characteristics of these applications. A special section called “Application Tips for the
LM3914 Adjustable Reference” has been included with
these schematics.
Application Hints
Three of the most commonly needed precautions for using
the LM3914 are shown in the first typical application drawing
showing a 0V–5V bar graph meter. The most difficult problem occurs when large LED currents are being drawn, especially in bar graph mode. These currents flowing out of the
ground pin cause voltage drops in external wiring, and thus
errors and oscillations. Bringing the return wires from signal
sources, reference ground and bottom of the resistor string
(as illustrated) to a single point very near pin 2 is the best solution.
Long wires from VLED to LED anode common can cause oscillations. Depending on the severity of the problem 0.05 µF
to 2.2 µF decoupling capacitors from LED anode common to
pin 2 will damp the circuit. If LED anode line wiring is inaccessible, often similar decoupling from pin 1 to pin 2 will be
sufficient.
If LED turn ON seems slow (bar mode) or several LEDs light
(dot mode), oscillation or excessive noise is usually the problem. In cases where proper wiring and bypassing fail to stop
oscillations, V+ voltage at pin 3 is usually below suggested
limits. Expanded scale meter applications may have one or
both ends of the internal voltage divider terminated at rela-
www.national.com
14
(Continued)
Greatly Expanded Scale (Bar Mode Only)
APPLICATION TIPS FOR THE LM3914 ADJUSTABLE
REFERENCE
GREATLY EXPANDED SCALE (BAR MODE ONLY)
Placing the LM3914 internal resistor divider in parallel with a
section ( ≅ 230Ω) of a stable, low resistance divider greatly
reduces voltage changes due to IC resistor value changes
with temperature. Voltage V1 should be trimmed to 1.1V first
by use of R2. Then the voltage V2 across the IC divider string
can be adjusted to 200 mV, using R5 without affecting V1.
LED current will be approximately 10 mA.
NON-INTERACTING ADJUSTMENTS FOR EXPANDED
SCALE METER (4.5V to 5V, Bar or Dot Mode)
This arrangement allows independent adjustment of LED
brightness regardless of meter span and zero adjustments.
First, V1 is adjusted to 5V, using R2. Then the span (voltage
across R4) can be adjusted to exactly 0.5V using R6 without
affecting the previous adjustment.
R9 programs LED currents within a range of 2.2 mA to 20 mA
after the above settings are made.
DS007970-15
ADJUSTING LINEARITY OF SEVERAL STACKED
DIVIDERS
Three internal voltage dividers are shown connected in series to provide a 30-step display. If the resulting analog meter
is to be accurate and linear the voltage on each divider must
be adjusted, preferably without affecting any other adjustments. To do this, adjust R2 first, so that the voltage across
R5 is exactly 1V. Then the voltages across R3 and R4 can
be independently adjusted by shunting each with selected
resistors of 6 kΩ or higher resistance. This is possible because the reference of LM3914 No. 3 is acting as a constant
current source.
The references associated with LM3914s No. 1 and No. 2
should have their Ref Adj pins (pin 8) wired to ground, and
their Ref Outputs loaded by a 620Ω resistor to ground. This
makes available similar 20 mA current outputs to all the
LEDs in the system.
If an independent LED brightness control is desired (as in
the previous application), a unity gain buffer, such as the
LM310, should be placed between pin 7 and R1, similar to
the previous application.
15
www.national.com
LM3914
Application Hints
LM3914
Application Hints
(Continued)
Non-Interacting Adjustments for Expanded Scale Meter (4.5V to 5V, Bar or Dot Mode)
DS007970-16
Other Applications
Adjusting Linearity of Several Stacked Dividers
DS007970-17
www.national.com
16
•
•
•
•
•
•
•
•
“Slow” — fade bar or dot display (doubles resolution)
•
Electronic “meter-relay” — display could be circle or
semi-circle
•
Moving “hole” display — indicator LED is dark, rest of bar
lit
•
Drives vacuum-fluorescent and LCDs using added passive parts
20-step meter with single pot brightness control
10-step (or multiples) programmer
Multi-step or “staging” controller
Combined controller and process deviation meter
Direction and rate indicator (to add to DVMs)
Exclamation point display for power saving
Graduations can be added to dot displays. Dimly light every other LED using a resistor to ground
LM3914
Connection Diagrams
Plastic Chip Carrier Package
Dual-in-Line Package
DS007970-18
Top View
Order Number LM3914V
See NS Package Number V20A
DS007970-19
Top View
Order Number LM3914N-1
See NS Package Number NA18A
Order Number LM3914N *
See NS Package Number N18A
* Discontinued, Life Time Buy date 12/20/99
17
www.national.com
LM3914
Physical Dimensions
inches (millimeters) unless otherwise noted
Note: Unless otherwise specified.
1. Standard Lead Finish:
200 microinches /5.08 micrometer minimum
lead/tin 37/63 or 15/85 on alloy 42 or equivalent or copper
2. Reference JEDEC registration MS-001, Variation AC, dated May 1993.
Dual-In-Line Package (N)
Order Number LM3914N-1
NS Package Number NA18A
Plastic Chip Carrier Package (V)
Order Number LM3914V
NS Package Number V20A
www.national.com
18
LM3914 Dot/Bar Display Driver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Dual-In-Line Package (N)
Order Number LM3914N *
NS Package Number N18A
* Discontinued, Life Time Buy date 12/20/99
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
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English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Order this document by MC145170–2/D
MC145170-2
PLL Frequency Synthesizer
with Serial Interface
The new MC145170–2 is pin–for–pin compatible with the MC145170–1. A
comparison of the two parts is shown in the table below. The MC145170–2 is
recommended for new designs and has a more robust power–on reset
(POR) circuit that is more responsive to momentary power supply
interruptions. The two devices are actually the same chip with mask options
for the POR circuit. The more robust POR circuit draws approximately 20 µA
additional supply current. Note that the maximum specification of 100 µA
quiescent supply current has not changed.
The MC145170–2 is a single–chip synthesizer capable of direct usage in
the MF, HF, and VHF bands. A special architecture makes this PLL easy to
program. Either a bit– or byte–oriented format may be used. Due to the
patented BitGrabber registers, no address/steering bits are required for
random access of the three registers. Thus, tuning can be accomplished via
a 2–byte serial transfer to the 16–bit N register.
The device features fully programmable R and N counters, an amplifier at
the fin pin, on–chip support of an external crystal, a programmable reference
output, and both single– and double–ended phase detectors with linear
transfer functions (no dead zones). A configuration (C) register allows the
part to be configured to meet various applications. A patented feature allows
the C register to shut off unused outputs, thereby minimizing noise and
interference.
In order to reduce lock times and prevent erroneous data from being
loaded into the counters, a patented jam–load feature is included. Whenever
a new divide ratio is loaded into the N register, both the N and R counters are
jam–loaded with their respective values and begin counting down together.
The phase detectors are also initialized during the jam load.
• Operating Voltage Range: 2.7 to 5.5 V
•
•
•
•
•
•
•
•
Maximum Operating Frequency:
185 MHz @ Vin = 500 mVpp, 4.5 V Minimum Supply
100 MHz @ Vin = 500 mVpp, 3.0 V Minimum Supply
Operating Supply Current:
0.6 mA @ 3.0 V, 30 MHz
1.5 mA @ 3.0 V, 100 MHz
3.0 mA @ 5.0 V, 50 MHz
5.8 mA @ 5.0 V, 185 MHz
Operating Temperature Range: –40 to 85°C
CMOS PLL FREQUENCY
SYNTHESIZER WITH SERIAL
INTERFACE
SEMICONDUCTOR
TECHNICAL DATA
16
1
P SUFFIX
PLASTIC PACKAGE
CASE 648
16
16
1
1
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SOG–16)
DT SUFFIX
PLASTIC PACKAGE
CASE 948C
(TSSOP–16)
PIN CONNECTIONS
R Counter Division Range: 1 and 5 to 32,767
OSCin
1
16 VDD
OSCout
2
15 φV
REFout
3
14 φR
fin
4
13 PDout
Din
5
12 VSS
ENB
6
11 LD
CLK
7
10 fV
Dout
8
9 fR
N Counter Division Range: 40 to 65,535
Direct Interface to Motorola SPI Serial Data Port
See Application Notes AN1207/D and AN1671/D
See web site mot–sps.com for MC145170 control software. Select in
order, Products, Wireless Semiconductor, Download, then PLL Demo
Software. Choose PLLGEN.EXE.
(Top View)
BitGrabber is a trademark of Motorola Inc.
COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS
Parameter
MC145170–2
MC145170–1
2.7 V
2.5 V
Minimum Supply Voltage
Maximum Input Current, fin
Dynamic Characteristics, fin (Figure 23)
Power–On Reset Circuit
ORDERING INFORMATION
Operating
Temp Range
Device
150 µA
120 µA
MC145170P2
Unchanged
–
MC145170D2
Improved
–
MC145170DT2
Plastic DIP
TA = –40 to 85°C
 Motorola, Inc. 1999
MOTOROLA RF PRODUCTS DEVICE DATA
Package
SOG–16
TSSOP–16
Rev 4
1
MC145170–2
BLOCK DIAGRAM
1
OSCin
OSCout
fR Control
15-stage R Counter
OSC
2
9
fR
15
BitGrabber R Register
15 Bits
3
Lock Detector
And Control
11
Phase/Frequency
Detector A And Control
13
LD
7
CLK
Shift
Register
And
Control
Logic
5
Din
8
Dout
ENB
4-Stage
Reference
Divider
3
REFout
BitGrabber C Register
8 Bits
16
POR
Phase/Frequency
Detector B And Control
6
BitGrabber N Register
16 Bits
16
fin 4
Input
AMP
PDout
14
15
10
fV Control
φR
φV
fV
Pin 16 = VDD
Pin 12 = VSS
16-Stage N Counter
This device contains 4,800 active transistors.
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 5.5
V
DC Input Voltage
Vin
–0.5 to VDD + 0.5
V
DC Output Voltage
Vout
–0.5 to VDD + 0.5
V
DC Input Current, per Pin
Iin
±10
mA
DC Output Current, per Pin
Iout
±20
mA
DC Supply Current, VDD and VSS Pins
IDD
±30
mA
Power Dissipation, per Package
PD
300
mW
Storage Temperature
Tstg
–65 to 150
°C
Lead Temperature, 1 mm from Case
for 10 seconds
TL
260
°C
Parameter
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
2. ESD data available upon request.
2
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = –40 to 85°C)
Parameter
Test Condition
Power Supply Voltage Range
Symbol
VDD
V
Guaranteed
Limit
Unit
VDD
–
2.7 to 5.5
V
Maximum Low–Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
dc Coupling to fin
VIL
2.7
4.5
5.5
0.54
1.35
1.65
V
Minimum High–Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
dc Coupling to fin
VIH
2.7
4.5
5.5
2.16
3.15
3.85
V
VHys
2.7
5.5
0.15
0.20
V
Minimum Hysteresis Voltage (CLK, ENB)
Maximum Low–Level Output Voltage
(Any Output)
Iout = 20 µA
VOL
2.7
5.5
0.1
0.1
V
Minimum High–Level Output Voltage
(Any Output)
Iout = – 20 µA
VOH
2.7
5.5
2.6
5.4
V
Minimum Low–Level Output Current
(PDout, REFout, fR, fV, LD, φR, φV)
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
IOL
2.7
4.5
5.5
0.12
0.36
0.36
mA
Minimum High–Level Output Current
(PDout, REFout, fR, fV, LD, φR, φV)
Vout = 2.4 V
Vout = 4.1 V
Vout = 5.0 V
IOH
2.7
4.5
5.5
–0.12
–0.36
–0.36
mA
Minimum Low–Level Output Current
(Dout)
Vout = 0.4 V
IOL
4.5
1.6
mA
Minimum High–Level Output Current
(Dout)
Vout = 4.1 V
IOH
4.5
–1.6
mA
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin)
Vin = VDD or VSS
Iin
5.5
±1.0
µA
Maximum Input Current
(fin)
Vin = VDD or VSS
Iin
5.5
±150
µA
Vin = VDD or VSS,
Output in High–Impedance State
IOZ
5.5
±100
nA
5.5
±5.0
µA
Maximum Output Leakage Current
(PDout)
(Dout)
Maximum Quiescent Supply Current
Vin = VDD or VSS; Outputs Open;
Excluding fin Amp Input Current Component
IDD
5.5
100
µA
Maximum Operating Supply Current
fin = 500 mVpp;
OSCin = 1.0 MHz @ 1.0 Vpp;
LD, fR, fV, REFout = Inactive and No Connect;
OSCout, φV, φR, PDout = No Connect;
Din, ENB, CLK = VDD or VSS
Idd
–
[Note 2]
mA
NOTES: 1. When dc coupling to the OSCin pin is used, the pin must be driven rail–to–rail. In this case, OSCout should be floated.
2. The nominal values at 3.0 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5.0 V are 3.0 mA @ 50 MHz, and 5.8 mA
@ 185 MHz. These are not guaranteed limits.
MOTOROLA RF PRODUCTS DEVICE DATA
3
MC145170–2
AC INTERFACE CHARACTERISTICS ( TA = –40 to 85°C, CL = 50 pF, Input tr = tf = 10 ns, unless otherwise noted.)
Symbol
Figure
No.
VDD
V
Guaranteed
Limit
fclk
1
2.7
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
Maximum Propagation Delay, CLK to Dout
tPLH, tPHL
1, 5
2.7
4.5
5.5
150
85
85
ns
Maximum Disable Time, Dout Active to High Impedance
tPLZ, tPHZ
2, 6
2.7
4.5
5.5
300
200
200
ns
Access Time, Dout High Impedance to Active
tPZL, tPZH
2, 6
2.7
4.5
5.5
0 to 200
0 to 100
0 to 100
ns
tTLH, tTHL
1, 5
2.7
4.5
5.5
150
50
50
ns
1, 5
2.7
4.5
5.5
900
150
150
ns
Parameter
Serial Data Clock Frequency (Note: Refer to Clock tw Below)
Maximum Output Transition Time, Dout
CL = 50 pF
CL = 200 pF
Unit
Maximum Input Capacitance – Din, ENB, CLK
Cin
–
10
pF
Maximum Output Capacitance – Dout
Cout
–
10
pF
Unit
TIMING REQUIREMENTS ( TA = –40 to 85°C, Input tr = tf = 10 ns, unless otherwise noted.)
Parameter
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
Minimum Inactive–High Pulse Width, ENB
Minimum Pulse Width, CLK
Maximum Input Rise and Fall Times, CLK
4
Symbol
Figure
No.
VDD
V
Guaranteed
Limit
tsu, th
3
2.7
4.5
5.5
55
40
40
ns
tsu, th, trec
4
2.7
4.5
5.5
135
100
100
ns
tw(H)
4
2.7
4.5
5.5
400
300
300
ns
tw
1
2.7
4.5
5.5
166
125
125
ns
tr, tf
1
2.7
4.5
5.5
100
100
100
µs
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
SWITCHING WAVEFORMS
Figure 1.
tf
90%
CLK 50%
10%
Figure 2.
tr
VDD
tw
VSS
tw
1/fclk
tPLH
Dout
VDD
50%
ENB
Dout
tPHL
tTLH
Dout
tTHL
tPLZ
High
Impedance
50%
10%
tPZH
90%
50%
10%
VSS
tPZL
High
Impedance
Figure 4.
tw(H)
Valid
Din
VDD
50%
ENB
th
VDD
50%
CLK
CLK
50%
First
CLK
Figure 5. Test Circuit
Last
CLK
Test Point
7.5 kΩ
* Includes all probe and fixture capacitance.
MOTOROLA RF PRODUCTS DEVICE DATA
trec
VDD
VSS
Figure 6. Test Circuit
Test Point
CL *
VSS
th
tsu
VSS
Device
Under
Test
VDD
50%
VSS
tsu
VSS
90%
50%
Figure 3.
VDD
tPHZ
Device
Under
Test
CL *
Connect to VDD
when testing tPLZ AND
tPZL. Connect to VSS when
testing tPHZ and tPZH.
* Includes all probe and fixture capacitance.
5
MC145170–2
LOOP SPECIFICATIONS ( TA = –40 to 85°C)
VDD
Guaranteed Range
Symbol
Figure
No.
V
Min
Max
Unit
Input Frequency, fin [Note}
Vin ≥ 500 mVpp Sine Wave,
N Counter Set to Divide Ratio
Such that fV ≤ 2.0 MHz
f
7
2.7
3.0
4.5
5.5
5.0
5.0
25
45
80
100
185
185
MHz
Input Frequency, OSCin
Externally Driven with ac–coupled
Signal
Vin ≥ 1.0 Vpp Sine Wave,
OSCout = No Connect,
R Counter Set to Divide Ratio
Such that fR ≤ 2 MHz
f
8a
2.7
3.0
4.5
5.5
1.0*
1.0*
1.0*
1.0*
22
25
30
35
MHz
Crystal Frequency, OSCin and OSCout
C1 ≤ 30 pF
C2 ≤ 30 pF
Includes Stray Capacitance
fXTAL
9
2.7
3.0
4.5
5.5
2.0
2.0
2.0
2.0
12
12
15
15
MHz
Output Frequency, REFout
CL = 30 pF
fout
10, 12
2.7
4.5
5.5
dc
dc
dc
–
10
10
MHz
2.7
4.5
5.5
dc
dc
dc
–
2.0
2.0
MHz
Parameter
Test Condition
Operating Frequency of the
Phase Detectors
f
Output Pulse Width, φR, φV, and LD
fR in Phase with fV
CL = 50 pF
Output Transition Times,
φR, φV, LD, fR, and fV
CL = 50 pF
Input Capacitance
fin
OSCin
tw
11, 12
2.7
4.5
5.5
–
20
16
–
100
90
ns
tTLH,
tTHL
11, 12
2.7
4.5
5.5
–
–
–
–
65
60
ns
Cin
–
–
–
–
–
–
7.0
7.0
pF
* IF lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in ac–coupled case. Also, see Figure 22 for dc coupling.
6
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
Figure 7. Test Circuit, fin
100 pF
Sine Wave
Generator
fin
fV
Test
Point
MC145170-2
Vin
50 Ω*
VSS
VDD
V+
* Characteristic impedance
Figure 8.
Figure 8a. Test Circuit, OSC Circuit Externally Driven [Note]
Figure 8b. Circuit to Eliminate Self–Oscillation,
OSC Circuit Externally Driven [Note]
V+
0.01 µF
Sine Wave
Generator
OSCin
Vin
5.0
MΩ
Test
Point
fR
0.01 µF
Sine Wave
Generator
OSCin
MC145170-2
VSS
1.0
MΩ
Vin
OSCout
50 Ω
1.0
MΩ
50 Ω
VDD
Test
Point
MC145170-2
OSCout
VSS
V+
fR
VDD
V+
No Connect
Figure 10. Switching Waveform
Figure 9. Test Circuit, OSC Circuit with Crystal
OSCin
C1
MC145170-2
REFout
OSCout
C2
VSS
VDD
1/f REFout
Test
Point
REFout
50%
V+
Figure 12. Test Load Circuit
Figure 11. Switching Waveform
Output
tw
Output
50%
tTHL
NOTE:
Device
Under
Test
90%
10%
tTLH
Test Point
CL *
* Includes all probe and
fixture capacitance.
Use the circuit of Figure 8b to eliminate self–oscillation of the OSCin pin when the MC145170–2 has power applied with no external signal
applied at Vin. (Self–oscillation is not harmful to the MC145170–2 and does not damage the IC.)
MOTOROLA RF PRODUCTS DEVICE DATA
7
MC145170–2
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 5)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the N register, or 3 bytes
(24 bits) to access the R register. Additionally, the R register
can be accessed with a 15–bit transfer (see Table 1). An
optional pattern which resets the device is shown in Figure
13. The values in the C, N, and R registers do not change
during shifting because the transfer of data to the registers is
controlled by ENB.
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V. The formats are
shown in Figures 13, 14, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to
10 kΩ must be used. Parameters to consider when sizing the
resistor are worst–case IOL of the driving device, maximum
tolerable power consumption, and maximum data rate.
Table 1. Register Access
(MSBs are shifted in first, C0, N0, and R0 are the LSBs)
Number
of Clocks
Accessed
Register
Bit
Nomenclature
9 to 13
8
16
15 or 24
Other Values ≤ 32
Values > 32
See Figure 13
C Register
N Register
R Register
None
See Figures
24 — 31
(Reset)
C7, C6, C5, . . ., C0
N15, N14, N13, . . ., N0
R14, R13, R12, . . ., R0
CLK
Serial Data Clock Input (Pin 7)
Low–to–high transitions on Clock shift bits available at Din,
while high–to–low transitions shift bits from Dout. The chip’s
16–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Four to eight clock cycles followed by five clock cycles are
needed to reset the device; this is optional. Eight clock cycles
are required to access the C register. Sixteen clock cycles
are needed for the N register. Either 15 or 24 cycles can be
used to access the R register (see Table 1 and Figures 13,
14, 15, and 16). For cascaded devices, see Figures 24 to 31.
CLK typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of Din for more
information.
8
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
the potential of either the VSS or VDD pin during
power up. That is, the CLK input should not be
floated or toggled while the VDD pin is ramping
from 0 to at least 2.7 V. If control of the CLK pin is
not practical during power up, the initialization
sequence shown in Figure 13 must be used.
ENB
Active–Low Enable Input (Pin 6)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an
inactive high state, shifting is inhibited, Dout is forced to the
high–impedance state, and the port is held in the initialized
state. To transfer data to the device, ENB (which must start
inactive high) is taken low, a serial transfer is made via Din
and CLK, and ENB is taken back high. The low–to–high
transition on ENB transfers data to the C, N, or R register
depending on the data stream length per Table 1.
NOTE
Transitions on ENB must not be attempted while
CLK is high. This puts the device out of
synchronization with the microcontroller.
Resynchronization occurs when ENB is high and
CLK is low.
This input is also Schmitt–triggered and switches near
50% of V DD , thereby minimizing the chance of loading
erroneous data into the registers. See the last paragraph of
Din for more information.
Dout
Three–State Serial Data Output (Pin 8)
Data is transferred out of the 16–1/2–stage shift register
through Dout on the high–to–low transition of CLK. This
output is a No Connect, unless used in one of the manners
discussed below.
Dout could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a
system check conducted at power up to test the integrity of
the system’s processor, PC board traces, solder joints, etc.
The pin could be monitored at an in–line QA test during
board manufacturing.
Finally, Dout facilitates troubleshooting a system and
permits cascading devices.
REFERENCE PINS
OSCin /OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form a reference oscillator when connected to
terminals of an external parallel–resonant crystal.
Frequency–setting capacitors of appropriate values as
recommended by the crystal supplier are connected from
each pin to ground (up to a maximum of 30 pF each,
including stray capacitance). An external feedback resistor of
1.0 to 5.0 MΩ is connected directly across the pins to ensure
linear operation of the amplifier. The required connections for
the components are shown in Figure 9.
If desired, an external clock source can be ac coupled to
OSC in . A 0.01 µF coupling capacitor is used for
measurement purposes and is the minimum size
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
recommended for applications. An external feedback resistor
of approximately 5 MΩ is required across the OSC in and
OSC out pins in the ac–coupled case (see Figure 8a or
alternate circuit 8b). OSCout is an internal node on the device
and should not be used to drive any loads (i.e., OSC out is
unbuffered). However, the buffered REF out is available to
drive external loads.
The external signal level must be at least 1 V p–p; the
maximum frequencies are given in the Loop Specifications
table. These maximum frequencies apply for R Counter
divide ratios as indicated in the table. For very small ratios,
the maximum frequency is limited to the divide ratio times
2 MHz. (Reason: the phase/frequency detectors are limited
to a maximum input frequency of 2 MHz.)
If an external source is available which swings virtually
rail–to–rail (VDD to VSS), then dc coupling can be used. In the
dc–coupled case, no external feedback resistor is needed.
OSCout must be a No Connect to avoid loading an internal
node on the device, as noted above. For frequencies below
1 MHz, dc coupling must be used. The R counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the OSCin pin. See Figure 22.
Each rising edge on the OSCin pin causes the R counter to
decrement by one.
REFout
Reference Frequency Output (Pin 3)
This output is the buffered output of the crystal–generated
reference frequency or externally provided reference source.
This output may be enabled, disabled, or scaled via bits in the
C register (see Figure 14).
REF out can be used to drive a microprocessor clock input,
thereby saving a crystal. Upon power up, the on–chip
power–on–initialize circuit forces REF out to the OSC in
divided–by–8 mode.
REFout is capable of operation to 10 MHz; see the Loop
Specifications table. Therefore, divide values for the
reference divider are restricted to two or higher for OSCin
frequencies above 10 MHz.
If unused, the pin should be floated and should be
disabled via the C register to minimize dynamic power
consumption and electromagnetic interference (EMI).
COUNTER OUTPUT PINS
fR
R Counter Output (Pin 9)
This signal is the buffered output of the 15–stage R
counter. fR can be enabled or disabled via the C register
(patented). The output is disabled (static low logic level) upon
power up. If unused, the output should be left disabled and
unconnected to minimize interference with external circuitry.
The fR signal can be used to verify the R counter’s divide
ratio. This ratio extends from 5 to 32,767 and is determined
by the binary value loaded into the R register. Also, direct
access to the phase detector via the OSCin pin is allowed by
choosing a divide value of 1 (see Figure 15). The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of fR must not exceed 2 MHz.
When activated, the fR signal appears as normally low and
pulses high. The pulse width is 4.5 cycles of the OSCin pin
signal, except when a divide ratio of 1 is selected. When 1 is
MOTOROLA RF PRODUCTS DEVICE DATA
selected, the OSCin signal is buffered and appears at the fR
pin.
fV
N Counter Output (Pin 10)
This signal is the buffered output of the 16–stage N
counter. fV can be enabled or disabled via the C register
(patented). The output is disabled (static low logic level) upon
power up. If unused, the output should be left disabled and
unconnected to minimize interference with external circuitry.
The fV signal can be used to verify the N counter’s divide
ratio. This ratio extends from 40 to 65,535 and is determined
by the binary value loaded into the N register. The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of fV must not exceed 2 MHz.
When activated, the fV signal appears as normally low and
pulses high.
LOOP PINS
fin
Frequency Input (Pin 4)
This pin is a frequency input from the VCO. This pin feeds
the on–chip amplifier which drives the N counter. This signal
is normally sourced from an external voltage–controlled
oscillator (VCO), and is ac–coupled into fin. A 100 pF
coupling capacitor is used for measurement purposes and is
the minimum size recommended for applications (see Figure
7). The frequency capability of this input is dependent on the
supply voltage as listed in the Loop Specifications table.
For small divide ratios, the maximum frequency is limited to
the divide ratio times 2 MHz. (Reason: the phase/frequency
detectors are limited to a maximum frequency of 2 MHz.)
For signals which swing from at least the VIL to VIH levels
listed in the Electrical Characteristics table, dc coupling
may be used. Also, for low frequency signals (less than the
minimum frequencies shown in the Loop Specifications
table), dc coupling is a requirement. The N counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the fin pin. See Figure 22.
Each rising edge on the fin pin causes the N counter to
decrement by 1.
PDout
Single–Ended Phase/Frequency Detector Output
(Pin 13)
This is a three–state output for use as a loop error signal
when combined with an external low–pass filter. Through use
of a Motorola patented technique, the detector’s dead zone
has been eliminated. Therefore, the phase/frequency
detector is characterized by a linear transfer function. The
operation of the phase/frequency detector is described below
and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: negative
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: positive
pulses from high impedance
Frequenc y and Phas e of fV = fR : es s entially
high–impedance state; voltage at pin determined by loop
filter
POL bit (C7) = high
9
MC145170–2
Frequency of fV > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: negative
pulses from high impedance
Frequenc y and Phas e of fV = fR : es s entially
high–impedance state; voltage at pin determined by loop
filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PD out can be forced to the
high–impedance state by utilization of the disable feature in
the C register (patented).
Frequency of fV < fR or Phase of fV Lagging fR: φR =
essentially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and
interchanged via the C register (patented).
LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies (see Figure
17).
This output can be enabled and disabled via the C register
(patented). Upon power up, on–chip initialization circuitry
disables LD to a static low logic level to prevent a false “lock”
signal. If unused, LD should be disabled and left open.
φR and φV
Double–Ended Phase/Frequency Detector Outputs
(Pins 14, 15)
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a linear trans fer func tion. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: φV =
negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV =
essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR =
negative pulses, φV = essentially high
POWER SUPPLY
VDD
Most Positive Supply Potential (Pin 16)
This pin may range from 2.7 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to
VSS using low–inductance capacitor(s) mounted very close
to the device. Lead lengths on the capacitor(s) should be
minimized. (The very fast switching speed of the device
causes current spikes on the power leads.)
VSS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes,
the VSS pin is tied to a ground plane.
Figure 13. Reset Sequence
Power
Up
ENB
CLK
1
2
3
1
2
3
4
5
One
Zero
4 or More Clocks
Din
Don't Cares
NOTE:
10
Zeroes
Don't Cares
This initialization sequence is usually not necessary because the on–chip power–on reset circuit performs the initialization
function. However, this initialization sequence must be used immediately after power up if control of the CLK pin is not
possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below
2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the on–chip
power–on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V.
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
ENB
1
CLK
2
3
4
5
6
7
MSB
C7
Din
8
*
LSB
C6
C5
C4
C3
C2
C1
C0
* At this point, the new byte is transferred to the C register and stored. No other registers
are affected.
C7 — POL:
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts
PDout and interchanges the φR function with φV as depicted in Figure 17. Also see the phase
detector output pin descriptions for more information. This bit is cleared low at power up.
C6 — PDA/B:
Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR
and φV to the static high state. When cleared low, phase/frequency detector B is enabled (φR
and φV) and phase/frequency detector A is disabled with PDout forced to the high–impedance
state. This bit is cleared low at power up.
C5 — LDE:
Enables the lock detector output when set high. When the bit is cleared low, the LD output is
forced to a static low level. This bit is cleared low at power up.
C4 – C2, OSC2 – OSC0: Reference output controls which determine the REFout characteristics as shown below. Upon
power up, the bits are initialized such that OSCin /8 is selected.
C4
C3
C2
0
0
0
dc (Static Low)
0
0
1
OSCin
0
1
0
OSCin /2
0
1
1
OSCin /4
1
0
0
OSCin /8 (POR Default)
1
0
1
OSCin /16
1
1
0
OSCin /8
1
1
1
OSCin /16
REFout Frequency
C1 — fVE:
Enables the fV output when set high. When cleared low, the fV output is forced to a static low
level. The bit is cleared low upon power up.
C0 — fRE:
Enables the fR output when set high. When cleared low, the fR output is forced to a static low
level. The bit is cleared low upon power up.
MOTOROLA RF PRODUCTS DEVICE DATA
11
12
CLK
ENB
MSB
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
X
9
R14
10
R13
11
R12
12
R11
13
R10
14
R9
15
R8
16
R7
17
R6
18
R5
19
Figure 15. R Register Access and Formats (Either 24 or 15 Clock Cycles Can Be Used)
R4
20
R3
21
R2
22
R1
23
LSB
24
*
X
CLK
ENB
1
Don't Care Bits
R13
2
R12
3
R11
4
R10
5
R9
6
R8
See Below
7
R7
8
R6
9
R5
10
R4
See Below
11
R3
12
R2
13
R1
14
See Below
15
*
See Below
Din
Octal Value
0
0
0
0
0
0
0
0
.
.
.
F
F
0
1
2
3
4
5
6
7
.
.
.
E
F
Hexadecimal Value
0
0
0
0
0
0
0
0
.
.
.
F
F
R Counter = ÷ 32,766
R Counter = ÷ 32,767
Decimal Equivalent
Not Allowed
R Counter = ÷ 1 (Direct Access to Reference Side of Phase/Frequency Detector)
Not Allowed
Not Allowed
Not Allowed
R Counter = ÷ 5
R Counter = ÷ 6
R Counter = ÷ 7
R0
R14
0
0
0
0
0
0
0
0
.
.
.
7
7
LSB
MSB
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
* At this point, the new data is transferred to the R register and stored. No other registers are affected.
Din
R0
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
MC145170–2
Figure 15.
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
Figure 16. N Register Access and Format (16 Clock Cycles Are Used)
ENB
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
N15
Din
16
*
LSB
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
Not Allowed
Not Allowed
Not Allowed
Not Allowed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
5
6
7
8
9
A
B
Not Allowed
Not Allowed
Not Allowed
N Counter = ÷ 40
N Counter = ÷ 41
N Counter = ÷ 42
N Counter = ÷ 43
F
F
F
F
F
F
E
F
N Counter = ÷ 65,534
N Counter = ÷ 65,535
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
N3
N2
N1
N0
Decimal Equivalent
Hexadecimal Value
* At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N and
R counters are jam–loaded and begin counting down together.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms
fR
Reference
OSCin ÷ R
VH
VL
fV
Feedback
(fin ÷ N)
PDout
VH
VL
*
φR
VH
High Impedance
VL
VH
VL
φV
LD
VH
VL
VH
VL
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, both the sinking and sourcing output FETs are turned on for a very short interval.
NOTE:
The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor. PDout, φR, and φV are shown with the polarity bit (POL) = low;
see Figure 14 for POL.
MOTOROLA RF PRODUCTS DEVICE DATA
13
MC145170–2
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola’s CMOS frequency
synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated
crystal oscillators (TCXOs) or crystal–controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of CMOS logic levels at the output may be
direct or dc coupled to OSCin. If the oscillator does not have
CMOS logic levels on the outputs, capacitive or ac coupling
to OSCin may be used (see Figures 8a and 8b).
For additional information about TCXO s , vis it
motorola.com on the world wide web.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference
source frequency. A fundamental mode crystal, parallel
resonant at the desired operating frequency, should be
connected as shown in Figure 18.
The crystal should be specified for a loading capacitance
(CL) which does not exceed 20 pF when used at the highest
operating frequencies listed in the Loop Specifications
table. Larger CL values are possible for lower frequencies.
Assuming R1 = 0 Ω, the shunt load capacitance (CL)
presented across the crystal can be estimated to be:
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency at the REFout pin (OSCout is not used because
loading impacts the oscillator). The frequency should
increase very slightly as the dc supply voltage is increased.
An overdriven crystal decreases in frequency or becomes
unstable with an increase in supply voltage. The operating
supply voltage must be reduced or R1 must be increased in
value if the overdriven condition exists. The user should note
that the oscillator start–up time is proportional to the value of
R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 2).
Figure 18. Pierce Crystal Oscillator Circuit
Frequency
Synthesizer
OSCin
R1*
C1
5.0 to 10 pF
C C out
in
C +
) C a ) C stray ) C1 C2
L
C ) C out
C1 ) C2
in
5.0 pF (see Figure 19)
6.0 pF (see Figure 19)
1.0 pF (see Figure 19)
external capacitors (see Figure 18)
the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
appropriate stray value to the values for Cin and Cout. For this
approach, the term Cstray becomes 0 in the above expression
for CL.
A good design practice is to pick a small value for C1, such
as 5 to 10 pF. Next, C2 is calculated. C1 < C2 results in a
more robust circuit for start–up and is more tolerant of crystal
parameter variations.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 20. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
14
C2
* May be needed in certain cases. See text.
where
Cin =
Cout =
Ca =
C1 and C2 =
Cstray =
OSCout
Rf
Figure 19. Parasitic Capacitances of the Amplifier
and Cstray
Ca
OSCin
Cin
OSCout
Cout
Cstray
Figure 20. Equivalent Crystal Networks
1
2
CS
LS
RS
1
2
CO
1
NOTE:
Re
Xe
2
Values are supplied by crystal manufacturer
(parallel resonant crystal).
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
D. Babin, “Designing Crystal Oscillators”, Machine
Design, March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
See web site mot–sps.com for MC145170–2 control
software. Select in order, Products, Wireless Semiconductor,
Download, then PLL Demo Software. Choose PLLGEN.EXE.
Table 2. Partial List of Crystal
Manufacturers
CTS Corp.
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE:
MOTOROLA RF PRODUCTS DEVICE DATA
Motorola cannot recommend one
supplier over another and in no
way suggests that this is a
complete listing of crystal
manufacturers.
15
MC145170–2
PHASE–LOCKED LOOP — LOW PASS FILTER DESIGN
(A)
PDout
VCO
R1
ωn =
ζ =
C
F(s) =
(B)
PDout
VCO
R1
ωn =
Kφ KVCO
NR1C
Nωn
2KφKVCO
1
R1sC + 1
Kφ KVCO
NC(R1 + R2)
R2
ζ =
C
F(s) =
0.5 ωn
ǒ R Că+
2
N
KφKVCO
Ǔ
R2sCă+ă1
(R1ă+ăR2)sCă+ă1
R2
(C)
φR
R1
-
φV
+
R1
R2
ωn =
C
A
VCO
MC33077 or
equivalent
(Note 3)
C
ζ =
Kφ KVCO
NCR1
ωnR2C
2
Assuming Gain A Is Very Large, Then:
F(s) =
R2sC + 1
R1sC
NOTES:
1. For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from
the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network
does not significantly affect ωn.
2. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of
the op amp.
3. For the latest information on MC33077 or equivalent, see the Motorola Analog IC web site at http://www.mot–sps.com/analog.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = VDD / 4π volts per radian for PDout
Kφ (Phase Detector Gain) = VDD / 2π volts per radian for φV and φR
KVCO (VCO Gain) =
2π∆fVCO
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ωn ≈ (2πfR/50) where
fR is the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher
fR–related VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola Semiconductor Products, Inc., 1998.
16
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
Figure 21. Example Application
VHF Output
Buffer
VHF VCO
Low-pass Filter
V+
2
3
V+
4
5
6
7
MCU
8
Optional
Threshold
Detector
Optional
(Note 5)
VDD
OSCin
OSCout
φV
REFout
φR
fin
Din
ENB
MC145170-2
1
PDout
VSS
LD
CLK
fV
Dout
fR
16
15
14
Optional
Loop Error Signals
(Note 1)
13
12
11
10
9
Integrator
(Note 4)
NOTES:
1. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked
Loop — Low–Pass Filter Design page for additional information. The φR and φV outputs swing
rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range
of the op amp used in the combiner/loop filter.
2. For optimum performance, bypass the VDD pin to VSS (GND) with one or more low–inductance
capacitors.
3. The R counter is programmed for a divide value = OSCin/fR. Typically, fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = N, where N is the divide value of
the N counter.
4. May be an R–C low–pass filter.
5. May be a bipolar transistor.
MOTOROLA RF PRODUCTS DEVICE DATA
17
MC145170–2
Figure 22. Low Frequency Operation Using dc Coupling
V+
VDD
14
A
1
2
C
OSCin
MC74HC14A
B
3
No Connect
MC145170-2
4
7
OSCout
D
fin
VSS
NOTE: The signals at Points A and B may be low–frequency sinusoidal
or square waves with slow edge rates or noisy signal edges. At
Points C and D, the signals are cleaned up, have sharp edge
rates, and rail–to–rail signal swings. With signals as described at
Points C and D, the MC145170–2 is guaranteed to operate down
to a frequency as low as dc.
Refer to the MC74HC14A data sheet for input switching levels
and hysteresis voltage range.
18
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
Figure 23. Input Impedance at fin — Series Format (R + jX)
(5.0 MHz to 185 MHz)
fin (Pin 4)
SOG Package
1
2
3
4
Marker
Frequency
(MHz)
Resistance
(Ω)
Reactance
(Ω)
Capacitance
(pF)
1
2
3
4
5
100
150
185
2390
39.2
25.8
42.6
- 5900
- 347
- 237
- 180
5.39
4.58
4.48
4.79
Figure 24. Cascading Two MC145170–2 Devices
Device #1
MC145170-2
Din
CLK
ENB
Device #2
MC145170-2
Dout
Din
CLK
ENB
Dout
33 kΩ
NOTE 1
CMOS
MCU
Optional
NOTES:
1. The 33 kΩ resistor is needed to prevent the Din pin from floating. (The Dout pin is a three–state output.)
2. See related Figures 25, 26, and 27.
MOTOROLA RF PRODUCTS DEVICE DATA
19
20
X
2
7
X
8
X
9
X
10
15
X
16
Figure 25.
C7
17
23
C Register Bits of Device #2
in Figure 24
C6
18
C0
24
X
25
X
26
31
X
1
X
2
8
X
9
X
X
32
Figure 26.
10
25
26
27
30
R9
31
39
40
X
41
42
44
45
Figure 26. Accessing the R Registers of Two Cascaded MC145170–2 Devices
NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
CLK
X
1
C7
33
C6
34
39
48
49
50
C Register Bits of Device #1
in Figure 24
55
C0
40
NOTE
56
NOTE
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ENB
D in
CLK
ENB
Figure 25. Accessing the C Registers of Two Cascaded MC145170–2 Devices
MC145170–2
D in
R13
R Register Bits of Device #2
in Figure 24
R1
R0
R14
NOTE: At this point, the new data is transferred to the R registers of both devices and stored. No other registers are affected.
R14
R7
R6
R Register Bits of Device #1
in Figure 24
R11
R0
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
MOTOROLA RF PRODUCTS DEVICE DATA
MOTOROLA RF PRODUCTS DEVICE DATA
CLK
ENB
X
1
X
2
8
X
9
X
10
15
X
16
17
23
24
25
N7
N15
NOTE: At this point, the new data is transferred to the N registers of both devices and stored. No other registers are affected.
N0
33
39
N7
41
N Register Bits of Device #1
in Figure 24
N8
40
47
N0
48
NOTE
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
N Register Bits of Device #2
in Figure 24
N8
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
N15
32
Figure 27.
D in
31
Figure 27. Accessing the N Registers of Two Cascaded MC145170–2 Devices
MC145170–2
21
MC145170–2
Figure 28. Cascading Two Different Device Types
V+
VPD
Device #1
MC145170-2
Din
CLK
ENB
VDD
VDD VCC
Dout
Din
Device #2
Note 2
CLK
ENB
VPD
Output A
(Dout)
33 kΩ
Note 1
CMOS
MCU
Optional
NOTES:
1. The 33 kΩ resistor is needed to prevent the Din pin from floating. (The Dout pin is a three–state output.)
2. This PLL Frequency Synthesizer may be a MC145190, MC145191, MC145192, MC145200, or MC145201.
3. See related Figures 29, 30, and 31.
22
MOTOROLA RF PRODUCTS DEVICE DATA
X
1
X
2
7
X
8
X
9
X
10
15
X
16
C7
17
23
Figure 29.
MOTOROLA RF PRODUCTS DEVICE DATA
CLK
X
26
31
X
1
X
2
16
A23
17
A22
18
20
X
32
A18
22
30
A8
32
39
A0
40
X
41
R14
42
R13
43
C6
34
39
46
R9
47
48
R8
40
55
C0
C Register Bits of Device #1
in Figure 28
R Register Bits of Device #1
in Figure 28
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
NOTE: At this point, the new data is transferred to the A register of Device #2 and R register of Device #1 and stored. No other registers are affected.
A9
31
C7
33
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
A Register Bits of Device #2
in Figure 28
A19
21
Figure 30. Accessing the A and R Registers of Two Different Device Types
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
D in
X
25
NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
C0
24
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
C Register Bits of Device #2
in Figure 28
C6
18
NOTE
R0
56
NOTE
ÇÇÇ
ÇÇÇ
ÇÇÇ
ENB
D in
CLK
ENB
Figure 29. Accessing the C Registers of Two Different Device Types
MC145170–2
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
Figure 30.
23
24
D in
CLK
ENB
X
1
X
2
8
X
9
X
10
15
X
16
23
R7
25
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
R Register Bits of Device #2
in Figure 28
R8
24
31
R0
32
N15
33
39
N7
41
N Register Bits of Device #1
in Figure 28
N8
40
47
N0
48
NOTE
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
NOTE: At this point, the new data is transferred to the R register of Device #2 and N register of Device #1 and stored. No other registers are affected.
R15
17
Figure 31. Accessing the R and N Registers of Two Different Device Types
MC145170–2
Figure 31.
MOTOROLA RF PRODUCTS DEVICE DATA
MC145170–2
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T–
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SOG–16)
ISSUE J
–A–
16
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
MOTOROLA RF PRODUCTS DEVICE DATA
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
25
MC145170–2
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC PACKAGE
CASE 948C–03
(TSSOP–16)
ISSUE B
A
-P-
16x
K
REF
0.200 (0.008)
16
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -U-.
T
9
B
L
PIN 1
IDENTIFICATION
1
8
-U-
C
0.100 (0.004)
-T-
M
D
SEATING
PLANE
K
J1
H
G
A
K1
M
J
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
--5.10
4.30
4.50
--1.20
0.05
0.25
0.45
0.55
0.65 BSC
0.22
0.23
0.09
0.24
0.09
0.18
0.16
0.32
0.16
0.26
6.30
6.50
0°
10 °
INCHES
MIN
MAX
--0.200
0.169
0.177
--0047
0.002
0.010
0.018
0.022
0.026 BSC
0.009
0.010
0.004
0.009
0.004
0.007
0.006
0.013
0.006
0.010
0.248
0.256
0°
10 °
A
F
SECTION A–A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the
logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1,
Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
852–26668334
Technical Information Center: 1–800–521–6274
HOME PAGE: http://www.motorola.com/semiconductors/
26
◊
MC145170–2/D
MOTOROLA RF PRODUCTS DEVICE
DATA
RF COMMUNICATIONS PRODUCTS
SA612A
Double-balanced mixer and oscillator
Product specification
Replaces data of September 17, 1990
IC17 Data Handbook
Philips Semiconductors
1997 Nov 07
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
DESCRIPTION
SA612A
PIN CONFIGURATION
The SA612A is a low-power VHF monolithic double-balanced mixer
with on-board oscillator and voltage regulator. It is intended for low
cost, low power communication systems with signal frequencies to
500MHz and local oscillator frequencies as high as 200MHz. The
mixer is a “Gilbert cell” multiplier configuration which provides gain
of 14dB or more at 45MHz.
D, N Packages
The oscillator can be configured for a crystal, a tuned tank
operation, or as a buffer for an external L.O. Noise figure at 45MHz
is typically below 6dB and makes the device well suited for high
performance cordless phone/cellular radio. The low power
consumption makes the SA612A excellent for battery operated
equipment. Networking and other communications products can
benefit from very low radiated energy levels within systems. The
SA612A is available in an 8-lead dual in-line plastic package and an
8-lead SO (surface mounted miniature package).
INPUT A 1
8
VCC
INPUT B 2
7
OSCILLATOR
GND 3
6
OSCILLATOR
OUTPUT A 4
5
OUTPUT B
SR00098
Figure 1. Pin Configuration
APPLICATIONS
• Cordless telephone
• Portable radio
• VHF transceivers
• RF data links
• Sonabuoys
• Communications receivers
• Broadband LANs
• HF and VHF frequency conversion
• Cellular radio mixer/oscillator
FEATURES
• Low current consumption
• Low cost
• Operation to 500MHz
• Low radiated energy
• Low external parts count; suitable for crystal/ceramic filter
• Excellent sensitivity, gain, and noise figure
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
DWG #
8-Pin Plastic Dual In-Line Plastic (DIP)
DESCRIPTION
-40 to +85°C
SA612AN
SOT97-1
8-Pin Plastic Small Outline (SO) package (Surface-Mount)
-40 to +85°C
SA612AD
SOT96-1
BLOCK DIAGRAM
8
7
6
5
V CC
OSCILLATOR
VOLTAGE
REGULATOR
GROUND
1
2
3
4
SR00099
Figure 2. Block Diagram
1997 Nov 07
2
853-0391 18662
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VCC
Maximum operating voltage
9
V
TSTG
Storage temperature
-65 to +150
°C
TA
Operating ambient temperature range SA612A
-40 to +85
°C
AC/DC ELECTRICAL CHARACTERISTICS
TA=25°C, VCC = 6V, Figure 3
SYMBOL
VCC
PARAMETER
TEST CONDITION
Power supply voltage range
LIMITS
Min
Typ
4.5
Max
8.0
V
DC current drain
2.4
fIN
Input signal frequency
500
MHz
fOSC
Oscillator frequency
200
MHz
Noise figured at 45MHz
5.0
dB
-13
dBm
Third-order intercept point at 45MHz
RFIN=-45dBm
Conversion gain at 45MHz
14
RIN
RF input resistance
1.5
CIN
RF input capacitance
Mixer output resistance
(Pin 4 or 5)
mA
dB
kΩ
3
pF
1.5
kΩ
radio 2nd IF and demodulator, the SA612A is capable of receiving
-119dBm signals with a 12dB S/N ratio. Third-order intercept is
typically -15dBm (that’s approximately +5dBm output intercept
because of the RF gain). The system designer must be cognizant of
this large signal limitation. When designing LANs or other closed
systems where transmission levels are high, and small-signal or
signal-to-noise issues not critical, the input to the SA612A should be
appropriately scaled.
DESCRIPTION OF OPERATION
The SA612A is a Gilbert cell, an oscillator/buffer, and a temperature
compensated bias network as shown in the equivalent circuit. The
Gilbert cell is a differential amplifier (Pins 1 and 2) which drives a
balanced switching cell. The differential input stage provides gain
and determines the noise figure and signal handling performance of
the system.
The SA612A is designed for optimum low power performance.
When used with the SA614A as a 45MHz cordless phone/cellular
1997 Nov 07
17
3.0
UNIT
3
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
TEST CONFIGURATION
0.5 to 1.3µH
22pF
1nF
5.5µH
34.545MHz THIRD OVERTONE CRYSTAL
10pF
VCC
100nF
6.8µF
10nF
8
7
6
5
150pF
OUTPUT
1.5 to
44.2µH
612A
330pF
1
2
3
120pF
4
47pF
0.209 to
0.283µH
INPUT
220pF
100nF
SR00101
Figure 3. Test Configuration
8
VCC
18k
BUFFER
6
7
1.5k
1.5k
4
5
25k
BIAS
BIAS
2
1
BIAS
1.5k
1.5k
3
GND
SR00102
Figure 4. Equivalent Circuit
1997 Nov 07
4
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
external signal can be injected at Pin 6 through a DC blocking
capacitor. External L.O. should be 200mVP-P minimum to 300mVP-P
maximum.
Besides excellent low power performance well into VHF, the
SA612A is designed to be flexible. The input, output, and oscillator
ports can support a variety of configurations provided the designer
understands certain constraints, which will be explained here.
Figure 7 shows several proven oscillator circuits. Figure 7a is
appropriate for cordless phones/cellular radio. In this circuit a third
overtone parallel-mode crystal with approximately 5pF load
capacitance should be specified. Capacitor C3 and inductor L1 act
as a fundamental trap. In fundamental mode oscillation the trap is
omitted.
The RF inputs (Pins 1 and 2) are biased internally. They are
symmetrical. The equivalent AC input impedance is approximately
1.5k || 3pF through 50MHz. Pins 1 and 2 can be used
interchangeably, but they should not be DC biased externally. Figure
5 shows three typical input configurations.
The mixer outputs (Pins 4 and 5) are also internally biased. Each
output is connected to the internal positive supply by a 1.5kΩ
resistor. This permits direct output termination yet allows for
balanced output as well. Figure 6 shows three single-ended output
configurations and a balanced output.
Figure 8 shows a Colpitts varacter tuned tank oscillator suitable for
synthesizer-controlled applications. It is important to buffer the
output of this circuit to assure that switching spikes from the first
counter or prescaler do not end up in the oscillator spectrum. The
dual-gate MOSFET provides optimum isolation with low current.
The FET offers good isolation, simplicity, and low current, while the
bipolar circuits provide the simple solution for non-critical
applications. The resistive divider in the emitter-follower circuit
should be chosen to provide the minimum input signal which will
assume correct system operation.
The oscillator is capable of sustaining oscillation beyond 200MHz in
crystal or tuned tank configurations. The upper limit of operation is
determined by tank “Q” and required drive levels. The higher the Q
of the tank or the smaller the required drive, the higher the
permissible oscillation frequency. If the required L.O. is beyond
oscillation limits, or the system calls for an external L.O., the
612A
612A
612A
1
2
1
2
1
INPUT
a. Single-Ended Tuned Input
b. Balanced Input (For Attenuation
of Second-Order Products)
2
c. Single-Ended Untuned Input
SR00103
Figure 5. Input Configuration
1997 Nov 07
5
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
CT*
12pF
5
5
CFU455
or Equivalent
612A
612A
Filter K&L 38780 or Equivalent
*CT matches 3.5kΩ to next stage
4
4
a. Single-Ended Ceramic Filter
b. Single-Ended Crystal Filter
5
5
612A
612A
4
4
c. Single-Ended IFT
d.. Balanced Output
SR00104
Figure 6. Output Configuration
L1
C2
C3
XTAL
8
7
C1
6
5
8
7
2
5
8
7
612A
612A
1
6
3
4
1
2
5
612A
3
TC02101S
a. Colpitts Crystal Oscillator
(Overtone Mode)
6
4
1
TC02111S
b. Colpitts L/C Tank Oscillator
2
3
4
TC02121S
c. Hartley L/C Tank Oscillator
SR00105
Figure 7. Oscillator Circuits
1997 Nov 07
6
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
5.5µH
+6V
10µF
0.10pF
1
0.1µF
8
2
TO
BUFFER
7
612A
10pF
7pF
3
6
4
5
1000pF
DC CONTROL VOLTAGE
FROM SYNTHESIZER
1000pF
0.06µH
MV2105
OR EQUIVALENT
0.01µF
100k
2k
3SK126
2N918
0.01pF
2N5484
2pF
TO SYNTHESIZER
330
100k
100k
0.01µF
TO SYNTHESIZER
1.0nF
SR00106
Figure 8. Colpitts Oscillator Suitable for Synthesizer Applications and Typical Buffers
1997 Nov 07
7
Philips Semiconductors
Product specification
Double-balanced mixer and oscillator
SA612A
TEST CONFIGURATION
0.5 to 1.3µH
22pF
44.545MHz THIRD OVERTONE CRYSTAL
5.5µH
6.8µF
5.6pF
1nF
VCC
100nF
10nF
8
7
6
5
3
4
612A
1
2
SFG455A3
OR EQUIVALENT
455kHZ
47pF
0.209 to 0.283µH
INPUT
45MHz IN
220pF
100nF
SR00107
Figure 9. Typical Application for Cordless/Cellular Radio
1997 Nov 07
8
Philips Semiconductors
Product specification
SA612A
3.50
6.00
3.25
5.75
NOISE FIGURE (dB)
SUPPLY CURRENT 9mA)
Double-balanced mixer and oscillator
8.5V
3.00
6.0V
2.75
4.5V
2.50
2.25
4.5V
6.0V
8.5V
5.50
5.25
5.00
4.75
2.00
4.50
1.75
4.25
4.00
–40 –30 –20 –10
1.50
–40 –30 –20 –10
0 10 20 30 40
TEMPERATURE OC
50
60 70
0
80 90
10 20 30 40 50
TEMPERATURE OC
60 70
80 90
SR00111
SR00108
Figure 10. ICC vs Supply Voltage
Figure 13. Noise Figure
RF1 = 45MHz, IF = 455kHz, RF2 = 45.06MHz
20.0
3rd ORDER PRODUCT
19.5
20
18.5
6.0V
8.5V
4.5V
18.0
17.5
17.0
IF OUTPUT POWER (dBm)
CONVERSION GAIN (dB)
19.0
16.5
16.0
15.5
15.0
14.5
14.0
–40 –30 –20 –10
0
10
20
30 40
50
60
70
80
0
–20
FUND. PRODUCT
–40
–60
90
TEMPERATURE OC
SR00109
–80
–60
–40
–20
0
RF INPUT LEVEL (dBm)
Figure 11. Conversion Gain vs Supply Voltage
20
SR00112
Figure 14. Third-Order Intercept and Compression
–10.0
–11.0
–11.5
–10
–12.0
–11
–12.5
–12
INTERCEPT (dBm)
INPUT INTERCEPT POINT (dBm)
–10.5
–13.0
–13.5
–14.0
–14.5
–15.0
–15.5
–13
–14
–15
–16
–16.0
–17
–16.5
–17.0
–40 –30 –20 –10
0
10
20
30
40
50
60 70
80
–18
90
TEMPERATURE OC
SR00110
4
5
6
7
VCC (VOLTS)
Figure 12. Third-Order Intercept Point
8
9
10
SR00113
Figure 15. Input Third-Order Intermod Point vs VCC
1997 Nov 07
9
Philips Semiconductors
Product specification
Double-balanced mixer oscillator
SA612
SO8: plastic small outline package; 8 leads; body width 3.9mm
1997 Nov 07
10
SOT96-1
Philips Semiconductors
Product specification
Double-balanced mixer oscillator
SA612
DIP8: plastic dual in-line package; 8 leads (300 mil)
1997 Nov 07
SOT97-1
11
Philips Semiconductors
Product specification
Double-balanced mixer oscillator
SA612
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
 Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
1997 Nov 07
12
a
Microphone Preamplifier with
Variable Compression and Noise Gating
SSM2165*
GENERAL DESCRIPTION
The SSM2165 is a complete and flexible solution for conditioning microphone inputs in computer audio systems. It is also
excellent for improving vocal clarity in communications and
public address systems. A low noise voltage controlled amplifier
(VCA) provides a gain that is dynamically adjusted by a control
loop to maintain a set compression characteristic. The compression ratio is set by a single resistor and can be varied from 1:1 to
over 15:1 relative to the fixed rotation point. Signals above the
rotation point are limited to prevent overload and to eliminate
“popping.” A downward expander (noise gate) prevents amplification of noise or hum. This results in optimized signal levels
prior to digitization, thereby eliminating the need for additional
gain or attenuation in the digital domain that could add noise or
impair accuracy of speech recognition algorithms. The flexibility
of setting the compression ratio and the time constant of the
level detector, coupled with two values of rotation point, make
the SSM2165 easy to integrate in a wide variety of microphone
conditioning applications.
The SSM2165 is an ideal companion product for audio codecs
used in computer systems, such as the AD1845 and AD1847.
The device is available in 8-lead SOIC and P-DIP packages, and
guaranteed for operation over the extended industrial temperature
range of –40°C to +85°C. As shown in Figure 1a, the SSM2165-1
has a rotation point of –25.7 dBu (40 mV)1, a VCA gain of 18 dB,
and gives –7.7 dBu (320 mV) before limiting. As shown in Figure
1b, the SSM2165-2 has a rotation point of –17.8 dBu (100 mV),
*Patents pending.
1
All signals are in rms volts or dBu (0 dBu = 0.775 V rms).
C2
10mF
+
V+
AUDIO
IN+
V+ BUFOUT
C1
0.1mF
+1
RA
2
VCAIN
RA
2
VOUT
VCA
BUFFER
LEVEL
DETECTOR
CONTROL
SSM2165
AVG CAP
C3
22mF
GND
+
R1
25kV
COMPRESSION
RATIO SET
a VCA gain of 8 dB and gives –9.8 dBu (250 mV) before limiting.
Both have a noise gate threshold of –64 dBu (500 µV), below
which downward expansion reduces the gain with a ratio of
approximately 1:3. That is, a –3 dB reduction of output signal
occurs with a –1 dB reduction of input signal. For applications
requiring adjustable noise gate threshold, VCA gain up to 18 dB,
and adjustable rotation point, please refer to the SSM2166.
0
–10
OUTPUT – dBu
APPLICATIONS
Microphone Preamplifier/Processor
Computer Sound Cards
Public Address/Paging Systems
Communication Headsets
Telephone Conferencing
Guitar Sustain Effects Generator
Computerized Voice Recognition
Surveillance Systems
Karaoke and DJ Mixers
FUNCTIONAL BLOCK DIAGRAM
–20
–30
–40
–50
–60
–80
–70
–60
–50
–40
INPUT – dBu
–30
–20
–10
Figure 1a. SSM2165-1 Compression and Gating Characteristics
0
–10
–20
OUTPUT – dBu
FEATURES
Complete Microphone Conditioner in an 8-Lead Package
Single +5 V Operation
Preset Noise Gate Threshold
Compression Ratio Set by External Resistor
Automatic Limiting Feature Prevents ADC Overload
Adjustable Release Time
Low Noise and Distortion
20 kHz Bandwidth (ⴞ1 dB)
Low Cost
–30
–40
–50
–60
–70
–80
–70
–60
–50
–40
INPUT – dBu
–30
–20
–10
Figure 1b. SSM2165-2 Compression and Gating Characteristics
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
SSM2165–SPECIFICATIONS (V+ = +5 V, f = 1 kHz, R = 100 k⍀, R
L
Parameter
AUDIO SIGNAL PATH
Voltage Noise Density
Noise
Total Harmonic Distortion
SSM2165-1
SSM2165-2
Input Impedance
Output Impedance
Load Drive
= 0 ⍀, TA = +25ⴗC, unless otherwise noted)
Symbol
Conditions
en
15:1 Compression, VIN = GND
20 kHz Bandwidth, VIN = GND
17
–109
Min
Typ
2nd and 3rd Harmonics, VIN = –30 dBu
2nd and 3rd Harmonics, VIN = –20 dBu
22 kHz Low-Pass Filter
0.2
0.2
Max
Units
nV/√Hz2
dBu1
THD+N
Resistive
Capacitive
1% THD
1% THD
1:1 Compression
VCA G = 18 dB
VCA G = 8 dB
CONTROL SECTION
VCA Dynamic Gain Range
VCA Fixed Gain
SSM2165-1
SSM2165-2
Rotation Point
SSM2165-1
SSM2165-2
Compression Ratio, Min
Compression Ratio, Max
Control Feedthrough
0.5
0.5
180
75
ZIN
ZOUT
Input Voltage Range
Output Voltage Range
Gain Bandwidth Product
SSM2165-1
SSM2165-2
POWER SUPPLY
Supply Voltage Range
Supply Current
Quiescent Output Voltage Level
Power Supply Rejection Ratio2
COMP
VS
ISY
1
1.4
kΩ
Ω
kΩ
nF
V rms
V rms
300
100
kHz
kHz
40
dB
18
8
dB
dB
40
100
1:1
15:1
±5
mV rms
mV rms
5
2
15:1 Compression
4.5
7.5
2.2
50
PSRR
%
%
mV
5.5
10
V
mA
V
dB
NOTES
1
0 dBu = 0.775 V rms.
2
Referred to input.
Specifications subject to change without notice.
–2–
REV. A
SSM2165
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10 V
Audio Input Voltage . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ ) . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
GND 1
VCAIN 2
8 V+
SSM2165
7 OUTPUT
TOP VIEW 6 COMP RATIO SET
(Not to Scale)
5 AVG CAP
AUDIO +IN 4
BUFOUT 3
ESD RATINGS
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . . 2.0 kV
THERMAL CHARACTERISTICS
Thermal Resistance
8-Lead Plastic DIP
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43°C/W
8-Lead SOIC
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43°C/W
PIN FUNCTION DESCRIPTIONS
Pin #
Mnemonic
1
2
GND
VCAIN
3
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Options
SSM2165-1P
SSM2165-2P
SSM2165-1S
SSM2165-2S
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Plastic DIP
Plastic DIP
Narrow SOIC
Narrow SOIC
N-8
N-8
SO-8
SO-8
4
5
6
7
8
Ground
VCA Input Pin. A typical
connection is a 1 µF–10 µF
capacitor from the buffer output
pin (Pin 3) to this pin.
Input Buffer Amplifier Output
BUFOUT
Pin. Must not be loaded by
capacitance to ground.
AUDIO +IN
Input Audio Signal. The input
signal should be ac-coupled
(0.1 µF typical) into this pin.
AVG CAP
Detector Averaging Capacitor.
A capacitor, 2.2 µF–22 µF, to
ground from this pin is the
averaging capacitor for the
detector circuit.
COMP RATIO SET Compression Ratio Set Pin. A
resistor to ground from this pin
sets the compression ratio as
shown in Figure 1.
OUTPUT
Output Signal.
V+
Positive Supply, +5 V Nominal.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2165 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
Function
WARNING!
ESD SENSITIVE DEVICE
SSM2165 –Typical Performance Characteristics
260
TA = +258C
VS = +5V
RL = 100kV
240
220
5mV
200
180
1s
100
RCOMP – kV
90
160
140
120
100
SSM2165–1
80
10
0%
60
SSM2165–2
40
TA = +258 C
COMPRESSION RATIO = 15:1
NOISE BW = 20kHz
20
0
1:1
2:1
5:1
COMPRESSION RATIO
10:1
15:1
Figure 5. Wideband Output Noise
Figure 2. Compression Ratio vs. RCOMP
70
5
COMP RATIO = 15:1
RCOMP = 0
VIN = 40mV rms
60
50
40
1
GAIN – dB
THD+N – %
TA = +258C
COMP RATIO = 1:1
RL = 100kV/10kV
VS = +5V
SSM2165–1
30
20
10
G = 18dB
G = 8dB
0
SSM2165–2
0.1
–10
0.050
0.01
0.1
INPUT – V rms
–20
1k
1
1M
–30
TA = +258C
VS = +5V
COMP RATIO = 1:1
V I N = –20dBu (–1)
V I N = –30dBu (–2)
RL = 100kV
–40
PSRR – dB
THD+N – %
1
100k
FREQUENCY – Hz
Figure 6. GBW Curves vs. VCA Gain
Figure 3. THD + N (%) vs. Input (V rms)
5
10k
V+ = 561V p-p
–50
SSM2165–1
–60
0.1
SSM2165–2
0.050
20
100
1k
FREQUENCY – Hz
10k
–70
20
30k
100
1k
FREQUENCY – Hz
10k
30k
Figure 7. PSRR vs. Frequency, Referred to Input
Figure 4. THD + N (%) vs. Frequency (Hz)
–4–
REV. A
SSM2165
20mV
200mV
100
90
100
90
TA = +258C
CAVG = 2.2mF
RL = 10kV
COMP RATIO = 1:1
VIN = 12.5mV (–1)
VIN = 40mV (–2)
10
0%
10
0%
10ms
Figure 8. Small Signal Transient Response
TA = +258C
CAVG = 2.2mF
RL = 10kV
COMP RATIO = 1:1
VIN = 125mV (–1)
VIN = 400mV (–2)
10ms
Figure 9. Large Signal Transient Response
APPLICATIONS INFORMATION
THEORY OF OPERATION
The SSM2165 is a complete microphone signal conditioning
system in a single integrated circuit. Designed primarily for
voiceband applications, this integrated circuit provides amplification, rms detection, limiting, variable compression, and downward expansion. The internal rms detector has a time constant
set by an external capacitor. An integral voltage-controlled
amplifier (VCA) provides up to 40 dB of gain in the signal path
with approximately 30 kHz bandwidth. The device operates on
a single +5 V supply, accepts input signals up to 1 V1, and produces output signal levels at limiting of 320 mV and 250 mV for
the SSM2165-1 and SSM2165-2 respectively, into loads > 5 kΩ.
Figure 10 illustrates the general transfer characteristic for the
SSM2165 where the output level in dBu is plotted as a function
of the input level in dBu (0 dBu = 0.775 V rms). For input
signals in the range of VDE (Downward Expansion) to VRP
(Rotation Point) an “r” dB change in the input level causes a
1 dB change in the output level. Here, “r” is defined as the
“compression ratio.” The compression ratio may be varied
from 1:1 (no compression) to over 15:1 via a single resistor,
RCOMP. Input signals above VRP are compressed with a fixed
compression ratio of approximately 10:1. This region of operation is the “limiting region.” Varying the compression ratio has
no effect on the limiting region. The breakpoint between the
compression region and the limiting region is referred to as the
“limiting threshold” or “rotation point,” and is different for the
SSM2165-1 and SSM2165-2, see Table I.
The SSM2165 contains an input buffer and automatic gain
control (AGC) circuit for audio and voice band signals. Circuit
operation is optimized by providing user-adjustable compression
ratio and time constant. A downward expansion (noise gating)
feature reduces background and circuit noise below 500 µV.
The rotation point determines the output signal levels before
limiting (referred to the input), and is 40 mV for the SSM2165-1
and 100 mV for the SSM2165-2.
LIMITING
REGION
OUTPUT – dB
LIMITING
THRESHOLD
(ROTATION POINT)
DOWNWARD COMPRESSION
EXPANSION REGION
THRESHOLD
1
(NOISE GATE)
r
VCA GAIN
Vrp
Figure 10. General Input/Output Characteristics of the
SSM2165
Output*
–1
–2
40 mV (–25.7 dBu)
100 mV (–17.7 dBu)
18 dB
8 dB
320 mV (–6 dBu)
250 mV (–8 dBu)
Input signals below VDE are downward expanded at a ratio of
approximately 1:3. As a result, the gain of the system is small
for very small input signal levels below VDE, even though it may
be quite large for input signals above VDE. The downward
expansion threshold, VDE, is fixed at 500 µV (–64 dBu) for both
dash versions.
All signals are in rms volts or dBu (0 dBu = 0.775 V rms).
REV. A
Gain
When the compression is set to 2:1, a –2 dB change of the
input signal level in the compression region causes –1 dB
change of the output level. Likewise, at 10:1 compression, a
–10 dB change of the input signal level in the compression
region causes a –1 dB change in the output level. The gain of
the system with an input signal level of VRP is fixed regardless of
the compression ratio, and is different for the SSM2165-1 and
SSM2165-2 (see Figures 1a and 1b). The “nominal gain” of
the system is 18 dB for the SSM2165-1, and 8 dB for the
SSM2165-2. System gain is measured at VRP and is (VOUT – VIN)
in dB.
1
1
Rotation Point
The term “rotation point” derives from the observation that the
straight line in the compression region “rotates” about this point
on the input/output characteristic as the compression ratio is
changed.
1
VDE
SSM2165
*At limiting.
DOWNWARD
EXPANSION
REGION
INPUT – dB
Table I. Characteristics vs. Dash Number
–5–
SSM2165
operation of the level detector down to 10 Hz, the value of the
capacitor should be around 22 µF. Some experimentation with
larger values for the AVG CAP may be necessary to reduce the
effects of excessive low frequency ambient background noise.
The value of the averaging capacitor affects sound quality: too
small a value for this capacitor may cause a “pumping effect”
for some signals, while too large a value can result in slow response times to signal dynamics. Electrolytic capacitors are
recommended here for lowest cost.
The SSM2165 Signal Path
Figure 11 illustrates the block diagram of the SSM2165. The
audio input signal is processed by the unity gain input buffer
and then by the VCA. The buffer presents an input impedance
of approximately 180 kΩ to the source. A dc voltage of approximately 1.5 V is present at AUDIO +IN (Pin 4), requiring the
use of a blocking capacitor (C1) for ground-referenced sources.
A 0.1 µF capacitor is a good choice for most audio applications.
The buffer is designed to drive only the low impedance input of
the VCA, and must not be loaded by capacitance to ground.
The VCA is a low distortion, variable-gain amplifier whose gain
is set by the internal control circuitry. The input to the VCA is
a virtual ground in series with 500 Ω. An external blocking
capacitor (C2) must be used between the buffer’s output and
the VCA input. The desired low frequency response and the
total of 1 kΩ impedance between amplifiers determines the
value of this capacitor. For music applications, 10 µF will give
high pass fC = 16 Hz. For voice/communications applications,
1 µF will give fC = 160 Hz. An aluminum electrolytic capacitor
is an economical choice. The VCA amplifies the input signal
current flowing through C6 and converts this current to a
voltage at the SSM2165’s output (Pin 7). The net gain from
input to output can be as high as 40 dB for high compression
ratios and depending on the gain set by the control circuitry.
The output impedance of the SSM2165 is typically less than
75 Ω, and the external load on Pin 7 should be >5 kΩ. The
nominal output dc voltage of the device is approximately 2.2 V.
Use a dc blocking capacitor for grounded loads.
AUDIO
IN+
C1
0.1mF
V+
C2
10mF
+
V+ BUFOUT
500V
500V
The rms detector filter time constant is approximately given by
10 × CAVG milliseconds where CAVG is in µF. This time constant controls both the steady-state averaging in the rms detector as well as the release time for compression, that is, the time
it takes for the system gain to react when a large input is followed by a small signal. The attack time, the time it takes for
the gain to be reduced when a small signal is followed by a large
signal, is mainly controlled by internal circuitry that speeds up
the attack for large level changes, and controlled partly by the
AVG CAP value. This limits overload time to under 1 ms in
most cases.
The performance of the rms level detector is illustrated in Figure 12 for CAVG = 2.2 µF and Figure 13 for CAVG = 22 µF. In
each of these photographs, the input signal to the SSM2165
(not shown) is a series of tone bursts in 6 successive 10 dB
steps. The tone bursts range from –66 dBu (0.5 mV rms) to
–6 dBu (0.5 V rms). As illustrated in the photographs, the
attack time of the rms level detector is dependent only on CAVG,
but the release times are linear ramps whose decay times are
dependent on both for CAVG and the input signal step size. The
rate of release is approximately 240 dB/s for a CAVG = 2.2 µF,
and 12 dB/s for a CAVG of 22 µF.
VCAIN
+1
VOUT
VCA
100mV
BUFFER
100
6dBV
90
LEVEL
DETECTOR
CONTROL
SSM2165
GND
AVG CAP
C3
22mF
+
R1
25kV
66dBV
COMPRESSION
RATIO SET
10
85dBV
0%
100ms
Figure 11. Functional Block Diagram and Typical Voice
Application
Figure 12. RMS Level Detector Performance with
CAVG = 2.2 µ F
The bandwidth of the SSM2165 is quite wide at all gain settings. The upper –3 dB point is approximately 300 kHz. The
GBW plots are shown in Figure 6. While the noise of the input
buffer is fixed, the input referred noise of the VCA is a function
of gain. The VCA input noise is designed to be a minimum
when the gain is at a maximum, thereby optimizing the usable
dynamic range of the part. A photograph of the SSM2165’s
wideband peak-to-peak output noise is illustrated in Figure 5.
100mV
100
90
The Level Detector
1s
6dBV
66dBV
The SSM2165 incorporates a full-wave rectifier and a patentpending, true rms level detector circuit whose averaging time
constant is set by an external capacitor connected to the AVG
CAP pin (Pin 5). Capacitor values from 18 µF to 22 µF have
been found to be more appropriate in voiceband applications,
where capacitors on the low end of the range seem more appropriate for music program material. For optimal low frequency
10
0%
85dBV
Figure 13. RMS Level Detector Performance with
CAVG = 22 µ F
–6–
REV. A
SSM2165
Control Circuitry
Downward Expansion Threshold
The output of the rms level detector is a signal proportional to
the log of the true rms value of the buffer output with an added
dc offset. The control circuitry subtracts a dc voltage from this
signal, scales it, and sends the result to the VCA to control the
gain. The VCA’s gain control is logarithmic: a linear change in
control signal causes a dB change in gain. It is this control law
that allows linear processing of the log rms signal to provide the
flat compression characteristic on the input/output characteristic shown in Figure 10.
The downward expansion threshold, or noise gate, is determined by a reference voltage internal to the control circuitry.
The noise gate threshold is 500 µV for both versions of the
SSM2165. Users requiring some other noise gate should consider using the SSM2166. High volume users may wish to consider a custom version of the SSM2165 with other noise gate
thresholds or rotation points.
Power-On/Power-Off Settling Time
Cycling the power supply to the SSM2165 will result in quick
settling times: the off-on settling time of the SSM2165 is less
than 200 ms, while the on-off settling time is less than 1 ms.
Note that transients may appear at the output of the device
during power up and power down. A clickless mute function is
available on the SSM2166 only.
Compression Ratio
Changing the scaling of the control signal fed to the VCA
causes a change in the circuit’s compression ratio, “r.” This
effect is shown in Figure 14. The compression ratio can be set
by connecting a resistor between the COMP RATIO pin (Pin
6) and GND. Lowering RCOMP gives smaller compression
ratios as indicated in Figure 2, with values of about 5 kΩ or less
resulting in a compression ratio of 1:1. AGC performance is
achieved with compression ratios between 2:1 and 15:1, and is
dependent on the application. A 200 kΩ potentiometer may be
used to allow this parameter to be adjusted.
PC Board Layout Considerations
Since the SSM2165 is capable of wide bandwidth operation at
high gain, special care must be exercised in the layout of the PC
board which contains the IC and its associated components.
The following applications hints should be considered and/or
followed:
1. In some high system gain applications, the shielding of input
wires to minimize possible feedback from the output of the
SSM2165 back to the input circuit may be necessary.
15:1
5:1
OUTPUT – dB
2. A single-point (“star”) ground implementation is recommended in addition to maintaining short lead lengths and
PC board runs. In systems where an analog ground and a
digital ground are available, the SSM2165 and its surrounding circuitry should be connected to the analog ground.
Wire-wrap board connections and grounding implementations are to be explicitly avoided.
VCA GAIN
2:1
1:1
3. The internal buffer of the SSM2165 was designed to drive
only the input of the internal VCA and its own feedback
network. Stray capacitive loading to ground from either Pin
3 or Pin 2 in excess of 5 pF to 10 pF can cause excessive
phase shift and can lead to circuit instability.
1
1
VDE
INPUT – dB
VRP
4. When using high impedance sources, it can be advantageous
to shunt the source with a capacitor to ground at the input
pin of the IC (Pin 4) to lower the source impedance at high
frequencies, as shown in Figure 15. A capacitor with a value
of 1000 pF is a good starting value and sets a low pass corner
at 31 kHz for 5 kΩ sources.
Figure 14. Effect of Varying the Compression Ratio
Rotation Point
An internal dc reference voltage in the control circuitry sets the
rotation point. The rotation point determines the output level
above which limiting occurs. That is, in the limiting region, a
10 dB change of input results in a 1 dB change of output. The
rotation point is set to 40 mV (–26 dBu) for the SSM2165-1
and 100 mV (–18 dBu) for the SSM2165-2. In the SSM2165,
limiting is compression at a fixed compression ratio of approximately 15:1. The fixed gain in the VCA is 18 dB for the
SSM2165-1 and 8 dB for the SSM2165-2. The output signals
at limiting are, therefore, 320 mV and 250 mV respectively.
These are summarized in Table I.
C1
0.1mF
AUDIO IN
(RS > 5kV)
Maximum Output
Since limiting occurs for signals larger than the rotation point
(VIN > VRP), the rotation point effectively sets the maximum
output signal level. The application will determine which version of the SSM2165 should be selected. The output level
should match the maximum input allowed by the following
stage. Occasional larger signal transients will then be attenuated
by the action of the limiter.
REV. A
–7–
4
+IN
CX
1000pF
SSM2165
NOTE: ADDITIONAL CIRCUIT DETAILS
OMITTED FOR CLARITY.
Figure 15. Circuit Configuration for Use with High
Impedance Signal Sources
SSM2165
C2
10mF
+
+5V
GENERATOR
AND AC
VOLTMETER
BUFOUT
V+
C1
0.1mF
VCAIN
+1
AC VOLTMETER
AND OSCILLOSCOPE
VCA
BUFFER
LEVEL
DETECTOR
+2V
CONTROL
HEADPHONES
SSM2165-1
2kV
+
MICROPHONE
(ELECTRET)
GND
AVG CAP
C3 +
22mF
1:1
R1 – COMPRESSION
15:1 RATIO SET
200kV
CW
Figure 16. Electret Microphone Preamp Example
Compression Adjustment—A Practical Example
STEP 1. Initialize Potentiometer
To illustrate how to set the compression ratio of the SSM2165,
we will take a practical example. The SSM2165 will be used
interface an electret-type microphone to a post-amplifier, as
shown in Figure 16. The signal from the microphone was measured under actual conditions to vary from 2 mV to 30 mV.
The post-amplifier requires no more than 350 mV at its input.
We will therefore choose the SSM2165-1, whose “rotation”
point is 40 mV and whose VCA fixed gain is 18 dB (×8), thus
giving 320 mV at limiting. From prior listening experience, we
will use a 2:1 compression ratio. The noise gate threshold of the
SSM2165-1 will operate when the input signal falls below 500 µV.
These objectives are summarized in Table II. The transfer characteristic we will implement is illustrated in Figure 18.
With power off, preset R1—Compression Ratio potentiometer
to zero ohms.
STEP 2. Check Setup
With power on, adjust the generator for an input level of
50 mV (–24 dBu), 1 kHz. The output meter should indicate
approximately 350 mV (–6.9 dBu). If not, check your setup.
STEP 3. Find the Rotation Point
Set the input level to 50 mV (–24 dBu), and observe the output
on the oscilloscope. The output will be in the limiting range of
operation. Slowly reduce the input signal level until the output
level just begins to stop limiting and follows the input down.
Increase the input so that the output is 320 mV (–7.7 dBu). You
have located the knee of the rotation point.
Table II. Objective Specification of Example
Input Range
Output Range
Limiting Level
Compression
Gain
Noise Gate
STEP 4. Adjust the Compression Ratio
With the input set as in Step 3, note the exact value of the input
signal level just below the knee (around 40 mV (–26 dBu)).
Next, reduce the input to 1/4 the value noted, (around 10 mV
(–38 dBu)), for a change of –12 dB. Next, increase the RCOMP
potentiometer resistance so the output is 160 mV (–13.7 dBu)
for an output change of –6 dB. You have now set the compression, which is the ratio of input change to output change, in dB,
to 2:1.
2 mV–30 mV
To 350 mV
320 mV
2:1
18 dB
500 µV
Test Equipment Setup
STEP 5. Confirm the Noise Gate Threshold
The recommended equipment and configuration is shown in
Figure 17. A low noise audio generator with a smooth output
adjustment range of 100 µV to 25 mV is a suitable signal
source. The output voltmeter should go up to 2 volts. The
oscilloscope is used to verify that the output is sinusoidal, that
no clipping is occurring in the buffer, and to observe the limiting and noise gating “knees.”
Set the input to 1 mV, and observe the output on the oscilloscope. A 20 dB pad between generator and input may facilitate
this measurement. Reduce the input gradually until the output
falls off more rapidly. This point is the noise gate threshold, and
should be approximately 500 µV (–64 dBu). The noise gate
threshold on the SSM2165 is fixed at 500 µV, a practical value
for many microphones. Should you require a different noise gate
threshold, consider using the SSM2166.
Breadboard Considerations
When building your breadboard, keep the leads to Pins 2 and 3
as short as possible. Use a central analog ground and decouple
power supply connections adequately.
SIGNAL
GENERATOR
AC
VOLTMETER
SSM2165-1
STEP 6. Listen
At this time, you may replace the signal generator with a
properly powered electret microphone and listen to the results
through a set of headphones. The microphone’s internal FET
usually requires around +2 V through a 2 kΩ resistor; this varies
with the manufacturer. Experiment with the compression ratio
value and averaging capacitor size. More compression will keep
the output steady over a wider range of microphone-to-source
distance. Varying the averaging capacitor, CAVG, changes the
AC
VOLTMETER
OSCILLOSCOPE
Figure 17. Test Equipment Setup
–8–
REV. A
SSM2165
SUMMARY
rms detector averaging time, and the decay time of the gate.
Both compression ratio and decay time are usually determined
by critical listening to the intended audio input.
We have implemented the transfer characteristic of Figure 18.
For inputs below the 500 µV noise gate threshold, circuit and
background noise will be downward expanded (gain-reduced) at
a ratio of approximately 1:3. That is, a –1 dB change in the
noise will result in –3 dB decrease at the output. Above threshold, the signal will increase at a rate of 1 dB for each 2 dB input
increase, until the rotation point is reached at an input of
approximately 40 mV. In the limiting region, the compression
ratio increases to approximately 15:1. That is, a 15 dB increase
in input will produce a 1 dB increase at the output, so there will
be little further increase for higher level inputs.
STEP 7. Record Values
OUTPUT – mV
With the power removed from the test fixture, measure and
record the values of the RCOMP and CAVG.
300
COMPRESSION
REGION
LIMITING REGION
Other Versions
45
The SSM2165 is an 8-lead version of the 14-lead SSM2166
which is recommended for applications requiring more versatility. The SSM2166 allows selection of noise gate threshold and
rotation point, and allows the buffer to provide up to 20 dB of
gain. Power-down and mute functions are also built in. Customized versions of the SSM2165 are available for large volume
users. The wide dynamic range of the SSM2165 makes it useful
in many applications other than microphone signal conditioning
such as a sustain generator for guitars. For further information,
contact your Analog Devices representative.
NOISE GATING REGION
0.5
2
30 40
INPUT – mV
Figure 18. Transfer Characteristic
REV. A
–9–
SSM2165
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2178a–0–6/99
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.210
(5.33)
MAX
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381)
0.008 (0.204)
8-Lead Narrow-Body SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
3 458
0.0099 (0.25)
0.0500 (1.27)
BSC
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
88
0.0500 (1.27)
0.0098 (0.25) 08
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
PRINTED IN U.S.A.
0.0098 (0.25)
0.0040 (0.10)
–10–
REV. A
TL071
TL071A - TL071B
LOW NOISE J-FET SINGLE OPERATIONAL AMPLIFIERS
■ WIDE COMMON-MODE (UP TO VCC+) AND
DIFFERENTIAL VOLTAGE RANGE
■ LOW INPUT BIAS AND OFFSET CURRENT
■ LOW NOISE en = 15nV/√Hz (typ)
■ OUTPUT SHORT-CIRCUIT PROTECTION
N
DIP8
(Plastic Package)
■ HIGH INPUT IMPEDANCE J–FET INPUT
STAGE
■ LOW HARMONIC DISTORTION : 0.01% (typ)
■ INTERNAL FREQUENCY COMPENSATION
■ LATCH UP FREE OPERATION
■ HIGH SLEW RATE : 16V/µs (typ)
D
SO8
(Plastic Micropackage)
DESCRIPTION
ORDER CODE
Package
The TL071, TL071A and TL071B are high speed
J–FET input single operational amplifiers incorporating well matched, high voltage J–FET and bipolar transistors in a monolithic integrated circuit.
Part Number
Temperature Range
TL071M/AM/BM
-55°C, +125°C
TL071I/AI/BI
-40°C, +105°C
TL071C/AC/BC
0°C, +70°C
Example : TL071CN
The devices feature high slew rates, low input bias
and offset currents, and low offset voltage temperature coefficient.
N
D
•
•
•
•
•
•
N = Dual in Line Package (DIP)
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
PIN CONNECTIONS (top view)
March 2001
1
8
2
7
3
6
4
5
12345678-
Offset null 1
Inverting input
Non-inverting input
VCCOffset null 2
Output
VCC+
N.C.
1/10
TL071 - TL071A - TL071B
SCHEMATIC DIAGRAM
V CC
Non-inverting
input
Inverting
input
100 Ω
200 Ω
Output
100 Ω
30k
8.2k
1.3k
1.3k
35k
35k
100 Ω
V CC
Offset Null1
Offset Null2
INPUT OFFSET VOLTAGE NULL CIRCUIT
TL071
N2
N1
100k Ω
V CC
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Vi
Parameter
Supply voltage - note
Input Voltage - note
TL071M, AM, BM
1)
2)
Vid
Differential Input Voltage - note
Ptot
Power Dissipation
3)
Output Short-circuit Duration - note
4)
Toper
Operating Free-air Temperature Range
Tstg
Storage Temperature Range
1.
2.
3.
4.
2/10
TL071I, AI, BI
TL071C, AC, BC
Unit
±18
V
±15
V
±30
V
680
mW
Infinite
-55 to +125
-40 to +105
-65 to +150
0 to +70
°C
°C
All voltage values, except differential
voltage, are with respect to the zero reference level (ground) of the supply voltages where the zero reference
level is the midpoint between VCC + and VCC -.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less.
Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating
is not exceeded
TL071 - TL071A - TL071B
ELECTRICAL CHARACTERISTICS
VCC = ±15V, Tamb = +25°C (unless otherwise specified)
Symbol
TL071I,M,AC,AI,AM,
BC,BI,BM
Parameter
Min.
Input Offset Voltage (Rs = 50Ω)
Tamb = +25°C
Vio
DVio
Typ.
Max.
3
3
1
10
6
3
13
7
5
TL071C
Unit
Min.
Typ.
Max.
3
10
mV
TL071
TL071A
TL071B
TL071
TL071A
TL071B
Tmin ≤ Tamb ≤ Tmax
13
µV/°C
Input Offset Voltage Drift
10
10
Iio
Input Offset Current
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
5
100
4
5
100
10
pA
nA
Iib
Input Bias Current -note 1)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
20
200
20
20
200
20
pA
nA
Avd
Large Signal Voltage Gain (RL = 2kΩ, Vo = ±10V)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
50
25
200
25
15
200
SVR
Supply Voltage Rejection Ratio (RS = 50Ω)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
80
80
86
70
70
86
ICC
Supply Current, no load
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
Vicm
Input Common Mode Voltage Range
CMR
Ios
SR
dB
mA
1.4
2.5
2.5
1.4
±11
+15
-12
±11
+15
-12
Common Mode Rejection Ratio (RS = 50Ω)
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
80
80
86
70
70
86
Output Short-circuit Current
Tamb = +25°C
Tmin ≤ Tamb ≤ Tmax
10
10
40
10
10
40
RL = 2kΩ
RL = 10kΩ
RL = 2kΩ
RL = 10kΩ
10
12
10
12
12
13.5
10
12
10
12
12
13.5
Slew Rate (Tamb = +25°C)
Vin = 10V, RL = 2kΩ, CL = 100pF, unity gain
8
16
8
16
Output Voltage Swing
Tamb = +25°C
±Vopp
V/mV
Tmin ≤ Tamb ≤ Tmax
mA
60
60
60
60
V
V/µs
µs
Rise Time (Tamb = +25°C)
Vin = 20mV, RL = 2kΩ, CL = 100pF, unity gain
0.1
0.1
Kov
Overshoot (Tamb = +25°C)
Vin = 20mV, RL = 2kΩ, CL = 100pF, unity gain
10
10
GBP
Gain Bandwidth Product (Tamb = +25°C)
Vin = 10mV, RL = 2kΩ, CL = 100pF, f= 100kHz
Input Resistance
V
dB
tr
Ri
2.5
2.5
%
MHz
2.5
4
1012
2.5
4
1012
Ω
3/10
TL071 - TL071A - TL071B
Symbol
Parameter
TL071I,M,AC,AI,AM,
BC,BI,BM
Min.
THD
en
∅m
1.
4/10
Total Harmonic Distortion (Tamb = +25°C,
f= 1kHz, RL = 2kΩ,CL = 100pF, Av = 20dB,
Vo = 2Vpp)
Typ.
Max.
TL071C
Unit
Min.
Typ.
Max.
%
0.01
0.01
Equivalent Input Noise Voltage
RS = 100Ω, f = 1KHz
15
15
nV
-----------Hz
Phase Margin
45
45
degrees
The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature.
TL071 - TL071A - TL071B
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus FREQUENCY
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus FREQUENCY
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus FREE AIR TEMP.
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus LOAD RESISTANCE
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus SUPPLY VOLTAGE
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE (V)
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE versus FREQUENCY
30
25
RL = 10 kΩ
Tamb = +25˚C
20
15
10
5
0
2
4
6
8
10
12
SUPPLY VOLTAGE ( V)
14
16
5/10
TL071 - TL071A - TL071B
LARGE SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION versus FREE AIR TEMP.
INPUT BIAS CURRENT versus FREE AIR
TEMPERATURE
100
1000
15V
10
DIFFERENTIAL VOLTAGE
AMPLIFICATION (V/V)
INPUT BIAS CURRENT (nA)
V CC =
1
0.1
0.01
-50
400
200
100
40
20
10
4
2
1
-25
0
25
50
75
100
V CC = 15V
V O = 10V
125
R L = 2k Ω
-75
-50
-25
DIFFERENTIAL
VOLTAGE
AMPLIFICATION
(left scale)
180
10
90
R = 2kW
L
C L = 100pF
V CC = 15V
T amb = +125°C
1
100
1K
10K
0
100K
1M
10M
250
225
200
175
150
125
100
75
50
25
0
0
25
50
SUPPLY CURRENT (mA)
TEMPERATURE (˚C)
6/10
-25
0
25
50
75
100
125
75
100
COMMON MODE REJECTION RATIO versus
FREE AIR TEMPERATURE
125
COMMON MODE MODE REJECTION
RATIO (dB)
-25
-50
89
V CC = 15V
No signal
No load
-50
125
100
TEMPERATURE (˚C)
SUPPLY CURRENT PER AMPLIFIER versus
FREE AIR TEMPERATURE
-75
75
V CC = 15V
No signal
No load
-75
FREQUENCY (Hz)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
50
TOTAL POWER DISSIPATION versus FREE AIR
TEMPERATURE
TOTAL POWER DISSIPATION (mW)
DIFFERENTIAL VOLTAGE
AMPLIFICATION (V/V)
LARGE SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT versus
FREQUENCY
PHASE SHIFT
(right scale)
25
TEMPERATURE (˚C)
TEMPERATURE (˚C)
100
0
88
R L = 10 kΩ
VC C = 15V
87
86
85
84
83
-75
-50
-25
0
25
50
TEMPERATURE (˚C)
75
100
125
TL071 - TL071A - TL071B
OUTPUT VOLTAGE versus ELAPSED TIME
28
6
4
24
OUTPUT
OUTPUT VOLTAGE (mV)
INPUT AND OUTPUT VOLTAGES
(V)
VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE
INPUT
2
0
VCC=
-2
15V
R L = 2 kW
C L= 100pF
Tamb = +25°C
-4
-6
0
0.5
1
1.5
2
2.5
3
OVERSHOOT
20
90%
16
12
8
V
4
0
tr
-4
3.5
0
0.1
0.2
TIME (m s)
= 15V
0.3
0.4
0.5
0.6
0.7
TIME ( µs)
EQUIVALENT INPUT NOISE VOLTAGE versus
FREQUENCY
TOTAL HARMONIC DISTORTION versus
FREQUENCY
1
VCC = 15V
A V = 10
R S = 100 Ω
T amb = +25˚C
60
50
40
30
20
10
0
10
40
100
400
1k
4k
FREQUENCY (Hz)
10k
40k 100k
TOTAL HARMONIC DISTORTION
(%)
70
EQUIVALENT INPUT NOISE
VOLTAGE (nV/VHz)
CC
R L = 2k Ω
Tamb = +25˚C
10%
V VCC = = 15V
15V
CC
A AV V= =1 1
V VO O(rms)
= =6V6V
(rms)
0.4
0.1
0.04
T amb
T amb= =+25˚C
+25˚C
0.01
0.004
0.001
100
400
1k
4k
10k
40k
100k
FREQUENCY (Hz)
7/10
TL071 - TL071A - TL071B
PARAMETER MEASUREMENT INFORMATION
Figure 1 : Voltage Follower
Figure 2 : Gain-of-10 Inverting Amplifier
10k Ω
1k Ω
-
-
eI
-
TL071
eI
CL = 100pF
eo
eo
TL071
RL = 2kΩ
RL
TYPICAL APPLICATIONS
(0.5Hz) SQUARE WAVE OSCILLATOR
R F = 1 0 0k Ω
3.3k Ω
+15V
TL0 71
1k Ω
-15V
C F= 3.3 µF
3.3k Ω
f osc=
9.1k Ω
1
2 x R F CF
HIGH Q NOTCH FILTER
TL071
R1
R2
fo =
1
= 1kHz
2 x R F CF
C3
R3
C1 = C2 =
C3
= 100pF
2
R1 = R2 = 2R3 = 1.5M
C1
8/10
C2
Ω
CL = 100pF
TL071 - TL071A - TL071B
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
Millimeters
Inches
Dim.
Min.
A
a1
B
b
b1
D
E
e
e3
e4
F
i
L
Z
Typ.
Max.
Min.
3.32
0.51
1.15
0.356
0.204
0.020
0.045
0.014
0.008
0.065
0.022
0.012
0.430
0.384
0.313
2.54
7.62
7.62
3.18
Max.
0.131
1.65
0.55
0.304
10.92
9.75
7.95
Typ.
0.100
0.300
0.300
6.6
5.08
3.81
1.52
0.125
0260
0.200
0.150
0.060
9/10
TL071 - TL071A - TL071B
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC MICROPACKAGE (SO)
Millimeters
Inches
Dim.
Min.
A
a1
a2
a3
b
b1
C
c1
D
E
e
e3
F
L
M
S
Typ.
Max.
Min.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
0.1
0.65
0.35
0.19
0.25
Typ.
Max.
0.026
0.014
0.007
0.010
0.069
0.010
0.065
0.033
0.019
0.010
0.020
0.189
0.228
0.197
0.244
0.004
45° (typ.)
4.8
5.8
5.0
6.2
1.27
3.81
3.8
0.4
0.050
0.150
4.0
1.27
0.6
0.150
0.016
0.157
0.050
0.024
8° (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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10/10
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