M29F040B 4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

M29F040B 4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

M29F040B

4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

PRELIMINARY DATA

SINGLE 5V

±

10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 45ns

PROGRAMMING TIME

– 8

µ s per Byte typical

8 UNIFORM 64 Kbytes MEMORY BLOCKS

PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

LOW POWER CONSUMPTION

– Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per

BLOCK

20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: E2h

PLCC32 (K)

19

32

1

PDIP32 (P)

Figure 1. Logic Diagram

VCC

TSOP32 (N)

8 x 20mm

8

A0-A18 DQ0-DQ7

W

E

G

M29F040B

VSS

AI02900

September 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/21

This datasheet has been downloaded from http://www.digchip.com

at this page

M29F040B

Figure 2A. PLCC Connections

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

9

1 32

M29F040B 25

A14

A13

A8

A9

A11

G

A10

E

DQ7

17

AI02901

Figure 2B. TSOP Connections

A11

A9

A8

A13

A14

A17

W

VCC

A18

A16

A15

A12

A7

A6

A5

A4

8

9

1

16

M29F040B

32

25

24

17

AI02902

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

A0

A1

A2

A3

Figure 2C. PDIP Connections

A18

A16

A15

A12

A0

DQ0

DQ1

DQ2

VSS

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

12

13

14

15

16

5

6

28

27

7

8

26

9

10

M29F040B

25

24

23

11 22

21

20

19

18

17

32

31

30

29

AI02910

VCC

W

A17

A14

A13

A8

A9

A11

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

2/21

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7

E

G

W

V

CC

V

SS

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Supply Voltage

Ground

SUMMARY DESCRIPTION

The M29F040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The

M29F040B is fully backward compatible with the

M29F040.

The memory is divided into blocks that can be erased independently so it is possible to preserve

M29F040B

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter

T

A

T

BIAS

T

STG

Ambient Operating Temperature (Temperature Range Option 1)

Ambient Operating Temperature (Temperature Range Option 6)

Ambient Operating Temperature (Temperature Range Option 3)

Temperature Under Bias

Storage Temperature

Value

0 to 70

–40 to 85

–40 to 125

–50 to 125

–65 to 150

Unit

°

C

°

C

°

C

°

C

°

C

V

IO

(2)

Input or Output Voltage –0.6 to 6 V

V

CC

V

ID

Supply Voltage

Identification Voltage

–0.6 to 6

–0.6 to 13.5

V

V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

valid data while old data is erased. Each block can be protected independently to prevent accidental

Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.

They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP32 (8 x 20mm),

PLCC32 and PDIP32 packages. Access times of

45ns, 55ns, 70ns and 90ns are available. The memory is supplied with all the bits erased (set to

‘1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus

Write operations they represent the commands sent to the Command Interface of the internal state machine.

Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is

High, V

IH

, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

V

CC

Supply Voltage. The V

CC

Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the Lockout Voltage,

V

LKO

. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/

Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1

µ

F capacitor should be connected between the V

CC

Supply Voltage pin and the V

SS

Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

CC4

.

V

SS

Ground. The V

SS

Ground is the reference for all voltage measurements.

3/21

M29F040B

Table 3. Block Addresses

Size (Kbytes)

64

64

64

64

64

64

64

64

Address Range

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See

Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs, applying a Low signal, V

IL

, to Chip Enable and Output Enable and keeping Write Enable

High, V

IH

. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V

IH

, during the whole Bus

Write operation. See Figures 8 and 9, Write AC

Waveforms, and Tables 12 and 13, Write AC

Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is

High, V

IH

.

Standby. When Chip Enable is High, V

IH

, the

Data Inputs/Outputs pins are placed in the highimpedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at V

IH the Supply Current is reduced to the TTL Standby Supply Current, I

CC2

.

To further reduce the Supply Current to the CMOS

Standby Supply Current, I

CC3

, Chip Enable should be held within V

CC

±

0.2V. For Standby current levels see Table 10, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply

Current, I

CC4

, for Program or Erase operations until the operation completes.

4/21

M29F040B

Table 4. Bus Operations

Operation E

Bus Read

Bus Write

Output Disable

Standby

Read Manufacturer

Code

V

IL

V

IL

X

V

IH

V

IL

Read Device Code

Note: X = V

IL or V

IH

.

V

IL

G

V

IL

V

IH

V

IH

X

V

IL

V

IL

Automatic Standby. If CMOS levels (V

CC

±

0.2V) are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is reduced to the CMOS Standby Supply Current, I

CC3

.

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.

They require V

ID to be applied to some pins.

W

V

IH

V

IL

V

IH

X

V

IH

V

IH

Address Inpu ts

Cell Address

Command Address

X

X

A0 = V

IL

, A1 = V

IL

, A9 = V

ID

,

Others V

IL or V

IH

A0 = V

IH

, A1 = V

IL

, A9 = V

ID

,

Others V

IL or V

IH

Data

Inputs/Outpu ts

Data Output

Data Input

Hi-Z

Hi-Z

20h

E2h

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory.

These codes can be read by applying the signals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block

Protection and Blocks Unprotection operations must only be performed on programming equipment. For further information refer to Application

Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

5/21

M29F040B

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus

Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a

Block Erase operation or following a Programming or Erase error then the memory will take up to 10

µ s to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation with A0 = V

IL and A1 = V

IL

. The other address bits may be set to either V

IL or V

IH

. The Manufacturer

Code for STMicroelectronics is 20h.

The Device Code can be read using a Bus Read operation with A0 = V

IH and A1 = V

IL

. The other address bits may be set to either V

IL or V

IH

. The

Device Code for the M29F040B is E2h.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = V

IL

,

A1 = V

IH

, and A16, A17 and A18 specifying the address of the block. The other address bits may be set to either V

IL or V

IH

. If the addressed block is protected then 01h is output on the Data Inputs/

Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the

Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock

Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.

6/21

M29F040B

Table 5. Commands

Command

Read/Reset

4 555

3 555

1st

AA

AA

2AA

2AA

2nd

55

55

Bus Write Operations

3rd 4th

555

555

A0

20

PA PD

5th 6th

1

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

X

3 555

F0

AA 2AA 55 X F0

3 555 AA 2AA 55 555 90 Auto Select

Program

Unlock Bypass

Unlock Bypass

Program

2 X A0 PA PD

Unlock Bypass Reset

Chip Erase

Block Erase

2

6

6+

X

555

555

90

AA

AA

X

2AA

2AA

00

55

55

555

555

80

80

555

555

AA 2AA

AA 2AA

55

55

555

BA

10

30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e

Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Unlock Bypass Reset Command. The Unlock

Bypass Reset command can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100

µ s, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

7/21

M29F040B

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(T

A

= 0 to 70

°

C, –40 to 85

°

C or –40 to 125

°

C)

Parameter

Chip Erase (All bits in the memory set to ‘0’)

Min

Typ

(1)

1.5

Typical after

100k W/E Cycles

(1)

1.5

Chip Erase

Block Erase (64 Kbytes)

Program

Chip Program

Program/Erase Cycles (per Block)

Note: 1. T

A

= 25

°

C, V

CC

= 5V.

100,000

5

0.6

8

4.5

5

0.6

8

4.5

Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50

µ s after the last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50

µ s of the last block. The 50

µ s timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100

µ s, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis-

Max

20

4

150

18

Unit

sec sec sec

µ s sec cycles ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Program/Erase Controller will suspend within

15

µ s of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the

Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

8/21

M29F040B

Table 7. Status Register Bits

Operation Address

Program Any Address

Program During Erase

Suspend

Program Error

Chip Erase

Block Erase before timeout

Block Erase

Any Address

Any Address

Any Address

Erasing Block

Non-Erasing Block

Erasing Block

Non-Erasing Block

Erase Suspend

Erasing Block

Non-Erasing Block

Good Block Address

Erase Error

Faulty Block Address

Note: Unspecified data bits should be ignored.

DQ7

DQ7

DQ7

DQ7

0

0

0

0

0

1

0

0

DQ6

Toggle

Toggle

DQ5

0

0

Toggle

Toggle

Toggle

Toggle

Toggle

Toggle

0

0

0

0

1

0

No Toggle 0

Data read as normal

Toggle 1

Toggle 1

1

1

1

1

0

0

1

1

DQ3

DQ2

Toggle

Toggle

No Toggle

Toggle

No Toggle

Toggle

No Toggle

Toggle

STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and

Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status Register are summarized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase

Controller has successfully completed its operation or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to

Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 3, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 4, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

9/21

M29F040B

Figure 3. Data Polling Flowchart

START

READ DQ5 & DQ7 at VALID ADDRESS

DQ7

=

DATA

NO

YES

NO

DQ5

= 1

YES

READ DQ7

DQ7

=

DATA

NO

YES

FAIL PASS

AI01369

Figure 4. Data Toggle Flowchart

START

READ

DQ5 & DQ6

DQ6

=

TOGGLE

YES

NO

NO

DQ5

= 1

YES

READ DQ6

DQ6

=

TOGGLE

YES

NO

FAIL PASS

AI01370

Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase

Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.

10/21

M29F040B

Table 8. AC Measurement Conditions

Parameter

AC Test Conditions

Load Capacitance (C

L

)

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

45 / 55

High Speed

30pF

10ns

0 to 3V

1.5V

M29F040B

70 / 90

Standard

100pF

10ns

0.45 to 2.4V

0.8V and 2V

Figure 5. AC Testing Input Output Waveform

High Speed

3V

0V

Standard

2.4V

0.45V

1.5V

2.0V

0.8V

AI01275B

Figure 6. AC Testing Load Circuit

1.3V

1N914

DEVICE

UNDER

TEST

3.3k

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

AI03027

Table 9. Capacitance

(T

A

= 25

°

C, f = 1 MHz)

Symbol Parameter

C

IN

Input Capacitance

C

OUT

Output Capacitance

Note: Sampled only, not 100% tested.

Test Condition

V

IN

= 0V

V

OUT

= 0V

Min Max

6

12

Unit

pF pF

11/21

M29F040B

Table 10. DC Characteristics

(T

A

= 0 to 70

°

C, –40 to 85

°

C or –40 to 125

°

C)

Symbol Parameter Test Condition

I

LI

I

LO

I

CC1

Input Leakage Current

Output Leakage Current

Supply Current (Read)

0V

V

IN

V

CC

0V

V

OUT

V

CC

E = V

IL

, G = V

IH

, f = 6MHz

I

CC2

I

CC3

I

CC4

(1)

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Supply Current (Program/Erase)

E = V

IH

E = V

CC

±

0.2V

Program/Erase

Controller active

V

IL

V

IH

V

OL

Input Low Voltage

Input High Voltage

Output Low Voltage

V

OH

Output High Voltage TTL

Output High Voltage CMOS

I

OL

= 5.8mA

I

OH

= –2.5mA

I

OH

= –100

µ

A

V

ID

I

ID

Identification Voltage

Identification Current

V

LKO

(1)

Program/Erase Lockout Supply

Voltage

Note: 1. Sampled only, not 100% tested.

2. T

A

= 25

°

C, V

CC

= 5V.

A9 = V

ID

Min

–0.5

2

2.4

V

CC

– 0.4

11.5

3.2

Typ.

(2)

7

30

Max

±

1

±

1

15

1

100

20

0.8

V

CC

+ 0.5

0.45

12.5

100

4.2

V

V

V

µ

A

V

V

V

V

Unit

µ

A

µ

A mA mA

µ

A mA

12/21

M29F040B

Table 11. Read AC Characteristics

(TA = 0 to 70

°

C, –40 to 85

°

C or –40 to 125

°

C)

Symbol Alt Parameter Test Condition

t

AVAV t

AVQV t

RC t

ACC

Address Valid to Next Address Valid

Address Valid to Output Valid t

ELQX

(1) t

LZ

Chip Enable Low to Output

Transition t

ELQV t

CE

Chip Enable Low to Output Valid t

GLQX

(1) t

OLZ

Output Enable Low to Output

Transition

Output Enable Low to Output Valid t

GLQV t

OE t

EHQZ

(1) t

GHQZ

(1) t t

HZ

DF

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z t

EHQX t

GHQX t

AXQX t

OH

Chip Enable, Output Enable or

Address Transition to Output

Transition

Note: 1. Sampled only, not 100% tested.

E = V

IL

,

G = V

IL

E = V

IL

,

G = V

IL

G = V

IL

G = V

IL

E = V

IL

E = V

IL

G = V

IL

E = V

IL

Min

Max

Min

Min

Max

Min

Max

Max

Max

45

0

45

0

25

15

15

45

M29F040B

55 70 / 90

Unit

45 55 70 ns

0

55

0

55

0

30

18

18

0

70

0

70

0

30

20

20

0 ns ns ns ns ns ns ns ns

Figure 7. Read Mode AC Waveforms

A0-A18

E

G

DQ0-DQ7 tAVQV tELQV tELQX tAVAV

VALID tGLQX tGLQV tGHQX tGHQZ

VALID tAXQX tEHQZ tEHQX

AI02903

13/21

M29F040B

Table 12. Write AC Characteristics, Write Enable Controlled

(T

A

= 0 to 70

°

C, –40 to 85

°

C or –40 to 125

°

C)

Symbol Alt Parameter

t

WHWL t

AVWL t

WLAX t

GHWL t

WHGL t

VCHEL t

AVAV t

ELWL t

WLWH t

DVWH t

WHDX t

WHEH t

WC t

CS t

WP t

DS t

DH t

CH t

WPH t

AS t

AH

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low t

OEH

Write Enable High to Output Enable Low t

VCS

V

CC

High to Chip Enable Low

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

0

0

50

20

0

40

0

0

45

45

0

40

25

0

0

50

20

0

40

M29F040B

55 70 / 90

55 70

0

40

25

0

0

0

45

30

0

0

0

0

50

20

0

45

Unit

ns ns ns ns ns

µ s ns ns ns ns ns ns

Figure 8. Write AC Waveforms, Write Enable Controlled

A0-A18 tAVAV

VALID tAVWL

E tELWL

G tGHWL tWLWH

W tWLAX tWHEH tWHGL tWHWL tWHDX

DQ0-DQ7 tDVWH

VALID

VCC tVCHEL

AI02908

14/21

M29F040B

Table 13. Write AC Characteristics, Chip Enable Controlled

(T

A

= 0 to 70

°

C, –40 to 85

°

C or –40 to 125

°

C)

Symbol Alt Parameter

t

EHEL t

AVEL t

ELAX t

GHEL t

EHGL t

VCHWL t

AVAV t

WLEL t

ELEH t

DVEH t

EHDX t

EHWH t

WC t

WS t

CP t

DS t

DH t

WH t

CPH t

AS t

AH

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low t

OEH

Chip Enable High to Output Enable Low t

VCS

V

CC

High to Write Enable Low

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

Min

0

0

50

20

0

40

0

0

45

45

0

40

25

0

0

50

20

0

40

M29F040B

55 70 / 90

55 70

0

40

25

0

0

0

45

30

0

0

0

0

50

20

0

45

Unit

ns ns ns ns ns

µ s ns ns ns ns ns ns

Figure 9. Write AC Waveforms, Chip Enable Controlled

A0-A18 tAVAV

VALID tAVEL

W tWLEL

G tGHEL tELEH

E

DQ0-DQ7 tDVEH

VALID tELAX tEHWH tEHGL tEHEL tEHDX

VCC tVCHWL

AI02909

15/21

M29F040B

Table 14. Ordering Information Scheme

Example:

Device Type

M29

Operating Voltage

F = V

CC

= 5V

±

10%

Device Function

040B = 4 Mbit (512Kb x8), Uniform Block

Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

K = PLCC32

N = TSOP32: 8 x 20 mm

P = PDIP32

Temperature Range

1 = 0 to 70

°

C

3 = –40 to 125

°

C

6 = –40 to 85

°

C

Optio n

T = Tape & Reel Packing

M29F040B 55 N 1 T

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content erased (to FFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

16/21

Table 15. Revision History

Date

July 1999 First Issue

09/21/99

I

CC1

Typ. specification added (Table 10)

I

CC3

Typ. specification added (Table 10)

Revision Details

M29F040B

17/21

M29F040B

Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data mm

Symbol inches

Typ Min Max Typ Min Max

A

A1

2.54

1.52

3.56

2.41

0.100

0.060

0.140

0.095

E1

E2 e

F

D1

D2

E

A2

B

B1

D

R

N

Nd

Ne

CP

1.27

0.89

32

7

9

13.89

12.45

0.00

0.33

0.66

12.32

11.35

9.91

14.86

0.38

0.53

0.81

12.57

11.56

10.92

15.11

14.10

13.46

0.25

0.10

0.050

0.035

32

7

9

0.547

0.490

0.000

0.013

0.026

0.485

0.447

0.390

0.585

0.015

0.021

0.032

0.495

0.455

0.430

0.595

0.555

0.530

0.010

0.004

Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

D

D1

1 N

A2

A1

B1 e

Ne

E1 E

F

0.51 (.020)

D2/E2

B

1.14 (.045)

Nd

A

R

CP

PLCC

Drawing is not to scale.

18/21

M29F040B

Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data mm inches

Symbol

Typ Min Max Typ Min Max

C

D

D1

A

A1

A2

B

E e

L

α

N

CP

0.50

0.05

0.95

0.15

0.10

19.80

18.30

7.90

0.50

0

°

32

1.20

0.15

1.05

0.27

0.21

20.20

18.50

8.10

0.70

5

°

0.10

0.020

0.002

0.037

0.006

0.004

0.780

0.720

0.311

0.020

0

°

32

0.004

0.047

0.006

0.041

0.011

0.008

0.795

0.728

0.319

0.028

5

°

Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline

A2

1 N e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Drawing is not to scale.

A1

α

L

19/21

M29F040B

Table 18. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data mm

Symbol inches

Typ Min Max Typ Min

A 5.08

D

D2

E

E1 e1

A1

A2

B

B1

C eA eB

L

S

α

N

1.52

38.10

15.24

2.54

15.24

41.78

13.59

0.38

3.56

0.38

0.20

15.24

3.18

1.78

0

°

32

4.06

0.51

0.30

42.04

13.84

17.78

3.43

2.03

10

°

0.060

1.500

0.600

0.100

0.600

1.645

0.535

0.015

0.140

0.015

0.008

0.600

0.125

0.070

0

°

32

Figure 12. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

Max

0.200

0.160

0.020

0.012

1.655

0.545

0.700

0.135

0.080

10

°

B1

N

S

D2

B

D

A2 A

A1 e1

L

E1 E

1

α eA eB

C

PDIP

Drawing is not to scale.

20/21

M29F040B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

1999 STMicroelectronics - All Rights Reserved

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21/21

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