datasheet for MS161000FKXA by Apta Group

datasheet for MS161000FKXA by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
1M x 16 SRAM MODULE
MS161000FKXA-10/12/15
Issue 1.0 : January 1992
PRELIMINARY
1,048,576 x 16 CMOS High Speed Static RAM
Features
Access Times of 100/120/150 ns.
Configurable as
8 / 16 bit wide outputs.
Operating Power 550 / 600 mW (typical).
Low Power Standby
1.68 mW (typical) -L version.
Completely Static Operation.
Battery back-up capability.
Directly TTL compatible.
Onboard Decoupling Capacitors.
Block Diagram
A17
A18
A19
CS1A
CS2A
A0~A16
CS8
CS7
CS6
CS5
1 OF 8
CS4
CS3
CS2
CS1
128Kx8
SRAM
WE
OE
A17
A18
A19
CS1B
CS2B
DATAA
DATAB
128Kx8
SRAM
CS1
1 OF 8
Package Details Dimensions in mm (inches).
55.88 (2.200)
Pin Definition
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
WE
OE
CS2B
CS2A
A19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
PACKAGE34
TOP VIEW33
32
31
30
29
28
27
26
25
24
23
VCC
A18
CS1B
CS1A
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Pin Functions
48.26
(1.900)
5.65
(0.222)
max
1.27 (0.050)
2.54 (0.100)
3.00-4.00 (0.118-0.157
A0 ~A19
D0A ~D7A
D0B ~D7B
CS1A
CS1B
CS2A
CS2B
OE
WE
VCC
GND
Address Inputs
Data A Input/Output
Data B Input/Output
Chip Select Data A (active low)
Chip Select Data B (active low)
Chip Select Data A (active high)
Chip Select Data B (active high)
Output Enable
Write Enable
Power (+5V)
Ground
ISSUE 1.0 : JANUARY 1992
MS161000FKXA-10/12/15
Absolute Maximum Ratings
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
VT
PT
TSTG
-0.5V to +7 V
16
W
-55 to +125 °C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(2) VT can be -3.5V pulse of less than 20ns.
Recommended Operating Conditions
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
min
4.5
2.2
-0.3
0
-40
VCC
VIH
VIL
TA
TAI
typ
5.0
-
max
5.5
VCC+0.5
0.8
70
85
V
V
V
°
C
°
C (-I suffix)
DC Electrical Characteristics (VCC=5V±10%,TA=0°C to +70°C)
Parameter
Symbol
Input Leakage Current
Test Condition
min
CS
A17~A19
A0~A16, WE, OE
Output Leakage Current 16 bit
ILI1
ILI2
ILI3
ILO
VIN=0V to VCC
Operating Supply Current 16 bit
8 bit
Average Supply Current 16 bit
8 bit
ICC016
ICC08
ICCA16
ICCA8
CS1 = VIL, CS2 = VCC-2.1, II/O = 0mA, I/P's Static
Standby Supply Current
ISB
ISB1
ISB2
CS1 = VCC-2.1 or CS2 = VIL , min. cycle
VOL
VOH
IOL=2.1mA
TTL
CMOS
-L part CMOS
Output Voltage Low
Output Voltage High
VIN=0V to VCC
VIN=0V to VCC
CS1 = VIH or CS2 = VIL, VI/O = 0V to VCC
As above
CS1=VIL, CS2=VCC-2.1, VIL•VIN•VCC-2.1, min.cycle
As above
CS1•VCC-0.2V or CS2-0.2V, 0.2V•VIN•VCC-0.2V
As above
IOH=-1.0mA
typ(1) max Unit
-
-
±1
±2
±32
±16
µA
µA
µA
µA
-
52
37
112
67
107
60
187
92
mA
mA
mA
mA
-
0.64
0.40
48
32
2
mA
mA
mA
2.4
-
0.4
-
V
V
Notes (1) CS1 and CS2 above are accessed through CS1A, CS1B, CS2A and CS2B as shown in the Operating Modes
Truth Table on page 6 to obtain 8 and 16 bit operation.
(2) Typical values are measured at 25°C and V CC = 5.0V.
Capacitance (VCC = 5V ± 10%,TA = 25°C, ƒ = 1MHz) These parameters are calculated, not measured.
Parameter
Input Capacitance
Chip Selects
A17~A19
A0~A16, WE, OE
Output Capacitance
16 bit
Symbol
CIN1
CIN2
CIN3
COUT
Test Condition
VIN=0V
VIN=0V
VIN=0V
VOUT=0V
2
typ
-
max
Unit
10
12
160
80
pF
pF
pF
pF
MS161000FKXA-10/12/15
ISSUE 1.0 : JANUARY 1992
Recommended AC Operating Conditions
Read Cycle
-10
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Select to Output (CS1A,B)
Chip Select to Output (CS2A,B)
Output Enable to Output Valid
Output Hold from Address Change
Chip Select to Output in Low Z (CS1A,B)
Chip Select to Output in Low Z (CS2A,B)
Output Enable to Output in Low Z
Chip Select to Output in High Z (CS1A,B)
Chip Select to Output in High Z (CS2A,B)
Output Enable to Output in High Z (2)
(2)
(2)
tRC
tAA
tCO1
tCO2
tOE
tOH
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
-12
-15
min
max
min
max
min
max
Unit
100
10
10
10
5
0
0
0
100
100
100
50
35
35
35
120
10
10
10
5
0
0
0
120
120
120
60
45
45
45
150
10
10
10
5
0
0
0
150
150
150
70
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle
t RC
Address
t AA
t OE
OE
t OLZ
t CLZ1
t OH
CS1A,B
t CO1
t CHZ1
t CO2
t CLZ2
tOHZ
CS2A,B ¸
Data Valid
Dout
t CHZ2
Notes: (1) WE is High for Read Cycle.
(2) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. At any given temperature and voltage condition, tCHZ max is less than tCLZ min both for a
given device and from device to device. This parameter is sampled and not 100% tested.
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V.
* Input rise and fall times: 5ns.
* Input and Output timing reference levels: 1.5V.
* Output load: see diagram.
* Module is tested in 16 bit mode.
I/O Pin
645•
1.76V
100pF
3
ISSUE 1.0 : JANUARY 1992
MS161000FKXA-10/12/15
Write Cycle
-10
Parameter
-12
-15
Symbol
min
max
min
max
min
max
Unit
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
100
90
90
0
75
10
0
40
0
5
35
-
120
100
100
0
85
15
0
45
0
5
40
-
150
120
120
0
95
20
0
50
0
5
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z (11)
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Write Cycle No. 1 Timing Waveform
tWC
Address
t AW
OE
tWR(4)
t CW
CS1A,B
CS2A,B
t WP(1)
t AS(3)
tOHZ(5)
WE
t DHC
Dout
tDW
tDH
Din
Write Cycle No. 2 Timing Waveform (5)
tWC
Address
tWR(4)
tCW (10)
CS1A,B
t AW
CS2A,B
tCW(10)
tWP(1)
WE
tOH
t AS(3)
tDHC
tWHZ(6)
tOW
(8)
(7)
Dout
tDW
tDH
(9)
Din
4
MS161000FKXA-10/12/15
ISSUE 1.0 : JANUARY 1992
Write Cycle Timing Waveform Notes
(1) A write occurs during the overlap (tWP) of CS1A/B low, CS2A/B high and WE low.
(2) If a bank becomes selected (CS1A/B low and CS2A/B high) simultaneously with WE going low or after WE
going low,the outputs remain in a high impedance state.
(3) If CS1A/B or CS2A/B goes inactive simultaneously with WE high, the output remains in a high impedance state.
(4) tWR is measured from the earlier of CS1A/B, CS2A/B and WE becoming inactive to the address change.
(5) OE is continuoulsy low. (OE=VIL)
(6) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(7) DOUT is in the same phase as written data of this write cycle.
(8) DOUT is the read data of next address.
(9) If CS1A/B or CS2A/B go inactive during this period, I/O pins are in the output state, input signals out of phase
must not be applied to I/O pins.
(10) tCW is measured from the later of CS1A/B and CS2A/B becoming active to end of write.
(11) tWHZ is defined as the time at which the outputs achieve the open circuit condition and is not referenced to
output voltage levels. This parameter is sampled and not 100% tested.
Low Vcc Data Retention Characteristics - L Version Only (TA=-0°C to +70°C)
Parameter
Symbol Test Condition
VCC for Data Retention
VDR
min
typ (1)
Data Retention Current
ICCDR VCC=3.0V,VIN • 0V, CS1A/B •VCC-0.2V or
Chip Deselect to Data Retention
Operation Recovery Time
tCDR
tR
CS2A/B - 0.2V.
See Retention Waveform
See Retention Waveform
2.0
-
-
0
5
32
-
2000
-
Note (1) Typical figures are measured at 25°C and specified loading.
Data Retention - CS1A/B Controlled
DATA RETENTION MODE
4.5V
tCDR
4.5V
tR
2.2V
2.2V
VDR
CS1A/B
CS1A/B>=VCC-0.2V
0V
Data Retention - CS2A/B Controlled
VCC
DATA RETENTION MODE
4.5V
Unit
CS1A/B • VCC-0.2V or CS2A/B - 0.2V,
0.2V • VIN • VCC-0.2V
VCC
max
tCDR
tR
CS2A/B
VDR2
0.4V
CS2A/B<=0.2V
0V
5
4.5V
V
µA
ns
ms
ISSUE 1.0 : JANUARY 1992
MS161000FKXA-10/12/15
Operating Modes
The Truth Table below defines the logic inputs required to operate the MS161000FKXA in all valid modes. Refer
to the DCElectrical Characteristics for the correct values of ISB and ICC for 8 bit or 16 bit operation.
MODE
CS1A CS2A CS1B CS2B
WE
OE
Data A
Data B
Current
STANDBY
1
X
1
X
X
X
HIGH Z
HIGH Z
ISB,1,2
STANDBY
X
0
X
0
X
X
HIGH Z
HIGH Z
ISB,1,2
O/P DISABLE
0
1
0
1
1
1
HIGH Z
HIGH Z
ICCO
8 BIT READ A
0
1
1
0
1
0
DOUT
HIGH Z
ICCA8
8 BIT READ B
1
0
0
1
1
0
HIGH Z
DOUT
ICCA8
16 BIT READ
0
1
0
1
1
0
DOUT
DOUT
ICCA16
8 BIT WRITE A
0
1
1
0
0
1
DIN
HIGH Z
ICCA8
8 BIT WRITE B
1
0
0
1
0
1
HIGH Z
DIN
ICCA8
16 BIT WRITE
0
1
0
1
0
1
DIN
DIN
ICCA16
1 = VIH
0 = VIL
X = Don't Care.
Ordering Information
MS161000FKXALI-10
Speed
10 = 100 ns
12 = 120 ns
15 = 150 ns
Temperature range
Blank = Commercial Temperature
I = Industrial Temperature
Power Consumption
Blank = Standard Power Part
L = Low Power Part
Package
FKXA = Plastic 44 pin 1.9" DIL.
Memory Organisation
16000 = 1M x 16 bit, user configurable as
2M x 8 bit.
6
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