DLP7000UV DLP 0.7 UV XGA 2x LVDS Type A DMD ® 1 Features

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DLP7000UV

DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015

DLP7000UV DLP

®

0.7 UV XGA 2x LVDS Type A DMD

1 Features

1

• 0.7-Inch Diagonal Micromirror Array

– 1024 × 768 Array of Aluminum, Micrometer-

Sized Mirrors

– 13.68-µm Micromirror Pitch

– ±12° Micromirror Tilt Angle (Relative to Flat

State)

– Designed for Corner Illumination

• Designed for Use With UV Light (363 to 420 nm):

– Window Transmission 98% (Single Pass,

Through Two Window Surfaces)

– Micromirror Reflectivity 88%

– Array Diffraction Efficiency 85%

– Array Fill Factor 92% (Nominal)

• Two 16-Bit, Low-Voltage Differential Signaling

(LVDS) Double Data Rate (DDR) Input Data

Buses

• Up to 400 MHz Input Data Clock Rate

• 40.64-mm by 31.75-mm by 6.0-mm Package

Footprint

• Hermetic Package

3 Description

DLP7000UV is a digitally controlled MEMS (microelectromechanical system) spatial light modulator

(SLM). When coupled to an appropriate optical system, the DLP7000UV can be used to modulate the amplitude, direction, and/or phase of incoming light.

The DLP7000UV DMD is an addition to the DLP

Discovery 4100 platform, which enables very fast pattern rates combined with high performance spatial light modulation operating beyond the visible spectrum into the UVA spectrum (363 nm to 420 nm).

The DLP7000UV digital micromirror device (DMD) is designed with a special window that is optimized for

UV transmission. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP7000UV makes it well suited to support a wide variety of industrial, medical, and advanced display applications.

The DLP7000UV DMD with a hermetic package is sold with a dedicated DLPC410 controller for high speed pattern rates of >32000 Hz (1-bit binary) and

>1900 Hz (8-bit gray), one DLPR410 (DLP Discovery

4100 Configuration PROM), and one DLPA200 (DMD micromirror driver).

2 Applications

• Industrial

– Direct Imaging Lithography

– Laser Marking and Repair Systems

– Computer-to-Plate Printers

– Rapid Prototyping Machines

– 3D Printers

• Medical

– Ophthalmology

– Photo Therapy

– Hyper-Spectral Imaging

PART NUMBER

Device Information

(1)

PACKAGE BODY SIZE (NOM)

DLP7000UV LCCC (203) 40.64 mm × 31.75 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

Illumination

Driver

DLPC410

DLP7000UV

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLP7000UV


www.ti.com

1

Features ..................................................................

1

2

Applications ...........................................................

1

3

Description .............................................................

1

4

Revision History.....................................................

2

5

Description (continued).........................................

3

6

Pin Configuration and Functions .........................

3

7

Specifications.......................................................

10

7.1

Absolute Maximum Ratings ....................................

10

7.2

Storage Conditions..................................................

10

7.3

ESD Ratings............................................................

10

7.4

Recommended Operating Conditions .....................

11

7.5

Thermal Information ................................................

11

7.6

Electrical Characteristics.........................................

12

7.7

LVDS Timing Requirements ...................................

13

7.8

LVDS Waveform Requirements ..............................

14

7.9

Serial Control Bus Timing Requirements................

15

7.10

Systems Mounting Interface Loads.......................

16

7.11

Micromirror Array Physical Characteristics ...........

17

7.12

Micromirror Array Optical Characteristics .............

18

7.13

Window Characteristics.........................................

19

7.14

Chipset Component Usage Specification .............

19

8

Detailed Description ............................................

20

8.1

Overview .................................................................

20

Table of Contents

8.2

Functional Block Diagram .......................................

21

8.3

Feature Description.................................................

21

8.4

Device Functional Modes........................................

29

8.5

Window Characteristics and Optics .......................

31

8.6

Micromirror Array Temperature Calculation............

32

8.7

Micromirror Landed-On/Landed-Off Duty Cycle .....

34

9

Application and Implementation ........................

36

9.1

Application Information............................................

36

9.2

Typical Application ..................................................

37

10

Power Supply Recommendations .....................

40

10.1

Power-Up Sequence (Handled by the DLPC410)

.................................................................................

40

11

Layout...................................................................

40

11.1

Layout Guidelines .................................................

40

11.2

Layout Example ....................................................

42

12

Device and Documentation Support .................

43

12.1

Device Support......................................................

43

12.2

Documentation Support ........................................

43

12.3

Community Resources..........................................

44

12.4

Trademarks ...........................................................

44

12.5

Electrostatic Discharge Caution ............................

44

12.6

Glossary ................................................................

44

13 Mechanical, Packaging, and Orderable

Information ...........................................................

44

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (July 2015) to Revision C Page

• Changed device status from Product Preview to Production Data ........................................................................................

1

• Added 3.7-W maximum value to illumination power density (from 363 nm to 420 nm) in

Recommended Operating

Conditions

............................................................................................................................................................................

11

• Updated

Figure 18

...............................................................................................................................................................

36

Changes from Revision A (June 2015) to Revision B Page

• Released full data sheet .........................................................................................................................................................

1

• Corrected minimum value of UVA spectrum from 365 nm to 363 nm in

Description

............................................................

1

Changes from Original (May 2015) to Revision A Page

• Corrected device part number ...............................................................................................................................................

1

2

Submit Documentation Feedback

Product Folder Links:

DLP7000UV

Copyright © 2015, Texas Instruments Incorporated

www.ti.com

DLP7000UV


5 Description (continued)

Reliable function and operation of the DLP7000UV requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control.

Electrically, the DLP7000UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over two 16-bit low voltage differential signaling (LVDS) double data rate (DDR) buses. Addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.

6 Pin Configuration and Functions

FLP Package

203-Pin LCCC

Bottom View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1



DLP7000UV


3

DLP7000UV


PIN

(1)

NAME

DATA INPUT

NO.

D_AN(0) B10

D_AN(1)

D_AN(2)

D_AN(3)

D_AN(4)

D_AN(5)

D_AN(6)

D_AN(7)

D_AN(8)

D_AN(9)

D_AN(10)

D_AN(11)

D_AN(12)

D_AN(13)

D_AN(14)

D_AN(15)

D_AP(0)

D_AP(1)

A13

D16

C17

B18

A17

A25

D22

C29

D28

E27

F26

G29

H28

J27

K26

B12

A11

TYPE

(I/O/P)

SIGNAL

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

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Pin Functions

DATA

RATE

(2)

INTERNAL

TERM

(3)

CLOCK DESCRIPTION TRACE (MILS)

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

Differential

Terminated -

100 Ω

Differential

Terminated -

100

Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100

Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100

Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100

Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

Input data bus A

(2x LVDS)

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

368.72

424.61

433.87

391.39

438.57

391.13

563.26

411.62

595.11

543.07

455.98

359.5

542.67

551.51

528.04

484.38

366.99

417.47

(1) The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected.

(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to the

LVDS Timing Requirements

for specifications and relationships.

(3) Refer to

Electrical Characteristics

for differential termination specification.

4




DLP7000UV

www.ti.com

NAME

PIN

(1)

NO.

D_AP(2) D14

D_AP(3)

D_AP(4)

D_AP(5)

D_AP(6)

D_AP(7)

D_AP(8)

D_AP(9)

D_AP(10)

D_AP(11)

D_AP(12)

D_AP(13)

D_AP(14)

D_AP(15)

D_BN(0)

D_BN(1)

D_BN(2)

D_BN(3)

D_BN(4)

C15

B16

A19

A23

D20

A29

B28

C27

D26

F30

H30

J29

K28

AB10

AC13

Y16

AA17

AB18

DLP7000UV


TYPE

(I/O/P)

SIGNAL

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Pin Functions (continued)

DATA

RATE

(2)

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

INTERNAL

TERM

(3)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

CLOCK

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_A

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DESCRIPTION

Input data bus A

(2x LVDS)

TRACE (MILS)

434.89

394.67

437.3

389.01

562.92

410.34

594.61

539.88

456.78

360.68

543.97

570.85

527.18

481.02

368.72

424.61

433.87

391.39

438.57



5


DLP7000UV

DLP7000UV


NAME

PIN

(1)

NO.

D_BN(5)

D_BN(6)

D_BN(7)

D_BN(8)

D_BN(9)

D_BN(10)

D_BN(11)

D_BN(12)

D_BN(13)

D_BN(14)

D_BN(15)

D_BP(0)

D_BP(1)

D_BP(2)

D_BP(3)

D_BP(4)

D_BP(5)

D_BP(6)

D_BP(7)

AC17

AC25

Y22

AA29

Y28

W27

V26

T30

R29

R27

N27

AB12

AC11

Y14

AA15

AB16

AC19

AC23

Y20

TYPE

(I/O/P)

SIGNAL

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS


DATA

RATE

(2)

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

INTERNAL

TERM

(3)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

CLOCK

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

Input LVCMOS DDR

Differential

Terminated -

100 Ω

DCLK_B

Input LVCMOS DDR

Differential

Terminated -

100 Ω

DCLK_B

DESCRIPTION

Input data bus B

(2x LVDS) Input data bus B (2x

LVDS)

www.ti.com

TRACE (MILS)

391.13

563.26

411.62

595.11

543.07

455.98

360.94

575.85

519.37

532.59

441.14

366.99

417.47

434.89

394.67

437.3

389.01

562.92

410.34

6




DLP7000UV

www.ti.com

NAME

PIN

(1)

NO.

D_BP(8) AC29

D_BP(9)

D_BP(10)

D_BP(11)

D_BP(12)

D_BP(13)

D_BP(14)

AB28

AA27

Y26

U29

T28

P28

D_BP(15)

DATA CLOCK

P26

DCLK_AN B22

DCLK_AP

DCLK_BN

B24

AB22

DLP7000UV


TYPE

(I/O/P)

SIGNAL

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS


DATA

RATE

(2)

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

INTERNAL

TERM

(3)

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

CLOCK

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DCLK_B

DESCRIPTION

Input data bus B

(2x LVDS)

TRACE (MILS)

594.61

539.88

456.78

360.68

578.46

509.74

534.59

440

Input LVCMOS

Input LVCMOS

Input LVCMOS

DCLK_BP AB24

DATA CONTROL INPUTS

Input LVCMOS

SCTRL_AN C21 Input LVCMOS

SCTRL_AP

SCTRL_BN

C23

AA21

Input LVCMOS

Input LVCMOS

SCTRL_BP AA23 Input LVCMOS

SERIAL COMMUNICATION AND CONFIGURATION

SCPCLK E3 Input LVCMOS

SCPDO

SCPDI

SCPENZ

PWRDNZ

B2

F4

D4

C3

Output LVCMOS

Input LVCMOS

Input LVCMOS

Input LVCMOS

–

–

–

–

DDR

DDR

DDR

DDR

–

–

–

–

–

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Differential

Terminated -

100 Ω

Pull-down

–

Pull-down

Pull-down

Pull-down

–

–

–

–

DCLK_A

Serial control for data bus A (2x

LVDS)

DCLK_A

DCLK_B

Serial control for data bus B (2x

LVDS)

DCLK_B

– Serial port clock

SCPCLK Serial port output

SCPCLK Serial port input

SCPCLK Serial port enable

– Device Reset

477.10

477.11

477.10

477.11

477.07

477.14

477.07

477.14

379.29

480.91

323.56

326.99

406.28



7


DLP7000UV

DLP7000UV


NAME

PIN

(1)

NO.

TYPE

(I/O/P)

SIGNAL

MODE_A D8 Input LVCMOS

MODE_B C11 Input LVCMOS

MICROMIRROR BIAS CLOCKING PULSE

MBRST(0)

MBRST(1)

MBRST(2)

P2

AB4

AA7

Input Analog

Input Analog

Input Analog

MBRST(3)

MBRST(4)

MBRST(5)

MBRST(6)

N3

M4

AB6

AA5

Input Analog

Input Analog

Input Analog

Input Analog


DATA

RATE

(2)

INTERNAL

TERM

(3)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Pull-down

Pull-down

CLOCK

–

–

–

–

–

–

–

–

–

DESCRIPTION

Data bandwidth mode select

MBRST(7) L3 Input Analog – – –

Micromirror Bias

Clocking Pulse

MBRST signals

clock micromirrors into state of

LVCMOS memory cell associated with each mirror.

MBRST(8)

MBRST(9)

MBRST(10)

MBRST(11)

MBRST(12)

MBRST(13)

MBRST(14)

MBRST(15)

POWER

Y6

K4

L5

AC5

Y8

J5

K6

AC7

Input Analog

Input Analog

Input Analog

Input Analog

Input Analog

Input Analog

Input Analog

Input Analog

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

VCC

VCC1

VCC2

A7,A15,C1,

E1,U1,W1,A

B2,AC9,AC

15

Power Analog

A21,A27,D3

0,M30,Y30, Power Analog

AC21,AC27

G1,J1,L1,N

1,R1

Power Analog

–

–

–

–

–

–

–

–

–

Power for

LVCMOS Logic

Power supply for

LVDS Interface

Power for High

Voltage CMOS

Logic

www.ti.com

TRACE (MILS)

396.05

208.86

–

–

–

8



DLP7000UV


www.ti.com

DLP7000UV


NAME

PIN

(1)

NO.

A1,A3,A5,A

9,B4,B8,B1

4,B20,B26,

B30,C7,

TYPE

(I/O/P)

VSS

C13,C19,C2

5,D6,D12,D

18,D24,E29,

F2,F28,

G3,G27,H2,

H4,H26,J3,J

25,K2,K30,L

25,

L27,L29,M2,

M6,M26,M2 Power Analog

8,N5,N25,N

29,P4,

RESERVED

_AA1

P30,R3,R5,

R25,T2,T26,

U27,V28,V3

0,W5,

W29,Y4,Y1

2,Y18,Y24,

AA3,AA9,A

A13,AA19,

AA25,AB8,A

B14,AB20,A

B26,AB30

RESERVED SIGNALS (NOT FOR USE IN SYSTEM)

AA1 Input LVCMOS

RESERVED

_B6

RESERVED

_T4

RESERVED

_U5

B6

T4

U5

Input

Input

Input

SIGNAL

LVCMOS

LVCMOS

LVCMOS

NO_CONN

ECT

AA11,AC3,

C5,C9,D10,

D2,E5,G5,H

6,P6,T6,

U3,V2,V4,W

3,Y10,Y2

– –


DATA

RATE

(2)

–

–

–

–

–

–

–

INTERNAL

TERM

(3)

Pull-down

Pull-down

Pull-down

Pull-down

–

CLOCK

–

–

–

–

–

–

DESCRIPTION

Common return for all power inputs

Pins should be connected to VSS

–

–

–

DO NOT

CONNECT

TRACE (MILS)

–

–

–

–

–

–



DLP7000UV


9

DLP7000UV


7 Specifications

www.ti.com

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

ELECTRICAL

V

V

V

V

|V

|V

CC

CCI

CC2

MBRST

CC

ID

|

– V

CCI

|

Voltage applied to V

CC

(2) (3)


CCI

(2) (3)


VCC2

(2) (3) (4)

Micromirror clocking pulse waveform voltage applied to MBRST[15:0]

Input Pins (supplied by DLPA200)

Supply voltage delta (absolute value)

(4)

Voltage applied to all other input pins

(2)

Maximum differential voltage, damage can occur to internal termination resistor if exceeded, see

Figure 2

I

OH

I

OL

ENVIRONMENTAL

Current required from a high-level output

Current required from a low-level output

T

T

C

GRADIENT

Case temperature – operational

(5)

Case temperature – non-operational

(5)

Device temperature gradient – operational

(6)

Relative humidity (non-condensing)

V

OH

= 2.4 V

V

OL

= 0.4 V

–0.5

–0.5

–0.5

-28

–0.5

20

-40

V

CC

4

4

8

28

0.3

+ 0.3

700

–20

15

30

80

5

95

V

V

V

V

V

V mV mA mA

°C

°C

°C

%RH

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended

Operating Conditions

. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V

SS

(3) Voltages V

CC

, V

CCI

, and V

CC2

(ground).

are required for proper DMD operation.

(4) Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The difference between VCC and VCCI, | VCC – VCCI|, should be less than the specified limit.

(5) DMD Temperature is the worst-case of any test point shown in

Case Temperature

, or the active array as calculated by the

Micromirror

Array Temperature Calculation

.

(6) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror array cavity. Refer to

Case Temperature

and

Micromirror Array Temperature Calculation

.

7.2 Storage Conditions

are applicable before the DMD is installed in the final product.

T stg

Storage temperature


MIN

-40

MAX

80

95

UNIT

°C

%RH

7.3 ESD Ratings

V

(ESD)

Electrostatic discharge

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001

(1)

All pins except MBRST[0:15]

MBRST[0:15] pins

VALUE UNIT

±2000

V

<250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.

10



DLP7000UV


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DLP7000UV


7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1)

MIN NOM MAX UNIT

ELECTRICAL

V

V

CC

CCI

Supply voltage for LVCMOS core logic

(2) (3)

Supply voltage for LVDS receivers

(2) (3)

Mirror electrode and HVCMOS supply voltage

(2) (3)

V

CC2

V

MBRST

|V

CC

– V

CCI

|

Clocking pulse waveform voltage applied to MBRST[15:0] input pins (supplied by DLPA200)

Supply voltage delta (absolute value)

(3)

ENVIRONMENTAL - For Illumination Source between 363 and 420 nm

< 363 nm

(6)

3.0

3.0

7.25

–27

3.3

3.3

7.5

3.6

3.6

7.75

26.5

0.3

V

V

V

V

V

T

C

T

GRADIENT

Illumination power density

(4) (5)

Case/array temperature

(8) (9)

Device temperature gradient – operational

(11)


Operating landed duty cycle

(12)

363 to 420 nm

(7)

> 420 nm

2 mW/cm

2

2.5

W/cm

2

W

20

3.7

Thermally limited

(7)

30

(10)

W/cm

°C

2

5

95

°C

%RH

25%

(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(2) All voltages referenced to VSS (ground).

(3) Voltages V

CC

, V

CCI

, and V

CC2

, are required for proper DMD operation.

(4) Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.

(5) Total integrated illumination power density, above or below the indicated wavelength threshold.

(6) The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363 nm should not be implemented simultaneously.

(7) Also limited by the resulting micromirror array temperature. Refer to


for information related to calculating the micromirror array temperature.

(8) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. Refer to

Micromirror

Array Temperature Calculation

for further details.

(9) Temperature is the highest measured value of any test point shown in Figure 17 or the active array as calculated by the

Micromirror

Array Temperature Calculation .

(10) Refer to


for thermal test point locations, package thermal resistance, and device temperature calculation.

(11) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror array cavity. Refer to Case Temperature and

Micromirror Array Temperature Calculation .

(12) Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other state (–12° or 12°).

7.5 Thermal Information

THERMAL METRIC

(1) (2)

DLP7000UV

FLP (LCCC)

203 PINS

0.9

UNIT

Active micromirror array resistance to TP1 °C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the

Recommended Operating Conditions

. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .



DLP7000UV


11

DLP7000UV


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7.6 Electrical Characteristics

V

IH

V

IL

I

IL

I

IH

I

CC

I

CCI

I

CC2

P

D

Z

IN over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)

V

OH

V

OL

V

MBRST

I

OZ

PARAMETERS

High-level output voltage

See

Figure 10

(1)

,

Low-level output voltage

See

Figure 10

(1)

,

Clocking Pulse Waveform applied to

MBRST[29:0] Input Pins (supplied by DLPA200)

High impedance output current

(1)

V

CC

= 3.0 V,

V

CC

= 3.6 V,

TEST CONDITIONS

I

OH

= –20 mA

I

OH

= 15 mA

MIN

2.4

-27

TYP MAX

0.4

26.5

UNIT

V

V

V

I

OH

I

OL

Z

LINE

C

I

C

O

C

IM

High-level output current

(1)

Low-level output current

(1)

High-level input voltage

(1)

Low-level input voltage

(1)

Low-level input current

(1)

High-level input current

(1)

Current into V

CC pin

Current into V

CCI pin

(2)

Current into V

CC2 pin

Power dissipation

Internal differential impedance

Line differential impedance (PWB,

Trace)

Input capacitance

(1)

Output capacitance

(1)

Input capacitance for MBRST[0:15] pins

V

CC

= 3.6 V

V

OH

= 2.4 V, V

CC

≥ 3 V

V

OH

= 1.7 V, V

CC

≥ 2.25 V

V

OL

= 0.4 V, V

CC

≥ 3 V

V

OL

= 0.4 V, V

CC

≥ 2.25 V

V

CC

= 3.6 V,

V

CC

= 3.6 V,

V

CC

= 3.6 V,

V

CCI

= 3.6 V

V

CC2

= 8.75 V f = 1 MHz f = 1 MHz f = 1 MHz

V

I

= 0 V

V

I

= V

CC

1.7

–0.3

95

90

220

2.0

10

–20

–15

15

14

µA mA mA

VCC + .3

0.7

–60

V

V

µA

200 µA

1475 mA

450 mA

25 mA

W

105 Ω

100 110

10

10

270

Ω pF pF pF

(1) Applies to LVCMOS pins only.

(2) Exceeding the maximum allowable absolute voltage difference between V

CC

Absolute Maximum Ratings

for details.

and V

CCI may result in excess current draw. See the

12



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7.7 LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted); see

Figure 1

DLP7000UV

DLPS061C – MAY 2015 – REVISED SEPTEMBER 2015 t w t s f

DCLK_* t c t h t skew

DCLK_* clock frequency {where * = [A, or B]}

Clock cycle - DLCK_*

Pulse width - DLCK_*

Setup time - D_*[15:0] and SCTRL_* before DCLK_*

Hold time, D_*[15:0] and SCTRL_* after DCLK_*

Skew between bus A and B

MIN

200

2.5

.35

.35

–1.25

NOM

1.25

MAX

400

1.25

UNIT

MHz ns ns ns ns ns

DCLK_AN

DCLK_AP

t h t s t c t h t s

SCTRL_AN

SCTRL_AP

D_AN(15:0)

D_AP(15:0)

DCLK_BN

DCLK_BP

t h t s t c t h t s

SCTRL_BN

SCTRL_BP

D_BN(15:0)

D_BP(15:0)

Figure 1. LVDS Timing Waveforms



DLP7000UV


13

DLP7000UV


7.8 LVDS Waveform Requirements


Figure 2

|V

ID

|

V

CM

V

LVDS t r t r

Input differential voltage (absolute difference)

Common mode voltage

LVDS voltage

Rise time (20% to 80%)

Fall time (80% to 20%)

V

LVDS

(v)

V

LVDSmax

V

LVDSmax

= V

CM

+ |½V |

T f

(20% - 80%)

MIN

100

0

100

100

V

LVDS

= V

CM

+/- | 1/2 V

ID

|

V

CM

NOM

400

1200

V

ID

www.ti.com

MAX

600

2000

400

400

UNIT

mV mV mV ps ps

V

LVDS min

T r

(20% - 80%)

V

LVDS min

= 0

Figure 2. LVDS Waveform Requirements

Time

14



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DLP7000UV


7.9 Serial Control Bus Timing Requirements


Figure 3

and

Figure 4

f

SCP_CLK t

SCP_SKEW t

SCP_DELAY t

SCP_EN t

_SCP t f_SCP

SCP clock frequency

Time between valid SCP_DI and rising edge of SCP_CLK

Time between valid SCP_DO and rising edge of SCP_CLK

Time between falling edge of SCP_EN and the first rising edge of

SCP_CLK

Rise time for SCP signals

Fall time for SCP signals

MIN

50

–300

30

NOM MAX

500

300

960

200

200

UNIT

kHz ns ns ns ns ns t c f clock

= 1 / t c

SCPCLK 50% 50% t

SCP_SKEW

SCPDI 50% t

SCP_DELAY

SCPD0 50%

Figure 3. Serial Communications Bus Timing Parameters

t r_SCP t f_SCP

SCP_CLK,

SCP_DI,

SCP_EN

Input Controller V

CC

V

CC

/2

0 v

Figure 4. Serial Communications Bus Waveform Requirements



DLP7000UV


15

DLP7000UV


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7.10 Systems Mounting Interface Loads

Maximum system mounting interface load to be applied to the:

PARAMETER

Thermal interface area (see

Figure 5 )

Electrical interface area

Datum A Interface area (see

Figure 5

)

(1)

MIN NOM MAX UNIT

111 N

423

400

N

N

(1) Combined loads of the thermal and electrical interface areas in excess of Datum A load shall be evenly distributed outside the Datum A area (423+ 111 – Datum A).

Figure 5. System Interface Loads

16



DLP7000UV


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7.11 Micromirror Array Physical Characteristics

DLP7000UV


M

N

P

Number of active columns

Number of active rows

Micromirror (pixel) pitch

Micromirror active array width

Micromirror active array height

Micromirror active border

M × P

N × P

Pond of micromirror (POM)

(1)

See

Figure 6

VALUE

1024

768

13.68

14.008

10.506

10

UNIT

micromirrors micromirrors

µm mm mm micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.

2

3

0

1

DMD Active Array

M x N Micromirrors

N

±

4

N

±

3

N

±

2

N

±

1

M x P

Pond of micromirrors (POM) omitted for clarity.

Details omitted for clarity.

Not to scale.

P

P

P

P

Refer to

Micromirror Array Physical Characteristics

for M, N, and P specifications.

Figure 6. Micromirror Array Physical Characteristics

N x P



DLP7000UV


17

DLP7000UV


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7.12 Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters.

a

PARAMETER

Micromirror tilt angle

β Micromirror tilt angle tolerance

(1) (4) (6) (7) (8)

Micromirror crossover time

(9)

Micromirror switching time at 400 MHz with global reset

(10)

TEST CONDITIONS

DMD parked state

Figure 12

(1) (2) (3)

, See

DMD landed state

See

Figure 12

(1) (4) (5)

See

Figure 12

MIN

–1

43

NOM

0

12

16

MAX

1

22

UNIT

degrees degrees

µs

µs

Non operating micromirrors

(11)

Non-adjacent micromirrors

Adjacent micromirrors

10

0 micromirrors

Orientation of the micromirror axis-of-rotation

(12)

See

Figure 11

44 45 46 degrees

Micromirror array optical efficiency

(13) (14)

363 to 420 nm, with all micromirrors in the ON state

66%

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Parking the micromirror array returns all of the micromirrors to an essentially flat (0

˚) state (as measured relative to the plane formed by the overall micromirror array).

(3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.

(4) Additional variation exists between the micromirror array and the package datums, as shown in the

Mechanical, Packaging, and

Orderable Information

.

(5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 will result in a micromirror landing in an nominal angular position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.

(6) Represents the landed tilt angle variation relative to the Nominal landed tilt angle.

(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.

(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some

System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast variations.

(9) Micromirror Cross Over time is primarily a function of the natural response time of the micromirrors.

(10) Micromirror switching is controlled and coordinated by the DLPC410 ( DLPS024 ) and DLPA200 ( DLPS015 ). Nominal Switching time depends on the system implementation and represents the time for the entire micromirror array to be refreshed.

(11) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.

(12) Measured relative to the package datums B and C, shown in the

Mechanical, Packaging, and Orderable Information

(13) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:

– Illumination wavelength, bandwidth/line-width, degree of coherence

– Illumination angle, plus angle tolerance

– Illumination and projection aperture size, and location in the system optical path

– IIlumination overfill of the DMD micromirror array

– Aberrations present in the illumination source and/or path

– Aberrations present in the projection path

The specified nominal DMD optical efficiency is based on the following use conditions:

– Visible illumination (363 to 420 nm)

– Input illumination optical axis oriented at 24° relative to the window normal

– Projection optical axis oriented at 0° relative to the window normal

– f / 3.0 illumination aperture

– f / 2.4 projection aperture

18

Based on these use conditions, the nominal DMD optical efficiency results from the following four components:

– Micromirror array fill factor: nominally 92%

– Micromirror array diffraction efficiency: nominally 85%

– Micromirror surface reflectivity: nominally 88%




DLP7000UV

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DLP7000UV


– Window transmission: nominally 98% for wavelengths 363nm to 420nm, applies to all angles 0° to 30° AOI (Angle of Incidence)

(single pass, through two surface transitions)

(14) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.

7.13 Window Characteristics

PARAMETER

(1)

Window material designation Corning 7056

Window refractive index

Window flatness

(2)

Window artifact size

Window aperture

Illumination overfill

Window transmittance, single–pass through both surfaces and glass

(5)

CONDITIONS

At wavelength 589 nm

Per 25 mm

Within the Window Aperture

(3)

See

(4)

Refer to

Illumination Overfill

Within the wavelength range 363nm to 420nm. Applies to all angles 0 to 30 AOI

MIN TYP MAX UNIT

1.487

98%

4 fringes

400 µm

(1) See

Window Characteristics and Optics

for more information.

(2) At a wavelength of 632.8 nm.

(3) See the section at the end of this document for details regarding the size and location of the window aperture.

(4) For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical

ICD in the Mechanical, Packaging, and Orderable Information section.

(5) See the TI application report Wavelength Transmittance Considerations for DMD Window, DLPA031 .

7.14 Chipset Component Usage Specification

The DLP7000UV is a component of one or more DLP® chipsets. Reliable function and operation of the

DLP7000UV requires that it be used in conjunction with the other components of the applicable DLP® chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP® DMD.



DLP7000UV


19

DLP7000UV


8 Detailed Description

www.ti.com

8.1 Overview

Optically, the DLP7000UV consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors

(micromirrors), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows (

Figure 11

). Each aluminum micromirror is approximately 13.68 microns in size (see the Micromirror Pitch in

Figure 11 ), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are

measured relative to a 0° flat state, which is parallel to the array plane (see

Figure 12 ). The tilt direction is

perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The On State landed position is directed towards Row 0, Column 0 (upper left) corner of the device package (see the Micromirror

Hinge-Axis Orientation in

Figure 11 ). In the field of visual displays, the 1024 by 768 pixel resolution is referred to

as XGA.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the micromirror clocking pulse is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror

clocking pulse will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell followed by a micromirror clocking pulse will result in the corresponding micromirror switching to a

–12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the

CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array

(depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a

DLPA200, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of active border micromirrors.

The pond of micromirror (POM) is not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array.

Figure 7

shows a DLPC410 and DLP7000UV Chipset Block Diagram. The DLPC410 and DLPA200 control and coordinate the data loading and micromirror switching for reliable DLP7000UV operation. The DLPR410 is the programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset components, see

Application and Implementation

. For a typical system application using the DLP Discovery

4100 chipset including the DLP7000UV, see

Figure 19

.

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8.2 Functional Block Diagram

DLP7000UV


DLP7000UV

Figure 7. DLPC410 and DLP7000UV Chipset Block Diagram

•

•

•

8.3 Feature Description

DMD

DLP7000UV - 0.7” XGA

Table 1. DLPC410 DMD Types Overview

ARRAY

1024 × 768

PATTERNS/s

32552

(1)

DATA RATE (Gbs)

25.6

(1) This is for single block mode resets.

Figure 7

is a simplified system block diagram showing the use of the following components:

•

DLPC410

DLPR410

DLPA200

DLP7000UV

MIRROR PITCH

13.6

μm

– Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200 timing and control

– [XCF16PFSG48C] serial flash PROM contains startup configuration information

(EEPROM)

– DMD micromirror driver for the DLP7000UV DMD

– Spatial Light Modulator (DMD)



DLP7000UV


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8.3.1 DLPC410 Controller

The DLP7000UV chipset includes the DLPC410 controller which provides a high-speed LVDS data and control interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in response to the inputs on the control interface.

For more information, see the DLPC410 data sheet ( DLPS024 ).

8.3.2 DLPA200 DMD Micromirror Driver

DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200 is required for DLP7000UV.

For more information on the DLPA200, see the DLPA200 data sheet ( DLPS015 ).

8.3.3 Flash Configuration PROM

The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be altered. For more information, see the DLPC410 data sheet ( DLPS024 ) and DLPR410 data sheet ( DLPS027 ).

8.3.4 DMD

8.3.4.1 DLP7000UV Chipset Interfaces

This section will describe the interface between the different components included in the chipset. For more information on component interfacing, see

Application and Implementation

.

8.3.4.1.1

DLPC410 Interface Description

8.3.4.1.1.1

DLPC410 IO

Table 2

describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the

DLPC410 data sheet.

PIN NAME

ARST

CLKIN_R

DIN_[A,B,C,D](15:0)

DCLKIN[A,B,C,D]

DVALID[A,B,C,D]

ROWMD(1:0)

ROWAD(10:0)

BLK_AD(3:0)

BLK_MD(1:0)

PWR_FLOAT

DMD_TYPE(3:0)

RST_ACTIVE

INIT_ACTIVE

VLED0

VLED1

Table 2. Input/Output Description

DESCRIPTION

Asynchronous active low reset

Reference clock, 50 MHz

LVDS DDR input for data bus A,B,C,D (15:0)

LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D

LVDS input used to start write sequence for bus A, B, C, and D

DMD row address and row counter control

DMD row address pointer

DMD mirror block address pointer

DMD mirror block reset and clear command modes

Used to float DMD mirrors before complete loss of power

DMD type in use

Indicates DMD mirror reset in progress

Initialization in progress.

System heartbeat signal

Denotes initialization complete

I/O

I

I

I

I

I

I

I

I

I

I

O

O

O

O

O

8.3.4.1.1.2

Initialization

The INIT_ACTIVE (

Table 2

) signal indicates that the DLP7000UV, DLPA200, and DLPC410 are in an initialization state after power is applied. During this initialization period, the DLPC410 is initializing the

DLP7000UV and DLPA200 by setting all internal registers to their correct states. When this signal goes low, the system has completed initialization. System initialization takes approximately 220 ms to complete. Data and command write cycles should not be asserted during the initialization.

22




DLP7000UV

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DLP7000UV


During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to correctly align the data inputs to the data clock. For more information, see the DLPC410 data sheet – Interface

Training Pattern.

8.3.4.1.1.3

DMD Device Detection

The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (

Table 2

) is an output from the

DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the automatic detection function. All other DMDs do not operate with the DLPC410.

8.3.4.1.1.4

Power Down

To ensure long term reliability of the DLP7000UV, a shutdown procedure must be executed. Prior to power removal, assert the PWR_FLOAT (

Table 2 ) signal and allow approximately 300 µs for the procedure to

complete. This procedure assures the mirrors are in a flat state.

8.3.4.2 DLPC410 to DMD Interface

8.3.4.2.1

DLPC410 to DMD IO Description

Table 3

lists the available controls and status pin names and their corresponding signal type, along with a brief functional description.

PIN NAME

DDC_DOUT_[A,B,C,D](15:0)

DDC_DCLKOUT_[A,B,C,D]

DDC_SCTRL_[A,B,C,D]

Table 3. DLPC410 to DMD I/O Pin Descriptions

DESCRIPTION

LVDS DDR output to DMD data bus A,B,C,D (15:0)

LVDS output to DMD data clock A,B,C,D

LVDS DDR output to DMD data control A,B,C,D

I/O

O

O

O



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8.3.4.2.2

Data Flow

Figure 8

shows the data traffic through the DLPC410. Special considerations are necessary when laying out the

DLPC410 to allow best signal flow.

LVDS BUS D

s

DIN_D(15:0) s

DCLK_D s

DVALID_D

LVDS BUS A

s

DOUT_A(15:0) s

DCLKOUT_A sSCTRL_A

DLPC410

LVDS BUS C

s

DIN_C(15:0) s

DCLK_C s

DVALID_C

LVDS BUS D

s

DOUT_D(15:0) s

DCLKOUT_D sSCTRL_D

Figure 8. DLPC410 Data Flow

Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the

DLPC410 (DVALID).

Output LVDS buses transfer data from the DLPC410 to the DLP7000UV. Output buses LVDS A and LVDS B are used as highlighted in

Figure 8 .

8.3.4.3 DLPC410 to DLPA200 Interface

8.3.4.3.1

DLPA200 Operation

The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD requirements.

The DLPA200 operates from a +12 volt power supply input. For more detailed information on the DLPA200, see the DLPA200 data sheet.

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DLP7000UV


8.3.4.3.2

DLPC410 to DLPA200 IO Description

The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000UV.

DLPA200

SCP bus

DLPC410

SCP bus

DLPA200

(Only with 1080p DMD)

Figure 9. Serial Port System Configuration

There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ .

Table 4

lists the available controls and status pin names and their corresponding signal type, along with a brief functional description.

A_SCPEN

PIN NAME

A_STROBE

A_MODE(1:0)

A_SEL(1:0)

A_ADDR(3:0)

B_SCPEN

B_STROBE

B_MODE(1:0)

B_SEL(1:0)

B_ADDR(3:0)

Table 4. DLPC410 to DLPA200 I/O Pin Descriptions

DESCRIPTION

Active low chip select for DLPA200 serial bus

DLPA200 control signal strobe

DLPA200 mode control

DLPA200 select control

DLPA200 address control

Active low chip select for DLPA200 serial bus (2)

DLPA200 control signal strobe (2)

DLPA200 mode control

DLPA200 select control

DLPA200 address control

O

O

O

O

O

I/O

O

O

O

O

O

The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0],

SEL[1:0] and reset group address A[3:0] (

Table 4

). The MODE[1:0] input determines whether a single output, two outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror

Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle.

8.3.4.4 DLPA200 to DLP7000UV Interface Overview

The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by regulators.

The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the

DMD type to determine the appropriate Micromirror Clocking Pulse waveform.



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A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror

Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state regardless of the address while a new address is set up, after which the mirror can be driven to a new latched state.

A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as off although the light is likely to be more than a mirror latched in the off state. System designers should carefully evaluate the impact of relaxed mirror conditions on optical performance.

8.3.5 Measurement Conditions

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

Figure 10

shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise and fall transition timing parameters are referenced to V

IL

MIN for output clocks.

MAX and V

IH

MIN for input clocks, V

OL

MAX and V

OH

LOAD CIRCUIT

From Output

Under Test

R

L

Tester

Channel

Figure 10. Test Load Circuit for AC Timing Measurements

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Package Pin

A1 Corner

Incident

Illumination

DMD

Micromirror

Array

0

Active Micromirror Array

(Border micromirrors eliminated for clarity)

DLP7000UV


Details Omitted For Clarity.

Not To Scale.

N ± 1

Micromirror Pitch

P (um)

Micromirror Hinge-Axis Orientation

³2Q 6WDWH´

Tilt Direction

45°

³2II 6WDWH´

Tilt Direction

P (um)

Figure 11. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation



27


DLP7000UV

DLP7000UV


Incident

Illumination

Package Pin

A1 Corner

Incident

Illumination

DLP7000UV www.ti.com

Two

“On-State”

Micromirrors

Two

“Off-State”

Micromirrors

a

± b

Illu m in a tio

In n

-L c id e n ig h t t

Pa th

Illu m in a tio n

-L ig h t

In c id e n t

Pa th

Silicon Substrate

“On-State”

Micromirror

“Off-State”

Micromirror

Path

Off-State-Light

-a

± b

For Reference

Flat-State

( “parked” )

Micromirror Position

Silicon Substrate

Figure 12. Micromirror Landed Positions and Light Paths

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8.4 Device Functional Modes

DLP7000UV


8.4.1 DMD Operation

The DLP7000UV has only one functional mode, it is set to be highly optimized for low latency and high speed in generating mirror clocking pulses and timings.

When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000UV can be operated in several display modes. The DLP7000UV is loaded as 16 blocks of 48 rows each.

Figure 13 ,

Figure 14 ,

Figure 15 , and Figure 16

show how the image is loaded by the different Micromirror Clocking Pulse modes.

There are four Micromirror Clocking Pulse modes that determine which blocks are reset when a Micromirror

Clocking Pulse command is issued:

• Single block mode

• Dual block mode

• Quad block mode

• Global mode

8.4.1.1 Single Block Mode

In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset to transfer the information to the mechanical state of the mirrors.

Data Loaded

Figure 13. Single Block Mode

8.4.1.2 Dual Block Mode

In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of the mirrors.

Data Loaded Reset

Figure 14. Dual Block Mode



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Device Functional Modes (continued)

8.4.1.3 Quad Block Mode

In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the information to the mechanical state of the mirrors.

Data Loaded Reset

Figure 15. Quad Block Mode

8.4.1.4 Global Mode

In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of the mirrors.

Reset

Data Loaded

Figure 16. Global Mode

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8.5 Window Characteristics and Optics

DLP7000UV


NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously.

8.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections.

8.5.2 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.

8.5.3 Pupil Match

TI recommends the exit pupil of the illumination is nominally centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

8.5.4 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.



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8.6 Micromirror Array Temperature Calculation

Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture, and the temperature gradient between case temperature and the predicted micromirror array temperature. (See

Figure 17

).

See the

Recommended Operating Conditions

for applicable temperature limits.

8.6.1 Package Thermal Resistance

The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the specified operational temperatures, refer to

Figure 17 . The total heat load on the DMD is

typically driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array.

8.6.2 Case Temperature

The temperature of the DMD case can be measured directly. For consistency, Thermal Test Point locations 1, 2, and 3 are defined, as shown in

Figure 17

.

INCIDENT

LIGHT

1

A

1

A

2

2

1

ARRAY

2

3

(10.16 [.400])

Figure 17. Thermal Test Point Location

3X (15.88 [.625])

3

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DLP7000UV


Micromirror Array Temperature Calculation (continued)

8.6.3 Micromirror Array Temperature Calculation

Active array temperature cannot be measured directly; therefore, it must be computed analytically from measurement points on the outside of the package, package thermal resistance, electrical power, and illumination heat load. The relationship between array temperature and the reference ceramic temperature (test point number 3 in

Figure 17 ) is provided by the following equations:

T

Array

= Measured Ceramic temperature at location (test point number 3) + (Temperature increase due to power incident to the array × array-to-ceramic resistance) (1)

T

Array

= T

Ceramic

+ (Q

Array

× R

Array-To-Ceramic

) where

• T

Ceramic

= Measured ceramic temperature (°C) at location (test point number 3)

• R

Array-To-Ceramic

= DMD package thermal resistance from array to outside ceramic (°C/W)

• Q

Array

= Total DMD array power, which is both electrical plus absorbed on the DMD active array (W)

• Q

Array

= Q

Electrical

+ (Q

Illumination

× DMD absorption constant (0.42)) where

• Q

Electrical

= Approximate nominal electrical internal power dissipation (W)

• Q

Illumination

= [Illumination power density × illumination area on DMD] (W)

• DMD absorption constant = 0.42

(2)

The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. The nominal electrical power dissipation of the DMD is variable and depends on the operating state of mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the active array, 11.9% on the array border, and 4.4% on the window aperture. A system aperture may be required to limit power incident on the package aperture since this area absorbs much more efficiently than the array.

Sample Calculation:

• Illumination power density = 2 W/cm

2

• Illumination area = (1.4008 cm × 1.0506 cm) / 83.7% = 1.76 cm

2

16.3% overfill)

(assumes 83.7% on the active array and

• Q

Illumination

= 2 W/cm

2

× 1.76 cm

2

= 3.52 W

• Q

Electrical

= 2.0 W

• R

Array-To-Ceramic

= 0.9 °C/W

• T

Ceramic

= 20°C (measured on ceramic)

• Q

Array

= 2.0 W + (3.52 W × 0.42) = 3.48 W

• T

Array

= 20°C + (3.48 W × 0.9°C/W) =23.1°C (3)



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8.7 Micromirror Landed-On/Landed-Off Duty Cycle

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8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages) always add to 100.

8.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical.

8.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life.

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle.

8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in

Table 5 .

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DLP7000UV


Table 5. Grayscale Value and Landed Duty Cycle

GRAYSCALE VALUE

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

LANDED DUTY CYCLE

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0



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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

www.ti.com

9.1 Application Information

The DLP7000UV devices require they be coupled with the DLPC410 controller to provide a reliable solution for many different applications. The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection collection optic.

Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC410. Applications of interest include lithography, 3D Printing, medical systems, and compressive sensing.

9.1.1 DMD Reflectivity Characteristics

TI assumes no responsibility for end-equipment reflectivity performance. Achieving the desired end-equipment reflectivity performance involves making trade-offs between numerous component and system design parameters. DMD reflectivity characteristics over UV exposure times are represented in

Figure 18 .

100

90

80

70

60

50

40

30

20

10

0

0 10000 20000 30000

Exposure Hours

40000

20 q C

25 q C

30 q C

50000

D001

2.3 W/cm

2

, 363 to 400 nm

Figure 18. Nominal DMD Relative Reflectivity Percentage and Exposure Hours

DMD reflectivity includes micromirror surface reflectivity and window transmission. The DMD was characterized for DMD reflectivity using a broadband light source (200-W metal-halide lamp). Data is based off of a 2.3-W/cm

2

UV exposure at the DMD surface (363-nm peak output) using a 363-nm high-pass filter between the light source and the DMD. (Contact your local Texas Instruments representative for additional information about power density measurements and UV filter details.)

9.1.2 Design Considerations Influencing DMD Reflectivity

Optimal, long-term performance of the digital micromirror device (DMD) can be affected by various application parameters. Below is a list of some of these application parameters and includes high level design recommendations that may help extend relative reflectivity from time zero:

• Illumination spectrum – using longer wavelengths for operation while preventing shorter wavelengths from striking the DMD

• Illumination power density – using lower power density

• DMD case temperature – operating the DMD with the case temperature at the low end of its specification

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Application Information (continued)

• Cumulative incident illumination – limiting the total hours of UV illumination exposure when the DMD is not actively steering UV light in the application. For example, a design might include a shutter to block the illumination or LED illumination where the LEDs can be strobed off during periods not requiring UV exposure.

• Micromirror landed duty cycle – applying a 50/50 duty cycle pattern during periods where operational patterns are not required.

9.2 Typical Application

DLP7000UV


OPTICAL

SENSOR

(CAMERA)

LED

DRIVERS

LEDS

OPTICS

USER

INTERFACE

CONNECTIVITY

(USB, ETHERNET, ETC.)

VOLATILE and

NON-VOLATILE

STORAGE

USER - MAIN

PROCESSOR / FPGA

LED

SENSORS

LVDS BUS (A,B)

DDC_DCLK, DVALID, DDC_DIN(15:0)

ROW and BLOCK SIGNALS

ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ

CONTROL SIGNALS

COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT

DLPC410 INFO SIGNALS

RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,

DMD_TYPE(3:0), DDC_VERSION(2:0)

DLPR410

PGM SIGNALS

PROM_CCK_DDC, PROGB_DDC,

PROM_DO_DDC, DONE_DDC, INTB_DDC

OSC

50 MHz

JTAG

ARSTZ

CLKIN_R

DLPC410

LVDS BUS (A,B)

DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)

SCP BUS

SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, A_SCPENZ

DLPA200 CONTROL

A_MODE(1:0), A_SEL(1:0),

A_ADDR(3:0), OEZ, INIT

DLPA200

A

MBRST1_(15:0)

VLED0

VLED1

DMD_RESET

DLP7000UV

~

POWER MANAGMENT

Figure 19. DLPC410 and DLP7000UV Embedded Example Block Diagram

9.2.1 Design Requirements

All applications using the DLP7000UV chipset require both the controller and the DMD components for operation.

The system also requires an external parallel flash memory device loaded with the DLPC410 Configuration and

Support Firmware. The chipset has several system interfaces and requires some support circuitry. The following interfaces and support circuitry are required:

• DLPC410 system interfaces:

– Control interface

– Trigger interface

– Input data interface

– Illumination interface

– Reference clock

• DLP7000UV interfaces:

– DLPC410 to DLP7000UV digital data

– DLPC410 to DLP7000UV control interface

– DLPC410 to DLP7000UV micromirror reset control interface

– DLPC410 to DLPA200 micromirror driver

– DLPA200 to DLP7000UV micromirror reset

Device Description:

The DLP7000UV XGA chipset offers developers a convenient way to design a wide variety of industrial, medical, telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data, and light patterns.



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Typical Application (continued)

The DLP7000UV XGA chipset includes the following four components: DMD Digital Controller (DLPC410),

EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000UV).

DLPC410 DMD Digital Controller

• Provides high speed LVDS data and control interface to the DLP7000UV.

• Drives mirror clocking pulse and timing information to the DLPA200.

• Supports random row addressing.

DLPR410 EEPROM

• Contains startup configuration information for the DLPC410.

DLPA200 DMD Micromirror Driver

• Generates Micromirror Clocking Pulse control (sometimes referred to as a Reset) of DMD mirrors.

DLP7000UV: DMD

• Steers light in two digital positions (+12° and –12°) using 1024 × 768 micromirror array of aluminum mirrors.

Table 6. DLP Discovery 4100 Chipset Configurations: 0.7 XGA Chipset

QTY

1

1

1

1

TI PART

DLP7000UV

DLPC410

DLPR410

DLPA200

DESCRIPTION

0.7 UV XGA Type A DMD

DLP Discovery 4100 DMD controller

DLP Discovery 4100 configuration PROM

DMD micromirror driver

Reliable function and operation of DLP7000UV XGA chipsets require the components be used in conjunction with each other. This document describes the proper integration and use of the DLP7000UV XGA chipset components.

The DLP7000UV XGA chipset can be combined with a user programmable Application FPGA (not included) to create high performance systems.

9.2.2 Detailed Design Procedure

The DLP7000UV DMD is designed with a window which allows transmission of Ultra-Violet (UV) light. This makes it well suited for UV applications requiring fast, spatially programmable light patterns using the micromirror array. UV wavelengths can affect the DMD differently than visible wavelengths. There are system level considerations which should be leveraged when designing systems using this DMD.

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9.2.3 Application Curve

100

40

30

20

60

50

90

80

70

DLP7000UV


UV AOI = 0 o

10

0

300 320 340 360 380 400 420

Wavelength (nm)

440 460 480 500

Type A UVA on 7056 glass (3-mm thick)

Figure 20. Corning 7056 Nominal UV Window Transmittance (Maximum Transmission Region)



DLP7000UV


39

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10 Power Supply Recommendations

www.ti.com

10.1 Power-Up Sequence (Handled by the DLPC410)

The sequence of events for DMD system power-up is:

1. Apply logic supply voltages to the DLPA200 and to the DMD according to DMD specifications.

2. Place DLPA200 drivers into high impedance states.

3. Turn on DLPA200 bias, offset, or reset supplies according to driver specifications.

4. After all supply voltages are assured to be within the limits specified and with all micromirror clocking pulse operations logically suspended, enable all drivers to either VOFFSET or VBIAS level.

5. Begin micromirror clocking pulse operations.

Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.

The DLP7000UV power-up and power-down procedures are defined by the DLPC410 data sheet ( DLPS024 ).

These procedures must be followed to ensure reliable operation of the device.

11 Layout

11.1 Layout Guidelines

The DLP7000UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These guidelines are targeted at designing a PCB board with these components.

11.1.1 Impedance Requirements

Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs

(DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across each pair.

11.1.2 PCB Signal Routing

When designing a PCB board for the DLP7000UV controlled by the DLPC410 in conjunction with the DLPA200, the following are recommended:

Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2

Memory, DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces should not crossover slots in adjacent power and/or ground planes.

SIGNAL

LVDS (DMD_DAT_xnn,

DMD_DCKL_xn, and

DMD_SCTRL_xn)

Table 7. Important Signal Trace Constraints

CONSTRAINTS

P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle

<2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)

Trace width: 4 mil (0.1 mm)

Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)

Maximum recommended trace length <6 inches (150 mm)

SIGNAL NAME

GND

VCC, VCC2

MBRST[15:0]

Table 8. Power Trace Widths and Spacing

MINIMUM TRACE MINIMUM TRACE

WIDTH SPACING

Maximize 5 mil (0.13 mm)

20 mil (0.51 mm)

10 mil (0.25 mm)

10 mil (0.25 mm)

10 mil (0.25 mm)

LAYOUT REQUIREMENTS

Maximize trace width to connecting pin as a minimum

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DLP7000UV

www.ti.com

DLP7000UV


11.1.3 Fiducials

Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

11.1.4 PCB Layout Guidelines

A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal layers.

11.1.4.1 DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS signals should have 100Ω differential impedance. The differential signals should be matched but kept as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not necessary.

11.1.4.1.1

Trace Length Matching

The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of

100 Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal

DMD routing must be considered in this calculation.

11.1.4.2 DLP7000UV Decoupling

General decoupling capacitors for the DLP7000UV should be distributed around the PCB and placed to minimize the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is discouraged. The power and ground pads of the DLP7000UV should be tied to the voltage and ground planes with their own vias.

11.1.4.2.1

Decoupling Capacitors

Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors meet the following guidelines:

• The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be tied to the voltage or ground plane through separate vias.

• The trace lengths of the voltage and ground connections for decoupling capacitors and components should be less than 0.1 inch to minimize inductance.

• The trace width of the power and ground connection to decoupling capacitors and components should be as wide as possible to minimize inductance.

• Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance and improve noise performance.

• Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

11.1.4.3 VCC and VCC2

The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND pads of the DMD should be tied to the VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the distance from the VCC2 and ground pads of the DMD. Using wide etch from the decoupling capacitors to the

DMD connection will reduce inductance and improve decoupling performance.



41


DLP7000UV

DLP7000UV


11.1.4.4 DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.

www.ti.com

11.1.4.5 DLPA200

The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the

DLPA200 (MBRST[15:0]) should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil.

The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet ( DLPS015 ) for mechanical package and layout information.

11.2 Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the dashed lines,

Figure 21

shows correct matching of signal pair lengths with serpentine sections to maintain the correct impedance.

Figure 21. Mitering LVDS Traces to Match Lengths

42



DLP7000UV


www.ti.com

12 Device and Documentation Support

DLP7000UV


12.1 Device Support

12.1.1 Device Nomenclature

Figure 22

provides a legend of reading the complete device name for any DLP device.

Figure 22. Device Nomenclature

12.1.1.1 Device Marking

The device marking consists of the fields shown in

Figure 23

.

TI Internal Numbering

2-Dimensional Matrix Code

(DMD Part Number and

Serial Number)

Part 1 of Serial Number

(7 characters)

YYYYYYY

DLP7000UVFLP

GHXXXXX LLLLLLM

LLLLLL

TI Internal Numbering

Figure 23. Device Marking

DMD Part Number

Part 2 of Serial Number

(7 characters)

12.2 Documentation Support

12.2.1 Related Documentation

The following documents contain additional information related to the use of the DLP7000UV device:

Table 9. Related Documentation

DOCUMENT TITLE

DLPC410 Digital Controller data sheet

DLPA200 DMD Micromirror Driver data sheet

DLPR410 EEPROM data sheet

DOCUMENT LINK

DLPS024

DLPS015

DLPS027



DLP7000UV


43

DLP7000UV


www.ti.com

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use .

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

44



DLP7000UV


PACKAGE OPTION ADDENDUM

www.ti.com

2-Oct-2015

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

DLP7000UVFLP ACTIVE LCCC FLP 203 1 Green (RoHS

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

W NIAU N / A for Pkg Type

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

Samples

www.ti.com

PACKAGE OPTION ADDENDUM

2-Oct-2015

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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