Si5350B B
S i 5 3 5 0 B -B
F ACTORY - P ROGRAMMABLE A NY - F REQUENCY CMOS
C L O C K G ENERATOR + V C X O
Features










www.silabs.com/custom-timing

Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each

output (0 ppm error)
Highly linear VCXO gain (kv)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ 
Configurable Spread Spectrum
selectable at each output

User-configurable control pins:
Output Enable (OEB_0/1/2)

Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)

Supports static phase offset

Rise/fall time control
Operates from a low-cost, fixed
frequency AT-cut, non-pullable
crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
(25 mA, core, typ)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation




20-QFN
Ordering Information:
See page 20
Applications




10-MSOP
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350B combines a clock generator and VCXO function into a single device. A
flexible architecture enables this user definable custom timing device to generate
any of the specified output frequencies from either the internal PLL or the VCXO.
This allows the Si5350B to replace multiple crystals, crystal oscillators, and VCXOs.
Custom pin-controlled Si5350B devices can be requested using the ClockBuilder
web-based part number utility: www.silabs.com/ClockBuilder.
Functional Block Diagram
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5350B-B
Si5350B-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
I2C or Pin
Frequency Reference
Programmed?
Outputs
Datasheet
Si5351A-B-GT
I2C
XTAL only
Blank
3
Si5351-B
Si5351A-B-GM
I2C
XTAL only
Blank
8
Si5351-B
Si5351B-B-GM
I2C
XTAL and/or Voltage
Blank
8
Si5351-B
Si5351C-B-GM
I2C
XTAL and/or CLKIN
Blank
8
Si5351-B
Si5351A-Bxxxxx-GT
I2C
XTAL only
Factory Pre-Programmed
3
Si5351-B
Si5351A-Bxxxxx-GM
I2C
XTAL only
Factory Pre-Programmed
8
Si5351-B
Si5351B-Bxxxxx-GM
I2C
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5351-B
Si5351C-Bxxxxx-GM
I2C
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5351-B
Si5350A-Bxxxxx-GT
Pin
XTAL only
Factory Pre-Programmed
3
Si5350A-B
Si5350A-Bxxxxx-GM
Pin
XTAL only
Factory Pre-Programmed
8
Si5350A-B
Si5350B-Bxxxxx-GT
Pin
XTAL and/or Voltage
Factory Pre-Programmed
3
Si5350B-B
Si5350B-Bxxxxx-GM
Pin
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5350B-B
Si5350C-Bxxxxx-GT
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
3
Si5350C-B
Si5350C-Bxxxxx-GM
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5350C-B
Notes:
1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5350B-B
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Si5350B Replaces Multiple Clocks and XOs 9
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Configuring the Si5350B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4. Voltage Control Input (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.0
3
Si5350B-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
TA
Core Supply Voltage
VDD
Output Buffer Voltage
Test Condition
VDDOx
Min
Typ
Max
Unit
–40
25
85
°C
3.0
3.3
3.60
V
2.25
2.5
2.75
V
1.71
1.8
1.89
2.25
2.5
2.75
3.0
3.3
3.60
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Core Supply Current*
Output Buffer Supply Current
(Per Output)*
Input Current
Output Impedance
Symbol
Test Condition
Min
Typ
Max
Unit
Enabled 3 outputs
—
20
30
mA
Enabled 8 outputs
—
25
40
mA
Power Down (PDN = VDD)
—
—
50
µA
IDDOx
CL = 5 pF
—
2.2
5.6
mA
IP0-P3
Pins P0, P1, P2, P3
VP0-P3 < 3.6 V
—
—
10
µA
IVC
VC
—
—
30
µA
ZOI
3.3 V VDDO, default high
drive
—
50
—

IDD
*Note: Output clocks less than or equal to 100 MHz.
4
Rev. 1.0
Si5350B-B
Table 4. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
0
VDD/2
VDD
V
VCXO Control Voltage Range
Vc
VCXO Gain (configurable)
kv
Vc = 10–90% of VDD
18
—
150
ppm/V
VCXO Control Voltage Linearity
KVL
Vc = 10–90% of VDD
–5
—
+5
%
VCXO Pull Range
(configurable)*
PR
VDD = 3.3 V
Vc = 10–90% of VDD
±30
0
±240
ppm
—
10
—
kHz
VCXO Modulation Bandwidth
Power-Up Time
TRDY
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
2
10
ms
Power-Up Time, PLL Bypass
Mode
TBYP
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
0.5
1
ms
TOE
From OEB assertion to valid
clock output, CL = 5 pF,
fCLKn > 1 MHz
—
—
10
µs
Output Frequency Transition
Time
TFREQ
fCLKn > 1 MHz
—
—
10
µs
Spread Spectrum Frequency
Deviation
SSDEV
Down spread. Selectable in
0.1% steps.
–0.1
—
–2.5
%
Spread Spectrum Modulation
Rate
SSMOD
30
31.5
33
kHz
Output Enable Time
*Note: Contact Silicon Labs for VCXO operation at 2.5 V.
Table 5. Input Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Crystal Frequency
Symbol
Test Condition
fXTAL
VC Input Resistance
Min
Typ
Max
Units
25
—
27
MHz
100
—
—
k
P0-P3 Input Low Voltage
VIL_P0-3
–0.1
—
0.3 x VDD
V
P0-P3 Input High Voltage
VIH_P0-3
0.7 x VDD
—
3.60
V
Rev. 1.0
5
Si5350B-B
Table 6. Output Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Frequency Range
Symbol
1
Load Capacitance
Duty Cycle
Min
Typ
Max
Units
0.0025
—
200
MHz
FCLK < 100 MHz
—
—
15
pF
FCLK  160 MHz, measured
at VDD/2
45
50
55
%
FCLK  160 MHz, measured
at VDD/2
40
50
60
%
20% - 80%, CL = 5 pF
—
1
1.5
ns
FCLK
CL
DC
Rise/Fall Time
Test Condition
tr/tf
Output High Voltage
VOH
VDD – 0.6
—
—
V
Output Low Voltage
VOL
—
—
0.6
V
—
40
95
70
155
50
90
70
150
50
95
Period Jitter2,3
Cycle-to-Cycle Jitter2,3
Period Jitter,
VCXO2,3
Cycle-to-Cycle Jitter,
VCXO2,3
JPER
JCC
JPER_VCXO
JCC_VCXO
20-QFN, 4 outputs running,
1 per VDDO
10-MSOP or 20-QFN,
all outputs running
—
20‐QFN, 4 outputs running, 1 per VDDO
—
ps pk-pk
ps pk
10-MSOP or 20-QFN,
all outputs running
—
20-QFN, 4 outputs running,
1 per VDDO
—
10-MSOP or 20-QFN,
all outputs running
—
70
155
20-QFN, 4 outputs running,
1 per VDDO
—
50
90
10-MSOP or 20-QFN,
all outputs running
—
70
150
ps pk-pk
ps pk
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,
24.576, 22.5792, 28.322, 125, and 48 MHz.
6
Rev. 1.0
Si5350B-B
Table 7. 25 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
25
—
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150

dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. 27 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
27
—
MHz
Load Capacitance
CL
6
—
12
pF
Equivalent Series Resistance
rESR
—
—
150

Crystal Max Drive Level Spec
dL
100
—
—
µW
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Rev. 1.0
7
Si5350B-B
Table 9. Thermal Conditions
Parameter
Symbol
Test Condition
Thermal Resistance Junction to Ambient
JA
Still Air
Thermal Resistance Junction to Case
JC
Still Air
Package
Value
Unit
10-MSOP
131
°C/W
20-QFN
119
°C/W
20-QFN
16
°C/W
Table 10. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Input Voltage
Temperature Range
Symbol
Test Condition
Value
Unit
VDD_max
–0.5 to 3.8
V
VIN_P0-3 Pins P0, P1, P2, P3
–0.5 to 3.8
V
VIN_VC
VC
–0.5 to (VDD+0.3)
V
VIN_XA/
B
Pins XA, XB
–0.5 to 1.3 V
V
–55 to 150
°C
TJ
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
8
Rev. 1.0
Si5350B-B
2. Typical Application
2.1. Si5350B Replaces Multiple Clocks and XOs
The Si5350B is a clock generation device that provides both synchronous and free-running clocks for applications
where power, board size, and cost are critical. An application where both free-running and synchronous clocks are
required is shown in Figure 1.
XA
OSC
27 MHz
Multi
Synth
0
PLL
Multi
Synth
1
XB
Multi
Synth
2
VCXO
CLK1
48 MHz
CLK2
28.322 MHz
CLK3
Multi
Synth
4
Multi
Synth
5
Si5350B
125 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
Multi
Synth
3
VC
CLK0
74.25 MHz
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Video/Audio
Processor
Figure 1. Example of an Si5350B in an Audio/Video Application
2.2. Applying a Reference Clock at XTAL Input
The Si5350B can be driven with a clock signal through the XA input pin.
VIN = 1 VPP
25/27 MHz
XA
0.1 µF
PLLA
Multi
Synth
1
OSC
XB
Multi
Synth
0
PLLB
Note: Float the XB input while driving
the XA input with a clock
Multi
Synth
N
Figure 2. Si5350B Driven by a Clock Signal
Rev. 1.0
9
Si5350B-B
2.3. HCSL Compatible Outputs
The Si5350B can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair.
ZO = 50 
PLLA
Multi
Synth
0
0
R1
511 
240 
OSC
PLLB
Multi
Synth
1
ZO = 50 
0
R1
511 
240 
Multi
Synth
N
R2
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 3. Si5350B Output is HCSL Compatible
10
R2
Rev. 1.0
HCSL
CLKIN
Si5350B-B
3. Functional Description
The Si5350B features a high-frequency PLL, a high-frequency VCXO and a high-resolution fractional MultiSynthTM
divider on each output. A block diagram of both the 3-output and the 8-output clock generators are shown in
Figure 4. Free-running clocks are generated from the on-chip oscillator + PLL, and a separate voltage controlled
oscillator (VCXO) is used to generate synchronous clocks. A fixed-frequency non-pullable standard AT-cut crystal
provides frequency stability for both the internal oscillator and VCXO. The flexible synthesis architecture of the
Si5350B generates up to eight non-integer related frequencies and any combination of free-running and/or
synchronous clocks.
10-MSOP
XA
OSC
VDDO
VDD
MultiSynth 0
F1_0
PLL
F2_0
XB
R0
CLK0
R1
CLK1
R2
CLK2
FS
MultiSynth 1
F1_1
VCXO
VC
F2_1
FS
P0
MultiSynth 2
F1_2
Control
Logic
F2_2
FS
MultiSynth 3
GND
VDD
20-QFN
MultiSynth 0
F1_0
XA
OSC
PLL
F2_0
VDDOA
R0
CLK0
FS
XB
MultiSynth 1
F1_1
VCXO
VC
F2_1
CLK1
R1
FS
MultiSynth 2
F1_2
F2_2
VDDOB
R2
CLK2
FS
MultiSynth 3
F1_3
F2_3
CLK3
R3
FS
MultiSynth 4
F1_4
F2_4
VDDOC
R4
CLK4
FS
MultiSynth 5
F1_5
P0
P1
P2
F2_5
Control
Logic
CLK5
R5
FS
VDDOD
MultiSynth 6
F1_6
P3
R6
CLK6
MultiSynth 7
F1_7
CLK7
R7
GND
Figure 4. Block Diagram of the 3 and 8 Output Si5350B Devices
Rev. 1.0
11
Si5350B-B
4. Configuring the Si5350B
The Si5350B is a factory-programmed custom clock generator that is user definable with a simple to use webbased utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that
allows the user to enter input and output frequencies along with other custom features as described in the following
sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum
configuration. A unique part number is assigned to each custom configuration.
4.1. Crystal Inputs (XA, XB)
The Si5350B uses a fixed-frequency non-pullable standard AT-cut crystal as a reference to synthesize its output
clocks and to provide the frequency stability for the VCXO.
4.1.1. Crystal Frequency
The Si5350B can operate using either a 25 MHz or a 27 MHz crystal.
4.1.2. Internal XTAL Load Capacitors
Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the
Si5350B. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8, or 10 pF. XTALs with
alternate load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by
using  4 pF capacitors on XA and XB) as shown in Figure 5.
XA
XB
Optional internal
load capacitance
0, 6, 8,10 pF
Optional additional
external load
capacitance
(< 2 pF)
Figure 5. External XTAL with Optional Load Capacitors
4.2. Output Clocks (CLK0–CLK7)
The Si5350B is orderable as a 3-output (10-MSOP) or 8-output (20-QFN) clock generator. Output clocks CLK0 to
CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency
select pins (FS0/1). See “4.3.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency
select pins. Each output clock can select its reference either from the PLL or from the VCXO.
4.2.1. Output Clock Frequency
Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKs4-7).
4.2.2. .Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB or to the VCXO.
The Si5350B supports several levels of spread spectrum allowing the designer to choose an ideal compromise
between system performance and EMI compliance. An optional spread spectrum enable pin (SSEN) is
configurable to enable or disable the spread spectrum feature. See “4.3.1. Spread Spectrum Enable (SSEN)” for
12
Rev. 1.0
Si5350B-B
details.
Reduced
Am plitude
and EM I
Center
Frequency
Am plitude
fc
fc
No Spread
Spectrum
D ow n Spread
Figure 6. Available Spread Spectrum Profiles
4.2.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.2.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350B as described in “4.3.4. Output Enable
(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as one of the
following: disable low, disable high, or disable in high-impedance.
4.2.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.3. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
4.3.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.3.2. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350B to minimize power consumption when its
output clocks are not being used. The Si5350B is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on
page 4.
4.3.3. Frequency Select (FS_0, FS_1)
The Si5350B offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either freerunning or synchronous clocks. This is a useful feature for applications that need to support more than one freerunning or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select
which frequency is generated from the clock output. In this example FS0 selects the output frequency on CLK0,
and FS1 selects the frequency on CLK1.
Rev. 1.0
13
Si5350B-B
27 MHz
FS0
Bit Level
F1_0:
74.25 MHz
1
F2_0:
74.25
MHz
1.001
FS1
Bit Level
XA
Free-running Frequency
0
XB
FS0
F1_1:
24.576 MHz
1
F2_1:
22.5792 MHz
Si5350B
FS1
Synchronous Frequency
0
CLK0
Free-running Clock
74.25
MHz
1.001
74.25 MHz or
Synchronous Clock
CLK1
24.576 MHz or 22.5792 MHz
Video/Audio
Processor
VC
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
Up to two frequency select pins are available on the Si5350B. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible. The frequency select feature is not available for CLKs 6 and 7.
The Si5350B uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Customizable FS Control
FS
FS
FS_0 Output Frequency
0
F1_0, F1_3, F1_5
1
F2_0, F2_3, F2_5
FS_0
FS
FS
FS
FS_1 Output Frequency
0
F1_1, F1_2, F1_4
1
F2_1, F2_2, F2_4
FS_1
FS
Glitchless Frequency Changes
MultiSynth 0
CLK0
MultiSynth 1
CLK1
MultiSynth 2
CLK2
MultiSynth 3
CLK3
MultiSynth 4
CLK4
MultiSynth 5
CLK5
New frequency starts
at its leading edge
Frequency_A
Frequency_B
Frequency_A
CLKx
Cannot be controlled
by FS pins
CLK6
Full cycle completes before
changing to a new frequency
CLK7
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
14
Rev. 1.0
Si5350B-B
4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350B. Similar to the FS pins, each OEB pin can
be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,
and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and
CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin
forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Customizable OEB Control
Glitchless Output Enable
CLK0
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB
OEB_0
CLK1
OEB
Clock starts on the
first leading edge
CLK2
OEB
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
Clock continues until
cycle is complete
CLK3
OEB_1
CLKx
OEB
CLK4
OEBx
OEB
CLK5
OEB
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
CLK6
OEB_2
OEB
CLK7
OEB
Figure 9. Example Configuration of a Pin-Controlled Output Enable
Rev. 1.0
15
Si5350B-B
4.4. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, lowcost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5350B include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 5 for VCXO specification details.
A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 10.
XA
Control VC
Voltage
XB
Fixed Frequency
Crystal (non-pullable)
OSC
Multi
Synth
0
R0
CLK0
VCXO
Multi
Synth
1
R1
CLK1
Multi
Synth
2
R2
CLK2
The clock frequency
generated from CLK0 is
controlled by the VC input
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
Figure 10. Using the Si5350B as a Multi-Output VCXO
4.4.1. Control Voltage Gain (kV)
The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency
(kv) is configurable from 18 ppm/V up to 150 ppm/V. This allows a configurable pull range from ±30 ppm to
±240 ppm @ VDD = 3.3 V as shown in Figure 11. Consult the factory for other pull range values.
A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of
PLL stability and jitter performance over the entire control voltage range.
Pull-in Range
@ VDD = 3.3 V
1000
750
pm/V
250 p
kv =
ppm/V
kv = 150
/V
ppm
6
kv =
500
f (ppm)
250
10
0
-10
VDD
2
-250
-500
-750
-1000
VC (Volts)
Figure 11. User-definable VCXO Pull Range
16
Rev. 1.0
VDD
Si5350B-B
4.5. Design Considerations
The Si5350B is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.5.1. Power Supply Decoupling/Filtering
The Si5350B has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor
should be mounted as close to the VDD and VDDO pins as possible without using vias.
4.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
4.5.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
4.5.4. External Crystal Load Capacitors
The Si5350B provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
4.5.5. Unused Pins
Unused control pins (P0–P4) should be tied to GND.
Unused voltage control pin should be tied to GND.
Unused output pins (CLK0–CLK7) should be left floating.
4.5.6. Trace Characteristics
The Si5350B features various output drive strength settings. It is recommended to configure the trace
characteristics as shown in Figure 12 when the default high output drive setting is used.
ZO = 50 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Figure 12. Recommended Trace Characteristics with Default Drive Strength Setting
Rev. 1.0
17
Si5350B-B
5. Pin Descriptions
XA
1
XB
2
VDD
CLK4
VDDOC
CLK5
CLK6
20
19
18
17
16
5.1. 20-pin QFN
15 CLK7
GND
PAD
14
VDDOD
13
CLK0
CLK1
VDDOB 10
9
11 VDDOA
CLK2
5
8
P1
CLK3
12
7
4
P3
P0
6
3
P2
VC
Figure 13. Si5350B 20-QFN Top View
Table 11. Si5350B 20-QFN Pin Descriptions
Pin Name
Pin
Number
Pin Type*
Function
XA
1
I
Input pin for external XTAL
XB
2
I
Input pin for external XTAL
VC
3
I
VCXO control voltage input
CLK0
13
O
Output clock 0
CLK1
12
O
Output clock 1
CLK2
9
O
Output clock 2
CLK3
8
O
Output clock 3
CLK4
19
O
Output clock 4
CLK5
17
O
Output clock 5
CLK6
16
O
Output clock 6
CLK7
15
O
Output clock 7
P0
4
I
User configurable input pin 0
P1
5
I
User configurable input pin 1
P2
6
I
User configurable input pin 2
P3
7
I
User configurable input pin 3
VDD
20
P
Core voltage supply pin
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7
GND
Center Pad
P
Ground
*Note: Pin Types: I = Input, O = Output, P = Power.
18
Rev. 1.0
Si5350B-B
5.2. 10-Pin MSOP
VDD
1
10
CLK0
XA
2
9
CLK1
XB
3
8
GND
VC
4
7
VDDO
P0
5
6
CLK2
Figure 14. Si5350B 10-MSOP Top View
Table 12. Si5350B 10-MSOP Pin Descriptions
Pin Name
Pin Number
Pin Type*
Function
XA
2
I
Input pin for external XTAL
XB
3
I
Input pin for external XTAL
Vc
4
I
VCXO control voltage input
CLK0
10
O
Output clock 0
CLK1
9
O
Output clock 1
CLK2
6
O
Output clock 2
P0
5
I
User configurable input pin 0
VDD
1
P
Core voltage supply pin
VDDO
7
P
Output supply pin for CLK0, CLK1, and CLK2
GND
8
P
Ground
*Note: Pin Types: I = Input, O = Output, P = Power.
Rev. 1.0
19
Si5350B-B
6. Ordering Information
Factory programmed Si5350B devices can be requested using the ClockBuilder web-based utility available at:
www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in
Figure 15.
Si5350B
BXXXXX
XXX
Blank = Bulk
R = Tape and Reel
GT =10-MSOP
GM =20-QFN
B
= Product Revision B
XXXXX = Unique Custom Code
. A five character code will be
assigned for each unique custom configuration
Evaluation Boards
Si535x‐B20QFN‐EVB
For evaluation of Si5350B‐Bxxxxx‐GM (20 QFN)
Figure 15. Custom Clock Part Numbers
20
Rev. 1.0
Si5350B-B
7. Package Outline
7.1. 20-pin QFN
Seating Plane
Figure 16 illustrates the package details for the Si5350B-B. Table 13 lists the values for the dimensions shown in
the illustration.
C
D2
B
D
A
D2/2
A1
L
E
E2
E2/2
b
A
e
Figure 16. 20-pin QFN Package Drawing
Rev. 1.0
21
Si5350B-B
Table 13. Package Dimensions
Dimension
A
Min
0.80
Nom
0.85
Max
0.90
A1
0.00
—
0.05
b
D
D2
e
E
E2
L
0.20
0.30
2.65
0.35
0.25
4.00 BSC
2.70
0.50 BSC
4.00 BSC
2.70
0.40
2.75
0.45
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
2.65
2.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
22
Rev. 1.0
Si5350B-B
8. Land Pattern: 20-Pin QFN
Figure 17 shows the recommended land pattern details for the Si5350 in a 20-Pin QFN package. Table 14 lists the
values for the dimensions shown in the illustration.
Figure 17. 20-Pin QFN Land Pattern
Rev. 1.0
23
Si5350B-B
Table 14. PCB Land Pattern Dimensions
Symbol
Millimeters
C1
4.0
C2
4.0
E
0.50 BSC
X1
0.30
X2
2.70
Y1
0.80
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters
(mm) unless otherwise noted.
2. This land pattern design is based on IPC7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask
defined (NSMD). Clearance between the
solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm
(5 mils).
6. The ratio of stencil aperture to land pad size
should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on
1.30 mm pitch should be used for the center
ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is
recommended.
9. The recommended card reflow profile is per
the JEDEC/IPC J-STD-020 specification for
Small Body components.
24
Rev. 1.0
Si5350B-B
8.1. 10-pin MSOP
Figure 18 illustrates the package details for the Si5350B-B. Table 15 lists the values for the dimensions shown in
the illustration.
Figure 18. 10-pin MSOP Package Drawing
Rev. 1.0
25
Si5350B-B
Table 15. 10-MSOP Package Dimensions
Dimension
A
A1
A2
b
c
D
E
E1
e
L
L2
q
aaa
bbb
ccc
ddd
Min
—
0.00
0.75
0.17
0.08
Nom
—
—
0.85
—
—
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.25 BSC
—
—
—
—
—
0.40
0
—
—
—
—
Max
1.10
0.15
0.95
0.33
0.23
0.80
8
0.20
0.25
0.10
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
26
Rev. 1.0
Si5350B-B
9. Land Pattern: 10-Pin MSOP
Figure 19 shows the recommended land pattern details for the Si5350B-B in a 10-Pin MSOP package. Table 16
lists the values for the dimensions shown in the illustration.
Figure 19. 10-Pin MSOP Land Pattern
Rev. 1.0
27
Si5350B-B
Table 16. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
Max
C1
4.40 REF
E
0.50 BSC
G1
3.00
—
X1
—
0.30
Y1
Z1
1.40 REF
—
5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body components.
28
Rev. 1.0
Si5350B-B
10. Top Marking
10.1. 20-Pin QFN Top Marking
Figure 20. 20-Pin QFN Top Marking
10.2. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5350
Line 2 Mark Format:
TTTTTT = Mfg Code*
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
Rev. 1.0
29
Si5350B-B
10.3. 10-Pin MSOP Top Marking
Figure 21. 10-Pin MSOP Top Marking
10.4. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Mold Dimple (Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5350
Line 2 Mark Format:
TTTT = Mfg Code*
Line 2 from the “Markings” section of the Assembly
Purchase Order form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
30
Rev. 1.0
Si5350B-B
DOCUMENT CHANGE LIST
Revision 0.75 to Revision 1.0









Extended frequency range from 8 MHz–160 MHz to
2.5 MHz–200 MHz.
Updated block diagrams for clarity.
Added complete Si5350/1 family table, Table 1.
Added top mark information.
Added land pattern drawings.
Added PowerUp Time, PLL Bypass mode, Table 4.
Clarified Down Spread step sizes in Table 4.
Updated max jitter specs (typ unchanged) in Table 6.
Clarified power supply sequencing requirement,
Section 4.5.2.
Rev. 1.0
31
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
Quality
Support and Community
www.silabs.com/CBPro
www.silabs.com/quality
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations
thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising