Intel 82575EB Gigabit Ethernet Controller Design Guide

The Intel® 82575EB is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This document provides design data for specific features. The document discusses the general design considerations for Ethernet controllers, how to design with the 82575EB, the power supplies required, and the layout guidelines for the Ethernet component.

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Intel 82575EB Gigabit Ethernet Controller Design Guide | Manualzz

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Key features

  • Two Integrated Gigabit Ethernet MACs
  • Two Integrated Gigabit Ethernet PHYs
  • PCI Express x4, x2, or x1 support
  • Supports 1000BASE-T, 100BASE-TX, and 10BASE-T
  • Wake-on-LAN support
  • Supports both integrated and discrete magnetics
  • Supports EEPROM-less operation
  • Provides both legacy and direct access to the Flash
  • Supports SMBus and NC-SI interfaces
  • Supports DMTF protocol

Frequently asked questions

The 82575EB requires a 25 MHz clock source.

The 82575EB requires three power rails: 3.3 V, 1.8 V, and 1.0 V.

The 82575EB provides three signals for disabling Ethernet functions: LAN0_DIS_N, LAN1_DIS_N, and DEV_OFF_N.

Integrated magnetics are typically easier to integrate into a design, but discrete magnetics offer more flexibility and can sometimes provide better performance.

The 82575EB provides both legacy and direct access to the Flash. Legacy access is through the CPU, while direct access is through the Flash Access Register (FLA).
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