Data Sheet HSMP - 389x & HSMP - 489x Series

Data Sheet HSMP - 389x & HSMP - 489x Series
HSMP - 389x & HSMP - 489x Series
Surface Mount RF PIN Switch Diodes
Data Sheet
Description
Features
The HSMP-389x series is ­ optimized for switching applications where low resistance at low current and low
capacitance are required. The HSMP-489x series products
feature ultra low parasitic inductance. These products are
specifically ­designed for use at frequencies which are much
higher than the upper limit for conventional PIN diodes.
• Unique Configurations in Surface Mount Packages
Pin Connections and Package Marking
– Add Flexibility
– Save Board Space
– Reduce Cost
• Switching
– Low Capacitance
– Low Resistance at Low Current
2
3
GUx
1
6
• Low Failure in Time (FIT) Rate[1]
• Matched Diodes for Consistent Performance
5
4
• Better Thermal Conductivity for Higher Power
Dissipation
• Lead-free Option Available
Notes:
1. Package marking provides orientation, identification, and date
code.
2. See “Electrical Specifications” for appropriate package marking.
Note:
1. For more information see the Surface Mount PIN Reliability Data Sheet.
Package Lead Code Identification,
SOT-23/143 (Top View)
Package Lead Code Identification,
SOT-323 (Top View)
SERIES
SINGLE
#2
#0
COMMON
ANODE
COMMON
CATHODE
#3
UNCONNECTED
TRIO
B
C
COMMON
ANODE
COMMON
CATHODE
E
#4
UNCONNECTED
PAIR
SERIES
SINGLE
Package Lead Code Identification,
SOT-363 (Top View)
6
5
1
2
4
L
3
LOW
INDUCTANCE
SINGLE
6
5
1
2
DUAL ANODE
5
1
2
4
R
3
SERIESÐ
SHUNT PAIR
4
6
5
T
3
1
2
HIGH
FREQUENCY
SERIES
489B
6
5
1
2
4
4890
V
3
ESD WARNING:
Handling Precautions Should Be Taken To Avoid Static Discharge.
Absolute Maximum Ratings[1] TC = +25°C
Symbol
Parameter
Unit
SOT-23/143
SOT-323/363
If
Forward Current (1 µs Pulse)
Amp
1
1
PIV
Peak Inverse Voltage
V
100
100
Tj
Junction Temperature
°C
150
150
Tstg
Storage Temperature
°C
-65 to 150
-65 to 150
θjc
Thermal Resistance[2]
°C/W
500
150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board.
6
4
F
DUAL ANODE
#5
DUAL SWITCH
MODEL
U
3
Electrical Specifications, TC = 25°C, each diode
Part Number
HSMP-
Package
Marking
Code
Lead
Code
Configuration
Minimum
Breakdown
Voltage VBR (V)
Maximum
Series Resistance
RS (Ω)
Maximum
Total Capacitance
CT (pF)
3890
3892
3893
3894
3895
389B
389C
389E
389F
389L
389R
389T
389U
389V
G0
G2
G3
G4
G5
G0
G2
G3
G4
GL
S
Z
GU
GV
0
2
3
4
5
B
C
E
F
L
R
T
U
V
Single
Series
Common Anode
Common Cathode
Unconnected Pair
Single
Series
Common Anode
Common Cathode
Unconnected Trio
Dual Switch Mode
Low Inductance
Single
Series-Shunt Pair
High Frequency
Series Pair
100
2.5
0.30
VR = VBR
Measure
IR ≤ 10 µA
IF = 5 mA
f = 100 MHz
VR = 5 V
f = 1 MHz
Test Conditions
High Frequency (Low Inductance, 500 MHz–3 GHz) PIN Diodes
Part
Number
HSMP-
Package
Marking
Code[1]
Configuration
Minimum
Breakdown
Voltage
VBR (V)
Maximum
Series
Resistance
R S (Ω)
Typical
Total
Capacitance
C T (pF)
Maximum
Total
Capacitance
CT (pF)
Typical
Total
Inductance
LT (nH)
489x
GA
Dual Anode
100
2.5
0.33
0.375
1.0
Test Conditions
VR = VBR
IF = 5 mA
f = 1 MHz
VR = 5 V
Measure
VR = 5 V
f = 1 MHz
IR ≤ 10 µA
f=500 MHz–
3 GHz
Typical Parameters at TC = 25°C
Part Number
HSMP-
Series Resistance
R S (Ω)
Carrier Lifetime
τ (ns)
389x
3.8
200
Test Conditions
IF = 1 mA
f = 100 MHz
IF = 10 mA
IR = 6 mA
Total Capacitance
C T (pF)
0.20 @ 5V
HSMP-389x Series Typical Performance, TC = 25°C, each diode
10
1
0.55
120
0.50
115
INPUT INTERCEPT POINT (dBm)
TOTAL CAPACITANCE (pF)
RF RESISTANCE (OHMS)
100
0.45
0.40
0.35
0.30
1 MHz
0.25
110
Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz
105
100
95
90
1 GHz
0.1
0.01
0.1
1
10
0.20
100
04
16
85
20
11
0
30
IF - FORWARD BIAS CURRENT (mA)
Figure 3. 2nd Harmonic Input Intercept
Point vs. Forward Bias Current.
Figure 2. Capacitance vs. Reverse
Voltage.
Figure 1. Total RF Resistance at 25 C
vs. Forward Bias Current.
100
200
160
IF - FORWARD CURRENT (mA)
T rr - REVERSE RECOVERY TIME (nS)
12
V R - REVERSE VOLTAGE (V)
IF - FORWARD BIAS CURRENT (mA)
V R = - 2V
120
80
V R = - 5V
40
V R = - 10 V
0
10
8
15
20
25
10
1
0.1
0.01
30
FORWARD CURRENT (mA)
125˚ C 25˚C - 50˚C
0
0.2
0.4
0.6
0.8
1.0
1.2
V F - FORWARD VOLTAGE (V)
Figure 5. Forward Current vs. Forward
Voltage.
Figure 4. Typical Reverse Recovery
Time vs. Reverse Voltage.
Typical Applications for Multiple Diode Products
1
2
2
"ON"
"OFF"
3
3
2
1
1
0
4
5
2
1
4
5
6
2
+V
-V
1
6
b1
b2
b3
RF in
Figure 6. HSMP-389L used in a SP3T Switch.
3
1
0
0
RF out
Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation Switch.
Typical Applications for Multiple Diode Products (continued)
1
+V
0
"ON"
"OFF"
2
0
+V
RF out
1
1
6
5
4
1
2
3
6
5
4
12
3
RF out
RF in
RF in
2
Figure 8. HSMP-389L Unconnected Trio used in a Positive
Voltage, High Isolation Switch.
Figure 9. HSMP-389T used in a Low Inductance Shunt
Mounted Switch.
Bias
Xmtr
Bias
Ant
Ant
C
λ
4
Xmtr
λ
4
C
Rcvr
Bias
Rcvr
bias
Antenna
Xmtr
PA
λ
4
LNA
HSMP-389V
λ
4
HSMP-389U
Rcvr
Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz
Transmit/Receive Switch.
Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz
Transmit/Receive Switch.
Typical Applications for Multiple Diode Products (continued)
RF COMMON
RF COMMON
RF 2
RF 1
RF 2
RF 1
BIAS 2
BIAS 1
BIAS
Figure 12. Simple SPDT Switch, Using Only Positive Current.
BIAS
Figure 13. High Isolation SPDT Switch, Dual Bias.
RF COMMON
RF COMMON
BIAS
RF 1
RF 2
RF 2
RF 1
BIAS
Figure 14. Switch Using Both Positive and Negative Bias
Current.
Figure 15. Very High Isolation SPDT Switch, Dual Bias.
Typical Applications for HSMP-489x Low Inductance Series
50 OHM MICROSTRIP LINES
Microstrip Series Connection for HSMP-489x Series
In order to take full advantage of the low inductance of the
HSMP‑489x series when using them in series applications,
both lead 1 and lead 2 should be connected together, as
shown in Figure 17.
3
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
1
2
Figure 18. Circuit Layout.
HSMP-489x
1.5 nH
Figure 16. Internal Connections.
1.5 nH
0.3 pF
0.3 nH
Figure 17. Circuit Layout.
0.3 nH
Microstrip Shunt Connections for HSMP-489x Series
In Figure 18, the center conductor of the microstrip line is
interrupted and leads 1 and 2 of the HSMP-489x diode are
placed across the resulting gap. This forces the 1.5 nH lead
inductance of leads 1 and 2 to appear as part of a low pass
filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt
inductance external to the diode is created by the via holes,
and is a good estimate for 0.032” thick material.
Co-Planar Waveguide Shunt Connection for HSMP-489x Series
Co-Planar waveguide, with ground on the top side of
the printed circuit board, is shown in Figure 20. Since it
eliminates the need for via holes to ground, it offers lower
shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit.
Figure 19. Equivalent Circuit.
Equivalent Circuit Model: HSMP-389x Chip*
Rs
Rj
0.5 Ω
Cj
Co-Planar Waveguide
Groundplane
0.12 pF*
Center Conductor
* Measured at -20 V
Groundplane
RT = 0.5 + Rj
CT = CP + Rj
Rj =
Figure 20. Circuit Layout.
20
I
0.9
Ω
I = Forward Bias Current in mA
* See AN1124 for package models
0.3 pF
0.75 nH
Figure 21. Equivalent Circuit.
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, carrier lifetime.
SMT Assembly
Assembly Information
0.026
0.079
0.039
0.018
Figure 22. Recommended PCB Pad Layout for Avago Technologies’
SC70 6L / SOT-363 Products.
Avago Technologies’ diodes have been qualified to the
time-temperature profile shown in Figure 26. This profile
is representative of an IR reflow type of surface mount
assembly process.
After ramping up from room temperature, the circuit
board with components attached to it (held in place with
solder paste) passes through one or more preheat zones.
The preheat zones increase the temperature of the board
and components to prevent thermal shock and begin
evaporating solvents from the solder paste. The reflow zone
briefly elevates the temperature sufficiently to produce a
reflow of the solder.
0.026
0.079
0.039
0.022
Figure 23. Recommended PCB Pad Layout for Avago Technologies’
SC70 3L / SOT-323 Products.
0.039
1
0.039
1
Reliable assembly of surface mount components is a
complex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reflow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
SOT package, will reach solder reflow temperatures faster
than those with a greater mass.
0.079
2.0
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not cause
deformation of the board or damage to components due
to thermal shock. The maximum temperature in the reflow
zone (TMAX) should not exceed 235°C.
These parameters are typical for a surface mount assembly process for Avago Technologies diodes. As a general
guideline, the circuit board and components should be
exposed only to the minimum temperatures and times
necessary to achieve a uniform reflow of solder.
0.035
0.9
250
T MAX
0.031
0.8
DIMENSIONS IN
inches
mm
Figure 24. Recommended PCB Pad Layout for Avago Technologies’
SOT-23 Products.
0.112
2.85
0.048
1.2
0.114
2.9
0.033
0.85
DIMENSIONS IN
0.033
0.85
inches
mm
Figure 25. Recommended PCB Pad Layout for Avago Technologies’
SOT-143 Products.
Preheat
Zone
Cool Down
Zone
50
60
120
180
TIME (seconds)
0.071
1.8
0.031
0.8
Reflow
Zone
100
0
0.033
0.85
0.047
1.2
150
0
0.079
2
0.061
2.05
TEMPERATURE (˚C)
200
Figure 26. Surface Mount Assembly Profile.
240
300
Package Dimensions
Outline SOT-363 (SC-70 6 Lead)
Symbol
E
D
HE
A
A
A1
Q1
e
b
c
L
Agilent (New)
MIN
MAX
(mm) (mm)
1.1
1.
1.
.
1.
.
0.
1.1
0.
1
0
0.1
0.1
0.
0.0 BCS
0.1
0.
0.1
0.
0.1
0.
Outline SOT-323 (SC-70 3 Lead)
e1
XXX
E
E1
e
L
B
C
D
A
A1
SYMBOL
A
A1
B
C
D
E1
e
e1
E
L
AGILENT
MIN
MAX
0.
1
0
0.1
0.1
0.
0.1
0.
1.
.
1.1
1.
0. typical
1.0 typical
1.
.
0. typical
Outline 23 (SOT-23)
e2
e1
SYMBOL
E
XXX
E1
e
B
C
D
A
A
A1
B
C
D
E1
e
e1
e
E
L
AGILENT
MIN
MAX
0.
1.
0
0.1
0.
0.
0.0
0.1
.
.1
1.1
1.
0.
1.0
1.
.0
0.
0.
.1
.
0.
0.
SYMBOL
A
A1
B
B1
C
D
E1
e
e1
e
E
L
AGILENT
MIN
MAX
0.
1.0
0.01
0.1
0.
0.
0.
0.
0.0
0.1
.
.0
1.
1.
0.
1.0
1.
.0
0.
0.
.1
.
0.
0.
A1
Outline 143 (SOT-143)
e1
E
XXX
E1
C
D
A
A1
10
L
B
e
Device Orientation
For Outlines SOT-23, -323
REEL
TOP VIEW
END VIEW
4 mm
CARRIER
TAPE
8 mm
USER
FEED
DIRECTION
ABC
For Outline SOT-143
ABC
For Outline SOT-363
TOP VIEW
END VIEW
TOP VIEW
4 mm
END VIEW
4 mm
8 mm
ABC
ABC
ABC
ABC
Note: "AB" represents package marking code.
"C" represents date code.
P
P2
D
E
P0
F
W
D1
t1
Ko
9 MAX
13.5 MAX
8 MAX
B0
A0
DESCRIPTION
SYMBOL
ABC
ABC
ABC
ABC
Note: "AB" represents package marking code.
"C" represents date code.
Tape Dimensions and Product Orientation
For Outline SOT-23
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
3.15 ± 0.10
2.77 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00+ 0.05
0.124 ± 0.004
0.109 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 ± 0.002
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 +0.30 –0.10 0.315 +0.012 –0.004
0.229 ±0.013
0.009 ±0.0005
DISTANCE
BETWEEN
CENTERLINE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
3.50 0.05
0.138 ±0.002
P2
2.00 ± 0.05
0.079 ±0.002
11
ABC
Note: "AB" represents package marking code.
"C" represents date code.
COVER TAPE
8 mm
ABC
Tape Dimensions and Product Orientation
For Outline SOT-143
D
P0
P
P2
E
F
W
D1
t1
9˚� MAX
9˚� MAX
K0
A0
B0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
3.19 ± 0.10
2.80 ± 0.10
1.31 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.126 ± 0.004
0.110 ± 0.004
0.052 ± 0.004
0.157 ± 0.004
0.039 + 0.010
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 +0.30 –0.10
0.254 ± 0.013
0.315+0.012 –0.004
0.0100 �± 0.0005
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P2
2.00 ± 0.05
0.079 ± 0.002
For Outlines SOT-323, -363
P
P2
D
P0
E
F
C
t1(CARRIER TAPE THICKNESS)
T t(COVER TAPE THICKNESS)
K0
An
A0
DESCRIPTION
D1
An
B0
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
2.40 ± 0.10
2.40 ± 0.10
1.20 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 ± 0.30
0.254 ± 0.02
0.315 ± 0.012
0.0100 ±0.0008
COVER TAPE
WIDTH
TAPE THICKNESS
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ±0.00004
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
C
Tt
F
3.50 ± 0.05
0.138 ± 0.002
P2
2.00 ± 0.05
0.079 ± 0.002
An
8°�
C MAX
10°�
C MAX
ANGLE
12
FOR SOT-323 (SC70-3 LEAD)
FOR SOT-363 (SC70-6 LEAD)
W
Ordering Information
Specify part number followed by option. For example:
HSMP - 389x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLK = Bulk, 100 pcs. per antistatic bag
-TR1 = Tape and Reel, 3000 devices per 7” reel
-TR2 = Tape and Reel, 10,000 devices per 13” reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated
Placement.”
For lead-free option, the part number will have the character “G” at the end, eg. -TR2G for a 10K pc lead-free reel.
Package Characteristics
Lead Material................................... Copper (SOT-323/363); Alloy 42 (SOT-23/143)
Lead Finish.................................................. Tin-Lead 85-15% (Non lead-free option)
................................................................................................ Tin 100% (Lead-free option)
Maximum Soldering Temperature............................................. 260°C for 5 seconds
Minimum Lead Strength............................................................................ 2 pounds pull
Typical Package Inductance....................................................................................... 2 nH
Typical Package Capacitance...............................................0.08 pF (opposite leads)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-3860EN - March 29, 2006
13
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