datasheet for EN29GL256 by Eon Silicon Solution

datasheet for EN29GL256 by Eon Silicon Solution
EN29GL256H/L
EN29GL256
256 Megabit (32768K x 8-bit / 16384K x 16-bit) Flash Memory
Page mode Flash Memory, CMOS 3.0 Volt-only
FEATURES
• Write operation status bits indicate program
and erase operation completion
• Single power supply operation
- Full voltage range: 2.7 to 3.6 volts read and
write operations
• Support for CFI (Common Flash Interface)
• High performance
- Access times as fast as 90 ns
• Persistent methods of Advanced Sector
Protection
• VIO Input/Output 1.65 to 3.6 volts
- All input levels (address, control, and DQ input
levels) and outputs are determined by voltage
on VIO input. VIO range is 1.65 to VCC
• WP#/ACC input
• 8-word/16-byte page read buffer
- Accelerates programming time (when VHH is
applied) for greater throughput during system
production
• 32-word/64-byte write buffer reduces overall
programming time for multiple-word updates
- Protects first or last sector regardless of
sector protection settings
• Secured Silicon Sector region
- 128-word/256-byte sector for permanent,
secure identification through an 8-word/16byte random Electronic Serial Number
- Can be programmed and locked at the factory
or by the customer
• Hardware reset input (RESET#) resets
device
• Ready/Busy# output (RY/BY#) detects
program or erase cycle completion
• Minimum 100K program/erase endurance
cycles.
• Uniform 64Kword/128KByte Sector
Architecture Two hundred fifty-six sectors
• Package Options
- 56-pin TSOP
- 64-ball 11mm x 13mm BGA
• Suspend and Resume commands for
Program and Erase operations
• Industrial Temperature Range.
GENERAL DESCRIPTION
The EN29GL256 offers a fast page access time of 25 ns with a corresponding random access time as
fast as 90 ns. It features a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed
in one operation, resulting in faster effective programming time than standard programming algorithms.
This makes the device ideal for today’s embedded applications that require higher density, better
performance and lower power consumption.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
CONNECTION DIAGRAMS
Figure 1. 56-pin Standard TSOP (Top View)
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RFU
RFU
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
RFU
VIO
Note: RFU= Reserved for future use
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 2. 64-ball Ball Grid Array (Top View, Balls Facing Down)
A8
B8
C8
RFU
A22
A23
A7
B7
C7
A13
A12
A6
E8
F8
G8
H8
VSS
RFU
RFU
RFU
D7
E7
F7
G7
H7
A14
A15
A16
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
WP# / ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
RFU
RFU
RFU
RFU
RFU
VIO
RFU
RFU
RY / BY#
D8
VIO
BYTE# DQ15 / A -1
VSS
Note: RFU= Reserved for future use
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
TABLE 1. PIN DESCRIPTION
Pin Name
FIGURE 3. LOGIC DIAGRAM
Function
EN29GL256
A23–A0
A23–A0
DQ0-DQ14
Data input/output.
DQ15 / A-1
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
CE#
Chip Enable
OE#
Output Enable
RESET#
Hardware Reset Pin
RY/BY#
Ready/Busy Output
WE#
Write Enable
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
VIO
V I/O Input.
BYTE#
Byte/Word mode selection
WP#/ACC
RFU
DQ0 – DQ15
(A-1)
A0 – A23
CE#
OE#
WE#
Reset#
WP#/ACC
Byte#
VI O
RY/BY#
Write Protect / Acceleration Pin
(WP# has an internal pull-up; when
unconnected, WP# is at VIH.)
Reserved for future use.
Not Connected to anything
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 2. PRODUCT SELECTOR GUIDE
Product Number
EN29GL256
Full Voltage Range: Vcc=2.7 – 3.6 V
VIO=1.65 – 3.6 V
Speed Option
-90
Max Access Time, ns (tacc)
90
Max Page Read Access, ns(tpacc)
25
Max CE# Access, ns (tce)
90
Max OE# Access, ns (toe)
35
BLOCK DIAGRAM
RY/BY#
Vcc
Vss
VIO
DQ0-DQ15 (A-1)
Blo ck Protect Switches
Erase Voltage Gen erator
Inp ut/Output Buffers
State
Control
WE#
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Vcc Detector
Timer
Ad dress Latch
STB
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0 -A23
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Product Overview
EN29GL256 is 256 Mb, 3.0-volt-only, page mode Flash devices optimized for today’s embedded
designs that demand a large storage array and rich functionality. This product offers uniform 64 Kword
(128 KB) uniform sectors and feature V I/O control, allowing control and I/O signals to operate from
1.65 V to VCC. Additional features include:
• Single word programming or a 32-word buffer for an increased programming speed
• Program Suspend/Resume and Erase Suspend/Resume
• Advanced Sector Protection methods for protecting sectors as required
• 128 words/256 bytes of Secured Silicon area for storing customer and factory secured information.
The Secured Silicon Sector is One Time Programmable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 3. Sector / Persistent Protection Sector Group Address Tables
PPB Group
A23-A18
Sector
PPB 0
PPB 1
PPB 2
SA0
000000
PPB 3
PPB 4
PPB 5
PPB 6
PPB 7
PPB 8
PPB 9
PPB 10
PPB 11
PPB 12
PPB 13
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Sector Size
(Kbytes / Kwords)
128/64
Address Range (h)
Word mode (x16)
000000–00FFFF
SA1
128/64
010000–01FFFF
SA2
128/64
020000–02FFFF
SA3
128/64
030000–03FFFF
SA4
128/64
040000–04FFFF
SA5
128/64
050000–05FFFF
SA6
128/64
060000–06FFFF
SA7
128/64
070000–07FFFF
SA8
128/64
080000–08FFFF
SA9
128/64
090000–09FFFF
SA10
128/64
0A0000–0AFFFF
SA11
128/64
0B0000–0BFFFF
SA12
128/64
0C0000–0CFFFF
SA13
128/64
0D0000–0DFFFF
SA14
128/64
0E0000–0EFFFF
SA15
128/64
0F0000–0FFFFF
SA16
128/64
100000–10FFFF
SA17
128/64
110000–11FFFF
SA18
128/64
120000–12FFFF
SA19
128/64
130000–13FFFF
SA20
128/64
140000–14FFFF
SA21
128/64
150000–15FFFF
SA22
128/64
160000–16FFFF
SA23
128/64
170000–17FFFF
SA24
128/64
180000–18FFFF
SA25
128/64
190000–19FFFF
SA26
128/64
1A0000–1AFFFF
SA27
128/64
1B0000–1BFFFF
SA28
128/64
1C0000–1CFFFF
SA29
128/64
1D0000–1DFFFF
SA30
128/64
1E0000–1EFFFF
SA31
128/64
1F0000–1FFFFF
SA32
128/64
200000–20FFFF
SA33
128/64
210000–21FFFF
SA34
128/64
220000–22FFFF
SA35
128/64
230000–23FFFF
SA36
128/64
240000–24FFFF
SA37
128/64
250000–25FFFF
SA38
128/64
260000–26FFFF
SA39
128/64
270000–27FFFF
SA40
128/64
280000–28FFFF
7
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
PPB 14
PPB 15
PPB 16
PPB 17
PPB 18
PPB 19
PPB 20
PPB 21
PPB 22
PPB 23
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
SA41
128/64
290000–29FFFF
SA42
128/64
2A0000–2AFFFF
SA43
128/64
2B0000–2BFFFF
SA44
128/64
2C0000–2CFFFF
SA45
128/64
2D0000–2DFFFF
SA46
128/64
2E0000–2EFFFF
SA47
128/64
2F0000–2FFFFF
SA48
128/64
300000–30FFFF
SA49
128/64
310000–31FFFF
SA50
128/64
320000–32FFFF
SA51
128/64
330000–33FFFF
SA52
128/64
340000–34FFFF
SA53
128/64
350000–35FFFF
SA54
128/64
360000–36FFFF
SA55
128/64
370000–37FFFF
SA56
128/64
380000–38FFFF
SA57
128/64
390000–39FFFF
SA58
128/64
3A0000–3AFFFF
SA59
128/64
3B0000–3BFFFF
SA60
128/64
3C0000–3CFFFF
SA61
128/64
3D0000–3DFFFF
SA62
128/64
3E0000–3EFFFF
SA63
128/64
3F0000–3FFFFF
SA64
128/64
400000–40FFFF
SA65
128/64
410000–41FFFF
SA66
128/64
420000–42FFFF
SA67
128/64
430000–43FFFF
SA68
128/64
440000–44FFFF
SA69
128/64
450000–45FFFF
SA70
128/64
460000–46FFFF
SA71
128/64
470000–47FFFF
SA72
128/64
480000–48FFFF
SA73
128/64
490000–49FFFF
SA74
128/64
4A0000–4AFFFF
SA75
128/64
4B0000–4BFFFF
SA76
128/64
4C0000–4CFFFF
SA77
128/64
4D0000–4DFFFF
SA78
128/64
4E0000–4EFFFF
SA79
128/64
4F0000–4FFFFF
SA80
128/64
500000–50FFFF
SA81
128/64
510000–51FFFF
SA82
128/64
520000–52FFFF
SA83
128/64
530000–53FFFF
8
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
PPB 24
PPB 25
PPB 26
PPB 27
PPB 28
PPB 29
PPB 30
PPB 31
PPB 32
PPB 33
PPB 34
SA84
128/64
540000–54FFFF
SA85
128/64
550000–55FFFF
SA86
128/64
560000–56FFFF
SA87
128/64
570000–57FFFF
SA88
128/64
580000–58FFFF
SA89
128/64
590000–59FFFF
SA90
128/64
5A0000–5AFFFF
SA91
128/64
5B0000–5BFFFF
SA92
128/64
5C0000–5CFFFF
SA93
128/64
5D0000–5DFFFF
SA94
128/64
5E0000–5EFFFF
SA95
128/64
5F0000–5FFFFF
SA96
128/64
600000–60FFFF
SA97
128/64
610000–61FFFF
SA98
128/64
620000–62FFFF
SA99
128/64
630000–63FFFF
SA100
128/64
640000–64FFFF
SA101
128/64
650000–65FFFF
SA102
128/64
660000–66FFFF
SA103
128/64
670000–67FFFF
SA104
128/64
680000–68FFFF
SA105
128/64
690000–69FFFF
SA106
128/64
6A0000–6AFFFF
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
SA107
128/64
6B0000–6BFFFF
SA108
128/64
6C0000–6CFFFF
SA109
128/64
6D0000–6DFFFF
SA110
128/64
6E0000–6EFFFF
SA111
128/64
6F0000–6FFFFF
SA112
128/64
700000–70FFFF
SA113
128/64
710000–71FFFF
SA114
128/64
720000–72FFFF
SA115
128/64
730000–73FFFF
SA116
128/64
740000–74FFFF
SA117
128/64
750000–75FFFF
SA118
128/64
760000–76FFFF
SA119
128/64
770000–77FFFF
SA120
128/64
780000–78FFFF
SA121
128/64
790000–79FFFF
SA122
128/64
7A0000–7AFFFF
SA123
128/64
7B0000–7BFFFF
SA124
128/64
7C0000–7CFFFF
SA125
128/64
7D0000–7DFFFF
SA126
128/64
7E0000–7EFFFF
SA127
128/64
7F0000–7FFFFF
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
PPB 35
PPB 36
PPB 37
PPB 38
PPB 39
PPB 40
PPB 41
PPB 42
PPB 43
PPB 44
PPB 45
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
SA128
128/64
800000–80FFFF
SA129
128/64
810000–81FFFF
SA130
128/64
820000–82FFFF
SA131
128/64
830000–83FFFF
SA132
128/64
840000–84FFFF
SA133
128/64
850000–85FFFF
SA134
128/64
860000–86FFFF
SA135
128/64
870000–87FFFF
SA136
128/64
880000–88FFFF
SA137
128/64
890000–89FFFF
SA138
128/64
8A0000–8AFFFF
SA139
128/64
8B0000–8BFFFF
SA140
128/64
8C0000–8CFFFF
SA141
128/64
8D0000–8DFFFF
SA142
128/64
8E0000–8EFFFF
SA143
128/64
8F0000–8FFFFF
SA144
128/64
900000–90FFFF
SA145
128/64
910000–91FFFF
SA146
128/64
920000–92FFFF
SA147
128/64
930000–93FFFF
SA148
128/64
940000–94FFFF
SA149
128/64
950000–95FFFF
SA150
128/64
960000–96FFFF
SA151
128/64
970000–97FFFF
SA152
128/64
980000–98FFFF
SA153
128/64
990000–99FFFF
SA154
128/64
9A0000–9AFFFF
SA155
128/64
9B0000–9BFFFF
SA156
128/64
9C0000–9CFFFF
SA157
128/64
9D0000–9DFFFF
SA158
128/64
9E0000–9EFFFF
SA159
128/64
9F0000–9FFFFF
SA160
128/64
A00000–A0FFFF
SA161
128/64
A10000–A1FFFF
SA162
128/64
A20000–A2FFFF
SA163
128/64
A30000–A3FFFF
SA164
128/64
A40000–A4FFFF
SA165
128/64
A50000–A5FFFF
SA166
128/64
A60000–A6FFFF
SA167
128/64
A70000–A7FFFF
SA168
128/64
A80000–A8FFFF
SA169
128/64
A90000–A9FFFF
SA170
128/64
AA0000–AAFFFF
SA171
128/64
AB0000–ABFFFF
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
10
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
PPB 46
PPB 47
PPB 48
PPB 49
PPB 50
PPB 51
PPB 52
PPB 53
PPB 54
101011
101100
101101
101110
101111
110000
110001
110010
110011
PPB 55
110100
PPB 56
110101
SA172
128/64
AC0000–ACFFFF
SA173
128/64
AD0000–ADFFFF
SA174
128/64
AE0000–AEFFFF
SA175
128/64
AF0000–AFFFFF
SA176
128/64
B00000–B0FFFF
SA177
128/64
B10000–B1FFFF
SA178
128/64
B20000–B2FFFF
SA179
128/64
B30000–B3FFFF
SA180
128/64
B40000–B4FFFF
SA181
128/64
B50000–B5FFFF
SA182
128/64
B60000–B6FFFF
SA183
128/64
B70000–B7FFFF
SA184
128/64
B80000–B8FFFF
SA185
128/64
B90000–B9FFFF
SA186
128/64
BA0000–BAFFFF
SA187
128/64
BB0000–BBFFFF
SA188
128/64
BC0000–BCFFFF
SA189
128/64
BD0000–BDFFFF
SA190
128/64
BE0000–BEFFFF
SA191
128/64
BF0000–BFFFFF
SA192
128/64
C00000–C0FFFF
SA193
128/64
C10000–C1FFFF
SA194
128/64
C20000–C2FFFF
SA195
128/64
C30000–C3FFFF
SA196
128/64
C40000–C4FFFF
SA197
128/64
C50000–C5FFFF
SA198
128/64
C60000–C6FFFF
SA199
128/64
C70000–C7FFFF
SA200
128/64
C80000–C8FFFF
SA201
128/64
C90000–C9FFFF
SA202
128/64
CA0000–CAFFFF
SA203
128/64
CB0000–CBFFFF
SA204
128/64
CC0000–CCFFFF
SA205
128/64
CD0000–CDFFFF
SA206
128/64
CE0000–CEFFFF
SA207
128/64
CF0000–CFFFFF
SA208
128/64
D00000–D0FFFF
SA209
128/64
D10000–D1FFFF
SA210
128/64
D20000–D2FFFF
SA211
128/64
D30000–D3FFFF
SA212
128/64
D40000–D4FFFF
SA213
128/64
D50000–D5FFFF
SA214
128/64
D60000–D6FFFF
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
PPB 57
PPB 58
PPB 59
PPB 60
PPB 61
PPB 62
PPB 63
PPB 64
PPB 65
110110
110111
111000
111001
111010
111011
111100
111101
111110
PPB 66
PPB 67
PPB 68
PPB 69
111111
SA215
128/64
D70000–D7FFFF
SA216
128/64
D80000–D8FFFF
SA217
128/64
D90000–D9FFFF
SA218
128/64
DA0000–DAFFFF
SA219
128/64
DB0000–DBFFFF
SA9220
128/64
DC0000–DCFFFF
SA221
128/64
DD0000–DDFFFF
SA222
128/64
DE0000–DEFFFF
SA223
128/64
DF0000–DFFFFF
SA224
128/64
E00000–E0FFFF
SA225
128/64
E10000–E1FFFF
SA226
128/64
E20000–E2FFFF
SA227
128/64
E30000–E3FFFF
SA228
128/64
E40000–E4FFFF
SA229
128/64
E50000–E5FFFF
SA230
128/64
E60000–E6FFFF
SA231
128/64
E70000–E7FFFF
SA232
128/64
E80000–E8FFFF
SA233
128/64
E90000–E9FFFF
SA234
128/64
EA0000–EAFFFF
SA235
128/64
EB0000–EBFFFF
SA236
128/64
EC0000–ECFFFF
SA237
128/64
ED0000–EDFFFF
SA238
128/64
EE0000–EEFFFF
SA239
128/64
EF0000–EFFFFF
SA240
128/64
F00000–F0FFFF
SA241
128/64
F10000–F1FFFF
SA242
128/64
F20000–F2FFFF
SA243
128/64
F30000–F3FFFF
SA244
128/64
F40000–F4FFFF
SA245
128/64
F50000–F5FFFF
SA246
128/64
F60000–F6FFFF
SA247
128/64
F70000–F7FFFF
SA248
128/64
F80000–F8FFFF
SA249
128/64
F90000–F9FFFF
SA250
128/64
FA0000–FAFFFF
SA251
128/64
FB0000–FBFFFF
SA252
128/64
FC0000–FCFFFF
SA253
128/64
FD0000–FDFFFF
SA254
128/64
FE0000–FEFFFF
SA255
128/64
FF0000–FFFFFF
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 4. Device OPERATING MODES
256M FLASH USER MODE TABLE
Operation
A0A23
CE#
OE#
WE#
RESET#
WP#/ACC
Read
Write
L
L
L
H
H
L
H
H
L/H
(Note 1)
A IN
A IN
Accelerated
Program
L
H
L
H
V HH
A IN
DQ0DQ7
DQ8-DQ15
BYTE#
BYTE#
= V IH
= V IL
DQ8D OUT
DQ14=
D IN
High-Z,
DQ15 =
D IN
A-1
B
B
B
B
B
B
B
B
D OUT
D IN
B
B
D IN
B
B
B
B
B
B
B
B
B
B
B
B
B
CMOS Standby
V cc
±0.3V
X
X
Vcc±0.3V
H
X
High-Z
High-Z
High-Z
Output Disable
Hardware Reset
L
X
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
B
B
Notes:
1. Addresses are A23:A0 in word mode; A23:A-1 in byte mode.
2. If WP# = VIL, on the outermost sector remains protected. If WP# = VIH, the outermost sector is unprotected. WP# has an
internal pull-up; when unconnected, WP# is at VIH. All sectors are unprotected when shipped from the factory (The Secured
Silicon Sector can be factory protected depending on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm.
Legend
L = Logic Low = VIL, H = Logic High = VIH, VHH = 8.5–9.5V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
13
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EN29GL256H/L
USER MODE DEFINITIONS
Word / Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If
the
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7
are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15
pin is used as an input for the LSB (A-1) address function.
VIO Control
The VIO allows the host system to set the voltage levels that the device generates and tolerates on all
inputs and outputs (address, control, and DQ signals). VIO range is 1.65 to VCC. For example, a VIO of
1.65-3.6 volts allows for I/O at the 1.65 or 3.6 volt levels, driving and receiving signals to and from other
1.65 or 3.6 V devices on the same data bus.
Read
All memories require access time to output array data. In a read operation, data is read from one
memory location at a time. Addresses are presented to the device in random order, and the
propagation delay through the device causes the data on its outputs to arrive with the address on its
inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from
the memory array, the system must first assert a valid address on A23-A0, while driving OE# and CE#
to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear
on DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to
valid output data.The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the
access time (tOE) has elapsed from the falling edge of OE#, assuming the tACC access time has been
meet.
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page
size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits
A23-A3. Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within
a page. The microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as
long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC.
When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE.
Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing
the “intra-read page” addresses.
Autoselect
The Autoselect mode provides manufacturer ID, Device identification, and sector protection information,
through identifier codes output from the internal register (separate from the memory array) on DQ7DQ0.
The device only support to use autoselect command to access autoselect codes. It does not support to
apply VID on address pin A9.
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or modifications due to changes in technical specifications.
14
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EN29GL256H/L
• The Autoselect command sequence may be written to an address within a sector that is either in the
read or erase-suspend-read mode.
• The Autoselect command may not be written while the device is actively programming or erasing.
• The system must write the reset command to return to the read mode (or erase-suspend-read mode
if the sector was previously in Erase Suspend).
• When verifying sector protection, the sector address must appear on the appropriate highest order
address bits. The remaining address bits are don't care and then read the corresponding identifier
code on DQ15-DQ0.
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are
described in detail in the following sections.
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data
is latched on the 1st rising edge of WE# or CE#.
Note the following:
• When the Embedded Program algorithm is complete, the device returns to the read mode.
• The system can determine the status of the program operation by reading the DQ status bits. Refer
to the Write Operation Status on page 25 for information on these status bits.
• An “0” cannot be programmed back to a “1.” A succeeding read shows that the data is still “0.”
• Only erase operations can convert a “0” to a “1.”
• Any commands written to the device during the Embedded Program/Erase are ignored except the
Suspend commands.
• Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is
in progress.
• A hardware reset and/or power removal immediately terminates the Program/Erase operation and
the Program/Erase command sequence should be reinitiated once the device has returned to the
read mode to ensure data integrity.
• Programming is allowed in any sequence and across sector boundaries for single word
programming
operation.
• Programming to the same word address multiple times without intervening erases is permitted.
Single Word Programming
Single word programming mode is one method of programming the Flash. In this mode, four Flash
command write cycles are used to program an individual Flash address. The data for this programming
operation could be 8 or 16-bits wide.
While the single word programming method is supported by most devices, in general Single Word
Programming is not recommended for devices that support Write Buffer Programming.
When the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
reading the DQ status bits.
• During programming, any command (except the Suspend Program command) is ignored.
• The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program
operation is in progress.
• A hardware reset immediately terminates the program operation. The program command sequence
should be reinitiated once the device has returned to the read mode, to ensure data integrity.
• Programming to the same address multiple times continuously (for example, “walking” a bit within a
word) is permitted.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
15
©2004 Eon Silicon Solution, Inc.,
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EN29GL256H/L
Figure 4. Single Word Program
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming
operation. This results in a faster effective word programming time than the standard “word”
programming algorithms. The Write Buffer Programming command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command
written at the Sector Address in which programming occurs. At this point, the system writes the number
of “word locations minus 1” that are loaded into the page buffer at the Sector Address in which
programming occurs. This tells the device how many write buffer addresses are loaded with data and
therefore when to expect the “Program Buffer to Flash” confirm command. The number of locations to
program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the
number of locations to program minus 1. For example, if the system programs 6 address locations, then
05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses A23–A5.
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write
buffer. (This means Write Buffer Programming cannot be performed across multiple “write-bufferpages.” This also means that Write Buffer Programming cannot be performed across multiple sectors. If
the system attempts to load programming data outside of the selected “write-buffer-page”, the operation
ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs
into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter is
decremented for every data load operation. Also, the last data loaded at a location before the “Program
Buffer to Flash” confirm command is the data programmed into the device. It is the software's
responsibility to comprehend ramifications of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT for each unique write-buffer-address location.
Once the specified number of write buffer locations have been loaded, the system must then write the
“Program Buffer to Flash” command at the Sector Address. Any other address/data write combinations
abort the Write Buffer Programming operation. The Write Operation Status bits should be used while
monitoring the last address location loaded into the write buffer. This eliminates the need to store an
address in memory because the system can load the last address location, issue the program confirm
command at the last loaded address location, and then check the write operation status at that same
address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during
Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard
suspend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
• Load a value that is greater than the page buffer size during the “Number of Locations to Program”
step.
• Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
• Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting
Address” during the “write buffer data loading” stage of the operation.
• Writing anything other than the Program to Buffer Flash Command after the specified number of
“data load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”),
DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED.
Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
17
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Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations. These flash
devices are capable of handling multiple write buffer programming operations on the same write buffer
address range without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed.
Figure 5. Write Buffer Programming Operation
This Data Sheet may be revised by subsequent versions
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EN29GL256H/L
Sector Erase
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The Command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All
other commands are ignored. If there are several sectors to be erased, Sector Erase Command
sequences must be issued for each sector. That is, only a sector address can be specified for each
Sector Erase command. Users must issue another Sector Erase command for the next sector to be
erased after the previous one is completed.
When the Embedded Erase algorithm is completed, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by using
DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4
illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for
timing waveforms.
Figure 6. Sector Erase Operation
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN29GL256H/L
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 13. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory to an all zero
data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain
FFFFh. The system is not required to provide any controls or timings during these operations.
When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7 or
DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware
reset immediately terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once that sector has returned to reading array data, to ensure the entire array is
properly erased.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. The sector address is required when
writing this command. This command is valid only during the sector erase operation. The Sector Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm. Addresses are don’t-cares when writing the Sector Erase Suspend command.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The
system can read data from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors
produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended.
After an erase-suspended program operation is complete, the device returns to the erase-suspendread
mode. The system can determine the status of the program operation using write operation status bits,
just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer
to Write Buffer Programming and the Autoselect for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
address of the erase-suspended sector is required when writing this command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written after the chip has
resumed erasing.
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation
or a “Write to Buffer” programming operation so that data can read from any non-suspended sector.
When the Program Suspend command is written during a programming process, the device halts the
programming operation within 15 µs maximum (5 µs typical) and updates the status bits. Addresses are
“don't-cares” when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any
nonsuspended sector. The Program Suspend command may also be issued during a programming
operation while an erase is suspended. In this case, data may be read from any addresses not within a
sector in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
This Data Sheet may be revised by subsequent versions
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EN29GL256H/L
The system may also write the Autoselect Command Sequence when the device is in Program
Suspend
mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not
stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program
Suspend mode, and is ready for another valid operation.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the write operation status bits, just as in the
standard program operation.
The system must write the Program Resume command (address bits are “don't care”) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the device
has resumed programming.
Accelerated Program
Accelerated single word programming and write buffer programming operations are enabled through
the
WP#/ACC pin. This method is faster than the standard program command sequences.
If the system asserts VHH on this input, the device automatically enters the Accelerated Program mode
and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Accelerated Program
mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in Accelerated Program mode, the
full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC
input, upon completion of the embedded program operation, returns the device to normal operation.
• Sectors must be unlocked prior to raising WP#/ACC to VHH.
• The WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device
damage may result.
• It is recommended that WP#/ACC apply VHH after power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from VHH to VIH/VIL before powering down VCC/ VIO .
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid
after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is
valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming.
Reading Data# Polling status on any word other than the last word to be programmed in the writebuffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# polling on DQ7 is active, then that sector returns to the
read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a
“1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
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EN29GL256H/L
After an erase command sequence is written, if all sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid.
Valid data on DQ7-D00 appears on successive read cycles.
Figure 7. Write Operation Status Flowchart
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any
address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the
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EN29GL256H/L
program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
that is being programmed or erased causes DQ6 to toggle. When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase 2suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in
progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use DQ7.
If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the
program command sequence is written, then returns to reading array data. DQ6 also toggles during the
erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change
in state.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for
erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typically, the system would note and store the value
of the toggle bit after the first read. After the second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or
erases operation. The system can read array data on DQ7–DQ0 on the following read cycle. However,
if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high. If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high.
If the toggle bit is no longer toggling, the device has successfully completed the program or erases
operation. If it is still toggling, the device did not complete the operation successfully, and the system
must write the reset command to return to reading array data. The remaining scenario is that the
system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may
continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algorithm when it returns to determine the status of
the operation.
Note
When verifying the status of a write operation (embedded program/erase) of a memory sector, DQ6
and DQ2 toggle between high and low states in a series of consecutive and contiguous status read
cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must
not be interleaved with read accesses to other memory sectors. If it is not possible to temporarily
prevent reads to other memory sectors, then it is recommended to use the DQ7 status bit as the
alternative method of determining the active or inactive status of the write operation.
This Data Sheet may be revised by subsequent versions
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DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not
successfully completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a
location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1.
Under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a
0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed.
Attempting to program a 0 to a 1 is masked during the programming operation. Under valid DQ5
conditions, the system must write the reset command to return to the read mode (or to the erasesuspend-read mode if a sector was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the output on DQ3 can be checked to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support
multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since
it immediately shows as a “1” after the first 30h command. Future devices may support this feature.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces
a “1”. The system must issue the “Write to Buffer Abort Reset” command sequence to return the device
to reading array data.
Table 5. Write Operation Status
DQ7
(note 2)
DQ6
DQ5
(note 1)
DQ3
DQ2
(note 2)
DQ1
RY/BY#
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No
Toggle
0
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Status
Standard
Mode
Program
Suspend
Mode
Erase
Suspend
Mode
Write to
Buffer
Program
Suspend
Read
Erase
Suspend
Read
Program Suspended
Sector
Non-Program
Suspended Sector
Erase Suspended
Sector
Non-Erase
Suspended Sector
No
Toggle
1
Invalid (Not allowed)
1
Data
1
0
N/A
Toggle
N/A
Data
1
0
Erase Suspend Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
0
Busy(note 3)
Abort(note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has
exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate
subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing
an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while
data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector or the
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
24
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
entire device. Table 3 indicate the address space that each sector occupies. The device address space
is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits required to
uniquely select a sector. ICC2 in “DC Characteristics” represents the active current specification for the
write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to VCC. This feature allows the host system to detect when data is
ready to be read by simply monitoring the RY/BY# pin, which is a dedicated output and controlled by
CE# (not OE#).
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately
terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores
all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the
device is ready to accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but
not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which
enables the system to read the boot-up firmware from the Flash memory upon a system reset.
Software Reset
Software reset is part of the command set that also returns the device to array read mode and must be
used for the following conditions:
1. To exit Autoselect mode
2. When DQ5 goes high during write status operation that indicates program or erase cycle was not
successfully completed
3. Exit sector lock/unlock operation.
4. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. After any aborted operations
The following are additional points to consider when using the reset command:
• This command resets the sectors to the read and address bits are ignored.
• Reset commands are ignored during program and erase operations.
• The reset command may be written between the cycles in a program command sequence before
programming begins (prior to the third cycle). This resets the sector to which the system was writing
to the read mode.
• If the program command sequence is written to a sector that is in the Erase Suspend mode, writing
the reset command returns that sector to the erase-suspend-read mode.
• The reset command may be written during an Autoselect command sequence.
• If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that sector to the erase-suspend-read mode.
• If DQ1 goes high during a Write Buffer Programming operation, the system must write the “Write to
Buffer Abort Reset” command sequence to RESET the device to reading array data. The standard
RESET command does not work during this condition.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
25
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware methods,
which are independent of each other. This section describes the various methods of protecting data
stored in the memory array. An overview of these methods in shown in Figure 7.
Figure 7. Advanced Sector Protection/Unprotection
Persistent Protection
Bit (PPB)
Dynamic Protection Bit
(DYB)
Memory Array
DYB 0
Sector 0
PPB 0
DYB 1
Sector 1
PPB 1
DYB 2
Sector 2
PPB 2
DYB 3
Sector 3
PPB 3
DYB 4
Sector 4
DYB 5
Sector 5
DYB 6
Sector 6
DYB 7
Sector 7
DYB 248
Sector 248
DYB 249
Sector 249
DYB 250
Sector 250
DYB 251
Sector 251
DYB 252
Sector 252
PPB 66
DYB 253
Sector 253
PPB 67
DYB 254
Sector 254
PPB 68
DYB 255
Sector 255
PPB 69
PPB Lock Bit
1. 0 = PPBs Locked,
1 = PPBs Unlocked.
2. Bit is volatile, and defaults to
“1” on reset.
3. Programming to “0” locks all
PPBs to their current state.
4. Once programmed to “0”,
requires hardware reset to
unlock.
PPB 4
PPB 65
8. 0 = Sector Protected,
1 = Sector Unprotected.
9. PPBs programmed individually,
but cleared collectively.
10.Sector 0~3 and 252~255 have
PPB for each sector. Sector
4~251 are 1 PPB per 4 sectors.
5. 0 = Sector Protected,
1 = Sector Unprotected.
6. DYB bits are only effective for
sectors that not protected via
PPB locking mechanism.
7. Volatile Bits: defaults to
unprotected after power up.
Lock Register
The Lock Register consists of 4 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent
Protection Mode Lock Bit is DQ1, Persistent Sector Protection OTP bit is DQ3 and DYB Lock Boot Bit is
DQ4. If DQ0 is ‘0’, it means that the Customer Secured Silicon area is locked and if DQ0 is ‘1’, it means
that it is unlocked. When DQ1 is set to ‘0’, the device is used in the Persistent Protection Mode. DQ3 is
programmed in the EON factory. When the device is programmed to disable all PPB erase command,
DQ3 outputs a ‘0’, when the lock register bits are read. Similarly, if the device is programmed to enable
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
26
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
all PPB erase command, DQ3 outputs a ‘1’ when the lock register bits are read. Likewise the DQ4 bit is
also programmed in the EON Factory. DQ4 is the bit which indicates whether Volatile Sector Protection
Bit (DYB) is protected or not after boot-up. When the device is programmed to set all Volatile Sector
Protection Bit protected after power-up, DQ4 outputs a ‘0’ when the lock register bits are read. Similarly,
when the device is programmed to set all Volatile Sector Protection Bit unprotected after power-up,
DQ4 outputs a ‘1’. Each of these bits in the lock register are non-volatile. DQ15- DQ5 are reserved and
will be 1’s.
Table 6. Lock Register
DQ15-5
DQ4
Reserved DYB Lock Boot Bit
DQ3
PPB One Time
Programmable Bit
0 = protected all 0 = All PPB Erase
DYB after boot-up Command disabled
(default = 1) 1 = unprotected all 1 = All PPB Erase
DYB after boot-up Command enabled
(default = 1)
(default = 1)
DQ2
DQ1
DQ0
Reserved
Persistent
Protection Mode
Lock Bit
Secured
Silicon Sector
Protection Bit
0 = protected
0 = Persistent
(default = 1) Protection enabled 1 = unprotect
(default = 1)
(default = 0)
Notes:
1. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for all Sector are disabled,
while reads from other sectors are allowed until exiting this mode.
2. Only DQ0 could be change by Lock Register Bits Command for user. Others bits were set by Factory.
After selecting a sector protection method, each sector can operate in any of the following three states:
1. Constantly locked: The selected sectors are protected and can not be reprogrammed unless PPB
lock bit is cleared via hardware reset, or power cycle.
2. Dynamically locked: The selected sectors are protected and can be altered via software commands.
3. Unlocked: The sectors are unprotected and can be erased and/or programmed.
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile. For Sector 0~3 and 252~255 have one PPB
for each sectors and for Sector 4~251 have one PPB every four sectors (refer to Figure 7 and Table 3.
Sector / Persistent Protection Sector Group Address Tables) and have the same endurances as the
Flash memory. Preprogramming and verification prior to erasure are handled by the device, and
therefore do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for the four sectors and Data polling on programming PPB address, array
data can not be read from any sectors.
3. Entry command disables reads and writes for all sectors selected.
4. Reads within that sector return the PPB status for that sector.
5. All Reads must be performed using the read mode.
6. The specific sector address are written at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out
without programming or erasing the PPB.
8. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
9. Exit command must be issued after the execution which resets the device to read mode and reenables reads and writes for all sectors.
10. The programming state of the PPB for given sectors can be verified by writing a PPB Status Read
Command to the device as described by the flow chart shown in Figure 8. User only can use DQ6
and RY/BY# pin to detect programming status.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
27
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
Figure 8. PPB Program Algorithm
Note: BA = base address
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
28
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Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs
only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to “1”).
By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to “0”) or
cleared (erased to “1”), thus placing each sector in the protected or unprotected state respectively. This
feature allows software to easily protect sectors against inadvertent changes yet does not prevent the
easy removal of protection when changes are needed.
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed. When the
parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset, the
DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectorsmay be
modified depending upon the PPB state of that sector (see Table 7).
3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen
(programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic
state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of
the sectors respectively. However, if there is a need to change the status of the persistently locked
sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting
the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the
desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates
normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early
in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the PPB and DYB
bits have the same function when WP#/ACC = VHH as they do when ACC =VIH.
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to
“0”), it locks all PPBs and when cleared (erased to “1”), allows the PPBs to be changed. There is only
one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit, but only a hardware reset or a power-up clears this
bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the
desired settings.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
29
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
Figure 9. Lock Register Program Algorithm
Advanced Sector Protection Software Examples
Table7. Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
30
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 7 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of
the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed.
The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See
also Figure 7 for an overview of the Advanced Sector Protection feature.
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
• When WP#/ACC is at VIL, the either the highest or lowest sector is locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented
via hardware means. The following subsections describes these methods:
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This
function is provided by the WP#/ACC pin and overrides the previously discussed Sector
Protection/Unprotection
method.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the
highest or lowest sector independently of whether the sector was protected or unprotected using the
method described in Advanced Sector Protection/Unprotection on page 27.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last
set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends
on whether they were last protected or unprotected.
The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal
pull-up; when unconnected, WP# is set at VIH.
Note
If WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is
increased.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must
provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater
than VLKO.
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on power-up.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
31
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Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
Power Conservation Modes
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance
state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and
RESET# inputs are both held at VCC ± 0.3 V. The device requires standard access time (tCE) for read
access, before it is ready to read data. If the device is deselected during erasure or programming, the
device draws active current until the operation is completed. ICC4 in “DC Characteristics” represents
the standby current specification
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new
data when addresses are changed. While in sleep mode, output data is latched and always available to
the system.
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence to
ensure data integrity.
When RESET# is held at VSS ± 0.3 V, the device draws ICC reset current (ICC5). If RESET# is held at
VIL but not within VSS ± 0.3 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high
impedance state. (With the exception of RY/BY#.)
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region. The Secured Silicon Sector is 128
words in length and all Secured Silicon reads outside of the 128-word address range returns invalid
data. The Secured Silicon Sector Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate
whether or not the Secured Silicon Sector is locked when shipped from the factory.
Please note the following general conditions:
• On power-up, or following a hardware reset, the device reverts to sending commands to the normal
address space.
• Reads outside of sector SA0 return memory array data.
• Sector SA0 is remapped from memory array to Secured Silicon Sector array.
• Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
• The Secured Silicon Sector is not accessible when the device is executing an Embedded Program
or Embedded Erase algorithm.
• When sector SA0 is suspended, if system enters Secured Silicon Sector mode, the Secured Silicon
Sector Region cannot be read. If the system suspends the flash in other sectors except SA0,
Secured Silicon Sector Region can be read normally.
• The ACC function is not available when the Secured Silicon Sector is enabled.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
32
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 8. Secured Silicon Sector Addresses
Secured Silicon Sector Address Range
000000h-000007h
Reserve for Factory
000008h-00007Fh
Determined by customer
Customer Lockable Secured Silicon Sector
The Customer Lockable Secured Silicon Sector is always shipped unprotected (DQ0 set to “1”),
allowing customers to utilize that sector in any manner they choose. If the security feature is not
required, the Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
• Once the Secured Silicon Sector area is protected, the Secured Silicon Sector Indicator Bit (DQ0) is
permanently set to “0.”
• The Secured Silicon Sector can be read any number of times, but can be programmed and locked
only once. The Secured Silicon Sector lock must be used with caution as once locked, there is no
procedure available for unlocking the Secured Silicon Sector area and none of the bits in the
Secured Silicon Sector memory space can be modified in any way.
• The accelerated programming (ACC) is not available when the Secured Silicon Sector is enabled.
• Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence which return the device to the memory array at sector 0.
• The address 0h~7h in Secured Silicon Sector is reserved for Factory.
Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region
until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
The Secured Silicon Sector Entry Command allows the following commands to be executed
• Read customer and factory Secured Silicon areas
• Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory
array. This mode of operation continues until the system issues the Exit Secured Silicon Sector
command sequence, or until power is removed from the device.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
33
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array
data.
The system can read CFI information at the addresses given in Tables 9~12.In word mode, the upper
address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in Tables
9~12. The system must write the reset command to return the device to the autoselect mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
34
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Table 9. CFI Query Identification String
Addresses
(Word Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 10. System Interface String
Addresses
(Word Mode)
Data
1Bh
0027h
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0003h
0004h
0009h
0000h
0005h
0005h
0004h
0000h
Description
Vcc Min (write/erase)
DQ7-DQ4: volt, DQ3-DQ0: 100mV
Vcc Max (write/erase)
DQ7-DQ4: volt, DQ3-DQ0: 100mV
Vpp Min voltage (00h = no Vpp pin present)
Vpp Max voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for min size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max timeout for byte/word write 2N times typical
Max timeout for buffer write 2N times typical
Max timeout per individual block erase 2N times typical
Max timeout for full chip erase 2N times typical (00h = not supported)
Table 11. Device Geometry Definition
Addresses
(Word mode)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
Data
0019h
0002h
0000h
0006h
0000h
0001h
00FFh
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Description
Device Size = 2N bytes. 2**25=32MB=256Mb
Flash Device Interface Description (refer to CFI publication 100);
01h = X16 only; 02h = x8/x16
Max number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification of CFI publication 100)
256 uniform sectors (7Fh + 1)
Erase Block Region 3 Information
(refer to the CFI specification of CFI publication 100)
Erase Block Region 3 Information
(refer to the CFI specification of CFI publication 100)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
35
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
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EN29GL256H/L
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification of CFI publication 100)
Table 12. Primary Vendor-specific Extended Query
Addresses
(Word Mode)
40h
41h
42h
43h
44h
Data
0050h
0052h
0049h
0031h
0034h
45h
000Ch
46h
0002h
47h
0001h
Sector Protect
0 = Not Supported, X = Minimum number of sectors per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0003h
Sector Protect/Unprotect Scheme
00h = High Voltage Sector Protection
01h = High Voltage + In-System Sector Protection
02h = HV + In-System + Software Command Sector Protection
03h = Software Command Sector Protection
4Ah
0000h
4Bh
0000h
4Ch
0002h
4Dh
0085h
4Eh
0095h
4Fh
00xxh
50h
0001h
52h
0008h
53h
000Fh
54h
0009h
55h
56h
0005h
0005h
57h
0000h
Description
Query Unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
00 = Required, 01 = Not Required
Technology (Bits 5-2) 0001 = 0.18um, 0010 = 0.13um, 0011 = 90nm
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Simultaneous Operation
00 = Not Supported, X = Number of Sectors
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Minimum WP#/ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4: Volts, DQ3=DQ0: 100mV
Maximum WP#/ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4: Volts, DQ3=DQ0: 100mV
Top/Bottom Boot Sector Flag
04 = Uniform sectors bottom WP# protect
05 = Uniform sectors top WP# protect
Program Suspend
00 = Not Supported, 01 = Supported
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
Hardware Reset Low Time-out during an embedded algorithm to
read mode Maximum 2N ns
Hardware Reset Low Time-out not during an embedded algorithm to
read mode Maximum 2N ns
Erase Suspend Latency Maximum 2N µs
Program Suspend Latency Maximum 2N µs
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
36
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Cycles
Table 13. EN29GL256 Command Definitions
Command
Sequence
Bus Cycles
1
st
Cycle
Addr Data
P
P
Read
1
RA
RD
Reset
1
XXX
F0
Word
Autoselect
Manufacturer ID
555
4
Byte
Device ID
Sector Protect
Verify
Program
Write to Buffer
Word
Byte
Word
Word
Byte
Word
Byte
Word
Program Buffer to
Flash
Byte
Write to Buffer Abort
Reset
Byte
Chip Erase
Sector Erase
555
AAA
Word
Word
Byte
Word
Byte
AA
4
6
1
3
6
6
555
AAA
2AA
555
555
AAA
SA
555
AAA
555
AAA
555
AAA
P
2AA
555
90
AAA
55
555
AAA
2AA
555
2AA
555
90
555
55
555
AA
P
55
2AA
AA
rd
Cycle
Addr
Data
AA
AAA
3
Cycle
Addr Data
P
555
555
4
Byte
nd
P
AA
AAA
4
2
90
AAA
55
55
555
AAA
A0
SA
25
AA
AA
AA
2AA
555
2AA
555
2AA
555
55
55
55
555
555
AAA
555
AAA
80
80
XXX
B0
Erase/Program Resume
1
XXX
30
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured Silicon Sector Exit
4
555
AA
2AA
55
555
90
1
55
AA
2
XX
PA
PD
Accelerated Program
5
th
6
th
Cycle
Addr Data
Cycle
Addr Data
Addr
000
100
000
200
X01
X02
(SA)
X02
(SA)
X04
X0E
X1C
2222
X0F
X1E
2201
22
PA
PD
WBL
PD
PA
SA
P
7F
1C
7F
1C
227E
7E
P
P
P
P
Cycle
Data
01
00
01
00
01
PD
WC
F0
AAA
1
Word
Byte
th
P
29
Erase/Program Suspend
CFI Query
4
555
AAA
555
AAA
XX
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
00
98
A0
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1 and maximum value is 31 for word and byte mode.
Note:
The data is 00h for an unprotected sector and 01h for a protected sector. This is same as PPB Status Read except that the
protect and unprotect statuses are inverted here
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
37
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
10
30
EN29GL256H/L
Global
Volatile Freeze
Global
Non-Volatile
Lock Register
Command
Sequence
Command Set
Entry
Bus Cycles
1
st
2
nd
3
rd
Cycle
Addr Data
Cycle
Addr Data
Cycle
Addr
Data
P
P
P
P
P
P
Word
3
555
AA
2AA
55
555
40
Byte
3
AAA
AA
55
55
AAA
40
XXX
Data
Program
2
XXX
A0
Read
1
00
RD
Command Set Exit
2
XXX
90
XXX
00
3
555
AA
2AA
55
555
C0
AAA
C0
PPB Command
Set Entry
Word
3
AAA
AA
55
55
PPB Program
2
XXX
A0
SA
00
All PPB Erase
2
XXX
80
00
30
PPB Status Read
1
SA
RD
PPB Command Set Exit
2
XXX
90
XXX
00
PPB Lock
Command Set
Entry
PPB Lock Set
Word
3
555
AA
2AA
55
555
50
Byte
3
AAA
AA
555
55
AAA
50
2
XXX
A0
XXX
00
PPB Lock Status Read
PPB Lock Command Set
Exit
1
XXX
RD
2
XXX
90
XXX
00
Word
3
555
AA
2AA
55
555
E0
Byte
3
AAA
AA
555
55
AAA
E0
2
XXX
A0
SA
00
DYB Clear
2
XXX
A0
SA
01
DYB Status Read
1
SA
RD
DYB Command Set Exit
2
XXX
90
XXX
00
DYB Command
Set Entry
Volatile
Cycles
Table 14. EN29GL256 Command Definitions
Byte
DYB Set
4
th
Cycle
Addr Data
P
P
5
th
Cycle
Addr Data
P
6
P
Note:
Protected State = “00h”, Unprotected State = “01h.”
38
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
P
Addr
Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits Amax–A16 uniquely select any sector.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
th
P
www.eonssi.com
Cycle
Data
EN29GL256H/L
Table 15. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
VCC Active Read Current
IIO2
VIO Non-Active Output
ICC2
VCC Intra-Page Read
Current
Test Conditions
Min
Typ
Max
Unit
0V≤ VIN ≤ Vcc
±5
µA
0V≤ VOUT ≤ Vcc
±1
µA
5MHz
15
30
mA
10MHz
25
45
mA
CE# = VIL , OE# = VIH
CE# = VIL , OE# = VIH , VCC =
VCCmax, f = 10 MHz
CE# = VIL , OE# = VIH , VCC =
VCCmax, f = 33 MHz
0.2
10
mA
1
10
5
15
CE# = VIL; OE# = VIH ;
VCC = VCC max
mA
ICC3
VCC Active Erase/
Program Current
CE# = VIL , OE# = VIH , VCC = VCCmax
20
30
mA
ICC4
VCC Standby Current
CE#, RESET# = VCC ± 0.3 V,
OE# = VIH , VCC = VCC max
VIL = Vss + 0.3 V/-0.1V,
1.5
10
µA
ICC5
VCC Reset Current
RESET# = Vss ± 0.3V
1.5
10
µA
ICC6
Automatic Sleep Mode
VIH = Vcc ± 0.3V
VIL = Vss ± 0.3V
1.5
10
µA
CE# = VIL, OE# = VIH,
VCC = VCCmax,
WP#/ACC = VHH
3
10
IACC
ACC Accelerated Program
Current
15
30
WP#/ACC
pin
mA
VCC pin
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
0.7 x
VIO
0.3 x
VIO
VIO +
0.3
VHH
Acceleration Program
Voltage
8.5
9.5
V
VOL
Output Low Voltage
IOL = 100 A
0.15 x
VIO
V
VOH
Output High Voltage
CMOS
IOH = -100 A
VLKO
Supply voltage (Erase and
Program lock-out)
0.85 x
VIO
2.3
V
V
V
2.5
V
Notes:
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that they draw power if not
at full CMOS supply voltages.
2. Maximum ICC specifications are tested with Vcc = Vcc max.
3. Not 100% tested.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
39
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 10. Test Conditions
Table 16. Test Specifications
Test Conditions
-90
Unit
30
pF
Input Rise and Fall times
5
ns
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
0.0-3.0
V
1.5
V
1.5
V
Output Load Capacitance, CL
B
B
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
40
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Table 17. Read-only Operations Characteristics
Parameter
Symbols
JEDEC
Standard
Speed
Test Setup
Description
Unit
-90
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable To Output Delay
tPACC
tGLQV
Min
90
ns
CE# = VIL
OE#= VIL
Max
90
ns
OE#= VIL
Max
90
ns
Page Access Time
Max
25
ns
tOE
Output Enable to Output Delay
Max
35
ns
tEHQZ
tDF
Chip Enable to Output High Z
Max
20
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
ns
tAXQX
tOH
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
ns
Output Enable
Hold Time
Min
0
ns
tOEH
Min
10
ns
Read
Toggle and
DATA# Polling
Notes:
1. High Z is Not 100% tested.
2. For - 90
Vcc = 2.7V – 3.6V
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 10. AC Waveforms for READ Operations
tBRCB
Addresses
Addresses Stable
tBACC
CE#
tBDF
tBOEB
OE#
tBOEHB
WE#
tBOH
tBCEB
HIGH Z
Output Valid
Outputs
HIGH Z
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
41
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 11. Page Read Operation Timings
Note: Addresses are A2:A-1 for byte mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
42
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Table 18. Hardware Reset (RESET#)
Paramete
r Std
tRP1
tRP2
tRH
tRB1
tRB2
tREADY1
tREADY2
Min
Min
Min
Min
Min
Speed
-90
10
500
50
0
50
Max
20
us
Max
500
ns
Test
Setup
Description
RESET# Pulse Width (During Embedded Algorithms)
RESET# Pulse Width (NOT During Embedded Algorithms)
Reset# High Time Before Read
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms)
to Read or Write
Reset# Pin Low (NOT During Embedded Algorithms)
to Read or Write
Unit
us
ns
ns
ns
ns
Figure 12. AC Waveforms for RESET#
Reset# Timings
tRB1
CE#, OE#
WE#
tREADY1
tRB2
RY/BY#
RESET#
tRP1
Reset Timing during Embedded Algorithms
CE#, OE#
tRH
RY/BY#
RESET#
tRP2
tREADY2
Reset Timing NOT during Embedded Algorithms
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
43
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Table 19. Word / Byte Configuration (BYTE#)
Std
Parameter
tBCS
tCBH
tRBH
Speed
Test
Setup
Description
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
-90
Min
Min
Min
0
0
0
Unit
ns
ns
ns
Figure 13. AC Waveforms for BYTE#
CE#
OE#
Byte#
tCBH
tBCS
Byte# timings for Read Operations
CE#
WE#
Byte#
tRBH
tBCS
RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
44
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Table 20. Write (Erase/Program) Operations
Parameter
Symbols
Speed
Description
Unit
-90
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
Min
90
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tWLAX
tAH
Address Hold Time
Min
45
ns
tDVWH
tDS
Data Setup Time
Min
40
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
Read
Toggle and
DATA# Polling
Read Recovery Time before
Write (OE# High to WE# Low)
MIn
0
ns
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time
tGHWL
tGHWL
tELWL
tCS
CE# SetupTime
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
25
ns
Write Buffer Program Operation
(Note 2, 3)
Typ
160
µs
Typ
8
µs
Max
200
µs
Typ
0.1
s
Max
2
s
Chip Erase Operation
Typ
60
s
tVHH
VHH Rise and Fall Time
Min
250
ns
tVCS
Vcc Setup Time
Min
50
µs
WE# High to RY/BY# Low
Max
90
ns
Recovery Time from RY/BY#
Min
0
ns
tWHWH1
tWHWH2
tWHWH1
tWHWH2
t BUSY
B
tRB
Programming Operation
(Word AND Byte Mode)
Sector Erase Operation
Notes: 1. Not 100% tested.
2. See table.22 Erase and Programming Performance for more information.
3. For 1~32 words bytes programmed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
45
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Table 21. Write (Erase/Program) Operations
Alternate CE# Controlled Writes
Parameter
Symbols
Speed
Description
Unit
-90
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
Min
90
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
40
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time before
Write (OE# High to CE# Low)
Min
0
ns
tWLEL
tWS
WE# SetupTime
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
Write Pulse Width
Min
45
ns
tEHEL
tCPH
Write Pulse Width High
Min
20
ns
Write Buffer Program Operation
(Note 2, 3)
Typ
160
µs
Typ
8
µs
Max
200
µs
Typ
0.1
s
Max
2
s
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Programming Operation
(Byte AND word mode)
Sector Erase Operation
Notes: 1. Not 100% tested.
2. See table.22 Erase and Programming Performance for more information.
3. For 1~32 words bytes programmed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
46
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
AC CHARACTERISTICS
Figure 14. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x2AA
Read Status Data (last two cycles)
tAH
SA
VA
VA
0x555 for chip
erase
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
0x55
Data
tDS
tWHWH2
0x30
tDH
Status
10 for chip
erase
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
47
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 15. Program Operation Timings
Program Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x555
Program Command Sequence (last 2 cycles)
tAH
PA
PA
PA
CE#
tGHWL
OE#
tCH
tWP
WE#
tWPH
tWHWH1
tCS
Data
OxA0
tDS
RY/BY#
Status
PD
tDH
DOUT
tRB
tBUSY
tVCS
VCC
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command
sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
48
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 16. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
Addresses
VA
VA
VA
tACC
tCH
tCE
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ[7]
Complement
DQ[6:0]
Status Data
Comple
-ment
Status
Data
Valid Data
True
True
Valid Data
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 17. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
tRC
VA
Addresses
tCH
VA
VA
VA
tACC
tCE
CE#
tOE
OE#
tOEH
WE#
tDF
tOH
Valid Status
DQ6, DQ2
tBUSY
(first read)
Valid Status
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
49
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Figure 18. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Chip Erase
0x555 for Program
0x2AA for Erase
Addresses
VA
tWC
tAS
tAH
WE#
tWH
tGHEL
OE#
tCP
tCPH
tWS
CE#
tDS
tWHWH1 / tWHWH2
tBUSY
tDH
Status
Data
0xA0 for
Program
0x55 for Erase
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 19. DQ2 vs. DQ6
Enter
Embedded
Erase
WE#
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Erase
Resume
Enter
Suspend
Program
Enter
Suspend
Read
Erase
Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
50
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
TABLE 22. ERASE AND PROGRAMMING PERFORMANCE
Typ
Limits
Max
Unit
Sector Erase Time
0.1
2
sec
Chip Erase Time
60
240
sec
Byte Programming Time
8
200
µs
Word Programming Time
8
200
µs
Byte
268.8
806.4
Word
134.4
403.2
Parameter
Chip Programming
Time
Total Write Buffer time
160
ACC Total Write Buffer time
60
Erase/Program Endurance
100K
sec
Comments
Excludes 00h programming prior
to erasure
Excludes system level overhead
µs
Minimum 100K cycles
cycles
Notes:
1. Typical program and erase times assume the following conditions: room temperature, 3V and checkboard
pattern programmed.
2. Maximum program and erase times assume the following conditions: worst case Vcc, 90 C and 100,000 cycles.
Table 23. 56-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.
Table 24. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Data Retention Time
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
51
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
-55 to +125
C
200
mA
OE#, RESET# and
WP#/ACC2
-0.5 to + 9.5
V
All other pins 3
-0.5 to Vcc+0.5
V
-0.5 to + 4.0
V
Ambient Temperature
With Power Applied
Output Short Circuit Current1
P
P
P
P
P
P
Voltage with
Respect to Ground
P
P
Vcc
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC input voltage on OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, OE#, RESET# and
WP#/ACC pins may undershoot V ss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below.
Maximum DC input voltage on OE#, and RESET# is 8.5V which may overshoot to 9.5V for periods up to 20ns.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V ss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is V cc + 0.5
V. During voltage transitions, outputs may overshoot to V cc + 1.5 V for periods up to 20ns. See figure below.
4.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B
B
B
B
B
B
RECOMMENDED OPERATING RANGES 1
P
P
Parameter
Value
Unit
-40 to 85
C
Full Voltage Range:
2.7 to 3.6V
V
Ambient Operating Temperature
Industrial Devices
Operating Supply Voltage
Vcc
1.
B
B
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Maximum Positive Overshoot
Waveform
52
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
FIGURE 20. 56L TSOP 14mm x 20mm package outline
SYMBOL
A
A1
A2
D
D1
E
e
b
L
R
MIN.
--0.05
0.95
--------0.17
0.5
0.08
0
DIMENSION IN MM
NOR
----1.00
20.00
18.40
14.00
0.50
0.22
0.60
0.15
0
Note : 1. Coplanarity: 0.1 mm
0
3
MAX
1.20
0.15
1.05
--------0.27
0.70
0.20
0
5
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
53
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
FIGURE 21. 64-ball Ball Grid Array (BGA), 11 X13 mm, Pitch 1mm package outline
SYMBOL
DIMENSION IN MM
A
MIN.
- --
NOR
- --
MAX
1.40
A1
A2
0.40
0.60
0.50
0.66
0.60
0.76
D
E
D1
12.90
10.90
- --
13.00
11.00
7.00
13.10
11.10
- --
E1
e
b
- -- -0.50
7.00
1.00
0.60
- -- -0.70
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
54
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code: XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
55
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
ORDERING INFORMATION
EN29GL256 H
-
90
Z
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
Z = 56-pin TSOP
BA = 64-Ball Ball Grid Array (BGA) 1.0mm pitch,
11mm x 13mm package
SPEED
90 = 90ns
SECTOR for WRITE PROTECT (WP#/ACC=L)
H = highest address sector protected
L = lowest address sector protected
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29GL = FLASH, 3V Page Mode Flash Memory
256 = 256 Megabit (32M x 8 / 16M x 16)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
56
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
EN29GL256H/L
Revisions List
Revision No Description
Date
A
2009/02/18
B
C
D
Preliminary
1. Add internal pull-up description for WP# pin in Table1 on Page 4
2. Add WP#/ACC, VIO pin in Figure3 on Page 4
3. Modify tOE from 30ns to 25ns in Table 17 on page 40 and Page 5
4. Add Secured Silicon Sector Entry/Exit command in Table13
5. Modify typo from Sector Erase Suspend to Erase/Program Suspend,
from Sector Erase Resume to Erase/Program resume in Table13
6. Modify package code for 56-pin TSOP from T to Z in ordering
information on Page 57
7. Del table 22 and Figure 20 Temporary Sector Unprotect Timing table and
Diagram and Figure 21.Sector Protect/Unprotect Timing Diagram
8. Modify Erase/Program performance in Table 20, 21 and 22.
Chip erase time from 64å60sec typ and 560å240sec max.
Add ACC and total write buffer time spec
9. Del tCEH on table 17
2009/05/12
10. Modify DC Characteristics in table 15
VHH from 10.5~11.5V to 8.5~9.5V
ICC1 5MHz 9å15mA typ, 10MHz 16å25mA typ
ICC4, ICC5 and ICC6 1å1.5uA typ, 5å10uA max
Add IIO2 and IACCspec
11. Del apply VID on address pin A9 to access autoselect codes function.
( Remove TABLE 5 and modify description Autoselect section for using
High voltage to get Autoselect Codes )
12. Modify A9 spec from 9.5V to Vcc+0.5V in ABSOLUTE MAXIMUM
RATINGS
13. Modify CFI 4Ah, 4Fh description and data of 4Fh in table 12
14. Modify CFI data for address 27h and 2Dh.
15. Modify typo Sector Architecture 128 to 256 sectors on page1
16. Modify typo Byte mode to Word mode on page7
1. Modify naming for DQ0 OTP Lock Bit to Secured Silicon Sector
Protection Bit on Page 28
2. Modify Table.8 Secured Silicon Sector Address Range 000000h000007h from Determined by customer to Reserve for Factory
3. Add note “The address 0h~7h in Secured Silicon Sector is reserved
for Factory“ on Page 34
2009/7/14
4. Update FIGURE 21. 64 ball Fortified Ball Grid Array (FBGA), 11 X13 mm,
Pitch 1mm package outline on page 55
5. Modify from Sector 0 to all sectors in note 1 of Table 6 and note 2, 3 and
note 9 of PPB section on page 28
6. Add “User only can use DQ6 and RY/BY# pin to detect programming
status” in note 10 on page29
Change the package code of 64-ball BGA on page 56.
2009/07/22
1. Correct typo in Table 20, “ t BUSY “ from Min. to Max on page 45.
B
E
F
G
H
2. Add a note "when sector SA0 is suspended, if system enters Secured 2010/01/26
Sector mode,..." on page 32.
1. Add Write Buffer byte mode command and note that maximum value is 31
for word and byte mode in page 37.
2. Change the speed option from 70ns to 90ns, and modify related 2010/03/31
parameter for 90ns speed.
Update the Output Load Capacitance from 100pF to 30pF on page 40
2011/01/17
and 41.
1. Add Table 13 “Note: The data is 00h for an unprotected sector and 01h for
a protected sector. This is same as PPB Status Read except that the
protect and unprotect statuses are inverted here” on page 37.
2012/06/05
2. Add Table 14 “Note: Protected State = “00h”, Unprotected State = “01h” on
page 38.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
57
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2012/06/05
www.eonssi.com
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