null  null
TMS320DM365
Evaluation Module
Technical
Reference
y
r
a
9
n
0
i
il m , 20
e
4
r
1
P
l
i
r
p
A
2009
DSP Development Systems
TMS320DM365 Evaluation
Module Technical Reference
510845-0001 Rev. A
April 2009
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505
Fax: 281.494.5310
[email protected] www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2009 Spectrum Digital, Inc.
Contents
1
Introduction to the DM365 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides you with a description of the DM365 Evaluation Module, key features, and
block diagram.
1.1 Key Features
..........................................................
1.2 Functional Overview of the DM365 EVM
.................................
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Boot / Configuration Switch Settings
.......................................
1.6 Power Supply
.........................................................
2
Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation of the major board components on the DM365 Evaluation Module.
2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Flash, NAND Flash
....................................................
2.1.1.1 One NAND
.........................................................
2.1.1.2 CPLD Interface
.....................................................
2.1.1.2.1 Register 0, CPLD Version
...........................................
2.1.1.2.2 Register 1, Test Register
............................................
2.1.1.2.3 Register 2, LED Register
............................................
2.1.1.2.4 Register 3, Board Mux Control Register
................................
2.1.1.2.5 Register 4, Board Switch Register
....................................
2.1.1.2.6 Register 5, Power Control Register
...................................
2.1.1.2.7 Register 6, GPIO Video Register
.....................................
2.1.1.2.8 Register 7, Media Card Status
.......................................
2.1.1.2.9 Register 8, DILC Output Pin Mapping
.................................
2.1.1.2.10 Register 9, DILC Input Pin Mapping
.................................
2.1.1.2.11 Register 10, Imager Internal I/O Direction Register 0
...................
2.1.1.2.12 Register 11, Internal I/O Mux Register 0
..............................
2.1.1.2.13 Register 12, Internal I/O Mux Register 1
.............................
2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1
...................
2.1.1.2.15 Register 14, Imager Internal I/O Mux Register 2
......................
2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3
.......................
2.1.1.2.17 Register 16, Imager Internal I/O Direction Register 2
....................
2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4
......................
2.1.1.2.19 Register 18, Imager Internal I/O Mux Register 5
......................
2.1.1.2.20 Register 19, Board RESET Register
................................
2.1.1.2.21 Register 720, CCD Internal I/O Direction Register 1
....................
2.1.1.2.22 Register 721, CCS Internal I/O Read/Write Register 1
..................
2.1.1.2.23 Register 722, CCD Internal I/O Direction Register 2
....................
2.1.1.2.24 Register 723, CCD Internal I/O Read/Write Register 2
..................
2.1.1.2.25 Register 724, CCD Internal I/O Direction Register 3
....................
1-1
1-2
1-4
1-4
1-5
1-6
1-7
2-1
2-2
2-2
2-2
2-4
2-6
2-6
2-6
2-6
2-7
2-7
2-8
2-9
2-9
2-10
2-10
2-11
2-11
2-12
2-12
2-13
2-13
2-14
2-14
2-15
2-15
2-16
2-16
2-17
2-17
2.1.1.2.26 Register 725, CCD Internal I/O Read/Write Register 3
..................
2.1.1.3 Key Pad Interface
..................................................
2.1.2 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Media Card Interface
..............................................
2.1.4 UART Interface
..................................................
2.1.5 USB Interface
....................................................
2.2 Input Video Port/Imager Input Port Interfaces
...............................
2.2.1 On Chip Video Output DAC
............................................
2.2.2 LCD Video Connectors
...............................................
2.3 AIC3101 Interface
....................................................
2.4 On Chip Voice Codec
...................................................
2.5 On Chip ADC
..........................................................
2.6 On Chip RTC
........................................................
2.7 Ethernet Interface
......................................................
2.8 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Daughter Card Interface
...............................................
2.10 DM365 CPU Video Clocks
............................................
2.11 Battery
.............................................................
3
Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the physical layout of the DM365 Evaluation Module and its connectors.
3.1 Board Layout
........................................................
3.2 Connectors
........................................................
3.2.1 J1, MiniAB USB Connector and Jumpers
................................
3.2.2 J2, 14 Pin External JTAG Header
........................................
3.2.3 J3, MSP430 JTAG Header
...........................................
3.2.4 J4, Spare Jumper Holder
...............................................
3.2.5 J5, 20 Pin ARM JTAG Emulation Header
..................................
3.2.6 J6, USB Capacitance Select
...........................................
3.2.7 J7, +5 Volts Input
....................................................
3.2.8 J12, SD/MMC/MS Card Interface
.......................................
3.2.9 J10, Imager Interface
................................................
3.2.10 J14, EMIF/UPI DC Interface
.........................................
3.2.11 J8, Y Component Video In, RCA Jack (Green)
..........................
3.2.12 J9, Pb Component Video In, RCA Jack (Blue)
..........................
3.2.13 J11, Pr Component Video In, RCA Jack (Red)
.........................
3.2.14 J15, S-Video In
....................................................
3.2.15 J13, CVBS/Y Input, RCA Jack (Yellow)
................................
3.2.16 J16, Composite TV Out, RCA Jack (Yellow)
............................
3.2.17 J17, Y Component Video Out, RCA Jack (Green)
........................
3.2.18 J20, Pb Component Video Out, RCA Jack (Blue)
........................
3.2.19 J21, Pr Component Video Out, RCA Jack (Red)
.........................
3.2.20 J18, J19, Video Output DC
...........................................
3.2.21 J22, CPLD Programming Header
.....................................
3.2.22 J23, I/O Interface Header
............................................
3.2.23 J24, DILC Host Connector
...........................................
3.2.24 J25, MMC/SD Connector
............................................
3.2.25 P1, RS-232 UART
..................................................
3.2.26 P2, Ethernet Interface
...............................................
2-18
2-19
2-19
2-19
2-20
2-20
2-20
2-21
2-21
2-22
2-23
2-23
2-23
2-24
2-24
2-25
2-25
2-25
2-26
3-1
3-3
3-5
3-6
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-12
3-13
3-13
3-14
3-14
3-15
3-15
3-16
3-16
3-17
3-18
3-19
3-19
3-20
3-21
3-22
3-23
3.2.27 P3, Microphone In
..................................................
3.2.28 P4, Line In
........................................................
3.2.29 P5, Line Out
.......................................................
3.2.30 P6, Headphone Out
.................................................
3.2.31 U1, Infrared Interface
...............................................
3.2.32 SPK1, Speaker Interface
.............................................
3.2.33 BHT1, Battery Interface
.............................................
3.2.34 M1, Microphone Interface
............................................
3.3 LEDs
................................................................
3.4 Switches
.............................................................
3.4.1 SW1, EMU0/1 Select Switch
...........................................
3.4.2 SW2, PWCTRO0 Pushbutton
.........................................
3.4.3 SW3, Non-Supported Pushbutton
......................................
3.4.4 SW4, Boot Mode / Configuration Select
..................................
3.4.5 SW5, Board Configuration Select
......................................
3.4.6 SW6 - SW21, Function Pushbuttons
....................................
3.4.7 SW22, MSP430 IO0 Pushbutton
.......................................
3.4.8 SW23, PRTSC Mode Select
..........................................
3.5 Jumpers
............................................................
3.5.1 JP1, Jumper Block
..................................................
3.6 Test Points
........................................................
A Schematics
..............................................................
Contains the schematics for the DM365 Evaluation Module
B Mechanical Information
..................................................
Contains the mechanical information about the DM365 Evaluation Module
3-24
3-24
3-25
3-25
3-26
3-26
3-27
3-27
3-28
3-29
3-30
3-30
3-30
3-31
3-32
3-32
3-33
3-33
3-34
3-34
3-35
A-1
B-1
About This Manual
This document describes the board level operations of the DM365 Evaluation Module
(EVM). The EVM is based on the Texas Instruments TMS320DM365 Processor.
The DM365 Evaluation Module is a table top card that allows engineers and software
developers to evaluate certain characteristics of the DM365 processor to determine if
the processor meets the designers application requirements. Evaluators can create
software to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM365 Evaluation Module will sometimes be referred to as the DM365 EVM or
EVM.
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents, Application Notes and User Guides
Information regarding the TMS320DM365 can be found at the following Texas
Instruments website:
http://www.ti.com
Table 1: Manual History
Revision
A
History
Beta Release
Table 2: Board History
PWB
Revision
C
History
Beta Release
Chapter 1
Introduction to the
DM365 EVM
Chapter One provides a description of the DM365 EVM along with the key
features and a block diagram of the circuit board.
Topic
1.1
1.2
1.3
1.4
1.5
1.6
Page
Key Features
Functional Overview of the DM365 EVM
Basic Operation
Memory Map
Boot / Configuration Switch Settings
Power Supply
1-2
1-4
1-4
1-5
1-6
1-7
1-1
Spectrum Digital, Inc
1.1 Key Features
USB
JTAG (14)
1 2
RS-232
SW1
The DM365 EVM is a standalone development platform that enables users to
evaluate and develop applications for the TMS320DM365 processor. Schematics,
logic equations and application notes are available to ease hardware development and
reduce time to market.
MSP430
JTAG
ENET
RJ45
JTAG (20)
IR
MIC
PWR
MIC IN
MSP430
KSZ8001
PHY
Battery
Reset
JTAG
MII
MUX
HD Video In Connector
USB
DDR2
16
DM365
Video In
DAC Out
HP OUT
SD Video
Decoder
TVP5146
Y
Pb/Cb
Pr/Cr
Comp
SW4
1
2
3
4
5
6
EMIF
I2C
ROM
SW5
1
One
NAND
HD Video
Decoder
TVP7002
2
3
4
5
6
S-Video
THS7303
J14 - EMIF
LINE OUT
I2C Bus
UART0
SD/MMC
SD/MMC
SD0 on Top
SD1 on Bottom
AIC
3101
SPI0
SPI
ROM
TPS65530
Power
LINE IN
THS7353
PRTSCC On
McBSP
Comp
NAND
Y
LEDs
CPLD
Pb/Cb
Pr/Cr
J19
J18
Digital
Video Out
Speaker
LCD Interface
J23
Keypad
Camera IF
Figure 1-1, Block Diagram DM365 EVM
The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments DM365 processor with an ARM9 processor operating up to
300 MHz.
• 1 video input port, supports composite or S video (NTSC or PAL formats)
• 1 set of 3 component video inputs supports capture up to 720P resolution
• 1 composite video DAC output (NTSC or PAL formats)
• 1 set of 3 component video DACs supports resolution up to 720P resolution
• 128 Mbytes of DDR2 DRAM
• UART Interface
• Dual SD/MMC/MS, MMC/SD Media Card Interfaces
1-2
DM365 EVM Technical Reference
Spectrum Digital, Inc
• 2 Gigabytes NAND Flash
• 128 Megabytes of One NAND
• AIC3101 stereo codec
• USB2 Interface
• 10/100 MBS RMII Ethernet Interface
• SPI EEPROM
• IR Remote Interface via MSP430
• Configurable boot load options
• 8 user LEDs/16 user push button switches
• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces
Figure 1-2, DM365 EVM
1-3
Spectrum Digital, Inc
1.2 Functional Overview of the DM365 EVM
The DM365 on the EVM interfaces to on-board peripherals through the 8/16-bit wide
Async EMIF peripheral interface pins. The DDR2 memory is connected to its own
dedicated 16 bit wide bus. The Async EMIF bus is also connected to the NAND and
One NAND flash.
On board video decoders and on chip encoders interface video streams to the DM365
processor. One composite channel and one set of 3 component channel
encoder/decoder are standard on the EVM. On screen display functions are
implemented in software on the DM365 processor.
An on-board AIC3101 codec allows the DSP to transmit and receive analog audio
signals. The I2C bus is used for the codec control interface, while the McBSP controls
the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond
to microphone input, headphone output, line input, and line output.
The EVM includes 8 user LEDs, 16 user push button switches, and an IR interface
which provide the user with application interaction.
An included +5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.2 to 1.35V CPU core voltage, +3.3V for peripherals
and +1.8V for DDR2 memory.
The DM365 EVM has a 10/100 ethernet interface which provides a standard high
speed link to other devices.
The on board media card interface allows the user to conveniently load/store data from
a variety of standard memory card formats. An on-chip Real Time Clock is integrated
into the DM365 for time based applications.
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio IDETM, or standard GDB
tool environments. Code Composer communicates with the board through an external
JTAG emulator.
1-4
DM365 EVM Technical Reference
Spectrum Digital, Inc
1.4 Memory Map
The DM365 processor has a byte addressable address space. There are some
limitations to byte addressing which are determined by peripheral interconnection to the
DM365 device. Program code and data can be placed anywhere in the unified address
space. Addresses are multiple sizes depending on hardware implementation. Refer to
the appropriate device data sheets for more details.
The memory map shows the address space of a generic DM365 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The other EMIF has 2 separate addressable regions called chip
enable spaces (CE0 & CE1). The NAND Flash, one NAND, and CPLD are mapped into
these chip enable spaces.
DM365 EVM
Address
0x00000000
Memory Map Address Space
ARM Instruction RAM
0x00007FFF
0x00008000
ARM Instruction ROM
0x0000BFFF
0x00010000
ARM RAM (Data)
0x00017FFF
0x01C00000
CFG Bus Peripherals
0x01FFFFFF
0x02000000
CE0 - ASYNC EMIF (Data)
0x03FFFFFF
0x04000000
CE1
0x05FFFFFF
0x20000000
DDR EMIF Control Regs
0x2007FFFF
0x80000000
DDR EMIF
0x87FFFFFF
0x88000000
0x8FFFFFFF
DDR Expansion
(reserved)
Figure 1-3, Memory Map, DM365 EVM
1-5
Spectrum Digital, Inc
Shown below is a break out of the memory spaces.
Memory Space
Address
0x02000000
NAND Chip Select 0 / One NAND
0x02004000
NAND Chip Select 1
0x40000000
CPLD Control Registers
Figure 1-4, DM365 EVM Chip Enable Memory Space
1.5 Boot / Configuration Switch Settings
The EVM has a configuration switch that allow users to control the Boot and EMIF
configuration state of the processor when it is released from reset. The switch SW4
determines the source for processor booting. By default the switches are configured to
NAND Flash boot. The EMIF configuration switch must be set accordingly. This switch
configures the DM365 pin muxing at RESET. The default for the pin muxing is shown
below. For additional pin muxing requirements please refer to the D365 data sheet.
Table 1: SW4, ARM Boot Mode Select
Pos 3
Pos 2
Pos 1
HW Code
Boot Mode
ON
ON
ON
000
NAND Boot *
ON
ON
OFF
001
ASYNC EMIF
ON
OFF
ON
010
MMC/SD Boot
ON
OFF
OFF
011
UART Boot
OFF
ON
ON
100
USB Boot
OFF
ON
OFF
101
SPI Boot
OFF
OFF
ON
110
EMAC Boot
OFF
OFF
OFF
111
HPI Boot
Table 2: SW4, ARM EMIF Configuration Mode Select
Pos 6
Pos 5
Pos 4
HW Code
Configuration Mode
ON
ON
ON
000
8-bit AEMIF Configuration *
ON
ON
OFF
001
16-bit AEMIF Configuration
* default setting
1-6
DM365 EVM Technical Reference
Spectrum Digital, Inc
1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J7), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted
into +1.2 to 1.35V, +1.8V and +3.3V using Texas Instruments TPS65530 power
management IC and various linear regulators. The +1.2 to 1.35V supply is used for the
DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on
the board. The +1.8 volt supply is used for DM365 DDR2 memory, and other on chip
peripherals.
1-7
Spectrum Digital, Inc
1-8
DM365 EVM Technical Reference
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the DM365 EVM.
Topic
2.1
Asychronous EMIF Interface
2.1.1 NAND Flash
2.1.1.1 One NAND
2.1.1.2 CPLD Interface
2.1.1.2.1 Register 0, CPLD Version
2.1.1.2.2 Register 1, Test Register
2.1.1.2.3 Register 2, LED Register
2.1.1.2.4 Register 3, Board Mux Control Register
2.1.1.2.5 Register 4, Board Switch Register
2.1.1.2.6 Register 5, Power Control Register
2.1.1.2.7 Register 6, GPIO Video Register
2.1.1.2.8 Register 7, Media Card Status
2.1.1.2.9 Register 8, DILC Output Pin Mapping
2.1.1.2.10 Register 9, DILC Input Pin Mapping
2.1.1.2.11 Register 10, Imager Internal I/O Direction Register 0
2.1.1.2.12 Register 11, Internal I/O Mux Register 0
2.1.1.2.13 Register 12, Internal I/O Mux Register 1
2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1
2.1.1.2.15 Register 14, Imager Internal I/O Mux Register 2
2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3
2.1.1.2.17 Register 16, Imager Internal I/O Direction Register 2
2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4
2.1.1.2.19 Register 18, Imager Internal I/O Mux Register 5
2.1.1.2.20 Register 19, Board RESET Register
2.1.1.2.21 Register 720, CCD Internal I/O Direction Register 1
2.1.1.2.22 Register 721, CCS Internal I/O Read/Write Register 1
2.1.1.2.23 Register 722, CCD Internal I/O Direction Register 2
2.1.1.2.24 Register 723, CCD Internal I/O Read/Write Register 2
2.1.1.2.25 Register 724, CCD Internal I/O Direction Register 3
2.1.1.2.26 Register 725, CCD Internal I/O Read/Write Register 3
Page
2-2
2-2
2-2
2-4
2-6
2-6
2-6
2-6
2-7
2-7
2-8
2-9
2-9
2-10
2-10
2-11
2-11
2-12
2-12
2-13
2-13
2-14
2-14
2-15
2-15
2-16
2-16
2-17
2-17
2-18
2-1
Spectrum Digital, Inc
Topic
2.1.1.3
2.1.2
2.1.3
2.1.4
2.1.5
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.9
2.10
2.11
2-2
Key Pad Interface
DDR2 Memory Interface
Media Card Interface
UART Interface
USB Interface
Input Video Port/Imager Input Port Interfaces
On Chip Video Output DAC
LCD Video Connectors
AIC3101 Interface
On Chip Voice Codec
On Chip ADC
On Chip RTC
Ethernet Interface
I2C Interface
MSP430
Daughter Card Interface
DM365 CPU/Video Clocks
Battery
Page
2-19
2-19
2-19
2-20
2-20
2-20
2-21
2-21
2-22
2-23
2-23
2-23
2-24
2-24
2-25
2-25
2-25
2-26
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1 Asynchronous EMIF Interface
An asynchronous 16 bit EMIF with two chip enables divide up the address space and
allow for asynchronous accesses on the EVM. This interface connects to the NAND,
One NAND, and CPLD registers on the EVM board.
2.1.1 NAND Flash
The DM365 has 2 gigabytes of NAND Flash memory mapped into the CE0 space. The
NAND Flash memory is used primarily for boot loading and file system on the DM365
EVM. The CE0 selects the device and needs to be configured to 8 bits wide when
accessing the NAND.
Switch SW5, position 1 (OFF) selects CE0 mapped to NAND. The NAND and One
NAND interface share the same CE0 chip select so only 1 device can be operational at
any given time.
When the NAND flash interface is selected the spare address lines can be used by the
internal DM365 key pad interface. This interface is enabled by setting a control bit in
the CPLD to enable the on board CBTLV switches to the keypad matrix.
2.1.1.1 One NAND
The EVM supports 128 Megabytes of One NAND. This interface is 16 bits wide and
CE0 must be configured for 16 bit wide operation when using One NAND. Switch SW5,
position 1 (ON) selects the One NAND device. When the One NAND is selected the on
board NAND is not available. Since the One NAND uses all the asynchronous
EMIF address lines the on-chip key pad controller on the DM365 cannot be used when
the One NAND is selected.
2-3
Spectrum Digital, Inc
2.1.1.2 CPLD Interface
The DM365 incorporates an Altera EPM2210, 256 Ball Grid Array(BGA) CPLD. The
CPLD incorporates a number of internal registers, glue logic, and I/O multiplexing to
allow for a very flexible development platform. The CPLD is accessed via EMIF CE1.
The interface is 8 bits wide. All registers show up as 4 mirror images in the memory
window due to 32 bit addressing and 8 bit data mapping, that is BA0 and BA1 are not
used in the memory decoder for registers.
Address lines A7-A3 and BA0 and BA1 are not used in the decoder so that these lines
can be used by the keypad decoder.
The base address of CE1 is 0x0400 0000. Each additional register is accessed on an
increment of 0x0000 0008. The addresses are in the following format:
A13, A12, A11, A10, A9, A8, Ax, Ax, Ax, Ax, Ax, A2, A1, Ax, Ax.
2-4
DM365 EVM Technical Reference
Spectrum Digital, Inc
The following sections describe the registers and their function. A list of the registers is
shown in the table below.
Table 1: CPLD Registers
Reg #
Address
A13 - A8
Address
A2-A1
Function
R/W
0
000000
00
CPLD Version
R
1
000000
01
Test Register
R,W
2
000000
10
LED Register
R,W
3
000000
11
Board Mux Control
R,W
4
000001
00
Board Switch Register
R
5
000001
01
Power Control Register
R,W
6
000001
10
GPIO Video Register
R,W
7
000001
11
Media Card Status
R
8
000010
00
DILC Output Pin Mapping
R,W
9
000010
01
DILC Input Pin Mapping
R
10
000010
10
Imager Internal I/O Direction Register 0
R,W
11
000010
11
Imager Internal I/O Mux Register 0
R,W
12
000011
00
Imager Internal I/O Mux Register 1
R,W
13
000011
01
Imager Internal I/O Direction Register 1
R,W
14
000011
10
Imager Internal I/O Mux Register 2
R,W
15
000011
11
Imager Internal I/O Mux Register 3
R,W
16
000100
00
Imager Internal I/O Direction Register 2
R,W
17
000100
01
Imager Internal I/O Mux Register 4
R,W
18
000100
10
Imager Internal I/O Mux Register 5
R,W
19
000100
11
Board RESET Register
R,W
720
111110
00
CCD Internal I/O Direction Register 1
R,W
721
111110
01
CCD Internal I/O Read/Write Register 1
R,W
722
111110
10
CCD Internal I/O Direction Register 2
R,W
723
111110
11
CCD Internal I/O Read/Write Register 2
R,W
724
111111
00
CCD Internal I/O Direction Register 3
R,W
725
111111
01
CCD Internal I/O Read/Write Register 3
R,W
2-5
Spectrum Digital, Inc
2.1.1.2.1 Register 0, CPLD Version
This read only, 8 bit register, contains the CPLD hardware version for version control.
The default value is 0x11.
2.1.1.2.2 Register 1, Test Register
This read only, 8 bit register, has a default value of 0xA5 and can be read and written to
test the memory interface.
2.1.1.2.3 Register 2, LED Register
This 8 bit, read/write register controls the user LEDs. A data bit of ‘0’ in each bit
location turns on an LED. Similarly a ‘1’ turns off the LED in each bit position.
2.1.1.2.4 Register 3, Board Mux Control Register
This 8 bit, read/write control register (default = 0x00) controls keypad, AIC, SD,
Ethernet, and Video In multiplexers as shown in the table below.
points as shown in the table below.
Table 2: Register 3, Board Mux Control Register
2-6
Bit #
Signal
7
EMIF_KEYPAD_CTL
6
SEL_SD1_GPIO_CTL
5
SEL_AICn_GPIO_CTL
4
Spare
3
SEL_ENET_GPIO_CTL
2
DECODER_IMAGER_S2_CTL
1
DECODER_IMAGER_S1_CTL
0
DECODER_IMAGER_S0_CTL
State
Function
0
Addresses on Muxes (ONE NAND Mode)
1
Addresses are available for keypad
0
Enables SD card slot 1
1
Signals for SD1 card slot 1 go to CPLD
imager GPIO
0
Enables McBSP signals to AIC3101 codec
1
McBSP signals go to CPLD for imager GPIO
Not currently used
0
Enable Ethernet signals to PHY
1
Ethernet signals go to CPLD for imager GPIO
S[2:0]
0 0 1 = Selects TVP7002 as input to DM365
video input port
0 1 0 = Selects imager as input to DM365
video input port
1 0 1 = Selects TVP5146 as input to DM365
video input port
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.5 Register 4, Board Switch Register
This 8 bit, read only register mirrors the values set on switch SW5. These signals are
shown in the table below.
Table 3: Register 4, Board Switch Register
Bit #
SW5 Position
Signal
7
Reserved
N/A
6
Reserved
N/A
5
1
SEL_NAND_LOW
0 = NAND mapped to CE0,
1 = ONE NAND mapped to CE0
4
2
SEL_EXTRA1
3
3
SEL_EXTRA2
2
4
SEL_EXTRA3
1
5
CPU_VSEL1
0 = Vcore at 1.2V
1 = Vcore at 1.35 V
0
6
SEL_NTAS_MODE
2.1.1.2.6 Register 5, Power Control Register
Register 5 is a 8 bit, read/write register that controls on board voltage regulator
functions. The default data value is 0b00000000. These controls are shown in the table
below.
Table 4: Register 5, Power Control Register
Bit #
Signal
Function
7
LCD_OE_5V
0,1 = Sets U32 FDC6331L Pin to 0,1
ENABLE_LCD_3V3
0 = Disables U31 TPS74701
1 = Enables U31 TPS74701
6
5
Reserved
4
EN7
0,1 = Sets U14 TPS65530 EN7 pin to 0,1
3
ENAFE
0,1 = Sets U14 TPS65530 ENAFE pin to 0,1
2
SEQ56
0,1 = Sets U14 TPS65530 SEQ56 pin to 0,1
1
EN56
0,1 = Sets U14 TPS65530 EN56 pin to 0,1
0
ENABLE_LCD_15V
0 = Disables U34 TPS61080 register
0 = Enables U34 TPS61080 register
2-7
Spectrum Digital, Inc
2.1.1.2.7 Register 6, GPIO Video Register
Register 6 is a 8 bit, read/write register that controls the mapping of GPIO30/32/33,
VDIN_WE, DRV_BUS. The default data value is 0b00000000. These controls are
shown in the table below.
Table 5: Register 6, GPIO Video Register
Bit #
Signal
Function
7
Reserved
6
Reserved
5
C_FIELD
1 = DM365 Ball E13 mapped to
EXP CONN CCD_FIELD
4
C_WE
1 = DM365 Ball E13 mapped to
EXP CONN CCD_WEN
3
24 BIT COLOR
1 = Map GPIO30,32,33 to
G1,R0,R1 on LCD EXP CONNS
2
C_WE_FLD_VBUS_DRV
1 = DM365 BALL E13 Drives U4, TPS2065
1
GIO33_VBUS_DRV
1 = GIO33 drives U4, TPS2065
0
VBUS_DRV_ALT
1 = Drives VBUS ENABLE to U4, TPS2065
ENABLE VBUS_DRV (U4, TPS2065) will = 1 when any of the following occur:
- When SW5-2 (SEL_EXTRA1_ = 1 for test
- When VBUS_DRV_ALT = 1
ENABLE VBUS_DRV (U4, TPS2065) will = DM365 GIO33 when
GIO33_VBUS_DRV = 1
ENABLE VBUS_DRV (U4, TPS2065) will = DM365 Ball E13 when
C_WE_FLD_VBUS_DRV = 1
2-8
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.8 Register 7, Media Card Status
Register 7 is a 8 bit, read only register that reads the “Insert” and “Write Protect” status
of media cards. These functions of these bits are shown in the table below.
Table 6: Register 7, Media Card Status
Bit #
Signal
Function
7
Reserved
Reads 0
6
Reserved
Reads 0
5
SD_MMC_1 WRITE PROTECT
0 = Write Protect
4
SD_MMC_1 INSERT
0 = Insert
3
Reserved
Reads 0
2
SD_MMC0 MS INSERT
0 = Insert
1
SD_MMC_0 WRITE PROTECT
0 = Write Protect
0
SD_MMC_0 INSERT
0 = Insert
2.1.1.2.9 Register 8, DILC Output Pin Mapping
Register 8 is a 8 bit, read/write register that maps DM365 GPIO and SPI2 pins to the
DILC connector. The default data value is 0b11111111. The mapping of these pins is
shown in the table below.
Table 7: Register 8, DILC Output Pin Mapping
Bit #
Signal
Function
7
DILC_DRV_VBUS
Register drives DILC DRV_VBUS pin
when bit 6 = 0
6
DILC_DRV_VBUS_IO
0 = Internal register bit 7 drives DILC pin
5
DILC_VBUS_DET_DRV
Register drives DILC pin VBUS_DET
when bit 4 = 0
4
DILC_VBUS_DET_IO
0 = Internal register bit 5 drives DILC pin
3
Reserved
N/A
2
CPU_GPIO32_IO
0 = IN, SPI2_DILC drives GIO32
1 = OUT, GIO32 drives SPI2_DILC
1
CPU_GPIO31_IO
0 = IN, SPI2_DILC drives GIO31
1 = OUT, GIO31 drives SPI2_DILC
0
CPU_GPIO30_IO
0 = IN, SPI2_DILC drives GIO30
1 = OUT, GIO30 drives SPI2_DILC
2-9
Spectrum Digital, Inc
2.1.1.2.10 Register 9, DILC Input Pin Mapping
Register 9 is a 8 bit, read only register that maps DILC pins to read contents on this
register. The mapping of these pins is shown in the table below.
Table 8: Register 9, DILC Input Pin Mapping
Bit #
Function
7
Reserved
6
Reads value of DILC connector pin GIO_DILC_DRV_VBUS1
5
Reads value of DILC connector pin GIO_DILC_DRV_DET
4
Reserved
3
Reads value of DILC connector pin GIO_DILC_DOCK_DET
2
Reads value of DILC connector pin GIO_DILC_CAM_PWR_DECT
1
Reads value of DILC connector pin GIO_DILC_AVJ_DET
0
Reads value of DILC connector pin GIO_DILC_CHG_CTL
2.1.1.2.11 Register 10, Imager Internal I/O Direction Register 0
Register 10 is a 8 bit, read/write register that controls DM365 GPIO to IMAGER
connector pin input/output mapping. The default data value is 0b11111111. This
mapping is shown in the table below.
Table 9: Register 10, Imager Internal I/O Direction Register 0
2-10
Bit #
Function
Mapping
7
0 = GPIO_MD8 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
6
0 = GPIO_MD7 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
5
0 = GPIO_MD6 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
4
0 = GPIO_MD5 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
3
0 = GPIO_MD4 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
2
0 = GPIO_MD3 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
1
0 = SPI4_SDI_GPIO_MD2 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
0
0 = GPIO_MD1 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.12 Register 11, Internal I/O Mux Register 0
Register 11 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 10: Register 11, Internal I/O Mux Register 0
Bit #
Muxing
7
0 = GPIO_MD4 MUX SELB
6
0 = GPIO_MD4 MUX SELA
5
0 = GPIO_MD3 MUX SELB
4
0 = GPIO_MD3 MUX SELA
3
0 = SPI4_SDI_GPIO_MD2 MUX SELB
2
0 = SPI4_SDI_GPIO_MD2 MUX SELA
1
0 = GPIO_MD1 MUX SELB
0
0 = GPIO_MD1 MUX SELA
2.1.1.2.13 Register 12, Internal I/O Mux Register 1
Register 12 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 11: Register 12, Internal I/O Mux Register 1
Bit #
Muxing
7
0 = GPIO_MD8 MUX SELB
6
0 = GPIO_MD8 MUX SELA
5
0 = GPIO_MD7 MUX SELB
4
0 = GPIO_MD7 MUX SELA
3
0 = GPIO_MD6 MUX SELB
2
0 = GPIO_MD6 MUX SELA
1
0 = GPIO_MD5 MUX SELB
0
0 = GPIO_MD5 MUX SELA
2-11
Spectrum Digital, Inc
2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1
Register 13 is a 8 bit, read/write register that controls DM365 GPIO to IMAGER
connector pin input/output mapping. The default data is 0b00000000. This mapping is
shown in the table below.
Table 12: Register 13, Imager Internal I/O Direction Register 1
Bit #
Function
Mapping
7
0 = GPIO_MD16 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
6
0 = GPIO_MD15 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
5
0 = GPIO_MD14 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
4
0 = GPIO_MD13 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
3
0 = GPIO_MD12 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
2
0 = GPIO_MD11 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
1
0 = GPIO_MD10 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
0
0 = GPIO_MD9 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
2.1.1.2.15 Register 14, Imager Internal I/O Mux Register 2
Register 14 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 13: Register 12, Imager Internal I/O Mux Register 2
2-12
Bit #
Muxing
7
0 = GPIO_MD12 MUX SELB
6
0 = GPIO_MD12 MUX SELA
5
0 = GPIO_MD11 MUX SELB
4
0 = GPIO_MD11 MUX SELA
3
0 = GPIO_MD10 MUX SELB
2
0 = GPIO_MD10 MUX SELA
1
0 = GPIO_MD9 MUX SELB
0
0 = GPIO_MD9 MUX SELA
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3
Register 14 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 14: Register 15, Imager Internal I/O Mux Register 3
Bit #
Muxing
7
0 = GPIO_MD16 MUX SELB
6
0 = GPIO_MD16 MUX SELA
5
0 = GPIO_MD15 MUX SELB
4
0 = GPIO_MD15 MUX SELA
3
0 = GPIO_MD14 MUX SELB
2
0 = GPIO_MD14 MUX SELA
1
0 = GPIO_MD13 MUX SELB
0
0 = GPIO_MD13 MUX SELA
2.1.1.2.17 Register 16, Imager Internal I/O Direction Register 3
Register 16 is a 8 bit, read/write register that controls DM365 GPIO to IMAGER
connector pin input/output mapping. The default data is 0b00000000. This mapping is
shown in the table below.
Table 15: Register 16, Imager Internal I/O Direction Register 3
Bit #
Function
Mapping
7
Reserved
6
0 = CCD_DDS_RST to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
5
0 = PWM_CCD_SUB to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
4
0 = GPIO_TACH to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
3
0 = GPIO_MST_SLV to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
2
0 = GPIO_MD19 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
1
0 = GPIO_MD18 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
0
0 = GPIO_MD17 to DM365 pin
0 = Outputs
1 = DM365 pins are inputs
2-13
Spectrum Digital, Inc
2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4
Register 17 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 16: Register 17, Imager Internal I/O Mux Register 4
Bit #
Muxing
7
0 = GPIO__MST_SLV MUX SELB
6
0 = GPIO__MST_SLV MUX SELA
5
0 = GPIO_MD19 MUX SELB
4
0 = GPIO_MD19 MUX SELA
3
0 = GPIO_MD18 MUX SELB
2
0 = GPIO_MD18 MUX SELA
1
0 = GPIO_MD17 MUX SELB
0
0 = GPIO_MD17 MUX SELA
2.1.1.2.19 Register 18, Imager Internal I/O Mux Register 5
Register 18 is a 8 bit, read/write register that controls DM365 GPIO Muxing to IMAGER
connector pin input. The default data is 0b00000000. The table below shows this
muxing.
Table 17: Register 17, Imager Internal I/O Mux Register 5
2-14
Bit #
Muxing
7
Reserved
6
Reserved
5
0 = CCD_DDS_RST MUX SELB
4
0 = CCD_DDS_RST MUX SELA
3
0 = PWM_CCD_SUB MUX SELB
2
0 = PWM_CCD_SUB MUX SELA
1
0 = GPIO_TACH MUX SELB
0
0 = GPIO_TACH MUX SELA
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.20 Register 19, Board RESET Register
Register 19 is a 8 bit, read/write register that allows the user to select reset to major
external peripherals. The default data is 0b00000000. The table below shows the
mapping of these bits.
Table 18: Register 19, Board RESET Register
Bit #
RESET Signal
State Action
7
Reserved
N/A
6
Reserved
N/A
5
Reserved
N/A
4
Reserved
N/A
3
ETHERNET_RESET
1 = Force Reset to Logic 0
0 = Map Reset to CPLD inputs
2
TVP7002_RESET
1 = Force Reset to Logic 0
0 = Map Reset to CPLD inputs
1
IC3106_RESET
1 = Force Reset to Logic 0
0 = Map Reset to CPLD inputs
0
TVP5146_RESET
1 = Force Reset to Logic 0
0 = Map Reset to CPLD inputs
2.1.1.2.21 Register 720, CCD Internal I/O Direction Register 1
Register 720 is a 8 bit, read/write register that controls CPLD GPIO to CCD Connector
pin input/output mapping. The default data is 0b11111111. The table below shows the
mapping of these bits.
Table 19: Register 720, CCD Internal I/O Direction Register 1
Bit #
Signal
State Action
7
0 = GPIO_0.7DIR
0 = Outputs, 1 = Inputs
6
0 = GPIO_0.6DIR
0 = Outputs, 1 = Inputs
5
0 = GPIO_0.5DIR
0 = Outputs, 1 = Inputs
4
0 = GPIO_0.4DIR
0 = Outputs, 1 = Inputs
3
0 = GPIO_0.3DIR
0 = Outputs, 1 = Inputs
2
0 = GPIO_0.2DIR
0 = Outputs, 1 = Inputs
1
0 = GPIO_0.1DIR
0 = Outputs, 1 = Inputs
0
0 = GPIO_0.0DIR
0 = Outputs, 1 = Inputs
2-15
Spectrum Digital, Inc
2.1.1.2.22 Register 721, CCD Internal I/O Read/Write Register 1
Register 721 is a 8 bit, read/write register that controls CPLD GPIO input on read, and
out value on write. The default data is 0b00000000. The table below shows the
mapping of these bits.
Table 20: Register 721, CCD Internal I/O Read/Write Register 1
Bit #
Signal
State Action
7
0 = GPIO_0.7
Write bit when DIR = 0
Read bit when DIR = 1
6
0 = GPIO_0.6
Write bit when DIR = 0
Read bit when DIR = 1
5
0 = GPIO_0.5
Write bit when DIR = 0
Read bit when DIR = 1
4
0 = GPIO_0.4
Write bit when DIR = 0
Read bit when DIR = 1
3
0 = GPIO_0.3
Write bit when DIR = 0
Read bit when DIR = 1
2
0 = GPIO_0.2
Write bit when DIR = 0
Read bit when DIR = 1
1
0 = GPIO_0.1
Write bit when DIR = 0
Read bit when DIR = 1
0
0 = GPIO_0.0
Write bit when DIR = 0
Read bit when DIR = 1
2.1.1.2.23 Register 722, CCD Internal I/O Direction Register 2
Register 722 is a 8 bit, read/write register that controls CPLD GPIO to CCD Connector
pin input/output mapping. The default data is 0b11111111. The table below shows the
mapping of these bits.
Table 21: Register 722, CCD Internal I/O Direction Register 2
2-16
Bit #
Signal
State Action
7
0 = GPIO_1.7DIR
0 = Outputs, 1 = Inputs
6
0 = GPIO_1.6DIR
0 = Outputs, 1 = Inputs
5
0 = GPIO_1.5DIR
0 = Outputs, 1 = Inputs
4
0 = GPIO_1.4DIR
0 = Outputs, 1 = Inputs
3
0 = GPIO_1.3DIR
0 = Outputs, 1 = Inputs
2
0 = GPIO_1.2DIR
0 = Outputs, 1 = Inputs
1
0 = GPIO_1.1DIR
0 = Outputs, 1 = Inputs
0
0 = GPIO_1.0DIR
0 = Outputs, 1 = Inputs
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.2.24 Register 723, CCD Internal I/O Read/Write Register 2
Register 723 is a 8 bit, read/write register that controls CPLD GPIO input on read, and
out value on write. The default data is 0b00000000. The table below shows the
mapping of these bits.
Table 22: Register 723, CCD Internal I/O Read/Write Register 2
Bit #
Signal
State Action
7
0 = GPIO_0.7
Write bit when DIR = 0
Read bit when DIR = 1
6
0 = GPIO_0.6
Write bit when DIR = 0
Read bit when DIR = 1
5
0 = GPIO_0.5
Write bit when DIR = 0
Read bit when DIR = 1
4
0 = GPIO_0.4
Write bit when DIR = 0
Read bit when DIR = 1
3
0 = GPIO_0.3
Write bit when DIR = 0
Read bit when DIR = 1
2
0 = GPIO_0.2
Write bit when DIR = 0
Read bit when DIR = 1
1
0 = GPIO_0.1
Write bit when DIR = 0
Read bit when DIR = 1
0
0 = GPIO_0.0
Write bit when DIR = 0
Read bit when DIR = 1
2.1.1.2.25 Register 724, CCD Internal I/O Direction Register 3
Register 724 is a 8 bit, read/write register that controls CPLD GPIO to CCD Connector
pin input/output mapping. The default data is 0b11111111. The table below shows the
mapping of these bits.
Table 23: Register 724, CCD Internal I/O Direction Register 3
Bit #
Signal
State Action
7
0 = GPIO_2.7DIR
0 = Outputs, 1 = Inputs
6
0 = GPIO_2.6DIR
0 = Outputs, 1 = Inputs
5
0 = GPIO_2.5DIR
0 = Outputs, 1 = Inputs
4
0 = GPIO_2.4DIR
0 = Outputs, 1 = Inputs
3
0 = GPIO_2.3DIR
0 = Outputs, 1 = Inputs
2
0 = GPIO_2.2DIR
0 = Outputs, 1 = Inputs
1
0 = GPIO_2.1DIR
0 = Outputs, 1 = Inputs
0
0 = GPIO_2.0DIR
0 = Outputs, 1 = Inputs
2-17
Spectrum Digital, Inc
2.1.1.2.26 Register 725, CCD Internal I/O Read/Write Register 3
Register 725 is a 8 bit, read/write register that controls CPLD GPIO input on read, and
out value on write. The default data is 0b00000000. The table below shows the
mapping of these bits.
Table 24: Register 725, CCD Internal I/O Read/Write Register 1
2-18
Bit #
Signal
State Action
7
0 = GPIO_0.7
Write bit when DIR = 0
Read bit when DIR = 1
6
0 = GPIO_0.6
Write bit when DIR = 0
Read bit when DIR = 1
5
0 = GPIO_0.5
Write bit when DIR = 0
Read bit when DIR = 1
4
0 = GPIO_0.4
Write bit when DIR = 0
Read bit when DIR = 1
3
0 = GPIO_0.3
Write bit when DIR = 0
Read bit when DIR = 1
2
0 = GPIO_0.2
Write bit when DIR = 0
Read bit when DIR = 1
1
0 = GPIO_0.1
Write bit when DIR = 0
Read bit when DIR = 1
0
0 = GPIO_0.0
Write bit when DIR = 0
Read bit when DIR = 1
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.1.1.3 Key Pad Interface
The DM365 has an internal key pad controller. The key pad interface is multiplexed with
the address lines on the asynchronous EMIF. CBTLV multiplexers are used to redirect
the key pad interface to the key pad matrix. This interface can only be used when CE0
is in the NAND configuration. A control bit in the CPLD enables the Mux select on the
CBTLV multiplexers. The 16 bit switch key pad matrix is set up on a 4 x 4 matrix on the
EVM. The mapping of the switches are shown in the table below.
Table 25: Key Pad Layout
Key-A0
Key-A0
Key-A1
Key-A1
Key-B0
SW6 / KEY 2
SW7 / LEFT
SW8 / EXIT
SW9 / DOWN
Key-B0
SW10 / ENTER
SW11 / UP
SW12 KEY 1
SW13 / RIGHT
Key-B1
SW14 / MENU
SW15 / REC
SW16 / REW
SW17 / SKIP-
Key-B1
SW18 / STOP
SW19 / FF
SW20 / SKIP+
SW2 / PLAY/
PAUSE
2.1.2 DDR2 Memory Interface
The DM365 device incorporates a dedicated 16 bit wide DDR2 memory bus. The EVM
uses a single 1 gigabit 16 bit wide memory on this bus, for a total of 128 megabytes of
memory for program, data, and video storage. The internal DDR controller uses a PLL
to control the DDR memory timing. Memory refresh for DDR2 is handled automatically
by the DM365 internal DDR controller.
2.1.3 Media Card Interface
The EVM supports 1 SD/MMC/MS and 1 SD/MMC media card interfaces. The
MMC/SD0 port is dedicated to the SD/MMC/MS media card. The insert and write
protect status can be read via CPLD register. MMC/SD1 port is configured to a second
SD/MMC media card. This port is multiplexed via CBTLV switches to be used as
general purpose I/O pins when the CPLD is appropriately configured for I/O
multiplexing. The insert and write protect pin status can be read via a CPLD register.
2-19
Spectrum Digital, Inc
2.1.4 UART Interface
The internal UART0 on the DM365 device is driven to connector P1. The UART’s
interface is routed to the RS-232 line drivers prior to being brought out to a DB-9
connector, P1.
2.1.5 USB Interface
The DM365 incorporates an on chip USB II controller. This interface is brought out to a
mini A/B connector. Two jumpers are provided to make a flexible Host peripheral, and
USB On The Go interface. J26 is used to manually select the ID pin state. J6 is used to
add additional capacitance to VBUS for host mode operation. A TPS2065 is used to
power VBUS via DRV_VBUS signal for Host mode applications. The CPLD selects the
source pin for DRV_VBUS signals via internal CPLD registers.
2.2 Input Video Port Interfaces/Imager Input Ports
The DM365 EVM supports composite, component, or imager video capture. CBT
multiplexers selected via CPLD registers chose the interface that is connected to the
DM365 video input port. A Texas Instruments TVP5146 is used to decode composite
video or S-video inputs into the device. J15 is used for the S-video inputs and J13 for
the composite inputs on the EVM.
A TVP7002 provides component image capture up to 720P resolution.
J11, J8, J9 interface to a THS7353 amplifier/filter which interfaces directly to the
TVP7002 which drives the DM365 input port.
J10, a DIN96 connector allows users to support imager interfaces. This is mapped
directly to the video input port via CBT mux. The figure below shows this mapping,
Composite
TVP
5146
DM365
S-Video
YPIF
Port
3 to 1 Mux
Component
TVP
7002
THS
7353
Component
Component
MUX_SEL
CLPD
J10, DIN96
Image
Connector
Figure 2-1, DM365 EVM Input Video Mapping
2-20
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.2.1 On Chip Video Output DAC
The DM365 incorporates 1 TV composite video output DAC and 3 component video
DACs to interface to composite and component video outputs. The TV Out DAC is
filtered and driven to RCA jack, J16.
The component output DACs are driven into a THS7303 video amplifier and output to
RCA connectors J21, J17, J20.
2.2.2 LCD Video Connectors
The DM365 incorporates 3 interface connectors; J18, J19, and J23 for digital video
output for interfacing to LCD displays. The pinouts for these displays are detailed in
section 3 of this manual.
2-21
Spectrum Digital, Inc
2.3 AIC3101 Interface
The EVM uses a Texas Instruments TLV320AIC3101 stereo codec for input and output
of audio signals. The codec samples analog signals on the microphone or line inputs
and converts them into digital data so it can be processed by the DSP. When the DSP
is finished with the data it uses the codec to convert the samples back into analog
signals on the line output so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I2C bus
is used as the AIC3101’s control channel. The control channel is generally only used
when configuring the codec, it is typically idle when audio data is being transmitted,
The DM365’s McBSP is used as the bi-directional data channel. All audio data flows
through the data channel. Many data formats are supported based on the three
variables of sample width, clock signal source and serial data format. The EVM
examples generally use a 16-bit sample width with the codec in master mode so it
generates the frame sync and bit clocks at the correct sample rate without effort on the
DSP side.
The codec is clocked via a 27 Mhz oscillator. The internal sample rate generator
subdivides the default system clock to generate common audio frequencies. The
sample rate is set by a codec register. The figure below shows the codec interface on
the DM365 EVM.
AIC33 Codec
AIC3101
Codec
MIC IN
2
IC
SCL
SDA
Control
I2C Format
SCL
SDA
LINE IN
Control Registers
Analog
Digital
LINE OUT
DR
DX
CLKR
CLKX
FSR
FSX
McBSP
I2S Format
DOUT
DIN
BCLK
WCLK
MIC IN
ADC
LINE IN
DAC
LINE OUT
HP OUT
HP OUT
Figure 2-2, DM365 EVM CODEC Interface
2-22
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.4 On Chip Voice Codec
The DM365 integrates a single channel voice codec. The input for this codec is
connected to on board microphone M1. The output of this codec is connected to on
board speaker SPK1.
2.5 On Chip Analog to Digital Converter (ADC)
The DM365 has an on chip 6 channel Analog to Digital Converter (ADC). Four of the
channels are interfaced to on board voltages and two channels are connected to test
points as shown in the table below.
Table 26: On Chip Analog to Digital Converter
Channel
Input Signal
ADC_CH0
CCD_PSMON
ADC_CH1
VCC_3V3
ADC_CH2
CPU_VCC_1V8
ADC_CH3
VCC_1V2
ADC_CH4
TP37
ADC_CH5
TP36
2.6 On Chip RTC
The DM365 integrates an on chip real time clock. The Real Time Clock is battery
backed up via TPS65510 and Battery BHT1. The EVM is not shipped with a backup
battery. The mode of operation for the Real Time Clock is configured via switch SW23,
as defined in section 3.
2-23
Spectrum Digital, Inc
2.7 Ethernet Interface
The DM365 incorporates an internal MII ethernet MAC which interfaces to a
Mircel 10/100 ethernet Phy. The 10/100 Mbit interface is isolated and brought out to a
RJ-45 standard ethernet connector, P2. The ethernet address is stored in the on board
I2C EEPROM manufacturing.
For GPIO modes of operation when the MII interface is not used CBTLV multiplexes
and directs the I/O to the on board CPLD used as imager expansion I/Os.
The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow
and indicate the status of the ethernet link. The green LED, when on, indicates link and
when blinking indicates link activity. The yellow LED, when illuminated, indicates full
duplex mode.
2.8 I2C Interface
The I2C bus on the DM365 is ideal for interfacing to the control registers of many
devices. On the DM365 EVM the I2C bus is used to configure the video decoders,
stereo Codec, video amplifiers, I2C EEPROM, and communicate with the MSP430.
An I2C ROM is also interfaced via the serial bus. The format of the bus is shown in the
figure below.
Start Slave Address W
ACK Sub Address ACK-S Data ACK-S Stop
Write Sequence
Start Slave Address R
Data
STOP
Read Sequence
Figure 2-3, I2C Bus Format
The addresses of the on board peripherals are shown in the table below.
Table 27: I2C Memory Map
2-24
Device
Address
R/W
Function
AIC3101
0x18
R/W
CODEC
MSP430
0x25
R/W
IR Controller
THS7303
0x2C
R/W
Video Output Amplifier
THS7353
0x2E
R/W
Video Input Amplifier
CAT24C256
0x50
R/W
I2C EEROM
TVP7002
0x5C
R/W
Component Decoder
TVP5146
0x5D
R/W
Composite 1 Decoder
DM365 EVM Technical Reference
Spectrum Digital, Inc
2.8.1 MSP430
The DM365 EVM incorporates infrared remote, interface using a MSP430
microcontroller. The I2C interface is used on the DM365 processor to communicate to
the MSP430. The MSP430 acts as a slave device on the I2C bus.
2.9 Daughter Card Interfaces
The EVM provides expansion connectors that can be used to accept plug-in daughter
cards. The daughter card allows users to build on their EVM platform to extend its
capabilities and provide customer and application specific interfaces. The
Asynchronous EMIF is brought out to J14. The video digital output port is brought out to
the daughter card interface along with I/O and imager interface is brought out to a
DIN96 connector as detailed previously.
2.10 DM365 CPU/Video Clocks
The DM365 EVM uses a 24 Megahertz crystal to generate the main input clock. The
DM365 has multiple internal PLLs which can multiply the input clock to generate the
internal clocks. The PLL’s multipliers are set via software on the DM365 device.
The Real Time clock uses a 32,768 hertz crystal.
2-25
Spectrum Digital, Inc
2.11 Battery
The DM365 EVM incorporates a battery holder to provide backup power to the
internal real time clock when the power is not applied to the board. The optional
battery should be +3 volt 20 millimeter coin type Lithium single cell.
Some common part numbers for batteries which should operate in the EVM are shown
in the table below.
Table 28: Battery Part Numbers
Part Numbers
CR2032
DL2032
BR2032
CR2025
BR2025
CR2016
BR2016
DL2016
These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,
Sony, Sieko, Toshiba, Varta, and other battery manufacturers.
2-26
DM365 EVM Technical Reference
Chapter 3
Physical Description
This chapter describes the physical layout of the DM365 EVM and its
interfaces.
Topic
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3.2.20
3.2.21
3.2.22
3.2.23
3.2.24
3.2.25
3.2.26
3.2.27
Page
Board Layout
Connectors
J1, USB MiniAB Connector and Jumpers
J2, 14 Pin External JTAG Connector
J3, MSP430 JTAG Header
J4, Spare Jumper Holder
J5, 20 Pin ARM JTAG Emulation Header
J6, USB Capacitance Select
J7, +5 Volts Input
J12, SD/MMC/MS Card Interface
J10, Imager Interface
J14, EMIF/UPI DC Interface
J8, Y Component Video In, RCA Jack (Green)
J9, Pb Component Video In, RCA Jack (Blue)
J11, Pr Component Video In, RCA Jack (Red)
J15, S-Video In
J13, CVBS/Y Input, RCA Jack (Yellow)
J16, Composite TV Out, RCA Jack (Yellow)
J17, Y Component Video Out, RCA Jack (Green)
J20, Pb Component Video Out, RCA Jack (Blue)
J21, Pr Component Video Out, RCA Jack (Red)
J18, J19, Video Output DC
J22, CPLD Programming Header
J23, I/O Interface Header
J24, DILC Host Connector
J25, MMC/SD Connector
P1, RS-232 UART
P2, Ethernet Interface
P3, Microphone In
3-3
3-5
3-6
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-12
3-13
3-13
3-14
3-14
3-15
3-15
3-16
3-16
3-17
3-18
3-19
3-19
3-20
3-21
3-22
3-23
3-24
3-1
Spectrum Digital, Inc
Topic
3.2.28
3.2.29
3.2.30
3.2.31
3.2.32
3.2.33
3.2.34
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.5
3.5.1
3.6
3-2
Page
P4, Line In
P5, Line Out
P6, Headphone Out
U1, Infrared Interface
SPK1, Speaker Interface
BHT1, Battery Interface
M1, Microphone Interface
LEDs
Switches
SW1, EMU0/1 Select Switch
SW2, PWCTRO0 Pushbutton
SW3, Non-Supported Pushbutton
SW4, Boot Mode / Processor Configuration Select
SW5, Board Configuration Select
SW6 - SW21, Function Pushbuttons
SW22, MSP430 IO0 Pushbutton
SW23, PRTSC Mode Select
Jumpers
JP1, Jumper Block
Test Points
3-24
3-25
3-25
3-26
3-26
3-27
3-27
3-28
3-29
3-30
3-30
3-30
3-31
3-32
3-32
3-33
3-33
3-34
3-34
3-35
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.1 Board Layout
The DM365 EVM is a 8.0 x 8.7 inch (203 x 221 mm.) ten (10) layer printed circuit board
which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout
of the top side of the DM365 EVM.
J4
P1
J6
J1
SW1 BHT1 J2 J5
P2 J10 J3 SW22
DS1
M1
JP1
P3
J7
P4
SW2
P5
SW3
P6
SW23
J8
J12
J9
SW4
J11
DS2-DS9
J14
J13
SW5
J15
J18
J16
SW6-8
J17
SW9-11
J20
SW12-14
J19
SW15-17
J21
J22
SPK1
SW18-20
J23
SW21
J24
Figure 3-1, DM365 EVM, Interfaces Top Side
3-3
Spectrum Digital, Inc
Figure 3-2 shows the layout of the bottom side of the DM365 EVM.
J25
Figure 3-2, DM365 EVM, Interfaces Bottom Side
3-4
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2 Connectors
The DM365 EVM has numerous connectors, option jumpers, and interfaces to control
and provide connections to various peripherals. These connectors and jumpers are
described in the following sections.
Table 1: DM365 Connectors
Connector
Size
Function
J1
1x4
USB MiniAB Connector
J2
2x7
14 Pin TI JTAG Emulation Header
J3
7x2
MSP430 JTAG Header
J4
3x2
Spare Jumper Holder
J5
10 x 2
20 Pin ARM JTAG Emulation Header
J6
2x1
USB Capacitor Select
J7
2
+5 Volts In
J8
2
Y Component Video In, RCA Jack (Grn)
Pb Component Video In, RCA Jack (Blue)
J9
2
J10
32 x 3
Imager Interface
J11
2
Pr Component Video In, RCA Jack (Red)
J12
2
SD/MMC/MS Card Interface
J13
2
CVBS/Y Input, RCA Jack (Yellow)
J14
30 x 2
EMIF/UPHI DC Interface
J15
4
S-video In, DIN connector
J16
2
Composite TV Out, RCA Jack (Yellow)
J17
2
Y Component Video Output, RCA Jack (Green)
J18
15 x 2
Video Output DC
J19
15 x 2
Video Output DC
J20
2
Pb Component Video Output, RCA Jack (Blue)
J21
2
Pr Component Video Output, RCA Jack (Red)
J22
5x2
CPLD Programming Header
J23
15 x 2
I/O Interface Header
J24
20 x 1
DILC Host Connector
J25
9
MMC/SD Card Interface
P1
9
RS-232 UART
P2
6
Ethernet Interface
P3
4
Microphone In
P4
4
Line In
P5
4
Line Out
P6
4
Headphone Out
U1
3
Infrared Interface
SPK1
2
Speaker
BHT1
2
Battery Holder
M1
2
Microphone
3-5
Spectrum Digital, Inc
3.2.1 J1, USB MiniAB Connector and Jumpers
Connector J1 is a mini A/B USB connector. The pinout for the J1 connector is shown in
the table below.
Table 2: J1, MiniAB USB Connector
Pins
Signal
1
USB_VBUS_CONN
2
USB_DM
3
USB_DP
4
USB_ID
5
GND
The EVM incorporates the ability to toggle the ID pin on the USB connector via
software control. The USB_ID pin on the DM365 controls this function.
For “USB ON The Go” mode remove jumper J6. This will allow the cable to configure
the ID pin on the DM365 processor.
The EVM supplies up to 500 ma of current to the USB_VBUS via a TPS61092 DC/DC
converter. This is enabled via the DM365’s DRV_VBUS pin. J50 supplies extra
capacitance for host mode operations. Remove J50 for “USB On The Go” operations.
Spare jumpers can be stored on connector J4.
3-6
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.2 J2, 14 Pin External JTAG Connector
Connector J2 is a 2 x 7 double row male header with pin 6 clipped to serve as a key.
This is the standard interface used by JTAG emulators to interface to Texas
Instruments processors. The pinout for the connector is shown in the figure below.
TMS
TDI
PD (+3.3V)
TDO
TCK-RET
TCK
EMU0
1
3
5
7
9
11
13
2
4
6
8
10
12
14
TRSTGND
no pin (key)
GND
GND
GND
EMU1
Header Dimensions
Pin-to-Pin spacing, 0.100 in. (X,Y)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
Figure 3-3, J2, 14 Pin External JTAG Connector
The signal names for each pin are shown in the table below.
Table 3: J2, 14 Pin External JTAG Connector
Pin #
Signal Name
Pin #
Signal Name
1
TMS
2
TRST-
3
TDI
4
GND
5
PD
6
no pin - key
7
TDO
8
GND
9
TCKRET
10
GND
11
TCK
12
GND
13
EMU0
14
EMU1
* Note: EMU0/EMU1 mode must be selected to ICEPICK mode
3-7
Spectrum Digital, Inc
3.2.3 J3, MSP430 JTAG Header
The J3, MSP430 JTAG header, is located on the top side of the board and is used to
provide a programming interface to the MSP430 microcontroller. The pinout for
the J3 connector is shown in the table below. This connector is typically used for
factory use only.
1
2
MSP430 EMU
Figure 3-4, J3, MSP430 JTAG Header
Table 4: J3, MSP430 JTAG Header
Pin #
Signal
Pin #
Signal
1
430_TDO/TDI
2
NC
3
NC
4
MSP430_3V3
5
NC
6
NC
7
TCK
8
NC
9
GND
10
NC
11
NC
12
NC
13
NC
14
NC
3.2.4 J4, Spare Jumper Holder
J4 is a 3 x 2 connector used to hold unused jumper plugs that from time to time may
be required in other connectors/jumpers on the D365 EVM. The pins on this connector
are not connected to any signals.
3-8
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.5 J5, 20 Pin ARM JTAG Emulation Header
The J5 emulation header is located on the top side of the board and is used to provide
an interface to ARM compatible JTAG emulators. The pinout for this connector is
shown in the table below.
Table 5: J5, 20 Pin ARM JTAG Emulation Header
Pin #
Signal
Pin #
Signal
1
VCC_3V3
2
VCC_3V3
3
ARM_TRSTn
4
Ground
5
ARM_TDI
6
Ground
7
ARM_TMS
8
Ground
9
ARM_TCK
10
Ground
11
ARM_TCKRET
12
Ground
13
ARM_TDO
14
Ground
15
ARM_RSTn
16
Ground
17
NC
18
Ground
19
NC
20
Ground
* Note: EMU0/EMU1 switch must be set to ARM mode
3.2.6 J6, USB Capacitance Select
The J6 jumper is used to provide more capacitance when the USB connector is used
in the host mode. When the jumper is shorted the extra capacitance is provided. These
open and shorted position are shown below.
Shorted
Open
USB VBUS
USB VBUS
J6
J6
Figure 3-5, J6, USB Capacitance Select
Table 6: J6, USB Capacitance Select
Position
Function
Open
6.8 uF Capacitance
Shorted
106.8 uF Capacitance
3-9
Spectrum Digital, Inc
3.2.7 J7, +5 Volts Input
Connector J7 is the input power connector. This connector brings in +5 volts to the
EVM. This is a 2.5mm. jack. The inside of the jack is tied to through a fuse to VCC_5V.
The other side is tied to ground and LED DS1. The figure below shows this connector
as viewed from the card edge.
+5V
J7
Ground
PC Board
Front View
Figure 3-6, J7, +5 Volt Input Connector
3.2.8 J12, SD/MMC/MS Card Interface
The J12 SD/MMC/MS Card Interface connector is located on the top side of the board
and is used to provide an interface to a SD/MMC/MS card. The pinout for the J12
connector is shown in the table below.
Table 7: J12, SD/MMC/MS Connector
3-10
Pin #
Signal
Pin #
Signal
1
SD.DATA3
2
SD.CMD
3
SD.VSS1
4
VCC_3V3
5
SD.CLK
6
SD.VSS2
7
SD.DATA0
8
SD.DATA1
9
SD.DATA2
10
GND
11
MS.BS
12
MS.DATA1
13
MS.SDIO/DATA0
14
MS.DATA2
15
MS.XINS
16
MS.DATA3
17
MS.CLK
18
VCC_3V3
19
GND
20
WP
21
INS
22
GND
23
GND
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.9 J10, Imager Interface
Connector J10 is 32 x 3 connector used to interface to external imager logic. The pin
out for this connector is shown in the table below.
Table 8: J10, Imager Interface
Pin
Signal
Pin
Signal
Pin
Signal
A1
Ground
B1
GPIO_MD10
C1
GND_STB
A2
Ground
B2
GPIO_MD9
C2
GND_STB
A2
CCD_PSMON
B2
GPIO_MD8
C2
3V3_STB
A4
GPIO_MD1
B4
GPIO_MD7
C4
5V_DC_J6
A5
5V_DC_J6
B5
5V_DC_J6
C5
5V_DC_J6
A6
GND_MTR
B6
MOT_PWR
C6
GPIO_MD19
A7
GND_MTR
B7
MOT_PWR
C7
GPIO_MD18
A8
NC
B8
CCD_DATA0
C8
GPIO_MST_SLV
A9
CDD_DATA2
B9
CCD_DATA15
C9
GPIO_MD17
A10
Ground
B10
CCD_DATA1
C10
GPIO_MD16
A11
CDD_DATA3
B11
GPIO_MD6
C11
GPIO_MD15
A12
Ground
B12
GPIO_MD5
C12
GPIO_MD14
A13
CDD_DATA4
B13
GPIO_MD4
C13
GPIO_MD13
A14
Ground
B14
Ground
C14
GPIO_TACH
A15
CDD_DATA5
B15
PWM_CCD_SUB
C15
GPIO_MD12
A16
Ground
B16
CCD_DDSRST
C16
GPIO_MD11
A17
CDD_DATA6
B17
GPIO_MD3
C17
I2C_DATA
A18
Ground
B18
GPIO_MD2
C18
I2C_SCLK
A19
CDD_DATA7
B19
SPI4_SDO
C19
VCC_CCD15V
A20
Ground
B20
SPI4_SCLK
C20
VCC_CCD15V
A21
CDD_DATA8
B21
Ground
C21
VCC_CCD_N75V
A22
Ground
B22
CDD_PCLK
C22
VCC_CCD_N75V
A23
CDD_DATA9
B23
Ground
C23
3V3_CCD
A24
Ground
B24
CDD_WEN
C24
3V3_CCD
A25
CDD_DATA10
B25
Ground
C25
5V_DC_J6
A26
Ground
B26
CDD_FIELD
C26
5V_DC_J6
A27
CDD_DATA11
B27
Ground
C27
Ground
A28
Ground
B28
CDD_HSYNC
C28
Ground
A29
CDD_DATA12
B29
Ground
C29
3V3A_CCD
A30
Ground
B30
CDD_VSYNC
C30
3V3A_CCD
A31
CDD_DATA13
B31
Ground
C31
AGND_IMAGER
A32
Ground
B32
CDD_DATA14
C32
AGND_IMAGER
3-11
Spectrum Digital, Inc
3.2.10 J14, EMIF/UPI DC Interface
Table 9: J14, EMIF/UPI DC Interface
3-12
Pin
Signal
Pin
Signal
2
Ground
1
Ground
4
EM_D0
3
EM_D1
6
EM_D2
5
EM_D3
8
EM_D4
7
EM_D5
10
EM_D6
9
EM_D7
12
Ground
11
Ground
14
EM_D8
13
EM_D9
16
EM_D10
15
EM_D11
18
EM_D12
17
EM_D13
20
EM_D14
19
EM_D15
22
Ground
21
Ground
24
EM_WAIT
23
EM_CLK
26
Ground
25
Ground
28
EM_CE0
27
EM_ADV
30
Ground
29
Ground
32
EM_CE1
31
EM_WE
34
Ground
33
Ground
36
EMIF_SEL
35
EM_OE
38
Ground
37
Ground
40
EM_BA0
39
EM_BA1
42
EM_A0
41
EM_A1
44
EM_A2
43
EM_A3
46
EM_A4
45
EM_A5
48
Ground
47
Ground
50
EM_A6
49
EM_A7
52
EM_A8
51
EM_A9
54
EM_A10
53
EM_A11
56
EM_A12
55
EM_A13
58
VCC_3V3
57
VCC_3V3
60
VCC_5V
59
VCC_5V
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.11 J8, Y Component Video In, RCA Jack (Green)
J8 is an RCA jack used as a Y component input to the THS7353, U15, pin 3. The
figure below shows this connector as viewed from the card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-7, J8, Y Component Video In, RCA Jack
Table 10: J8, Y Component Video In, RCA Jack
Pin #
Signal Name
1
TVP_AGND
2
CH2-INA, U15, Pin 3
3
TVP_AGND
4
TVP_AGND
3.2.12 J9, Pb Component Video In, RCA Jack (Blue)
J9 is an RCA jack used as a Pb component input to the THS7353, U15, pin 4. The
figure below shows this connector as viewed from the card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-8, J9, Pb Component Video In, RCA Jack
Table 11: J9, Pb Component Video In, RCA Jack
Pin #
Signal Name
1
TVP_AGND
2
CH3-INA, U15, Pin 4
3
TVP_AGND
4
TVP_AGND
3-13
Spectrum Digital, Inc
3.2.13 J11, Pr Component Video In, RCA Jack (Red)
J11 is an RCA jack used as a Pr component input to the THS7353, U15, pin 2. The
figure below shows this connector as viewed from the card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-9, J11, Pr Component Video In, RCA Jack
Table 12: J11, Pr Component Video In, RCA Jack
Pin #
Signal Name
1
TVP_AGND
2
CH1-INA, U15, Pin 2
3
TVP_AGND
4
TVP_AGND
3.2.14 J15, S-Video In
Connector J15 is a four pin mini din connector which interfaces to the TVP5146
encoder, U24. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146.
Do NOT plug into this connector with the power on. The figure below shows this
connector as viewed from the card edge.
Pin 3
Pin 1
Pin 4
Pin 2
Figure 3-10, J15, Front View, Mini Din Connector
Table 13: J15, S-Video In, Mini Din Connector
3-14
Pin #
Signal Name
1
GND
2
GND
3
VI_1_C, U24, Pin 2
4
Chroma
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.15 J13, CVBS/Y Input, RCA Jack (Yellow)
J13 is an RCA jack used as the CVBS/Y input to the TVP5146. The figure below shows
this connector as viewed from the card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-11, J13, CVBS/Y Input, RCA Jack
Table 14: J13, CVBS/Y Input, RCA Jack
Pin #
Signal Name
1
DEC_GND
2
VI_2_B, U24, Pin 8, TVP5146
3
DEC_GND
2
DEC_GND
3.2.16 J16, Composite TV Out, RCA Jack (Yellow)
J16 is an RCA jack used as a TV output from the DM365. This connector brings out a
TV signal. The figure below shows this connector as viewed from the card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-12, J16, Composite TV Out RCA Jack
Table 15: J16, Composite TV Out, RCA Jack
Pin #
Signal Name
1
DEC_GND
2
U18-3, Pin A10
3
DEC_GND
2
DEC_GND
3-15
Spectrum Digital, Inc
3.2.17 J17, Y Component Video Out, RCA Jack (Green)
J17 is an RCA jack used as a green component output from the THS7303 DAC, U23,
pin 17, signal CH2-OUT. The figure below shows this connector as viewed from the
card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-13, J17, Y Component Video Out, RCA Jack
Table 16: J17, Y Component Video Out, RCA Jack
Pin #
Signal Name
1
DENC_GND
2
THS7303 DAC, U23, pin 19,signal CH2-OUT
3
DENC_GND
4
DENC_GND
3.2.18 J20, Pb Component Video Out, RCA Jack (Blue)
J20 is an RCA jack used as a Pb component output from the THS7303 DAC, U23,
pin 15, signal CH3-OUT. The figure below shows this connector as viewed from the
card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Input
Figure 3-14, J20, Pb Component Video Out, RCA Jack
Table 17: J20, Pb Component Video Out, RCA Jack
Pin #
Signal Name
1
DENC_GND
2
3-16
THS7303 DAC, U23, pin 15,signal CH3-OUT
3
DENC_GND
2
DENC_GND
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.19 J21, Pr Component Video Output, RCA Jack (Red)
J21 is an RCA jack used as a Pr component output from the THS7303 DAC, U23,
pin 19, signal CH1-OUT. The figure below shows this connector as viewed from the
card edge.
Pin 1,3,4 Shield (ground)
Pin 2, Signal Output
Figure 3-15, J21, Pr Component Video Out, RCA Jack
Table 18: J21, Pr Component Video Out, RCA Jack
Pin #
Signal Name
1
DENC_GND
2
THS7303 DAC, U23, pin 19, signal CH1-OUT
3
DENC_GND
4
DENC_GND
3-17
Spectrum Digital, Inc
3.2.20 J18, J19, Video Output DC
Connectors J18 and J19 make up the interface to the video output DC interface. The
signals on each of these connectors are shown in the tables below.
Table 19: J18, Video Output DC
Pin
Signal
Pin
Signal
1
BL_6V6
2
LCD_3V3
3
BL_6V6_RTN
4
LCD_3V3
5
Ground
6
Ground
7
VDOUT_VSYNC
8
NC
9
Ground
10
LCD_V5
11
VDOUT_HSYNC
12
LCD_V5
13
Ground
14
Ground
15
VDOUT_VCLK
16
CDOUT_FIELD
17
Ground
18
15V_LCD
19
BAT_VIN
20
15V_LCD
21
BAT_VIN
22
Ground
23
SPI1_SDI
24
VDOUT_EXTCLK
25
SPI1_SDENA0
26
I2C_DATA
27
SPI1_SDO
28
I2C_SCLK
29
SPI__SCLK
30
Ground
Table 20: J19, Video Output DC
3-18
Pin
Signal
Pin
Signal
1
VDOUT_Y0
2
VDOUT_C0
3
R1_GIO33
4
Ground
5
VDOUT_Y1
6
VDOUT_C1
7
R1_GIO32
8
Ground
9
VDOUT_Y2
10
VDOUT_C2
11
R1_GIO30
12
Ground
13
VDOUT_Y3
14
VDOUT_C3
15
Ground
16
Ground
17
VDOUT_Y4
18
VDOUT_C4
19
Ground
20
Ground
21
VDOUT_Y5
22
VDOUT_C5
23
Ground
24
Ground
25
VDOUT_Y6
26
VDOUT_C6
27
Ground
28
Ground
29
VDOUT_Y7
30
VDOUT_C7
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.21 J22, CPLD Programming Header
The J22, CPLD programming header, is for use by the factory. This header is not
intended to be used outside the factory. The signals on this header are shown in the
table below.
Table 21: J22, CPLD Programming Header
Pins
Signal
Pins
Signal
1
ISR_TCK
2
Ground
3
ISR_TDO
4
VCC_3V3
5
ISR_TMS
6
NC
7
NC
8
NC
9
ISR_TDI
10
Ground
3.2.22 J23, I/O Interface Header
Connector J23 is an I/O interface header allowing the user to connect external
logic to interface with the I/O pins on the CPLD U33. The signals on this header are
shown in the table below.
Table 22: J23, I/O Interface Header
Pins
Signal
Pins
Signal
2
VCC_1V8
1
VCC_1V8
4
NC
3
NC
6
CPLD.COMM_GIO6
5
CPLD.COMM_GIO7
8
CPLD.COMM_GIO16
7
CPLD.COMM_GIO17
10
CPLD.COMM_GIO54
9
CPLD.COMM_GIO67
12
CPLD.COMM_GIO65
11
CPLD.COMM_GIO31
14
CPLD.COMM_GIO63
13
CPLD.COMM_GIO64
16
CPLD.COMM_GIO62
15
CPLD.COMM_GIO61
18
CPLD.COMM_GIO60
17
CPLD.COMM_GIO59
20
CPLD.COMM_GIO58
19
CPLD.COMM_GIO57
22
CPLD.COMM_GIO56
21
CPLD.COMM_GIO32
24
NC
23
NC
26
NC
25
NC
28
CPLD.CONN_RESETn
27
NC
30
Ground
29
Ground
3-19
Spectrum Digital, Inc
3.2.23 J24, DILC Host Connector
J24 is the DILC Host Connector. The signals on this connector are shown in the table
below.
Table 23: J24, DILC Host Connector
3-20
Pins
Signal
1
CAM_PWR
2
CAM_PWR
3
SPI2_SCLK_DILC
4
Ground
5
SPI2_SDO_DILC
6
Ground
7
SPI2_SDI_DILC
8
Ground
9
LINEOUT
10
AVJ_DET
11
TP53
12
TP33
13
GIO_DILC_CHG_CTL
14
CD1
15
CD2
16
VBUS1
17
TP54
18
Ground
19
TVOUT
20
Ground
MP1
Ground
MP2
Ground
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.24 J25, MMC/SD Connector
The J25 MMC/SD connector is located on the bottom side of the board and is used to
provide an interface to a MMC/SD card. The pinout for the J25 connector is shown in
the table below.
Table 24: J25, MMC/SD Connector
Pin #
Signal
Pin #
Signal
1
CONN_SD1_DATA3
2
CONNSD1_CMD
3
GND
4
VCC_3V3
5
CONN_SD1_CLK
6
GND
7
CONN_SD1_DATA0
8
CONN_SD1_DATA1
9
CONN_SD1_DATA2
10
WP, VCC_3V3
11
GND
12
CARD_DETECT
3-21
Spectrum Digital, Inc
3.2.25 P1, RS-232 UART
The P1 connector is a 9 pin male D-connector which provides a UART interface to the
EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U3) and is
located on the top side of the board. A view of the connector from the card edge is
shown in the figure below. The signals present on this connector are defined in the
following table.
4
5
9
3
8
2
7
1
6
Figure 3-16, P1, DB9 Male Connector
The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.
Table 25: P1, RS-232 UART Pinout
3-22
Pin #
Signal Name
1
NC
2
R_IN, U3, Pin 8
3
T_OUT, U3, pin 13
4
NC
5
GND
6
NC
7
Pin 8
8
Pin 7
9
NC
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.26 P2, Ethernet Interface
The P2 connector is located on the top side of the board and is used to provide an
Ethernet interface. P2 integrates the magnetics and standard RJ-45 connector. The
two tables below show the signals present on the magnetics interface and the
connector side.
Table 26: P2, Magnetics/LEDs Interface Signals
Pin #
Signal
Pin #
Signal
1
TX+, U5, Pin 41
2
TX-, U5, Pin 40
3
RX+, U5, Pin 33
4
VDD_3V3A
5
VDD_3V3A
6
RX-, U5, Pin 32
7
NC
8
GND_E_NET
9
VCC_3V3A
10
EPHY_LED2
11
VCC_3V3A
12
EPHY_LED0
The ethernet connector incorporates 2 LEDs which give link and transmit status from
the ethernet controller.
Table 27: P2, RJ-45 Connector
Pin #
Signal
Pin #
Signal
1
TXD+
2
TXD-
3
RXD+
4
TXD-CT
5
RXD-CT
6
RXD-
7
NC
8
GND
9
LED1+
10
LED1-
11
LED2+
12
LED2-
3-23
Spectrum Digital, Inc
3.2.27 P3, Microphone In
The microphone input, P3, is a 3.5 mm. stereo jack. Both inputs are connected to the
microphone so it is monaural. The signal is connected to signals “MIC2R” and “MIC2L”
of the TVL320AIC3101. The signals on the plug are shown in the figure below.
Ground (sleeve)
Microphone In (tip and ring)
Figure 3-17, P3, Microphone Input Jack
Table 28: P3, Microphone Input Jack
Pin #
Signal Name
1
GND_AIC
2
MIC2L, MIC2R, U7, Pins 14,16
3
MIC2L, MIC2R, U7, Pins 14,16
4
GND_AIC
3.2.28 P4, Line In
Connector P4 is an audio stereo line input to the TVL320AIC3101, U7, on the EVM.
The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown
in the figure below.
Ground (sleeve)
Left Line In (ring)
Right Line In (tip)
Figure 3-18, P4, Audio Stereo Line In Jack
Table 29: P4, Audio Stereo Line In
3-24
Pin #
AIC3101 Signal
1
GND_AIC
2
LINE1LP, U7, Pin 10
3
LINE1RP, U7, Pin 12
4
GND_AIC
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.29 P5, Line Out
The connector P5, is an audio stereo output from the TVL320AIC3101, U7, on the
EVM. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are
shown in the figure below.
Ground (sleeve)
Right Line Out (ring)
Left Line Out (tip)
Figure 3-19, P5, Audio Line Out Stereo Jack
Table 30: P5, Audio Line Out Stereo Jack
Pin #
AIC3101 Signal
1
GND_AIC
2
LEFT_LO+, U7, Pin 27
3
RIGHT_LO+, U7, Pin 29
4
NC
3.2.30 P6, Headphone Out
The P6 connector is a 3.5 mm. stereo headphone output from the TVL320AIC3101,
U7, on the EVM. This connector is located on the top side of the board. A view of the
connector from the card edge is shown in the figure below. The signals present on this
connector are defined in the following table.
Headphone Out
Figure 3-20, P6, Headphone Out Interface
Table 31: P6, Headphone Out Interface
Pin #
AIC3101 Signal
1
GND_AIC
2
HPLOUT, U7, Pin 19
3
HPROUT, U7, Pin 23
4
NC
3-25
Spectrum Digital, Inc
3.2.31 U1, Infrared Interface
U1 is an infrared receiver mounted on the edge of the board. This device interfaces to
the MSP430 mircrocontroller. The view of U1 is shown from a board edge view in the
figure below.
U1
PC Card
Figure 3-21, U1, IR Interface, Card Edge View
The receiver supports interaction with an Infrared remote control included with your
EVM.
Table 32: U1, Infrared Interface
U1 Pin #
MSP430 Signal, Pin #
1
P1.2/TA1/A1+/A4-, U2, Pin 4
2
GND
3
VCC_3V3
3.2.32 SPK1, Speaker Interface
The speaker interface SPK1 provides a speaker output driven directly from the DM365
processor. The connections going to the processor are shown in the table below.
Table 33: SPK1, Speaker Interface
3-26
SPK1 Pin #
DM365 Name, Pin #
1
SPP, U18, Pin B9
2
SPN, U18, Pin A9
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.2.33 BHT1, Battery Interface
BHT1 is a holder for a BA2032SM battery. The signals on each pin are shown below
in the table below.
Table 34: BHT1, Battery Interface
BHT1 Pin #
BHT1 Connection
1
VBK, Up, Pin 13
2
Ground
3.2.34 M1, Microphone Interface
The microphone interface, M1, provides a microphone input directly into the DM365
processor. The connections going to the processor are shown in the table below.
Table 35: M1, Microphone Interface
M1 Pin #
DM365 Signal Name, Pin #
1
MICIP, U18-9, Pin B8
2
MICIN, U18-9, Pin C9
3-27
Spectrum Digital, Inc
3.3 LEDs
The EVM has nine (9) LEDs which are located on the top side of the board.
Information regarding the LEDs are shown in the table below.
Table 36: LEDs
3-28
LED #
Use
Color
DS1
+5 Volts present
Green
DS2
User control via MSP430 I2C
Green
DS3
User control via MSP430 I2C
Green
DS4
User control via MSP430 I2C
Green
DS5
User control via MSP430 I2C
Green
DS6
User control via MSP430 I2C
Green
DS7
User control via MSP430 I2C
Green
DS8
User control via MSP430 I2C
Green
DS9
User control via MSP430 I2C
Green
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.4 Switches
The EVM has twenty-three (23) switches. The function of these switches are shown in
the table below.
Table 37: Switches
Switch
Function
Type
Silkscreen
SW1
EMU0/EMU1 Control
2 Position DIP
SW2
PRTSC ON
Push Button/Momentary
SW3
Non-Supported
Push Button/Momentary
SW4
Boot/Config Select
6 Position DIP
SW5
Board Select
6 Position DIP
SW6
User Readable
Push Button/Momentary
KEY2
SW7
User Readable
Push Button/Momentary
LEFT
SW8
User Readable
Push Button/Momentary
EXIT
SW9
User Readable
Push Button/Momentary
DOWN
SW10
User Readable
Push Button/Momentary
ENTER
PRTSCC
SW11
User Readable
Push Button/Momentary
UP
SW12
User Readable
Push Button/Momentary
KEY1
SW13
User Readable
Push Button/Momentary
RIGHT
SW14
User Readable
Push Button/Momentary
MENU
SW15
User Readable
Push Button/Momentary
REC
SW16
User Readable
Push Button/Momentary
REW
SW17
User Readable
Push Button/Momentary
SKIP -
SW18
User Readable
Push Button/Momentary
STOP
SW19
User Readable
Push Button/Momentary
FF
SW20
User Readable
Push Button/Momentary
SKIP +
SW21
Short to Ground
Push Button/Momentary
PLAY PAUSE
SW22
Short to Ground
Push Button/Momentary
SW23
PRTSC Mode
2 Position DIP
3-29
Spectrum Digital, Inc
3.4.1 SW1, EMU0/1 Select Switch
SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0
and EMU1 pins on the TMS320DM365 processor. A view of the switch is shown in the
figure below. The selection options with this switch are in the table below.
EMU1
Elevated
Actuator
H
S1
L
EMU0
Figure 3-22, SW1, EMU0/1 Select Switch
Table 38: SW1, EMU0/1 Select
State at Reset
EMU1
EMU0
Function
L(0)
L(0)
Reserved
L(0)
H(1)
Reserved
H(1)
L(0)
Reserved
H(1)
H(1)
ICE PICK Mode *
Both ARM & DSP JTAG Enabled
* is the factory shipped configuration
3.4.2 SW2, PWCTRO0 Pushbutton
Switch SW2 is a push button momentary switch that forces the PWCTRO0 signal on
the DM365, U18-11, pin J3, to ground when the switch is depressed.
3.4.3 SW3, Non-Supported Pushbutton
Switch SW3 is a not currently used for any function
3-30
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.4.4 SW4, Boot Mode / Configuration Select
Switch SW4 is a 6 position DIP switch used to select the ARM Boot Mode and
processor configuration. The first 3 positions selection the ARM boot mode. The last
3 positions select the processor configuration. The figure and tables below show these
options.
SW4
Elevated
Actuator
OFF
ON
BTSEL2
BTSEL1
BTSEL0
AECFG2
AECFG1
AECFG0
Figure 3-23, SW4, Boot Mode / Configuration Select
Table 39: SW4, Boot Mode Select
Pos 3
Pos 2
Pos 1
HW Code
Boot Mode
ON
ON
ON
000
NAND Boot *
ON
ON
OFF
001
ASYNC EMIF
ON
OFF
ON
010
MMC/SD Boot
ON
OFF
OFF
011
UART Boot
OFF
ON
ON
100
USB Boot
OFF
ON
OFF
101
SPI Boot
OFF
OFF
ON
110
EMAC Boot
OFF
OFF
OFF
111
HPI Boot
Table 40: SW4, Configuration Select
Pos 6
Pos 5
Pos 4
HW Code
Configuration Mode
ON
ON
ON
000
8-bit AEMIF Configuration *
ON
ON
OFF
001
16-bit AEMIF Configuration
* default setting
3-31
Spectrum Digital, Inc
3.4.5 SW5, Board Configuration Select
Switch SW5 is a 6 position switch that configures specific board functions. The figure
below shows the switch as it appears on the EVM.
SW5
NAND /ONE NAND
EXTRA1
EXTRA2
EXTRA3
VCORE ADJUST
NTSC / PAL
Elevated
Actuator
OFF
ON
Figure 3-24, SW5, Board Configuration Select
The table below shows the function of each switch position on SW5.
Table 41: SW5, Board Configuration Select
Position
1
2
3
4
5
6
State
Bit
Value
Function
OFF
0
SELNAND *
ON
1
SELONENAND
OFF
0
Reserved *
ON
1
Reserved
OFF
0
Reserved *
ON
1
Reserved
OFF
0
Reserved *
ON
1
Reserved
OFF
0
Vcore = 1.2 Volts
ON
1
Vcore = 1.35 Volts *
OFF
0
NTSC (CPLD register bit) *
ON
1
PAL (CPLD register bit)
* = default
3-32
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.4.6 SW6 - SW21, Function Pushbuttons
Switches SW6 through SW21 are push button momentary switches that are inputs in
to the DM365 processor. These switches can be read with software and their function is
determined by the application.
3.4.7 SW22, MSP430 IO0 Pushbutton
Switch SW22 is a push button momentary switch reserved for future use.
3.4.8 SW23, PRTSC Mode Select
Switch SW23 is a 2 position DIP switch that allows the user to select ______________.
Only one switch should be engaged at a time. The figure below shows the switch as it
appears on the EVM.
3
2
PWRRST
PWRCNTON
ON
4
1
SW23
Elevated
Actuator
Figure 3-25, SW23, PRTSC Mode Select
The table below shows the setting for SW23.
Table 42: SW23, PRTSC Mode Select
Position #
Signal Name
Function
1-4
XRESET pulled high on TPS65510
______________________
2-3
CS pulled high on TPS65510
______________________ *
* default
3-33
Spectrum Digital, Inc
3.5 Jumpers
The following section describes the jumpers on the DM365 EVM.
3.5.1 JP1, Jumper Block
Jumper block JP1 allows the user to connect signals from the DM365 processor to the
TVL320AIC3101, U7. The signals on this 9 x 2 header are shown in the table below.
Table 43: JP1, Jumper Block
3-34
Pin #
Signal Name
Pin #
Signal Name
2
AIC_McBSP_CLKX
1
AIC_BCLK, U7, Pin 2
4
AIC_McBSP_CLKR
3
AIC_BCLK, U7, Pin 2
6
AIC_McBSP_FSX
5
AIC_WCLK
8
AIC_McBSP_FSR
7
AIC_WCLK
10
AIC_McBSP_DX
9
AIC_DIN
12
AIC_McBSP_DR
11
AIC_DOUT
14
I2C_DATA
13
SDA, U7, Pin 9
16
I2C_SCLK
15
SDL, U7, Pin 8
18
Ground
17
Ground
DM365 EVM Technical Reference
Spectrum Digital, Inc
3.6 Test Points
The EVM has 55 test points. The following 2 figures identify the position of each test
point. The next two tables lists each test point and the signal appearing on that test
point.
TP8
TP11-TP16
TP20-TP21
TP9
TP7
TP3,TP4
TP1
TP2
TP5
TP6
TP17-TP19
TP10
TP23,TP26
TP22,TP29
TP24,TP25
TP31-TP34
TP27,TP28
TP30
TP42,TP43
TP35-TP37
TP41
TP38
TP44,TP45
TP40
TP39
TP46-TP48
TP49,TP50
TP51
TP52
Figure 3-26, DM365 EVM, Top Side Test Points
3-35
Spectrum Digital, Inc
TP53,TP54
Figure 3-27, DM365 EVM, Bottom Side Test Points
3-36
DM365 EVM Technical Reference
Spectrum Digital, Inc
Table 44: DM365 EVM Test Points
Test Point
#
Signal
Test Point
#
Signal
TP1
GND
TP33
U20, Pin 25, SOGOUT
TP2
GND
TP34
U20, Pin 23, SVSOUT
TP3
MSP430_IO3
TP35
U18-9, C9, LINEO
TP4
MSP430_IO4
TP36
U18-10, A6, ADC_CH5
TP5
VCC_5V
TP37
U18-10, D7, ADC_CH4
TP6
MSP430_IO2
TP38
U20, Pin 80, EXT_CLK
TP7
U5, Pin 25, INT#PHYAD0
TP39
VREF, U18-3, D11
TP8
VCC_3V3, VBUS_OCn2, U4, Pin 5
TP40
GND
TP10
U9, Pin6, PWMON
TP41
GND
TP20
U18-13, L1, MXI1
TP46
U33A, F2, B1.IO_21
TP21
U18-13, K1, MXO1
TP47
U33A, P7, B4.IO_47
TP24
U18-14, R1, RSV1
TP48
U33A, P11, B4.IO_21
TP25
U18-11, K2, PWCTRO0
TP49
U33A, M4, B1.IO_58
TP26
DM360 RESETn, U18-13, H3
TP50
U33A, P2, B1.IO_65
TP27
U18-14, R4, RSV2
TP51
GND
TP28
U18-11, L5, PWCTRO1
TP52
GND
TP30
U18-14, A1, RSV0
TP53
J24, Pin 11,12, BAT_CHG
TP31
U20, Pin 24, HSOUT
TP54
J24, Pin 19
TP32
U20, Pin 22, FIDOUT
3-37
Spectrum Digital, Inc
There are 18 power test points on the EVM. These test points provide a convenient
mechanism to check the EVM’s multiple power supplies. The table below shows the
voltages for each test point and what the supply is used for.
Table 45: Power Test Points
3-38
Access
Test Point
Voltage
Shunt
Power Domain
T1
+1.8V
0.02 ohms
VCC_1V8, U18-14, R12, CPU_VDD_DDR
TP9
+3.3V
0.02 ohms
VCC_3V3, U18-14, P5, CPU_VDDSHV
TP11
+1.2V
0.02 ohms
VCC_1V2, U18-14, R3
TP12
+3.3V
0.02 ohms
VCC_3V3
TP13
+1.8V
0.02 ohms
VCC_1V8
TP14
+1.8V
0.02 ohms
VCC_1V8, U18-14, N4
TP15
+1.2V
0.02 ohms
VCC_1V2, U18-14, J14, CPU_VDD
TP16
+1.8V
0.02 ohms
VCC_1V8, U18-10, G9
TP17
+1.8V
0.02 ohms
VCC_1V8, U18-14, E5
TP18
+1.8V
0.02 ohms
1V8_BB_UP, U18-11, K6
TP19
+1.2V
0.02 ohms
1V2_BB_UP, U18-11, K7,J6
TP22
+1.8V
0.02 ohms
VCC_1V8, U18-9, E9
TP23
+1.8V
0.02 ohms
VCC_1V8, U18-13, L6
TP29
+3.3V
0.02 ohms
VCC_3V3, U18-9, E10
TP42
+3.3V
0.02 ohms
VCC_3V3, U18-14, R14, CPU_VDDSHV10
VCC_1V8, U18-3, D10
TP43
+1.8V
0.02 ohms
TP44
+1.2V
0.02 ohms
VCC_1V2, U18-3, E12
TP45
+1.2V
0.02 ohms
VCC_1V2, U18-14, M14, CPU_VDDS
DM365 EVM Technical Reference
Appendix A
Schematics
This appendix contains the schematics for the DM365 EVM.
A-1
4
3
2
REV
D
DATE
APPROVED
A
Initial schematic ready for layout - Alpha Release
03/04/08
RRP
B
Updates for initial prototype build
09/24/08
RRP
C
BETA Release
10/30/08
RRP
D
SCHEMATIC CONTENTS
SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 SHEET15 SHEET16 SHEET17 SHEET18 SHEET19 SHEET20 SHEET21 SHEET22 SHEET23 SHEET24 SHEET25 SHEET26 SHEET27 SHEET28 SHEET29 SHEET30 SHEET31 SHEET32 SHEET33 SHEET34 SHEET35 SHEET36 SHEET37 SHEET38 SHEET39 SHEET40 SHEET41 SHEET42 SHEET43 SHEET44 SHEET45 SHEET46 SHEET47SHEET48 SHEET49 SHEET50 SHEET51 SHEET52 SHEET53 -
C
REVISION STATUS OF EVM
B
1
DESCRIPTION
Assembly
510840-0001
C
PWB
510841-0001
C
LOGIC
510842-0001
C
DM365 EVM Technical Reference
REVISION STATUS OF SHEETS
REV
C
C
C
SHEET
51
52
53
REV
C
C
C
C
C
C
C
C
C
C
SHEET
41
42
43
44
45
46
47
48
49
50
REV
C
C
C
C
C
C
C
C
C
C
SHEET
31
32
33
34
35
36
37
38
39
40
REV
C
C
C
C
C
C
C
C
C
C
SHEET
21
22
23
24
25
26
27
28
29
30
DWN
R.R.P.
CHK
A
T.W.K.
ENGR
REV
C
C
C
C
C
C
C
C
C
C
SHEET
11
12
13
14
15
16
17
18
19
20
REV
SHEET
C
1
C
2
C
3
C
C
4
5
5
C
6
C
7
C
8
C
9
C
10
NEXT ASSY
USED ON
APPLICATION
4
R.R.P.
ENGR-MGR
R.R.P.
QA
C.M.D.
MFG
R.R.P.
RLSE
R.R.P.
DATE
03/04/2008
DATE
03/04/2008
DATE
03/04/2008
DATE
03/04/2008
DATE
03/04/2008
DATE
03/04/2008
DATE
03/04/2008
TITLE SHEET
DM365 DDR2 INTERFACE
DM365 EMIF/BOOT MODES/CFG MODES
DM365 USB
DM365 VIDEO PORT IN
DM365 VIDEO PORT OUT
DM365 ANALOG VIDEO OUT
DM365 SD/MMC/MS IF
DM365 I/O
DM365 JTAG,CLKS,RESET
DM365 ADC
DM365 MIC/SPEAKER
DM365 POWER PINS
DM365 POWER CONTROL
DM365 GROUND PINS
DM365 DECOUPLING CAPS
DDR2 MEMORY
USB INTERFACE CONNECTOR
JTAG CONNECTORS
CPLD BANK A
CPLD BANK B
CPLD BANK C
CPLD BANK D
CLPD POWER
HOST/EMIF DC INTERFACE
NAND FLASH
ONE NAND
I2C/SPI EEPROM
RS232 INTERFACE
SD/MMC/MS IF
SD.MMC IF 2
VIDEO COMPONENT OUT
VIDEO INPUT MULTIPLEXER
VIDEO INPUT DC CONNECTORS
TVP7002
HD VIDEO IN CONNECTORS
TVP5146 DECODER
McBSP MUX
AIC3101
VIDEO DC OUTPUT CONNECTORS
DILC HOST CONNECTOR
ETHERNET MUX
ETHERNET PHY
MSP430 IR CONTROLLER
SWITCHES
LEDS
POWER SUPPLY TPS65510
POWER SUPPLY TPS65530
POWER SUPPLY
DECODER 3V3,1V8 POWER
ALT CPU CORE POWER
ALT 3V3 POWER
POWER IN
C
I2C
ADDRESS
Device
0x18
0x25
0x2C
0x2E
0x50
0x5D
0x5C
AIC3101
MSP430
THS7303
THS7353
CAT24C256
TVP5146
TVP7002
B
SPECTRUM DIGITAL INCORPORATED
Page Contents:
TITLE SHEET
Size: B
DWG NO
Date:
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
1
of
53
Spectrum Digital, Inc
A-2
5
5
4
3
2
1
T_DDR_A9
T_DDR_A4
T_DDR_A13
T_DDR_A7
4
3
2
1
5
6
7
8
RN9
DDR_A9
DDR_A4
DDR_A13
DDR_A7
DDR_A9 17
DDR_A4 17
DDR_A13 17
DDR_A7 17
RPACK4-22
U18-4
D
D
17 DDR_DQ15
17 DDR_DQ14
17 DDR_DQ13
17 DDR_DQ12
17 DDR_DQ11
17 DDR_DQ10
17 DDR_DQ9
17 DDR_DQ8
17 DDR_DQ7
17 DDR_DQ6
17 DDR_DQ5
17 DDR_DQ4
C
17 DDR_DQ3
17 DDR_DQ2
17 DDR_DQ1
17 DDR_DQ0
17 DDR_DQM1
17 DDR_DQM0
DDR_DQ15
V6
DDR_DQ15
DDR_DQ14
V7
DDR_DQ14
DDR_DQ13
R7
DDR_DQ13
DDR_DQ12
W7
DDR_DQ12
DDR_DQ11
V8
DDR_DQ11
DDR_DQ10
R8
DDR_DQ10
D DR_DQ9
U8
DDR_DQ9
D DR_DQ8
W8
DDR_DQ8
D DR_DQ7
R9
DDR_DQ7
D DR_DQ6
W9
DDR_DQ6
D DR_DQ5
V9
DDR_DQ5
D DR_DQ4
W10
DDR_DQ4
D DR_DQ3
V10
DDR_DQ3
D DR_DQ2
R10
DDR_DQ2
D DR_DQ1
V11
DDR_DQ1
D DR_DQ0
U11
DDR_DQ0
DDR_A13
DDR_A12
DDR_A11
DDR_A10
T16
V17
W18
V16
T_DDR_A13
T_DDR_A12
T_DDR_A11
T_DDR_A10
DDR_A9
DDR_A8
DDR_A7
DDR_A6
DDR_A5
DDR_A4
DDR_A3
DDR_A2
U16
W17
T15
W16
V15
U15
T14
W15
T_DDR_A9
T_DDR_A8
T_DDR_A7
T_DDR_A6
T_DDR_A5
T_DDR_A4
T_DDR_A3
T_DDR_A2
DDR_A1
DDR_A0
V14
U14
T_DDR_A1
T_DDR_A0
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
V13
T13
W14
T_DDR_BA2
T_DDR_BA1
T_DDR_BA0
DDR_CS
T12
T_DDR_CS
DDR_RAS
U12
T_DDR_RAS
DDR_CAS
V12
T_DDR_CAS
DDR_WE
W13
T_DDR_WE
DDR_CKE
R13
T_DDR_CKE
DDR_DQM1
R280
22
T_DDR_DQM1
W6
DDR_DQM[1]
DDR_DQM0
R284
22
T_DDR_DQM0
T11
DDR_DQM[0]
DDR_CLK
W11
T_DDR_CLKP
T7
DDR_DQS[1]
DDR_CLK
W12
T_ DDR_CLKN
T_DDR_DQS1
17 T_DDR_DQS1
differential pair
T_DDR_DQSN1
17 T_DDR_DQSN1
U6
T_DDR_DQS0
17 T_DDR_DQS0
T_DDR_DQSN0
17 T_DDR_DQSN0
T10
differential pair
R277
10 T_DDR_STRBEN
DDR_STRBEN_DEL
RN8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RPACK8-22
DDR_A12
DDR_A11
DDR_A8
DDR_A10
DDR_A6
DDR_A5
DDR_A2
DDR_A1
T_DDR_A0
T_DDR_WE
T_DDR_BA2
T_DDR_CAS
T_DDR_A3
T_DDR_RAS
T_DDR_CS
T_DDR_BA1
RN7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RPACK8-22
DDR_A0
DDR_WE
DDR_ BA2
DDR_CAS
DDR_A3
DDR_RAS
DDR_CS
DDR_ BA1
DDR_A12 17
DDR_A11 17
DDR_A8 17
DDR_A10 17
DDR_A6 17
DDR_A5 17
DDR_A2 17
DDR_A1 17
DDR_A0 17
DDR_WE 17
DDR_BA2 17
DDR_CAS 17
DDR_A3 17
DDR_RAS 17
DDR_CS 17
DDR_BA1 17
C
R82
22
R84
T_DDR_BA0
R302
22
T_DDR_CKE
R299
22
DDR_CL KP
22
DDR_ BA0
DDR_BA0 17
DDR_CKE
DDR_CKE 17
DDR_CLKP 17
DDR_CLKN
DD R_CLKN 17
differential pair
DDR_DQSN[1]
DDR_DQS[0]
U9
DDR_DQSN[0]
T8
DDR_DQGATE0
T9
DDR_DQGATE1
B
DDR_STRBEN
T_DDR_A12
T_DDR_A11
T_DDR_A8
T_DDR_A10
T_DDR_A6
T_DDR_A5
T_DDR_A2
T_DDR_A1
DDR_PADREFP
R11
DDR_VREF
P11
50 OHM 0.5%
R50
B
VREF_STL
TMS320DM365
VREF_STL 17
DDR_STRBEN is trace to DDR memory
for delay compensation
This net is equal to the DDR_CLKP ( or DDR_CLKN )
plus
the length of DDR_DQXX Average Trace length
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 DDR INTERFACE
Size: B
DWG NO
A-3
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
2
of
53
Spectrum Digital, Inc
C260
0.1uF
4
3
2
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
VCC_3V3
1
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
R326
10K
U18-5
C339
20,25,27
20,25,27
20,25,27
20,25,27
20,25,27
20,25,27
VCC_3V3
0.1uF
U26
D
16
R327
25,26,27 EM_WAIT
25,27
25,27
25,27
25,27
EM_D15
EM_D14
EM_D13
EM_D12
25,27 EM_D11
25,27 EM_D10
25,27 EM_D9
25,27 EM_D8
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
33
RPACK4-33
1
2
3
4
RPACK4-33
1
2
3
4
RPACK4-33
20,25,26,27
20,25,26,27
20,25,26,27
20,25,26,27
C
EM_D7
EM_D6
EM_D5
EM_D4
20,25,26,27 EM_D3
20,25,26,27 EM_D2
20,25,26,27 EM_D1
20,25,26,27 EM_D0
T_EM_WAIT
RN14
8
7
6
5
T_EM_D15
T_EM_D14
T_EM_D13
T_EM_D12
J18
EM_WAIT/GIO52/HRDY
P18
P16
P19
P15
EM_D15/GIO64/HD15
EM_D14/GIO63/HD14
EM_D13/GIO62/HD13
EM_D12/GIO61/HD12
RN20
8
7
6
5
T_EM_D11
T_EM_D10
T_EM_D9
T_EM_D8
N16
N18
N19
N15
EM_D11/GIO60/HD11
EM_D10/GIO59/HD10
EM_D9/GIO58/HD9
EM_D8/GIO57/HD8
T_EM_D7
T_EM_D6
T_EM_D5
T_EM_D4
L16
L18
L19
L15
EM_D7/HD7
EM_D6/HD6
EM_D5//HD5
EM_D4/HD4
EM_D7
EM_D6
EM_D5
EM_D4
1
2
3
4
RN15
8
7
6
5
EM_D3
EM_D2
EM_D1
EM_D0
RPACK4-33
1
2
3
4
RN16
8
7
6
5
T_EM_D3
T_EM_D2
T_EM_D1
T_EM_D0
K15
K19
K16
K18
EM_D3/HD3
EM_D2/HD2
EM_D1/HD1
EM_D0/HD0
RPACK4-33
5
6
7
8
RN12
4
3
2
1
V18
U18
V19
U19
T_EM_A13
T_EM_A12
T_EM_A11
T_EM_A10
EM_A9/GIO74/AECFG[1]
EM_A8/GIO73/AECFG[0]
EM_A7/GIO72/KEYA3
EM_A6/GIO71/KEYA2
T18
T19
T17
R18
RPACK4-33
T_EM_A9
5
T_EM_A8
6
T_EM_A7
7
T_EM_A6
8
RN18
4
3
2
1
EM_A5/GIO70/KEYA1
EM_A4/GIO69/KEYA0
EM_A3/GIO68/KEYB3
EM_A2/HCNTLA
R16
R19
R15
M18
RPACK4-33
T_EM_A5
5
T_EM_A4
6
T_EM_A3
7
T_EM_A2
8
RN19
4
3
2
1
M19
L17
R17
P17
RPACK4-33
T_EM_A1
5
T_EM_A0
6
T_EM_BA1
7
T_EM_BA0
8
RN13
4
3
2
1
EM_A13/GIO78/BTSEL[2]
EM_A12/GIO77/BTSEL[1]
EM_A11/GIO76/BTSEL[0]
EM_A10/GIO75/AECFG[2]
EM_A1/HHWIL
EM_A0/GIO67/KEYB2/HCNTLB
EM_BA1/GIO66/KEYB1/HINTN
EM_BA0/EM_A14/GIO65/KEYB0
1A
7
2A
9
3A
12
4A
8
M15
EM_ADV/GIO51/HR/W
M16
EM_WE/GIO54/HDS2
J15
EM_OE/GIO53/HDS1
J19
EM_CE1/GIO55/HAS
J17
EM_CE0/GIO56/HCS
M17
GND
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
2
3
5
6
11
10
14
13
EM_A7
S
OE
1
15
KEYPAD_EMIF
EMIF_SEL
EM_A7 25,27
KEY_A3 45
EM_A6 25,27
KEY_A2 45
EM_A5 25,27
KEY_A1 45
EM_A4 25,27
KEY_A0 45
EM_A6
EM_A5
EM_A4
SN74CBTLV3257PW
C340
VCC_3V3
0.1uF
U25
EM_A2
EM_A1
16
EM_A2 20,25,26,27
EM_A1 20,25,26,27
VCC
4
1A
7
2A
9
12
EM_CLK/GIO50
D
VCC
4
8
3A
4A
GND
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
2
3
5
6
11
10
14
13
S
OE
1
15
EM_A3
EM_A3 25,27
KEY_B3 45
EM_A0 25,27
KEY_B2 45
EM_BA1 25,27
KEY_B1 45
EM_BA0 25,27
KEY_B0 45
EM_A0
EM_BA1
EM_BA0
C
KEYPAD_EMIF
SN74CBTLV3257PW
20,25 EMIF_SEL
23 EMIF_KEYPAD
EMIF_SEL
VCC_3V3
TMS320DM365
R117
10K
B
RPACK4-33
8
7
6
5
T_EM_CLK
T_EM_ADV
T_EM_WE
T_EM_OE
RN21
1
2
3
4
R115
10K
EM_CLK
EM_ADV
EM_WE
EM_OE
B
EM_CLK 25,27
EM_ADV 25,27
EM_WE 20,25,26,27
EM_OE 20,25,26,27
VCC_3V3
DM365 EVM Technical Reference
R131
10K
R363
20K
R362
20K
R361
20K
R360
20K
R359
20K
R358
20K
T_EM_CE1
R330
33
EM_CE1
T_EM_CE0
R332
33
EM_CE0
R130
10K
EM_CE1 20,25
EM_CE0 20,25
VCC_3V3
A
SPECTRUM DIGITAL INCORPORATED
SW4
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
1
2
3
4
5
6
12
11
10
9
8
7
BOOT_M2
BOOT_M1
BOOT_M0
CFG_M2
CFG_M1
CFG_M0
R351
R350
R349
R348
R347
R346
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
SW DIP-6/SM
A
DM365 Evaluation Module
Title:
Page Contents:
DM365 EMIF/BOOT MODES/CFG MODES
Size: B
DWG NO
Revision:
C
510842-0001
INTERNAL PULL DOWNS ON BOOT AND CONFIG PINS
Date:
5
4
3
2
Sheet
Monday, April 13, 2009
1
3
of
53
Spectrum Digital, Inc
A-4
5
5
4
3
2
1
D
D
Differential Pair 90 ohm differential impedance
TP12
CPU_VCC_3V3
1
2
C33
0.02
C168
0.01uF
1.0uF
U18-7
E2
NFM21PC474R1C3D
1
3
2
R42
C200
0.01uF
C210
0.001uF
P4
VDDA33_USB
P3
VSSA33_USB
N5
VDDA18_USB
C47
0.1uF
USB_VBUS
N2
USB_VBUS
USB_DM
P1
USB_DM
USB_DM 18
USB_DP
N1
USB_DP
USB_DP 18
USB_ID
M1
USB_VBUS 18
CPU_VCC_1V8
0.02
TP13
C167
0.01uF
C
1
C209
0.01uF
2
R43
C34
1.0uF
E3
NFM21PC474R1C3D
1
3
2
C199
0.01uF
C51
1uF
P2
M5
M4
C219
C
VSSA18_USB
USB_ID
USB_ID 18
VDDA12LDO_USB
VSSA
.22uF
TMS320DM365
B
B
Page Contents:
DM365 USB
Size: B
DWG NO
A-5
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
4
of
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
U18-1
D
33
33
33
33
33
33
33
33
VDIN_Y7
VDIN_Y6
VDIN_Y5
VDIN_Y4
VDIN_Y3
VDIN_Y2
VDIN_Y1
VDIN_Y0
VDI N_Y7
VDI N_Y6
VDI N_Y5
VDI N_Y4
VDI N_Y3
VDI N_Y2
VDI N_Y1
VDI N_Y0
C12
A13
B13
D12
A14
B15
D14
D15
YIN7/GIO103/SPI3_SCLK
YIN6/GIO102/SPI3_SIMO
YIN5/GIO101/SPI3_SCS[0]
YIN4/SPI3_SOMI/SPI3_SCS[1]
YIN3/GIO99
YIN2/GIO98
YIN1/GIO97
YIN0/GIO96
33
33
33
33
33
33
33
33
VDIN_C7
VDIN_C6
VDIN_C5
VDIN_C4
VDIN_C3
VDIN_C2
VDIN_C1
VDIN_C0
VDIN_C7
VDIN_C6
VDIN_C5
VDIN_C4
VDIN_C3
VDIN_C2
VDIN_C1
VDIN_C0
A15
C15
B16
A16
A17
C16
A18
B17
CIN7
CIN6
CIN5
CIN4
CIN3
CIN2
CIN1
CIN0
C14
HD/GIO95
33 VDIN_HD
VDIN_HD
33 VDIN_VD
VDIN_VD
B14
VD/GIO95
21 VDIN_WEN
VDIN_WEN
R337
0
E13
C_WE_FIELD/GIO93/CLKOUT0/USBDRVVBUS
33 VDIN_PCLK
VDIN_PCLK
R291
0
D13
D
PCLK
C
C
TMS320DM365
B
B
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 VIDEO IN
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
5
of
53
Spectrum Digital, Inc
A-6
5
5
4
3
D
2
D
VDOUT_VCLK 40
VDOUT_EXTCLK 20,40
OSC MODE SELECT
VCC_3V3
U18-2
C
1
VCLK/GIO79
B18
GIO80/EXTCLK/B2/PWM3
B19
R136
33
R318
0
R341
NO-POP
GIO81(OSCCFG)/LCD_FIELD/R2/PWM3
LCD_OE/GIO82
VSYNC/GIO83
HSYNC/GIO84
C18
C19
G18
G15
CPU_FIELD
CPU_LCD_OE
CPU_VSYNC
CPU_ HSYNC
C PU_FIELD
CPU_LCD_OE
CPU_VSYNC
CPU_ HSYNC
GIO92/COUT7(G4)/PWM0
GIO91/COUT6(G3)/PWM1
GIO90/COUT5(G2)/PWM2/RTO0
GIO89/COUT4(B7)/PWM2/RTO1
GIO88/COUT3(B6)/PWM2/RTO2
GIO87/COUT2(B5)/PWM2/RTO3
GIO86/COUT19B4)/PWM3/STTRIG
GIO85/COUT0(B3)/PWM3
E18
E19
E15
E17
D16
D19
D18
D17
CPU_COUT7
CPU_COUT6
CPU_COUT5
CPU_COUT4
CPU_COUT3
CPU_COUT2
CPU_COUT1
CPU_COUT0
CPU_COUT7
CPU_COUT6
CPU_COUT5
CPU_COUT4
CPU_COUT3
CPU_COUT2
CPU_COUT1
CPU_COUT0
YOUT7(R7)
YOUT6(R6)
YOUT5(R5)
YOUT4(R4)
YOUT3(R3)
YOUT2(G7)
YOUT1(G6)
YOUT0(G5)
G16
G19
F15
F18
F16
F19
F17
E16
CPU_YOUT7
CPU_YOUT6
CPU_YOUT5
CPU_YOUT4
CPU_YOUT3
CPU_YOUT2
CPU_YOUT1
CPU_YOUT0
CPU_YOUT7
CPU_YOUT6
CPU_YOUT5
CPU_YOUT4
CPU_YOUT3
CPU_YOUT2
CPU_YOUT1
CPU_YOUT0
RN22
1
2
3
4
1
2
3
4
5
6
7
8
RN17
1
2
3
4
5
6
7
8
RN23
RPACK4-33
8
7
6
5
16
15
14
13
12
11
10
9
RPACK8-33
16
15
14
13
12
11
10
9
VDOUT_FIELD 20,40
VDOUT_LCD_OE 40
VDOUT_VSYNC 40
VDOUT_HSYNC 40
VDOUT_C7
VDOUT_C6
VDOUT_C5
VDOUT_C4
VDOUT_C3
VDOUT_C2
VDOUT_C1
VDOUT_C0
22,40
22,40
22,40
22,40
22,40
22,40
22,40
22,40
VDOUT_Y7
VDOUT_Y6
VDOUT_Y5
VDOUT_Y4
VDOUT_Y3
VDOUT_Y2
VDOUT_Y1
VDOUT_Y0
40
40
40
40
40
40
40
40
R102
2.2K
C
RPACK8-33
TMS320DM365
B
B
Page Contents:
DM365 VIDEO PORT OUT
Size:B
DWG NO
A-7
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
6
of
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
R120
0
1
TV_OUT 41
D
D
U18-3
J16
RCA JACK(YELLOW)
2
L31
3
1
4
2.7uH
R125
C102
270pF
2150 1%
C101
270pF
R126
2100 1%
A10
TVOUT
B10
VFB
B11
IDACOUT
A11
IREF
D10
VDDA18_DAC
E11
VSSA18_DAC
E12
VDDA12_DAC
F11
VSSA12_DAC
D11
VREF
COMPPR
C11
DAC_3_R/PR 32
COMPY
B12
DAC_1_G/Y 32
COMPPB
A12
DAC_2_B/PB 32
DSP_GND
DSP_GND
DSP_GND
TP43
CPU_VCC_1V8
1
R290
2
R95
0.02
E9
NFM21PC474R1C3D
1
3
2400 1%
IBIAS
DSP_GND
VDDA1P8V_DAC
C
C
C83
10uF
2
C314
2.2uF
C77
0.01uF
C76
.1uF
L22
BLM21B050S
VDDA1P2V_DAC
DSP_GND
TP44
VCC_1V2
1
2
R103
0.02
E10
NFM21PC474R1C3D
1
3
C95
0.01uF
2
C334
2.2uF
DSP_GND
TP39
TEST POINT
C93
.1uF
1
VR EF
L27
TMS320DM365
BLM21B050S
C298
0.1uF
DAC_3V3
DSP_GND
B
B
DSP_GND
R475
1K
R474
7.5K
CPU_VCC_3V3
DAC_3V3
L36
R476
4.99K
INDUCTOR
3
DSP_GND
INDUCTOR
2
4
VREF_1.24V
DSP_GND
U114
TLV431ADBV
DSP_GND
A
C416
0.1uF
5
DM365 EVM Technical Reference
L37
R477
0
1
DSP_GND
SPECTRUM DIGITAL INCORPORATED
Page Contents:
DM365 ANALOG VIDEO OUT
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
7
of
53
Spectrum Digital, Inc
A-8
5
5
4
3
2
1
U18-8
30 SD0_CLK
D
30 SD0_CMD
VCC_3V3
C166
U38
31 CONN_SD1_CLK
20 CPU_GPIO43
31 CONN_SD1_CMD
20 CPU_GPIO42
CPU_GPIO43
CPU_GPIO42
SEL_SD1n_GPIO
C
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
1
15
S
OE
SD0_DATA3
SD0_DATA2
SD0_DATA1
SD0_DATA0
R91
33
J16
MMCSD0_CLK
SD0_CMD
R93
33
H15
MMCSD0_CMD
H16
MMCSD0_DATA3
H17
MMCSD0_DATA2
H19
MMCSD0_DATA1
H18
MMCSD0_DATA0
SD0_DATA3
SD0_DATA2
SD0_DATA1
SD0_DATA0
RN11
1
2
3
4
RPACK4-33
8
7
6
5
0.1uF
VCC
2
3
5
6
11
10
14
13
30
30
30
30
SD0_CLK
D
16
1A
4
SD1_CLK
R70
33
T6
GIO43/MMCSD1_CLK/EM_A20
2A
7
SD1_CMD
R62
33
R6
GIO42/MMCSD1_CMD/EM_A19
3A
9
W5
GIO41/MMCSD1_DATA3/EM_A18
U5
GIO40/MMCSD1_DATA2/EM_A17
R5
GIO39/MMCSD1_DATA1/EM_A16
V5
GIO38/MMCSD1_DATA0/EM_A15
4A
GND
RN5
SD1_DATA3
SD1_DATA2
SD1_DATA1
SD1_DATA0
12
R228
360
8
1
2
3
4
RPACK4-33
8
7
6
5
SN74CBTLV3257PW
C
TMS320DM365
VCC_3V3
C201
U40
31 CONN_SD1_DATA3
20 CPU_GPIO41
31 CONN_SD1_DATA2
20 CPU_GPIO40
31 CONN_SD1_DATA1
20 CPU_GPIO39
31 CONN_SD1_DATA0
20 CPU_GPIO38
20 SEL_SD1n_GPIO
CPU_GPIO41
CPU_GPIO40
CPU_GPIO39
CPU_GPIO38
SEL_SD1n_GPIO
B
0.1uF
VCC
2
3
5
6
11
10
14
13
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
1
15
S
OE
16
1A
4
2A
7
3A
9
4A
12
GND
8
B
SN74CBTLV3257PW
R265
2K
Page Contents:
DM365 SD/MMC/MS INTERFACE
Size: B
DWG NO
A-9
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
8
of
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
VCC_3V3
D
D
R270
2.2K
R269
2.2K
U18-6
McBSP_DX
McBSP_CLKX
McBSP_FSX
McBSP_DR
McBSP_CLKR
McBSP_FSR
38 McBSP_DX
38 McBSP_CLKX
38 McBSP_FSX
38 McBSP_DR
38 McBSP_CLKR
38 McBSP_FSR
GPIO37
20 GPIO37
RN4
16
15
14
13
12
11
10
9
R275
RPACK8-33
1
2
3
4
5
6
7
8
33
D5
A5
C6
E6
B6
E7
T5
GIO21/UART1_RTS/I2C_SDA
F3
GIO20/UART1_CTS/I2C_SCL
F1
GIO18/UART0_TXD
E2
UART0_TXD
GIO19/UART0_RXD
E3
UART0_RXD
GIO37/SPI4_SCS[0]/McBSP_CLKS/CLKOUT0
GIO17/TX_EN/UART1_RXD
E4
R279
33
GIO16/TX_CLK/UART1_TXD
E1
R276
33
D1
D3
C1
B1
4
3
2
1
GIO49/McBSP_DX
GIO48/McBSP_CLKX
GIO47/McBSP_FSX
GIO46/McBSP_DR
GIO45/McBSP_CLKR
GIO44/McBSP_FSR
C
RPACK4-33
8
7
6
5
RPACK4-33
8
GIO32_CPU
7
GIO31_CPU
6
GIO30_CPU
5
20 SPI4_SDI_GPIO_MD2
20 SPI4_SCLK
20 SPI4_SDO
20 GIO33_CPU
GIO33_CPU
R469
2.2K
20 GIO32_CPU
20 GIO31_CPU
20 GIO30_CPU
40 SPI1_SDENA0
40 SPI1_SCLK
40 SPI1_SDI
40 SPI1_SDO
20 PWM1
B
R530
R531
20 GPIO0
RPACK4-33
8
7
6
5
RN1
1
2
3
4
RPACK4-33
8
7
6
5
RN2
1
2
3
4
R73
33
UART0_TXD 29
UART0_RXD 29
CPU.TX_EN 42
GIO35/SPI4_SOMI/SPI4_SCS[1]/CLKOUT1
GIO36/SPI4_SCLK/EM_A21/EM_A14
GIO34/SPI4_SIMO/SPI4_SOMI/UART1_RXD
V3
W2
U4
T4
GIO33/SPI2_SDENA[0]/USBDRVVBUS/R1
GIO32/SPI2_SCLK/R0
GIO31/SPI2_SOMI/SPI2_SCS[1]/CLKOUT2
GIO30/SPI2_SIMO/G1
GIO10/RXD3
GIO9/RXD2
GIO8/RXD1
GIO7/RXD0
B2
C2
A2
A3
CPU.RXD3
CPU.RXD2
CPU.RXD1
CPU.RXD0
GIO6/RX_CLK
B3
CPU.RX_CLK 42
U2
V1
T2
U1
GIO29/SPI1_SCS[0]/G0
GIO28/SPI1_SCLK/B1
GIO27/SPI1_SOMI/SPI1_SCS[1]/B0
GIO26/SPI1_SIMO
GIO15/COL
D2
CPU.COL 42
GIO4/RX_ER
A4
CPU.RX_ER 42
GIO3/CRS
C5
CPU.CRS
GIO5/RX_DV
B4
CPU.RX_DV 42
GIO2/MDIO
C4
GIO1/MDCLK
D6
T1
T3
V2
R2
GIO25/SPI0_SCS[0]/PWM1/UART1_TXD
GIO24/SPI0_SCLK
GIO23/SPI0_SOMI/SPI0_SCS[1]/PWM0
GIO22/SPI0_SIMO
B5
RN10
C
CPU.TXCLK 42
5
6
7
8
RPACK4-33
W3
W4
V4
0
GPIO0
I2C_SCLK 20,28,32,34,35,36,37,39,40,44
GIO14/TXD3
GIO13/TXD2
GIO12/TXD1
GIO11/TXD0
0
28 SPI0_SDENA0
28 SPI0_SCLK
28 SPI0_SDI
28 SPI0_SDO
20 PWM0
RN3
1
2
3
4
RN6
1
2
3
4
I2C_DATA 20,28,32,34,35,36,37,39,40,44
CPU.TXD3
CPU.TXD2
CPU.TXD1
CPU.TXD0
42
42
42
42
42
42
42
42
42
B
CPU.MDIO 42
CPU.MDC 42
GIO0
TMS320DM365
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 I/O
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
9
of
53
Spectrum Digital, Inc
A-10
5
5
4
3
VCC_3V3
2
1
TP26
CPU_VCC_1V8
D
D
TP23
1
2
E7
NFM21PC474R1C3D
3
1
TEST POINT_0
C227
0.1uF
C225
0.01uF
0.02
R57
C212
2.2uF
2
R258
NO-POP
1
U18-13
R262
21 CPU_RESETn
R482
14 DSP_PWCTR_OUT0
360
NO-POP
DM360_RESETn
R257
NO-POP
H3
RESET
19 CPU_TCK
F4
TCK
19 CPU_RTCK
F2
RTCK
19 CPU_TDI
F5
TDI
G4
TDO
G2
TMS
19 CPU_TRSTn
H5
TRST
19 CPU_EMU0
G5
EMU0
19 CPU_EMU1
H4
EMU1
19 CPU_TDO
L6
MXI1
L1
C52
1
19 CPU_TMS
C
VDDMX1
R271
NO-POP
1
MXO1
K1
VSS_MX1
L2
27 pF
TP20
Y1
24MHz
TP21
C53
R272
C
27 pF
0
TMS320DM365
B
B
A-11
Page Contents:
DM365 JTAG,RESET,CLOCKS
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
10 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
CCD_PSMON
R89
1K
D
D
R315
1K
VCC_3V3
AGND_DM360
1K
R287
1K
CPU_VCC_1V8
R80
U18-10
TP16
AGND_DM360
1K
C
R292
1K
E8
ADC_CH0
B7
ADC_CH1
VDDA18_ADC
A7
ADC_CH2
D8
ADC_CH3
D7
ADC_CH4
A6
ADC_CH5
2
E5
NFM21PC474R1C3D
3
1
G9
C54
1 uF
C198
0.01uF
0.02
R46
C170
1.0uF
L58
VSSA_ADC
CPU_VCC_1V8
1
2
R78
C
BLM18AG121SN1D
F8
AGND_DM360
AGND_DM360
VCC_1V2
TMS320DM365
R87
AGND_DM360
1K
R311
1K
AGND_DM360
TP37
1
R83
1K
TEST POINT
R300
1K
B
AGND_DM360
TP36
1
B
R77
1K
TEST POINT
DM365 EVM Technical Reference
R283
1K
AGND_DM360
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 ADC
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
A
510842-0001
Monday, April 13, 2009
Sheet
1
11 o f
53
Spectrum Digital, Inc
A-12
5
5
4
3
2
1
D
D
CPU_VCC_3V3
VDA_MIC
L43
BLM21B050S
VDA_MIC
C134
0.1uF
1
CPU_VCC_3V3
VCC_3V3
E6
NFM21PC474R1C3D
1
3
2
R183
NO-POP
MIC_PLUS
C
C133
R61
0.02
+
C
R184
2.2k
AGND_DM360
TP29
MICR_P
C343
1.0uF
C224
0.01uF
L73
2
M1
C215
0.01uF
C216
0.01uF
U18-9
Right MIC
E10
VDDA33_VC
MICIP
B8
MICIN
C8
LINEO
C9
VCOM
A8
SPP
B9
SPN
A9
R182
1
R53
C203
0.01uF
AGND_DM360
2
0.02
E9
C207
0.01uF
C55
0.1uF
F9
AGND_DM360
BLM21B050S
MIC_MINUS
1uF
TP35
Test Point_1
C279
AGND_DM360
10uF
LINEOUT 41
VDDA18_VC
VSSA18_VC
TMS320DM365
R181
2.2K
+
MICR_M
AGND_DM360
R435
0
R433
0
2
E1
NFM21PC474R1C3D
1
3
2
C193
0.01uF
L59
VSSA33_VC
TP22
CPU_VCC_1V8
C169
1.0uF
D9
B
SPK1
8 OHM
1
AGND_DM360
B
NO-POP
C132
BLM21B050S
VCC_1V8
+
1
2
1uF
C60
0.1uF
AGND_DM360
R434
NO-POP
SPECTRUM DIGITAL INCORPORATED
A
A-13
Page Contents:
DM365 MIC/SPEAKER
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
12 o f
53
Spectrum Digital, Inc
AGND_DM360
4
TP15
VCC_1V2
2
VCC_1V3
C31
4.7uF
2
1
U18-14
0.02
CPU_VDD
C171
1.0uF
C194
2.2uF
D
J14
M13
L13
M12
K12
J12
H12
M10
K8
J8
H8
G8
H7
M6
G6
CVDD.15
CVDD.14
CVDD.13
CVDD.12
CVDD.11
CVDD.10
CVDD.9
CVDD.8
CVDD.7
CVDD.6
CVDD.5
CVDD.4
CVDD.3
CVDD.2
CVDD.1
VDDS33.9
VDDS33.8
VDDS33.7
VDDS33.6
VDDS33.5
VDDS33.4
VDDS33.3
VDDS33.2
VDDS33.1
P5 CPU_VDDSHV
F6
H6
N6
P6
F7
L12
H13
F10
1
TP9
CPU_VDDSHV
1
R45
C164
2.2uF
3
CPU_VDD
0.02
CPU_VCC_3V3
2
R31
C160
1.0uF
C156
2.2uF
C28
4.7uF
D
TP14
CPU_VCC_1V8
TP45
1
C
2
CPU_VDDS
R104
C96
4.7uF
0.02
C348
2.2uF
M14
H14
G14
H11
P7
J7
VDDS18.6
VDDS18.5
VDDS18.4
VDDS18.3
VDDS18.2
VDDS18.1
VDDA18_PLL
N4
3
C44
C197
0.001uF 0.1uF
E4
NFM21PC474R1C3D
1
2
CPU_VDDS
2
CPU_VCC_1V8
1
0.02
R44
C40
0.1uF
C333
1.0uF
TP11
2
VPP
0.02
R3
VCC_1V2
1
R41
C188
0.01uF
C189
0.1uF
C
C172
1.0uF
C36
0.01uF
C173
1.0uF
CPU_VCC_1V8
TP17
1
0.02
C192
2.2uF
CPU _VDD_DDR
T1
1
R92
C315
2.2uF
2
CPU_VDD_DDR
0.02
DM365 EVM Technical Reference
TP42
2
R94
C324
2.2uF
VDD18_SLDO
R12
P12
N11
P10
P9
N9
VDD18_DDR.6
VDD18_DDR.5
VDD18_DDR.4
VDD18_DDR.3
VDD18_DDR.2
VDD18_DDR.1
R14
P14
L14
K14
F13
F12
VDD_AEMIF1_18_33.2
VDD_AEMIF1_18_33.1
VDD_AEMIF2_18_33.2
VDD_AEMIF2_18_33.1
VDD_ISIF18_33.2
VDD_ISIF18_33.1
C231
1uF
B
C309
1.0uF
CPU_VCC_3V3
C87
4.7uF
E5
C206
0.1uF
CPU_VCC_1V8
C86
4.7uF
D4
2
R242
B
VDDRAM
CPU_VDDSHV10
1
0.02
C318
1.0uF
TMS320DM365
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 POWER
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
13 o f
53
Spectrum Digital, Inc
A-14
5
5
4
3
2
TP19
2
1
U18-11
C221
0.02
VDD12_PRTCSS.1 RTCXO
VDD12_PRTCSS.2
TP18
1
2
R241
C191
2.2uF
CPU_1V8_BB_UP
CPU_1V8_BB_UP
0.02
47 TPS65510_CS
32.768KHz
Y2
RTCXI
G1
K6
VDDS18_PRTCSS VSS_32K
H2
1V8_BB_UP
M3
PWRST
J28
HEADER 2
C220
R268
R462
0
10pF
R473
10k
0
C195
0.1uF
C205
0.1uF
2
1
M2
47 TPS65510_XRESET
NO-POP
VCC_3V3
3
2
R273
R274
D
R243
10K
4
R478
0
R480
0
DSP_PWCTR_OUT0 10
U39
JP2
HEADER 2
PWRCNTON
0
0
PWCTRO0
K2
PWCTRO1
L5
PWCTRO2
L4
1V8_BB_UP
R486
10K
1
2
1V8_BB_UP
R259
H1
1
C211
0.1uF
5
K7
J6
1
2
C204
0.001uF
C190
1.0uF
10pF
4
R240
D
1
44 ALT_POWERUP_RESET
R466
PWCTR_OUT0 21
SN74LVC1G07
0
MSP430_PWCTR_OUT1 44
PWCTR_OUT2
PWCTR_OUT1 48,51,52
PWCTR_OUT3
PWCTRO3
L3
PWCTRIO0
J3
PWCTRIO1
J2
PWCTR_IO1
PWCTRIO2
J1
PWCTR_IO2
PWCTRIO3
J5
PWCTR_IO3
PWCTRIO4
J4
PWCTR_IO4
PWCTRIO5
K5
PWCTR_IO5
PWCTRIO6
K4
PWCTR_IO6
C
3
1V2_BB_UP
R198
0
C
TMS320DM365
R244
10K
R245
10K
R246
10K
R247
10K
R248
10K
1V8_BB_UP
TP66
TEST POINT
R483
1
0
R484
10K
1V8_BB_UP
B
R485
SW2
A
A1
B
NO-POP
B
B1
CPU_1V8_BB_UP
PUSHBUTTON SW
VCC_3V3
U13
C196
0.1uF
1
PWCTR_OUT2
PWCTR_OUT3
PWCTR_IO1
PWCTR_IO2
PWCTR_IO3
PWCTR_IO4
PWCTR_IO5
PWCTR_IO6
A
R250
10K
R235
CPU_1V8_BB_UP
0
VCCA VCCB1
VCCB2
24
23
3
4
5
6
7
8
9
10
A1
A2
A3
A4
A5
A6
A7
A8
21
20
19
18
17
16
15
14
2
22
DIR
OE
11
12
GND1
GND2 GND3
B1
B2
B3
B4
B5
B6
B7
B8
C185
0.1uF
C184
0.1uF
3V3_PWCTR_OUT2 21
3V3_PWCTR_OUT3 21
3V3_PWCTR_IO1 21
3V3_PWCTR_IO2 21
3V3_PWCTR_IO3 21
3V3_PWCTR_IO4 21
3V3_PWCTR_IO5 21
3V3_PWCTR_IO6 21
SPECTRUM DIGITAL INCORPORATED
A-15
Page Contents:
DM365 POWER
Size: B
DWG NO
13
U-74AVC8T245
Date:
5
4
3
A
DM365 Evaluation Module
Title:
2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
14 o f
53
Spectrum Digital, Inc
CPU_1V8_BB_UP
4
3
2
1
D
D
U18-12
U18-15
RSV0(NC)
A1
1
TP30
TEST POINT
RSV1(NC)
R1
1
TP24
TEST POINT
RSV2(GND)
R4
1
TP27
TEST POINT
W19
A19
N14
F14
E14
P13
J13
N12
G12
M11
L11
K11
J11
G11
L10
K10
J10
H10
M9
L9
K9
J9
H9
P8
N8
M8
L8
M7
L7
W1
C
TMS320DM365
R529
0
B
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSS.6
VSS.7
VSS.8
VSS.9
VSS.10
VSS.11
VSS.12
VSS.13
VSS.14
VSS.15
VSS.16
VSS.17
VSS.18
VSS.19
VSS.20
VSS.21
VSS.22
VSS.23
VSS.24
VSS.25
VSS.26
VSS.27
VSS.28
VSS.29
VSS.30
C
B
TMS320DM365
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
DM365 POWER
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
15 o f
53
Spectrum Digital, Inc
A-16
5
5
4
3
2
1
CPU_VDD
C305
0.01uF
C302
0.01uF
C304
0.01uF
C296
0.01uF
C229
0.01uF
C252
0.01uF
C228
0.01uF
C253
0.01uF
C237
0.01uF
C289
0.01uF
C292
0.01uF
C262
0.01uF
C288
0.01uF
C295
0.01uF
C232
0.01uF
D
D
15
CPU_VDD
C68
10uF
C80
10uF
C81
10uF
CPU_VDD_DDR
C284
0.01uF
C276
0.01uF
C282
0.01uF
C270
0.01uF
C256
0.01uF
C263
0.01uF
C
C
6
CPU_VDD_DDR
C78
10uF
C79
10uF
CPU_VDDS
B
B
CPU_VDDSHV10
C281
0.01uF
C226
0.01uF
C285
0.01uF
C267
0.01uF
C248
0.01uF
C255
0.01uF
C293
0.01uF
C272
0.01uF
C290
0.01uF
C291
0.01uF
C294
0.01uF
SPECTRUM DIGITAL INCORPORATED
A
A-17
Page Contents:
DM365 DECOUPLING CAPACITORS
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
16 o f
53
Spectrum Digital, Inc
C303
0.01uF
4
3
2
1
C61
2.2uF
E8
NFM21PC474R1C3D
1
2
3
DDR_ VDD
DDR_VDD
C230
4.7uF
C236
0.01uF
C233
0.01uF
C234
0.01uF
C268
0.01uF
C283
0.01uF
C235
0.01uF
C286
0.01uF
C269
0.01uF
C258
0.01uF
D
D
U19
DDR_VDD
C266
0.1uF
C
R293
1K 1%
VREF_STL
2 VREF_STL
C274
0.1uF
R304
1K 1%
R303
B
0
D1
H1
V1
M9
R9
F3
K3
F9
D9
K7
F7
K1
F1
H9
K9
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
VDDQ.5
VDDQ.6
VDDQ.7
VDDQ.8
VDDQ.9
VDDQ.10
M1
VDDL
M2
VREF
V3
V7
N9
RFU1
RFU2
ODT
DM365 EVM Technical Reference
H2
D2
A1
A2
A8
A9
AA1
AA2
AA8
AA9
N.C.1
N.C.2
N.C.3
N.C.4
N.C.5
N.C.6
N.C.7
N.C.8
N.C.9
N.C.10
M7
VSSDL
E2
G2
J2
L2
D7
E8
G8
H7
J8
L8
U9
M3
H3
D3
T1
VSSQ.1
VSSQ.2
VSSQ.3
VSSQ.4
VSSQ.5
VSSQ.6
VSSQ.7
VSSQ.8
VSSQ.9
VSSQ.10
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
CS
WE
CAS
RAS
CK
CK
P8
N3
P7
N7
N8
M8
DDR_ CS
DDR_WE
DDR_CAS
DDR_RAS
DDR_CLKN
DDR_CLKP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
NC/A13
BA0
BA1
BA2
R8
R3
R7
T2
T8
T3
T7
U2
U8
U3
R2
U7
V2
V8
P2
P3
P1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CS 2
DDR_WE 2
DDR_CAS 2
DDR_RAS 2
DDR_CLKN 2
DDR_CLKP 2
DDR_A0 2
DDR_A1 2
DDR_A2 2
DDR_A3 2
DDR_A4 2
DDR_A5 2
DDR_A6 2
DDR_A7 2
DDR_A8 2
DDR_A9 2
DDR_A10 2
DDR_A11 2
DDR_A12 2
DDR_A13 2
DDR_BA0 2
DDR_BA1 2
DDR_BA2 2
CKE
N2
DDR_CKE
LDM
UDM
J3
E3
DDR_DQM0
DDR_DQM1
LDQS
LDQS
J7
H8
DDR_DQS0
DDR_DQSN0
UDQS
UDQS
E7
D8
DDR_DQS1 R74
DDR_DQSN1R76
C
DDR_CKE 2
DDR_DQM0 2
DDR_DQM1 2
R81
R79
33
33
T_DDR_DQS0 2
T_DDR_DQSN0 2
33
33
T_DDR_DQS1 2
T_DDR_DQSN1 2
RPACK4-33
DQ0
DQ1
DQ2
DQ3
K8
K2
L7
L3
T_DDR_DQ0
T_DDR_DQ1
T_DDR_DQ2
T_DDR_DQ3
T_DDR_DQ15
T_DDR_DQ8
T_DDR_DQ10
T_DDR_DQ13
8
7
6
5
RN27
1
2
3
4
DDR_DQ15
DDR_DQ8
DDR_DQ10
DDR_DQ13
RPACK4-33
8
7
6
5
RN28
1
2
3
4
DDR_DQ14
DDR_DQ9
DDR_DQ12
DDR_DQ11
RPACK4-33
8
7
6
5
RN30
1
2
3
4
DDR_DQ7
DDR_DQ0
DDR_DQ2
DDR_DQ5
RPACK4-33
RN31
DQ4
DQ5
DQ6
DQ7
L1
L9
J1
J9
T_DDR_DQ4
T_DDR_DQ5
T_DDR_DQ6
T_DDR_DQ7
T_DDR_DQ14
T_DDR_DQ9
T_DDR_DQ12
T_DDR_DQ11
DQ8
DQ9
DQ10
DQ11
F8
F2
G7
G3
T_DDR_DQ8
T_DDR_DQ9
T_DDR_DQ10
T_DDR_DQ11
T_DDR_DQ7
T_DDR_DQ0
T_DDR_DQ2
T_DDR_DQ5
DQ12
DQ13
DQ14
DQ15
G1
G9
E1
E9
T_DDR_DQ12
T_DDR_DQ13
T_DDR_DQ14
T_DDR_DQ15
T_DDR_DQ6
T_DDR_DQ1
T_DDR_DQ4
T_DDR_DQ3
8
7
6
5
DDR_DQ15 2
DDR_DQ8 2
DDR_DQ10 2
DDR_DQ13 2
DDR_DQ14 2
DDR_DQ9 2
DDR_DQ12 2
DDR_DQ11 2
DDR_DQ6
DDR_DQ1
DDR_DQ4
DDR_DQ3
1
2
3
4
B
DDR_DQ7
DDR_DQ0
DDR_DQ2
DDR_DQ5
2
2
2
2
DDR_DQ6
DDR_DQ1
DDR_DQ4
DDR_DQ3
2
2
2
2
MT47H64M16HR-3:E
Layout for the 92-ball DDR Package but
populate the 84-ball MT47H64M16HR-3:E.
84 Ball memories resisde in the center
section of the 92 Ball Package
A
SPECTRUM DIGITAL INCORPORATED
Page Contents:
DDR2 MEMORY
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
17 o f
53
Spectrum Digital, Inc
A-18
5
CPU_VCC_1V8
5
4
2
1
USB_VBUS
VCC_5V
U4
IN1
IN2
1
GND
10uF
TPS2065D
OUT1
OUT2
OUT3
8
7
6
D
OCn
+C136
2
3
EN
D
L1
USB_VBUS
5
C135
NO-POP
4
4 USB_VBUS
3
VCC_3V3
BLM21PG221SN1
R162
100K
J6
+
R188
10K
VCC_3V3
DRV_VBUS
R8
1
2
HEADER 2
TP8
R6
NO-POP
23 DRV_VBUS
C5
6.8uF
+
C2
100uF
VBUS_OCn2
0
R7
10K
USB_OVER_CURRENT
USB_OVER_CURRENT 23
C
C
J1
USB_ID
USB_ID
1
2
3
4
5
miniAB
VBUS
DD+
ID
GND
S1
S2
S3
S4
4
USB_VBUS_CONN
USB_DM
USB_DP
U SB_ID
6
7
8
9
4 USB_DM
4 USB_DP
USB_DM
USB_DP
DIFFERENTIAL PAIR
90 OHM DIFFERENTIAL
IMPEDANCE
SHORT AND STRAIGHT AS
POSSIBLE,
MINIMUM NUMBER OF VIAS
VCC_3V3
1
2
3
B
R468
0
J4
2
4
6
A
1
3
5
SPECTRUM DIGITAL INCORPORATED
A-19
Title:
SPARE JUMPERS
Page Contents:
DM365 USB
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
HEADER 3X2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
18 o f
53
Spectrum Digital, Inc
HEADER 3
L38
BLM21PG221SN1
R467
1.5K
J26
B
4
3
2
1
D
D
R159
2.2K
VCC_3V3
TI_TRSTn
R165
33
R167
R166
33
33
R170
R169
R168
33
33
33
CPU_TRSTn 10
J2
2
4
6
8
10
12
14
KEY
TI_EMU1
TRST
TMS
GND
TDI
nc
PD
GND
TDO
GND TCKRET
GND
TCK
EMU1
EMU0
TI_TMS
TI_TDI
TI_PWR_DECT
TI_TDO
TI_TCK_RET
TI_TCK
TI_EMU0
1
3
5
7
9
11
13
CPU_TMS 10
CPU_TDI 10
CPU_TDO 10
CPU_RTCK 10
CPU_TCK 10
TSW-107-14-G-D-006
14 PIN TI JTAG INTERFACE
C
C
R148
33
R160
CPU_EMU0 10
33
CPU_EMU1 10
VCC_3V3
SWITCH CONTROLS JTAG TAP:
R149
10K
DM365 EVM Technical Reference
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
ARM_TRSTn
ARM_TDI
ARM_TMS
ARM_TCK
ARM_TCKRET
ARM_TDO
ARM_RSTn
ARM_TDI
4
5
6
EMU1
EMU0
FUNCTION
0
0
RESERVED
0
1
RESERVED
1
0
RESERVED
1
1
ICE PICK MODE *
* DEFAULT
CASD20TB
ARM_TCK
J5
1
2
3
B_ARM_TCKRET
B
SW1
ARM_TDO
R164
0
ARM_TMS
R177
0
ARM_TRSTn
VCC_3V3
R157
10K
R150
2.2K
B
VCC_3V3
R158
2.2K
R171
10k
ARM_RSTn 21
ARM_DEBUG_REQ
ARM_DEBUG_ACK
SAMTEC-TSM-110-DV
20 PIN ARM JTAG INTERFACE
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
JTAG INTERFACE
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
19 o f
53
Spectrum Digital, Inc
A-20
5
5
4
3
2
VCC_3V3
U33A
D
TP46
TEST POINT
1
C
9
9
PWM1
TP49
TEST POINT
1
TP50
TEST POINT
1
D3
C2
C3
E3
D2
E4
D1
E5
E2
F3
E1
F4
F2
F5
F1
F6
G2
G3
G1
G4
H2
G5
H1
H3
J1
H4
J2
J4
K1
J3
K2
K5
L1
K4
L2
K3
M1
L5
M2
L4
L3
N1
M4
N2
M3
N3
P2
3,25 EMIF_SEL
3,25 EM_CE0
3,25 EM_CE1
3,25,26,27 EM_A1
3,25,26,27 EM_A2
3,25,27 EM_A8
3,25,27 EM_A9
3,25,27 EM_A10
3,25,27 EM_A11
3,25,27 EM_A12
3,25,27 EM_A13
3,25,26,27 EM_OE
3,25,26,27 EM_D7
3,25,26,27 EM_D6
3,25,26,27 EM_D5
3,25,26,27 EM_D4
3,25,26,27 EM_D3
3,25,26,27 EM_D2
3,25,26,27 EM_D1
3,25,26,27 EM_D0
26 NAND_CE0n
26 NAND_CE1n
27 ONENAND_CE
9 SPI4_SCLK
9 SPI4_SDI_GPIO_MD2
9 SPI4_SDO
8 SEL_SD1n_GPIO
9 GPIO0
9 GPIO37
9 GIO33_CPU
9 GIO32_CPU
9 GIO31_CPU
9 GIO30_CPU
8 CPU_GPIO38
8 CPU_GPIO39
8 CPU_GPIO40
8 CPU_GPIO41
8 CPU_GPIO42
8 CPU_GPIO43
6,40 VDOUT_FIELD
6,40 VDOUT_EXTCLK
9,28,32,34,35,36,37,39,40,44 I2C_DATA
9,28,32,34,35,36,37,39,40,44 I2C_SCLK
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
0
0
0
R425
R426
R424
GPIO0
GPIO37
GIO33_CPU
GIO32_CPU
GIO31_CPU
GIO30_CPU
CPU_GPIO38
CPU_GPIO39
CPU_GPIO40
CPU_GPIO41
CPU_GPIO42
CPU_GPIO43
R523
R524
0
0
1
VCC_3V3
B1.IO_1
B1.IO_2
B1.IO_5
B1.IO_6
B1.IO_7
B1.IO_8
B1.IO_9
B1.IO_10
B1.IO_11
B1.IO_18
B1.IO_19
B1.IO_20
B1.IO_21
B1.IO_22
B1.IO_23
B1.IO_24
B1.IO_25
B1.IO_26
B1.IO_27
B1.IO_28
B1.IO_29
B1.IO_30
B1.IO_31
B1.IO_32
B1.IO_33
B1.IO_34
B1.IO_35
B1.IO_36
B1.IO_37
B1.IO_40
B1.IO_41
B1.IO_42
B1.IO_43
B1.IO_44
B1.IO_47
B1.IO_48
B1.IO_49
B1.IO_50
B1.IO_51
B1.IO_52
B1.IO_54
B1.IO_57
B1.IO_58
B1.IO_59
B1.IO_60
B1.IO_62
B1.IO_65
VCCIO.B1.1
VCCIO.B1.2
VCCIO.B1.3
VCCIO.B1.4
C1
H6
J6
P1
C407
0.1uF
C382
0.1uF
C383
0.1uF
C403
0.1uF
D
C
B1.TMS
B1.TDI
B1.TCK
B1.TDO
PWM0
B
ISR_TMS
ISR_TDI
ISR_TCK
ISR_TDO
N4
L6
P3
M5
ISR_TMS
ISR_TCK
ISR_TDO
B
VCC_3V3
VCC_3V3
J22
H5
J5
3,25,26,27 EM_WE
1
3
5
7
9
RN24
ISR_TCK
ISR_TDO
ISR_TMS
8
7
6
5
ISR_TDI
1
2
3
4
RPACK4-10K
HEADER 5X2
EPM2210GF256C5N
L80
VCC_3V3
A
1
SPECTRUM DIGITAL INCORPORATED
2
A
U35
BLM21PG221SN1D
C410
.1uF
c402-25
1
EN
VCC
4
2
GND
OUT
3
DM365 Evaluation Module
Title:
R145
33
Page Contents:
CPLD SECTION A
Size: B
DWG NO
12 MHz
A-21
Date:
5
4
3
2
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
20 o f
53
Spectrum Digital, Inc
2
4
6
8
10
B1.GLK0
B1.GLK1
4
3
2
VCC_3V3
48,51 SEL_EXTRA_3
48,51 CPU_VSEL1
VCC_3V3
1
VCC_3V3
U33B
SW5
D
R401
R400
R399
R398
R397
R396
1K
1K
1K
1K
1K
1K
1
2
3
4
5
6
1
2
3
4
5
6
D
SEL_NAND_LOW
SEL_EXTRA_1
SEL_EXTRA_2
SEL_EXTRA_3
CPU_VSEL1
SEl_NTSC_MODE
12
11
10
9
8
7
DIP_SWITCH_6
R373
10K
R372
10K
R371
10K
R370
10K
R369
10K
R368
10K
5 VDIN_WEN
14 PWCTR_OUT0
14 3V3_PWCTR_OUT2
14 3V3_PWCTR_OUT3
14 3V3_PWCTR_IO1
14 3V3_PWCTR_IO2
14 3V3_PWCTR_IO3
14 3V3_PWCTR_IO4
14 3V3_PWCTR_IO5
14 3V3_PWCTR_IO6
44 MSP430_INT
37 TVP5146_RESETn
39 AIC3101_RESETn
35 TVP_7002_RSTn
43 ENET_RESETn
48 CPLD_B-ADJ
PWCTR_OUT0
3V3_PWCTR_OUT3
3V3_PWCTR_OUT3
3V3_PWCTR_IO1
3V3_PWCTR_IO2
3V3_PWCTR_IO3
3V3_PWCTR_IO4
3V3_PWCTR_IO5
3V3_PWCTR_IO6
MSP430_INT
TVP5146_RESETn
AIC3101_RESETn
TVP_7002_RSTn
ENET_RESETn
CPLD_B-ADJ
10 CPU_RESETn
46 PB_SWITCH
19 ARM_RSTn
C
42 CPU_GPIO17
42 CPU_GPIO16
42 CPU_GPIO15
42 CPU_GPIO14
42 CPU_GPIO13
42 CPU_GPIO12
42 CPU_GPIO11
42 CPU_GPIO10
42 CPU_GPIO9
42 CPU_GPIO8
42 CPU_GPIO7
42 CPU_GPIO6
42 CPU_GPIO5
42 CPU_GPIO4
42 CPU_GPIO3
42 CPU_GPIO2
42 CPU_GPIO1
42 SEL_ENET_IO0
42 SEL_ENET_IO1
SEL_ENET_IO0
SEL_ENET_IO1
33 CPLD_CCD-DATA01
33 CPLD_CCD-DATA00
B
EN7
ENAFE
SEQ56
EN56
ENABLE_LCD_15V
48
EN7
48 ENAFE
48 SEQ56
48
EN56
49 ENABLE_LCD_15V
B16
C13
A15
C12
B14
D12
B13
C11
A13
D11
B12
E11
A12
C10
B11
D10
A11
E10
B10
C9
A10
D9
B9
E9
A9
A8
B8
E8
A7
D8
B7
C8
A6
E7
B6
D7
A5
C7
B5
E6
A4
D6
B4
C6
C4
C5
B3
D5
A2
B1
D4
B2.IO_1
B2.IO_2
B2.IO_3
B2.IO_4
B2.IO_13
B2.IO_14
B2.IO_15
B2.IO_16
B2.IO_17
B2.IO_18
B2.IO_19
B2.IO_20
B2.IO_21
B2.IO_22
B2.IO_23
B2.IO_24
B2.IO_25
B2.IO_26
B2.IO_27
B2.IO_28
B2.IO_29
B2.IO_30
B2.IO_31
B2.IO_32
B2.IO_33
B2.IO_34
B2.IO_35
B2.IO_36
B2.IO_37
B2.IO_38
B2.IO_39
B2.IO_40
B2.IO_41
B2.IO_42
B2.IO_43
B2.IO_44
B2.IO_45
B2.IO_46
B2.IO_47
B2.IO_48
B2.IO_49
B2.IO_50
B2.IO_51
B2.IO_52
B2.IO_53
B2.IO_54
B2.IO_55
B2.IO_56
B2.IO_63
B2.IO_64
B2.IO_65
VCCIO.B2.1
VCCIO.B2.2
VCCIO.B2.3
VCCIO.B2.4
C399
0.1UF
A3
A14
F8
F9
C390
0.1UF
C389
0.1UF
C397
0.1UF
C
B
DM365 EVM Technical Reference
EPM2210GF256C5N
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
CPLD SECTION B
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
21 o f
53
Spectrum Digital, Inc
A-22
5
5
4
3
2
1
D
D
VCC_3V3
U 33C
C
B
SEL_AICn_GPIO
LED4
LED5
LED6
LED7
DECODER_IMAGER_S0
DECODER_IMAGER_S1
DECODER_IMAGER_S2
CCD-WEN
CCD-FIELD
R422
R421
0
0
44 MP430_IO1
44 MP430_IO2
P14
P15
N13
N14
M14
N15
M13
N16
L14
M15
L13
M16
L12
L15
L11
L16
K14
K15
K13
K16
K12
J15
J14
J16
J13
H16
H13
H15
H14
G16
G12
G15
G13
F16
G14
F15
F11
E16
F12
E15
F13
D16
F14
D15
E12
D14
E13
C15
C14
E14
D13
B3.IO_3
B3.IO_5
B3.IO_6
B3.IO_11
B1.IO_12
B1.IO_13
B1.IO_14
B3.IO_15
B3.IO_16
B3.IO_17
B3.IO_18
B3.IO_19
B3.IO_20
B3.IO_21
B3.IO_22
B3.IO_23
B3.IO_24
B3.IO_25
B3.IO_26
B3.IO_27
B3.IO_28
B3.IO_29
B3.IO_30
B3.IO_31
B3.IO_32
B3.IO_33
B3.IO_34
B3.IO_35
B3.IO_36
B3.IO_37
B3.IO_38
B3.IO_39
B1.IO_40
B3.IO_41
B3.IO_42
B3.IO_43
B3.IO_44
B3.IO_45
B3.IO_46
B3.IO_47
B3.IO_48
B3.IO_49
B3.IO_50
B3.IO_51
B3.IO_52
B3.IO_55
B3.IO_58
B3.IO_61
B3.IO_64
B3.IO_65
B3.IO_67
J12
H12
B3.GLK2
B3.GLK3
VCC_3V3
VCCIO.B3.1
VCCIO.B3.2
VCCIO.B3.3
VCCIO.B3.4
C16
H11
J11
P16
C392
0 .1UF
C391
0.1UF
C406
0.1UF
C401
0 .1UF
C
B
EPM2210GF256C5N
A
SPECTRUM DIGITAL INCORPORATED
A-23
Page Contents:
CPLD SECTION C
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
22 o f
53
Spectrum Digital, Inc
38 CPLD_McBSP_CLKX
38 CPLD_McBSP_FSX
38 CPLD_McBSP_DX
38 CPLD_McBSP_CLKR
38 CPLD_McBSP_FSR
38 CPLD_McBSP_DR
38 SEL_AICn_GPIO
33 CPLD_CCD-DATA02
46
LED4
46
LED5
46
LED6
46
LED7
33 CPLD_CCD-DATA03
33 DECODER_IMAGER_S0
33 DECODER_IMAGER_S1
33 DECODER_IMAGER_S2
6,40 VDOUT_C7
6,40 VDOUT_C6
6,40 VDOUT_C5
6,40 VDOUT_C4
6,40 VDOUT_C3
6,40 VDOUT_C2
6,40 VDOUT_C1
6,40 VDOUT_C0
34 PWM_CCD_SUB
34 CCD-DDSRST
34 GPIO_MST_SLV
34 GPIO_TACH
34 GPIO_MD19
34 GPIO_MD18
34 GPIO_MD17
34 GPIO_MD16
34 GPIO_MD15
34 GPIO_MD14
34 GPIO_MD13
34 GPIO_MD12
34 GPIO_MD11
34 GPIO_MD10
34 GPIO_MD9
34 GPIO_MD8
34 GPIO_MD7
34 GPIO_MD6
34 GPIO_MD5
34 GPIO_MD4
34 GPIO_MD3
34 GPIO_MD1
34 CCD-WEN
34 CCD-FIELD
34 SPI4_SDI_GPIO_MD2_CONN
34 SPI4_SCLK_CONN
34 SPI4_SDO_CONN
4
3
2
1
VCC_3V3
VCC_3V3
U33D
D
D
TP48
TEST POINT
1
C
TP47
TEST POINT
B
1
18 USB_OVER_CURRENT
18 DRV_VBUS
40 LCD_OE_5V
49 ENABLE_LCD_3V3
27 ONENAND_INT
27 ONENAND_RST
40 R1_GIO33
40 R0_GIO32
40 G1_GIO30
46
LED0
46
LED1
46
LED2
46
LED3
3 EMIF_KEYPAD
30 MS.INS
30 SD/MMC.INS
30 SD/MMC.WP
31 SD/MMC1.WP
31 SD/MMC1.INS
40 CPLD.CONN_RESETn
40 CPLD.CONN_GIO6
40 CPLD.CONN_GIO16
40 CPLD.CONN_GIO54
40 CPLD.CONN_GIO65
40 CPLD.CONN_GIO63
40 CPLD.CONN_GIO62
40 CPLD.CONN_GIO60
40 CPLD.CONN_GIO58
40 CPLD.CONN_GIO56
40 CPLD.CONN_GIO7
40 CPLD.CONN_GIO17
40 CPLD.CONN_GIO67
40 CPLD.CONN_GIO31
40 CPLD.CONN_GIO64
40 CPLD.CONN_GIO61
40 CPLD.CONN_GIO59
40 CPLD.CONN_GIO57
40 CPLD.CONN_GIO32
41 GIO_DILC_DOCK_DET
41 GIO_DILC_CAM_PWR_DET
41 SPI2_SCLK_DILC
41 SPI2_SDO_DILC
41 SPI2_SDI_DILC
41 GIO_DILC_AVJDET
41 GIO_DILC_CHG_CTL
41 GIO_DILC_DRV_VBUS1
41 GIO_DILC_VBUS_DET
USB_OVER_CURRENT
DRV_VBUS
LCD_OE_5V
ENABLE_LCD_3V3
ONENAND_INT
ONENAND_RST
LED0
LED1
LED2
LED3
EMIF_KEYPAD
MS.INS
SD/MMC.INS
SD/MMC.WP
SD/MMC1.WP
SD/MMC1.INS
CPLD.CONN_RESETn
CPLD.CONN_GIO6
CPLD.CONN_GIO16
CPLD.CONN_GIO54
CPLD.CONN_GIO65
CPLD.CONN_GIO63
CPLD.CONN_GIO62
CPLD.CONN_GIO60
CPLD.CONN_GIO58
CPLD.CONN_GIO56
CPLD.CONN_GIO7
CPLD.CONN_GIO17
CPLD.CONN_GIO67
CPLD.CONN_GIO31
CPLD.CONN_GIO64
CPLD.CONN_GIO61
CPLD.CONN_GIO59
CPLD.CONN_GIO57
CPLD.CONN_GIO32
GIO_DILC_DOCK_DET
GIO_DILC_CAM_PWR_DET
SPI2_SCLK_DILC
SPI2_SDO_DILC
SPI2_SDI_DILC
GIO_DILC_AVJDET
GIO_DILC_CHG_CTL
GIO_DILC_DRV_VBUS1
GIO_DILC_VBUS_DET
R1
P4
T2
P5
R3
N5
R4
P6
T4
N6
R5
M6
T5
P7
R6
N7
T6
M7
R7
P8
T7
N8
R8
N9
T8
T9
R9
P9
T10
M10
R10
N10
T11
P10
R11
M11
T12
N11
R12
P11
T13
M12
R13
N12
R14
P12
T15
R16
P13
DM365 EVM Technical Reference
M8
M9
B4.IO_2
B4.IO_3
B4.IO_4
B4.IO_5
B4.IO_6
B4.IO_7
B4.IO_14
B4.IO_15
B4.IO_16
B4.IO_17
B4.IO_18
B4.IO_19
B4.IO_20
B4.IO_21
B4.IO_22
B4.IO_23
B4.IO_24
B4.IO_25
B4.IO_26
B4.IO_27
B4.IO_28
B4.IO_29
B4.IO_30
B4.IO_31
B4.IO_32
B4.IO_33
B4.IO_34
B4.IO_35
B4.IO_36
B4.IO_37
B4.IO_38
B4.IO_39
B4.IO_40
B4.IO_41
B4.IO_42
B4.IO_43
B4.IO_44
B4.IO_45
B4.IO_46
B4.IO_47
B4.IO_48
B4.IO_49
B4.IO_50
B4.IO_51
B4.IO_52
B4.IO_53
B4.IO_54
B4.IO_63
B4.IO_64
VCCIO.B4.1
VCCIO.B4.2
VCCIO.B4.3
VCCIO.B4.4
L8
L9
T3
T14
C384
0.1UF
C404
0.1UF
C385
0.1UF
C395
0.1 UF
C
B
B4.DEV_OE
B4.DEV_CLRn
EPM2210GF256C5N
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
CPLD SECTION D
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
23 o f
53
Spectrum Digital, Inc
A-24
5
5
4
3
2
1
D
D
VCC_CPLD_1V8
U33E
F10
G11
H8
H10
J7
J9
K6
L7
VCCINT.1
VCCINT.2
VCCINT.3
VCCINT.4
VCCINT.5
VCCINT.6
VCCINT.7
VCCINT.8
GNDINT.1
GNDINT.2
GNDINT.3
GNDINT.4
GNDINT.5
GNDINT.6
GNDINT.7
GNDINT.8
F7
G6
H7
H9
J8
J10
K11
L10
VCC_CPLD_1V8
C388
0.1uF
C
GNDIO.1
GNDIO.2
GNDIO.3
GNDIO.4
GNDIO.5
GNDIO.6
GNDIO.7
GNDIO.8
GNDIO.9
GNDIO.10
GNDIO.11
GNDIO.12
GNDIO.13
GNDIO.14
GNDIO.15
GNDIO.16
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
C394
0.1uF
C402
0.1uF
C387
0.1uF
C396
0.1UF
C393
0.1UF
C398
0.1UF
C400
0.1UF
C
VCC_CPLD_1V8
C420
10uF
C421
10uF
B
B
EPM2210GF256C5N
A-25
Page Contents:
CPLD POWER
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
24 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
D
D
J14
3,20,26,27
3,20,26,27
3,20,26,27
3,20,26,27
EM_D0
EM_D2
EM_D4
EM_D6
EM_D0
EM_D2
EM_D4
EM_D6
EM_D8
EM_D10
EM_D12
EM_D14
3,27 EM_D8
3,27 EM_D10
3,27 EM_D12
3,27 EM_D14
3,26,27 EM_WAIT
EM_CE0
3,20 EM_CE0
EM_CE1
3,20 EM_CE1
3,20 EMIF_SEL
C
R413
10K
3,27 EM_BA0
3,27 EM_A0
3,20,26,27 EM_A2
3,27 EM_A4
3,27 EM_A6
3,20,27 EM_A8
3,20,27 EM_A10
3,20,27 EM_A12
EM_BA0
EM_A0
EM_A2
EM_A4
EM_A6
EM_A8
EM_A10
EM_A12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
EM_D1
EM_D3
EM_D5
EM_D7
EM_D1
EM_D3
EM_D5
EM_D7
EM_D9
EM_D11
EM_D13
EM_D15
EM_CLK
EM_ADV
EM_WE
EM_OE
EM_BA1
EM_A1
EM_A3
EM_A5
EM_A7
EM_A9
EM_A11
EM_A13
VCC_3V3
3,20,26,27
3,20,26,27
3,20,26,27
3,20,26,27
EM_D9 3,27
EM_D11 3,27
EM_D13 3,27
EM_D15 3,27
EM_CLK 3,27
EM_ADV 3,27
EM_WE 3,20,26,27
EM_OE 3,20,26,27
C
EM_BA1
EM_A1
EM_A3
EM_A5
3,27
3,20,26,27
3,27
3,27
EM_A7
EM_A9
EM_A11
EM_A13
3,27
3,20,27
3,20,27
3,20,27
VCC_3V3
HEADER 30X2
VCC_5V
VCC_5V
B
B
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
EMIF/UHPI DC INTERFACE
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
25 o f
53
Spectrum Digital, Inc
A-26
5
5
4
3
2
1
D
D
VCC_3V3
R376
3,20,25,27 EM_A2
3,20,25,27 EM_A1
3,20,25,27 EM_WE
NAND_CLE
NAND_ALE
EM_WE
VCC_3V3
VCC_3V3
C369
0.1uF
B
R367
10K
NC.1
NC.2
NC.3
NC.4
NC.5
R/B2n
R/Bn
RE
CE
CE2
NC.11
VCC.1
VSS.1
NC.14
NC.15
CLE
ALE
WE
WP
NC.20
NC.21
NC.22
NC.23
NC.24
MH2
3,20,25,27 EM_OE
20 NAND_CE0n
20 NAND_CE1n
0
0
1
2
3
4
5
6
NAND_RB 7
8
9
10
11
12
0 13
14
15
16
17
18
19
20
21
22
23
24
MH1
R391
R389
NAND_RE
NAND_CE0n
NAND_CE1n
3,25,27 EM_WAIT
C
U28
R114
10K
MH2
R116
10K
MH1
VCC_3V3
DNU.48
NC.47
NC.46
NC.45
I/O7
I/O6
I/O5
I/O4
NC.40
NC.39
DNU/VSS
VCC.2
VSS.2
NC.35
NC.34
NC.33
I/O3
I/O2
I/O1
I/O0
NC.28
NC.27
DNU.26
DNU.25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
EM_D7
EM_D6
EM_D5
EM_D4
R378
EM_D7
EM_D6
EM_D5
EM_D4
3,20,25,27
3,20,25,27
3,20,25,27
3,20,25,27
0
C
VCC_3V3
C366
0.1uF
EM_D3
EM_D2
EM_D1
EM_D0
C359
2.2uF
EM_D3 3,20,25,27
EM_D2 3,20,25,27
EM_D1 3,20,25,27
EM_D0 3,20,25,27
MT29F16G08FAAWC:A
B
A-27
Page Contents:
NAND FLASH
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
26 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
D
U27
VCC_3V3
R375
10K
R380
10K
R390
10K
R481
10K
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
E2
B4
A1
H1
G1
F3
A2
CE
OE
WE
RDY
INT
AVD
RESET
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
D1
A3
A6
B1
C3
C4
B5
B2
C1
D6
D5
C2
C5
E3
B3
D3
VccIO
VccCORE
C6
B6
ONENAND_CE
20 ONENAND_CE
EM_OE
3,20,25,26 EM_WE
EM_WE
A5
A4
E4
E5
G4
H6
CLK
E1
EM_D15 3,25
EM_D14 3,25
EM_D13 3,25
EM_D12 3,25
EM_D11 3,25
EM_D10 3,25
EM_D9 3,25
EM_D8 3,25
EM_D7 3,20,25,26
EM_D6 3,20,25,26
EM_D5 3,20,25,26
EM_D4 3,20,25,26
EM_D3 3,20,25,26
EM_D2 3,20,25,26
EM_D1 3,20,25,26
EM_D0 3,20,25,26
C
VCC_3V3
R379
0
C98
C371
C372
C361
C362
0.1 uF
0.1 uF
0.1 uF
0.1 uF
22uF
1
2
3
4
5
6
7
3,20,25,26 EM_OE
VSS.1
VSS.2
NC.E4
NC.E5
NC.G4
NC.H6
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
C
D4
F1
F2
D2
F5
G5
E6
F6
F4
G6
H3
H2
H5
H4
G3
G2
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
EM_BA0
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
EM_A7
EM_A6
EM_A5
EM_A4
EM_A3
EM_A2
EM_A1
EM_A0
EM_BA1
3,25 EM_BA0
3,20,25 EM_A13
3,20,25 EM_A12
3,20,25 EM_A11
3,20,25 EM_A10
3,20,25 EM_A9
3,20,25 EM_A8
3,25 EM_A7
3,25 EM_A6
3,25 EM_A5
3,25 EM_A4
3,25 EM_A3
3,20,25,26 EM_A2
3,20,25,26 EM_A1
3,25 EM_A0
3,25 EM_BA1
8
9
10
11
12
13
14
15
D
B
KFG1G16U2B-DIB6000
EM_WAIT
3,25,26 EM_WAIT
B
ONENAND_INT
23 ONENAND_INT
EM_ADV
3,25 EM_ADV
ONENAND_RST
23 ONENAND_RST
EM_CLK
3,25 EM_CLK
DM365 EVM Technical Reference
R377
10K
R392
R364
10K
10K
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
ONE NAND
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
27 o f
53
Spectrum Digital, Inc
A-28
5
5
4
3
2
1
VCC_3V3
D
D
VCC_3V3
C213
R267
10K
0.1uF
R255
10K
U16
1
2
3
4
9 SPI0_SDENA0
9 SPI0_SDI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8
7
6
5
SPI0_SCLK 9
SPI0_SDO 9
VCC_3V3
AT25640AN-10SU-2.7
R266
10K
C
C
VCC_3V3
VCC_3V3
R124
NO-POP
R123
NO-POP
R122
NO-POP
R393
NO-POP
R394
NO-POP
R395
NO-POP
C365
0.1uF
B
U29
8
VCC
9,20,32,34,35,36,37,39,40,44 I2C_DATA
I2C_DATA
R513
0
5
SDA
9,20,32,34,35,36,37,39,40,44 I2C_SCLK
I2C_SCLK
R514
0
6
SCL
A0
A1
A2
WP
VSS
CAT24C256
1
2
3
7
4
B
A-29
Page Contents:
SPI EEPROM
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
28 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
VCC_3V3
VCC_3V3
VCC_3V3
SILKSCREEN:
UART
+
C130
1uF
C6
10uF
R186
10K
R178
10K
U3
FORCEOFF
16
FORCEON
12
T_OUT
13
DB9M
L2
9 UART0_TXD
UART0_TXD
11
T_IN
1uH
C124
10pF
9 UART0_RXD
UART0_RXD
9
R_OUT
R_IN
8
EN
INVALID
10
GND_E_RS232
GND_E_RS232
2
C1+
C2+
5
C2-
6
V+
3
V-
7
C7
1uF
C
1uH
C123
10pF
4
14
C1-
GND
MAX3221CPWRG4
P1
C118
10pF
GND_E_RS232
R1
10K
5
9
4
8
3
7
2
6
1
C119
10pF
L3
1
D
GND_E_RS232
10
VCC
GND_E_RS232
11
15
D
GND_E_RS232
C4
1uF
C
C127
1uF
C131
1uF
L41
BLM21PG221SN1D
L40
BLM21PG221SN1D
GND_E_RS232
B
B
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
RS232
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
29 o f
53
Spectrum Digital, Inc
A-30
5
5
4
VCC_3V3
3
VCC_3V3
2
1
VCC_3V3
D
D
+ C308
10uF
R309
51K
R305
51K
R312
51K
R323
51K
R294
51K
C307
VCC_3V3
.1uF
R333
51K
VCC_3V3
R329
NO-POP
R288
NO-POP
R335
NO-POP
SCDB1C0101/B1A0102
20
M1
M2
M3
M4
M5
M6
M1
M2
M3
M4
M5
M6
19
18
17
16
15
14
13
12
11
10
MS.CLK
MS.DATA3
MS.DATA2
MS.DATA0
MS.DATA1
MS.CMD.BS
C
INS
WP
8 SD0_DATA0
8 SD0_DATA1
MS.INS 23
MS.VSS2
MS.VCC
MS.SCLK
MS.DATA3
MS.XINS
MS.DATA2
MS.SDIO/DATA0
MS.DATA1
MS.BS
MS.VSS1
21
SD_DATA0
SD_DATA1
SD.DAT2
SD.DAT3
SD.CMD
SD.VSS1
SD.VDD
SD.CLK
SD.VSS2
SD.DAT0
SD.DAT1
COM
SD_CLK
8 SD0_CLK
C
9
1
2
3
4
5
6
7
8
GND.1
SD_DATA2
SD_DATA3
SD_CMD
8 SD0_DATA2
8 SD0_DATA3
8 SD0_CMD
22
23
R316
100K
VCC_3V3
J12
R66
51K
R69
0
R68
51K
SD/MMC.INS 23
SD/MMC.WP 23
MS.CMD.BS
MS.DATA1
MS.DATA0
MS.DATA2
MS.DATA3
MS.CLK
B
B
A
DM365 Evaluation Module
Title:
Page Contents:
SD/MMC/MS CARD INTERFACE
Size: B
DWG NO
Revision:
A-31
Date:
5
4
3
2
510842-0001
Sheet
Monday, April 13, 2009
1
30 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
4
3
2
1
D
D
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
R336
51K
+ C311
C
R313
51K
R319
51K
R67
51K
R281
51K
R289
51K
R307
51K
10uF
R325
51K
C310
C
.1uF
J25
CONN_SD1_DATA2
CONN_SD1_DATA3
CONN_SD1_CMD
8 CONN_SD1_DATA2
8 CONN_SD1_DATA3
8 CONN_SD1_CMD
9
1
2
3
4
5
6
7
8
CON N_SD1_CLK
8 CONN_SD1_CLK
CONN_SD1_DATA0
CONN_SD1_DATA1
8 CONN_SD1_DATA0
8 CONN_SD1_DATA1
R285
NO-POP
R297
NO-POP
DAT2
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
WP
COM
CARD_DETECT
WP
CO
CD
SD/MMC1.WP 23
SD/MMC1.INS 23
R331
0
R310
NO-POP
MMC/SD_CARD
B
B
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
A
DM365 Evaluation Module
Title:
Page Contents:
SD/MMC CARD INTERFACE
Size: B
DWG NO
Revision:
Date:
5
4
3
2
509902-0001
Monday, April 13, 2009
Sheet
1
31 o f
53
Spectrum Digital, Inc
A-32
5
5
4
3
2
1
D
D
20
19
CH1-SAG
18
CH2-OUT
17
C115
C116
2
CH1-INA
0
3
CH2-INA
7 DAC_2_B/PB
R340
0
4
CH3-INA
R101
75
R100
75
5
R99
75
C
DENC_GND
DENC_GND
DENC_GND
C336
NO-POP
C325
NO-POP
C326
NO-POP
DENC_GND
DENC_GND
CH2-INB
7
CH3-INB
8
I2C-A1
9
I2C-A0
DENC_GND
R133
75
J21
RCA JACK(RED)
2
.01uF
DENC_GND
C108
330uF
DENC_GND
R357
.01uF
J17
RCA JACK(GRN)
2
267 1%
CH1-INB
DENC_GND
CH3-OUT
15
CH3-SAG
14
I2C-SCL
13
I2C-SDA
12
VS+
11
C112
C113
R353
330uF
R141
75
C
.01uF
267 1%
DENC_GND
DENC_GND
GND.1
DENC_GND
VCC_DENC
16
75
267 1%
C109
CH2-SAG
6
10
R356
R146
4
1
3
0
R339
+
R338
7 DAC_1_G/Y
+
7 DAC_3_R/PR
330uF
4
1
3
NC20
CH1-OUT
NC1
+
U23
1
THS7303
L28
BEAD
VCC_DENC
VCC_3V3
C327
C347
C89
C88
.01uF
33uF
33uF
J20
RCA JACK(BLUE)
2
1uF
R355
NO-POP
4
1
3
R98
NO-POP
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
B
R97
0
B
R345
0
DENC_GND
DENC_GND
I2C_DATA
R107
100
9,20,28,34,35,36,37,39,40,44 I2C_SCLK
I2C_SCLK
R108
100
I2C_SDA_7303
I2C_SCL_7303
C352
27pF
DENC_GND
C353
27pF
DENC_GND
PL4
1
2
SPECTRUM DIGITAL INCORPORATED
A
A
PLANE LINK
DM365 Evaluation Module
Title:
Page Contents:
COMPONENT VIDEO OUTPUT
Size: B
DWG NO
DENC_GND
A-33
Date:
5
4
3
2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
32 o f
53
Spectrum Digital, Inc
9,20,28,34,35,36,37,39,40,44 I2C_DATA
4
3
2
1
VID_4V1
HD_ CLKIN
35 HD_CLKIN
CCD-DATA3
CCD-DATA2
CCD-DATA1
CCD-DATA0
CCD-DATA03
CCD-DATA02
CCD-DATA01
CCD-DATA00
34
34
34
34
34
34
C
CCD-DATA15
CCD-DATA14
CCD-DATA13
CCD-DATA12
CCD-VSYNC
CCD-HSYNC
CCD-PCLK
VCC.1
S0
S1
S2
1
56
55
54
52
50
47
45
43
41
39
36
34
32
30
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
2
4
6
9
11
13
15
18
21
23
25
27
53
51
48
46
44
42
40
37
35
33
31
29
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
1B3
2B3
3B3
4B3
5B3
6B3
7B3
8B3
9B3
10B3
11B3
12B3
3
5
7
10
12
14
16
20
22
24
26
28
DECODER_IMAGER_S0
DECODER_IMAGER_S1
DECODER_IMAGER_S2
R286
DECODER_IMAGER_S0 22
DECODER_IMAGER_S1 22
DECODER_IMAGER_S2 22
VDIN_Y7
VDIN_Y6
VDIN_Y5
VDIN_Y4
VDIN_Y3
VDIN_Y2
VDIN_Y1
VDIN_Y0
VD IN_VD
VDIN_HD
360
VID_4V1
5
5
5
5
5
5
5
5
5
5
D
VCC_5V
R63
1.5K
D6
LM4040DCIM3-4.1
3
VDIN_PCLK 5
TVP5146_Y7
TVP5146_Y6
TVP5146_Y5
TVP5146_Y4
TVP5146_Y3
TVP5146_Y2
TVP5146_Y1
TVP5146_Y0
TVP5146_Y7 37
TVP5146_Y6 37
TVP5146_Y5 37
TVP5146_Y4 37
TVP5146_Y3 37
TVP5146_Y2 37
TVP5146_Y1 37
TVP5146_Y0 37
TVP5146VSYNC 37
TVP5146HSYNC 37
C
TVP5146PCLK 37
GND.4
GND.3
GND.2
GND.1
8
7
6
5
34 CCD-PCLK
CCD-DATA15
CCD-DATA14
CCD-DATA13
CCD-DATA12
CCD -VSYNC
CCD-HSYNC
U17
1
H D_ Y7
H D_ Y6
H D_ Y5
H D_ Y4
H D_ Y3
H D_ Y2
H D_ Y1
H D_ Y0
35 HD_Y7
35 HD_Y6
35 HD_Y5
35 HD_Y4
35 HD_Y3
35 HD_Y2
35 HD_Y1
35 HD_Y0
35 HD_VSYNC
35 HD_HSYNC
34
34
34
34
560pF
2
D
17
C250
C251
0.1uF
1
2
3
4
49
38
19
8
RN26
RPACK4-33
R298
10K
35
35
35
35
35
35
35
35
560pF
HD _C7
HD _C6
HD _C5
HD _C4
HD _C3
HD _C2
HD _C1
HD _C0
HD_C7
HD_C6
HD_C5
HD_C4
HD_C3
HD_C2
HD_C1
HD_C0
CCD-DATA11
CCD-DATA10
CCD-DATA09
CCD-DATA08
CCD-DATA07
CCD-DATA06
CCD-DATA05
CCD-DATA04
CCD-DATA11
CCD-DATA10
CCD-DATA9
CCD-DATA8
CCD-DATA7
CCD-DATA6
CCD-DATA5
CCD-DATA4
R301
10K
S0
S1
S2
1
56
55
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
2
4
6
9
11
13
15
18
21
23
25
27
53
51
48
46
44
42
40
37
35
33
31
29
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
1B3
2B3
3B3
4B3
5B3
6B3
7B3
8B3
9B3
10B3
11B3
12B3
3
5
7
10
12
14
16
20
22
24
26
28
DECODER_IMAGER_S0
DECODER_IMAGER_S1
DECODER_IMAGER_S2
R328
VD IN_C7
VD IN_C6
VD IN_C5
VD IN_C4
VD IN_C3
VD IN_C2
VD IN_C1
VD IN_C0
360
TVP5146_C7
TVP5146_C6
TVP5146_C5
TVP5146_C4
TVP5146_C3
TVP5146_C2
TVP5146_C1
TVP5146_C0
TVP5146_C7
TVP5146_C6
TVP5146_C5
TVP5146_C4
TVP5146_C3
TVP5146_C2
TVP5146_C1
TVP5146_C0
5
5
5
5
5
5
5
5
B
37
37
37
37
37
37
37
37
SPECTRUM DIGITAL INCORPORATED
GND.4
GND.3
GND.2
GND.1
A
R295
10K
U21
54
52
50
47
45
43
41
39
36
34
32
30
49
38
19
8
DM365 EVM Technical Reference
34
34
34
34
34
34
34
34
17
C299
C300
0.1uF
B
SN74CBT16214DGGR
VID_4V1
CPLD_CCD-DATA03
CPLD_CCD-DATA02
CPLD_CCD-DATA01
CPLD_CCD-DATA00
VCC.1
22
22
21
21
Page Contents:
VIDEO INPUT MULTIPLEXER
Size:B
DWG NO
SN74CBT16214DGGR
Date:
5
4
A
DM365 Evaluation Module
Title:
3
2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
33 o f
53
Spectrum Digital, Inc
A-34
5
5
4
3
2
1
D
D
5V_DC_J6
5V_DC_J6
3V3_STB
GND_STB
MTR_3V3 5V_DC_J6
J10A
GPIO_MD1
5V_DC_J6
22 GPIO_MD1
GND_MTR
33 CCD-DATA02
CCD-DATA2
33 CCD-DATA03
CCD-DATA3
33 CCD-DATA04
CCD-DATA4
33 CCD-DATA05
CCD-DATA5
33 CCD-DATA06
CCD-DATA6
33 CCD-DATA07
CCD-DATA7
33 CCD-DATA08
CCD-DATA8
C
33 CCD-DATA09
CCD-DATA9
33 CCD-DATA10
CCD-DATA10
33 CCD-DATA11
CCD-DATA11
33 CCD-DATA12
CCD-DATA12
33 CCD-DATA13
CCD-DATA13
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
J10B
22
22
22
22
GPIO_MD10
GPIO_MD9
GPIO_MD8
GPIO_MD7
33 CCD-DATA00
33 CCD-DATA15
33 CCD-DATA01
22 GPIO_MD6
22 GPIO_MD5
22 GPIO_MD4
22 PWM_CCD_SUB
22 CCD-DDSRST
22 GPIO_MD3
22 SPI4_SDI_GPIO_MD2_CONN
22 SPI4_SDO_CONN
22 SPI4_SCLK_CONN
GPIO_MD10
GPIO_MD9
GPIO_MD8
GPIO_MD7
5V_DC_J6
MOT-PWR
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
CCD-DATA0
CCD-DATA15
CCD-DATA1
GPIO_MD6
GPIO_MD5
GPIO_MD4
PWM_CCD_SUB
CCD-DDSRST
GPIO_MD3
SPI4_SDI_GPIO_MD2_CONN
SPI4_SDO_CONN
SPI4_SCLK_CONN
33 CCD-PCLK
CCD-PCLK
22 CCD-WEN
C CD-WEN
22 CCD-FIELD
CCD-F IELD
33 CCD-HSYNC
C CD-HSYNC
33 CCD-VSYNC
C CD -VSYNC
33 CCD-DATA14
CCD-DATA14
PCN10-96P-2.54DSA,HIROSE CL583-0002-4
J10C
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
VCC_CCD15V5
VCC_CCD15V
+
C259
10uF
C265
0.01uF
9,20,28,32,35,36,37,39,40,44 I2C_DATA
9,20,28,32,35,36,37,39,40,44 I2C_SCLK
22 GPIO_MD19
22 GPIO_MD18
22 GPIO_MST_SLV
22 GPIO_MD17
22 GPIO_MD16
22 GPIO_MD15
22 GPIO_MD14
22 GPIO_MD13
22 GPIO_TACH
22 GPIO_MD12
22 GPIO_MD11
I2C_DATA
I2C_SCLK
5 V_DC_J6
GPIO_MD19
GPIO_MD18
GPIO_MST_SLV
GPIO_MD17
GPIO_MD16
GPIO_MD15
GPIO_MD14
GPIO_MD13
GPIO_TACH
GPIO_MD12
GPIO_MD11
R515
0
R516
0
VCC_CCD_N7V5
VCC_CCD_N7V5
3V3_CCD
C278
10uF
+
CCD_PSMON
C271
0.01uF
5 V_DC_J6
3V3A_CCD
PCN10-96P-2.54DSA,HIROSE CL583-0002-4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C
PCN10-96P-2.54DSA,HIROSE CL583-0002-4
AGND_IMAGER
3V3_CCD
C90
3.3uF
C329
+
0.01uF
B
C75
3.3uF
B
+
C287
0.01uF
AGND_IMAGER
3V3A_CCD
AFE_3V3
L68
BLM41P750SPT
L53
5V_DC_J6
L71
BLM41P750SPT
GND_STB
BLM41P750SPT
BLM41P750SPT
C85
3.3uF
VCC_3V3
L78
+
C306
0.01uF
3V3_CCD
BLM41P750SPT
L81
BLM41P750SPT
SPECTRUM DIGITAL INCORPORATED
A
A
GND_MTR
L74
DM365 Evaluation Module
Title:
BLM41P750SPT
A-35
Page Contents:
IMAGER INTERFACE
Size:B
DWG NO
Revision:
C
510842-0001
AGND_IMAGER
Date:
5
4
3
2
Monday, April 13, 2009
Sheet
1
34 o f
53
Spectrum Digital, Inc
3V3_STB
L48
5V_DC_J6
VCC_5V
4
3
2
1
TVP_AVCC_1V8
RIN2
10
65
64
63
62
61
59
58
57
56
55
R_0
R_1
R_2
R_3
R_4
R_5
R_6
R_7
R_8
R_9
RIN3
9
75
SDA
9,20,28,32,34,36,37,39,40,44 I2 C_SCLK
R518
0
74
SCL
73
I2CA
R320
NO-POP
77
COAST
R321
0
76
CLAMP
R314
0
R317
0
A
70
PWDN
72
TMS
VCC_3V3
10
NO-POP
R322
0
0.1uF
C277
C301
C249
0.1uF
0.1uF
0.1uF
C66
0.1uF
C239
1
C238
0.1uF
R278
10
THS7353_CH2 36
0.01uF
100
SOGIN_2
99
C
GIN3
98
SOGIN_3
97
GIN4
96
C71
0.1uF
C257
0.1uF
C70
0.1uF
C254
0.1uF
C275
C280
0.1uF
0.1uF
C69
0.1uF
TVP_AGND
BIN1
18
BIN2
17
BIN3
16
HSYNC_A
VSYNC_A
HSYNC_B
VSYNC_B
81
78
82
79
C64
R71
10
THS7353_CH3 36
0.1uF
C245
0.1uF
TVP_AGND
C246
0.1uF
TVP_AVCC_3V3
B
L21
BLM21PG221SN1D
TVP_AGND
TVP_VCC_PLL
PLL_F
89
FILT2
88
FILT1
87
R306
TVP_VCC_PLL
R296
0
NO-POP
R86
1.5K 1%
TVP_AVCC_1V8
C74
0.1uF
C72
4700pF
R85
SPECTRUM DIGITAL INCORPORATED
NO-POP
R308
NO-POP
A
DM365 Evaluation Module
Page Contents:
TVP7002 HD VIDEO IN
Size: B
DWG NO
TVP_AGND
TVP_AGND
Date:
5
C297
0.1uF
TVP_AGND
Title:
R324
C273
THS7353_CH1 36
TVP_ANALOG_VCC_1V9
101
DM365 EVM Technical Reference
VCC_3V3
R72
C67
0.1uF
2
NSUB.1
NSUB.2
9,20,28,32,34,36,37,39,40,44 I2C_DATA
0.1uF
21
91
RESETB
0
PLL_A18GND.1
PLL_A18GND.2
PLL_A18GND.3
71
R517
83
86
90
EXT_CLK
A18_GND.4
A18_GND.3
A18_GND.2
A18_GND.1
21 TVP_7002_RSTn
80
20
8
5
3
TP38
TP-60
D
VCC_DEC_3V3
A33GND.4
A33GND.3
A33_GND.2
A33_GND.1
22
0.1uF
TVP_AGND TVP_AGND TVP_AGND TVP_AGND TVP_AGND
95
92
15
12
DATACLK
R282
33 HD_CLKIN
C244
0.1uF
TVP_VCC_PLL
GND.1
GND.2
28
B
SOGIN_1
40
68
B_0
B_1
B_2
B_3
B_4
B_5
B_6
B_7
B_8
B_9
C261
0.1uF
VCC_3V3
GIN1
IOGND.5
IOGND.4
IOGND.3
IOGND.2
IOGND.1
38
37
36
35
34
33
32
31
30
29
C65
TVP_AGND
GIN2
RN29 RPACK8-22
B_TVP_CR_CB2
9
8
B_TVP_CR_CB3
10
7
B_TVP_CR_CB4
11
6
B_TVP_CR_CB5
12
5
B_TVP_CR_CB6
13
4
B_TVP_CR_CB7
14
3
B_TVP_CR_CB8
15
2
B_TVP_CR_CB9
16
1
C243
0.1uF
4
6
7
19
11
SOGOUT
HD _C0
HD _C1
HD _C2
HD _C3
HD _C4
HD _C5
HD _C6
HD _C7
C264
0.1uF
A18VDD.1
A18VDD.2
A18VDD.3
A18VDD.4
84
85
PLL_A18VDD.1
PLL_A18VDD.2
13
14
93
94
A33VDD.1
A33VDD.2
A33VDD.3
A33VDD.4
RIN1
HSOUT
25
PWRPAD
HD_C0
HD_C1
HD_C2
HD_C3
HD_C4
HD_C5
HD_C6
HD_C7
IOVDD.1
IOVDD.2
IOVDD.3
IOVDD.4
VSOUT
G_0
G_1
G_2
G_3
G_4
G_5
G6
G7
G8
G9
C240
0.1uF
VCC_1V8
24
52
51
50
49
48
47
46
45
44
43
C242
0.1uF
TVP_AGND
23
RN32 RPACK8-22
B_TVP_Y2
9
8
B_TVP_Y3
10
7
B_TVP_Y4
11
6
B_TVP_Y5
12
5
B_TVP_Y6
13
4
B_TVP_Y7
14
3
B_TVP_Y8
15
2
B_TVP_Y9
16
1
C247
0.1uF
TVP_AGND
22
H D_Y0
H D_Y1
H D_Y2
H D_Y3
H D_Y4
H D_Y5
H D_Y6
H D_Y7
C241
TVP7002
22
C
33
33
33
33
33
33
33
33
TVP_AVCC_1V8
R527
TP31
TP-60
HD_Y0
HD_Y1
HD_Y2
HD_Y3
HD_Y4
HD_Y5
HD_Y6
HD_Y7
TVP_VCC_PLL
R528
TP33
TP-60
33
33
33
33
33
33
33
33
FIDOUT
67
60
54
42
27
33 HD_HSYNC
22
DVDD.1
DVDD.2
U20
TP34
TP-60
D
33 HD_VSYNC
26
41
53
66
TP32
TP-60
39
69
VCC_1V8 TVP_AVCC_3V3
VCC_3V3
TVP_AVCC_3V3
4
3
2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
35 o f
53
Spectrum Digital, Inc
A-36
5
5
4
3
2
1
C73
0.1uF
J11
RCA JACK(RED)
2
4
1
3
U15
35 THS7353_CH1
20
NC20
19
CH1OUT
18
CH1ADJ
NC1
1
CH1-INA
2
CH2-INA
3
CH3-INA
4
CH1-INB
5
CH2-INB
6
CH3-INB
7
I2C-A1
8
I2C-A0
9
R88
75
TVP_AGND
D
17
35 THS7353_CH2
16
CH2ADJ
15
CH3OUT
14
CH3ADJ
D
C48
0.1uF
J8
RCA JACK(GRN)
2
4
1
3
35 THS7353_CH3
CH2OUT
TVP_AGND
13
I2C-SCL
12
I2C-SDA
11
VS+
GND.1
R56
75
TVP_AGND
TVP_AGND
10
TVP_AGND
C63
0.1uF
L20
BLM21PG221SN1D
9,20,28,32,34,35,37,39,40,44 I2C_SCLK
9,20,28,32,34,35,37,39,40,44 I2C_DATA
I2C_SCLK
I2C_DATA
R65
R64
100
J9
RCA JACK(BLUE)
2
VCC_DEC_3V3
R75
75
I2C_SCL_7353
100
C208
C218
C49
C59
1uF
.01uF
33uF
33uF
C
4
1
3
THS7353
C
TVP_AGND
I2C_SDA_7353
TVP_AGND
C223
22pF
C222
22pF
TVP_AGND
TVP_AGND
VCC_DEC_3V3
L23
B
U22
1
2
BLM21PG221SN1D
C313
2.2uF
VOUT2
VOUT1
10
9
4
BIAS
PG
3
7
SS
FB
8
5
EN
GND
6
10uF
C82
5.6pF
R334
4.99K
TVP_AGND
TVP_AGND
VOUT = 0.8 * ( 1+R401/R402 )
11
L24
B
C62
R90
6.81K
TVP_AGND
BLM21PG221SN1D
TVP_AGND
PLACE NEAR TVP7002
TVP_AGND
SPECTRUM DIGITAL INCORPORATED
A
A-37
Page Contents:
TVP7002 HD VIDEO IN
Size:B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
36 o f
53
Spectrum Digital, Inc
C84
0.001uF
TVP_ANALOG_VCC_1V9
TPS74701
IN1
IN2
PP1
TVP_AGND
4
3
1.8VD_DDEC
2
C322
1
C360
0.1uF
C364
C323
0.1uF
0.1uF
C338
C342
C356
C335
C321
C357
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R354
NO-POP
NO-POP
35
FSS/GPIO
33
PWRDWN
34
RESETB
IOVDD1
IOVDD2
IOVDD3
3.3VD_DDEC
R366
PLL_A18VDD
3.3VD_DDEC
A18VDD_REF
1.8VA_DDEC
3.3VD_DDEC
38
48
61
0.1uF
DEC_GND
D
3.3VD_DDEC
C330
.1uF
31
41
55
67
0.1uF
DVDD1
DVDD2
DVDD3
DVDD4
C345
0.1uF
4
5
20
21
C358
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
0.1uF
11
14
25
78
C350
0.1uF
76
C346
0.1uF
3.3VA_DDEC 1.8VD_DDEC
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD
CH1_A18VDD
C328
12
C319
0.1uF
1.8VA_DDEC
R96
DEC_GND
2K
21 TVP5146_RESETn
J15
749181-1
R519
0
29
SDA
9,20,28,32,34,35,36,39,40,44 I2C_SCLK
R520
0
28
SCL
80
VI_1_A
1
VI_1_B
2
VI_1_C
7
VI_2_A
8
VI_2_B
9
VI_2_C
L76
3
2.7uH
L77
2.7uH
C363
680pF
C370
330pF
C349
4
C355
C354
1
C97
330pF
2
.1uF
R106
75
0.1uF
0.1uF
DEC_GND
DEC_GND
5
7
DEC_GND
6
DEC_GND
DEC_GND DEC_GND
DEC_GND
L75
2.7uH
L72
C332
2.7uH
LUMA
C337
C351
C341
330pF
680pF
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
43
44
45
46
47
50
51
52
53
54
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
57
58
59
60
63
64
65
66
69
70
TVP5146_Y7
TVP5146_Y6
TVP5146_Y5
TVP5146_Y4
TVP5146_Y3
TVP5146_Y2
TVP5146_Y1
TVP5146_Y0
TVP5146_Y7
TVP5146_Y6
TVP5146_Y5
TVP5146_Y4
TVP5146_Y3
TVP5146_Y2
TVP5146_Y1
TVP5146_Y0
33
33
33
33
33
33
33
33
RN34
RPACK8-33
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TVP5146_C7
TVP5146_C6
TVP5146_C5
TVP5146_C4
TVP5146_C3
TVP5146_C2
TVP5146_C1
TVP5146_C0
TVP5146_C7
TVP5146_C6
TVP5146_C5
TVP5146_C4
TVP5146_C3
TVP5146_C2
TVP5146_C1
TVP5146_C0
33
33
33
33
33
33
33
33
HS/CS/GPIO
72
R112
22
TVP5146HSYNC 33
VS/VBLK/GPIO
73
R113
22
TVP5146VSYNC 33
FID/GPIO
71
GLCO/12CA
37
R365
AVID/GPIO
36
2K
DATACLK
40
R352
75
16
R344
VI_3_A
22
TVP5146PCLK 33
3.3VD_DDEC
3.3VD_DDEC
R111
DEC_GND
DEC_GND
DEC_GND
17
C94
C92
0.1uF
0.1uF
18
C331
L70 2.7uH
DEC_GND
C312
680pF
C316
330pF
DEC_GND
DEC_GND
DEC_GND
DEC_GND
23
1.8VA_DDEC
1
L29
2
BLM41P750SPT
XTAL1
74
XTAL2
75
R342
DEC_GND
VCC_DEC_3V3
81
DEC_GND
PL5
2
BLM41P750SPT
1
100K
R110
THERMAL
NO-POP
Y3
14.31818mhz
0
C367
C368
33pF
33pF
C320
0.1uF
3.3VA_DDEC
1
L26
R109
VI_4_A
R105 .1uF
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
VCC_DEC_1V8
VI_3_C
R374
4.7K
75
DEC_GND
R343
2.2K
4.7K
.1uF
C91
0.1uF
B
30
C344
L69 2.7uH
C317
330pF
INTREQ
DEC_GND DEC_GND
10
15
24
79
3
6
19
22
26
13
77
DM365 EVM Technical Reference
3
1
4
J13
RCA JACK(YELLOW)
2
VI_3_B
DGND1
DGND2
DGND3
DGND4
DGND5
IOGND1
IOGND2
IOGND3
DEC_GND
SPECTRUM DIGITAL INCORPORATED
27
32
42
56
68
39
49
62
B
C
.1uF
330pF
A
U24
TVP5146
CH2_A18GND
CH3_A18GND
CH4_A18GND
CH1_A18GND
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
AGND
A18GND_REF
PLL_A18GND
C
9,20,28,32,34,35,36,39,40,44 I2C_DATA
D
RN33
RPACK8-33
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
A
2
Title:
DM365 Evaluation Module
PLANE LINK
1.8VD_DDEC
VCC_DEC_1V8
VCC_DEC_3V3
Page Contents:
3.3VD_DDEC
TVP5146 VIDEO DECODER
DEC_GND
1
L25
2
BLM41P750SPT
1
L30
DEC_GND
2
BLM41P750SPT
Size: B
DWG NO
5
4
3
2
Revision:
C
510842-0001
Date: Monday, April 13, 2009
Sheet
1
37 o f
53
Spectrum Digital, Inc
A-38
5
3.3VA_DDEC
5
4
3
2
1
VCC_3V3
C181
D
D
0.1uF
U11
16
VCC
9 McBSP_CLKX
4
1A
9 McBSP_FSX
7
2A
9
3A
12
4A
9 McBSP_DX
8
R239
360
GND
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
2
3
5
6
11
10
14
13
S
OE
1
15
AIC_McBSP_CLKX 39
CPLD_McBSP_CLKX 22
AIC_McBSP_FSX 39
CPLD_McBSP_FSX 22
AIC_McBSP_DX 39
CPLD_McBSP_DX 22
SEL_AICn_GPIO
SN74CBTLV3257PW
VCC_3V3
C180
0.1uF
U12
16
C
VCC
9 McBSP_CLKR
4
1A
9 McBSP_FSR
7
2A
9
3A
12
4A
9 McBSP_DR
8
R238
360
GND
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
2
3
5
6
11
10
14
13
S
OE
1
15
AIC_McBSP_CLKR 39
CPLD_McBSP_CLKR 22
AIC_McBSP_FSR 39
CPLD_McBSP_FSR 22
AIC_McBSP_DR 39
CPLD_McBSP_DR 22
SEL_AICn_GPIO
C
SEL_AICn_GPIO 22
SN74CBTLV3257PW
R233
2K
B
B
Title:
Page Contents:
A-39
Size: B
McBSP Muxes
DWG NO
4
3
2
Revision:
C
510842-0001
Sheet
Date: Monday, April 13, 2009
5
A
DM365 Evaluation Module
1
38 o f
53
Spectrum Digital, Inc
SPECTRUM DIGITAL INCORPORATED
A
Spectrum Digital, Inc
A-40
VCC_3V3
L45
VCC_3V3
BLM21PG221SN1D
+
5
6
C141
.1uF
C146
.1uF
C14
10uF
L46
C129 .1uF
Line In
3
R179
C21
L9
C157
.1uF
1uF
C147
.1uF
BLM21PG221SN1D
+
C151
.1uF
C16
.1uF
C17
.1uF
VCC_3V3
R180
5.6K
GND_AIC
C128
220pF
L50
5
6
GND_AIC
R190
4
2
1
C27
10uF
C19
.1uF
C161
C138 .1uF
.1uF
5.6K
U7
L39
BLM21PG221SN1D
+
C153
.1uF
P4
P3
C13
10uF
5.6K
4
2
1
Mic In GND_AIC
3
BLM21PG221SN1D
VCC_1V8
R191
5.6K
BLM21PG221SN1D
GND_AIC
C137
220pF
C144
.1uF
TVL320AIC3101
32
7
6
DVDD
IOVDD
DVSS
10
MIC1LP/LINE1LP
11
MIC1LM/LINE1LM
12
MIC1RP/LINE1RP
13
MIC1RM/LINE1RM
DRVDD.1
DRVDD.2
AVDD.1
AVSS1
18
24
25
17
AVSS2
26
HPLOUT
HPLCOM
DRVSS.1
19
20
21
HPRCOM
HPROUT
22
23
GND_AIC
GND_AIC
GND_AIC
GND_AIC
C125
.1uF
GND_AIC
R174
330
R175
10K
GND_AIC
16
14
MIC2L/LINE2L/MICDET
MIC2R/LINE2R
15
MICBIAS
31
RESET
P6
GND_AIC
C158
GND_AIC
C163
1
2
4
33uF,6.3V
L52
BLM21PG221SN1D
L55
BLM21PG221SN1D
33uF,6.3V
3
R225
20K
Headphone Out
6
5
R173
47K
+
.1uF
R227
20K
GND_AIC
21 AIC3101_RESETn
JP1
10
10
10
10
10
10
AIC_BCLK
AIC_BCLK
AIC_WCLK
AIC_WCLK
AIC_DIN
AIC_DOUT
2
3
4
5
BCLK
WCLK
DIN
DOUT
9
8
SDA
SCL
29
RIGHT_LO-
30
GND_AIC
GND_AIC
P5
C142
10uF,6.3V
L44
10uF,6.3V
L47
1
2
4
BLM21PG221SN1D
C152
3
BLM21PG221SN1D
HEADER 9X2
R9
NO-POP
GND_AIC
6
5
R32
R27
R23
R19
R13
R11
28
RIGHT_LO+
+
1
3
5
7
9
11
13
15
17
MCLK
TPAD
2
4
6
8
10
12
14
16
18
27
LEFT_LO-
R218
20K
R10
NO-POP
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
R12
20K
VCC_3V3
Line Out
1
33
AIC_McBSP_CLKX
38 AIC_McBSP_CLKX
AIC_McBSP_CLKR
38 AIC_McBSP_CLKR
AIC_McBSP_FSX
38 AIC_McBSP_FSX
AIC_McBSP_FSR
38 AIC_McBSP_FSR
AIC_McBSP_DX
38 AIC_McBSP_DX
AIC_McBSP_DR
38 AIC_McBSP_DR
28,32,34,35,36,37,40,44 I2C_DATA
28,32,34,35,36,37,40,44 I2C_SCLK
LEFT_LO+
+
C122
220pF
C120
.1uF
+
R172
330
GND_AIC
R200
20K
GND_AIC
DM365 EVM Technical Reference
VCC_3V3
GND_AIC
C165
U8
.1uF
1
EN
VCC
4
2
GND
OUT
3
27Mhz
SPECTRUM DIGITAL INCORPORATED
R18
22
Title:
Page Contents:
Size:B
DM365 Evaluation Module
AIC3101 AUDIO INTERFACE
DWG NO
Date: Monday, April 13, 2009
Revision:
C
510842-0001
Sheet
39 o f
53
5
4
3
2
1
R134
33
23 G1_GIO30
R135
33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
6 VDOUT_Y0
33
23 R0_GIO32
6 VDOUT_Y1
6 VDOUT_Y2
6 VDOUT_Y3
6 VDOUT_Y4
6 VDOUT_Y5
6 VDOUT_Y6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
VDOUT_C0 6,22
VDOUT_C1 6,22
23
23
23
23
23
23
23
23
VDOUT_C2 6,22
VDOUT_C3 6,22
VDOUT_C4 6,22
VDOUT_C5 6,22
23 CPLD.CONN_GIO6
CPLD.CONN_GIO16
CPLD.CONN_GIO54
CPLD.CONN_GIO65
CPLD.CONN_GIO63
CPLD.CONN_GIO62
CPLD.CONN_GIO60
CPLD.CONN_GIO58
CPLD.CONN_GIO56
VDOUT_C6 6,22
23 CPLD.CONN_RESETn
VDOUT_C7 6,22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
MH2
6 VDOUT_Y7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
J23
CPLD.CONN_GIO7 23
CPLD.CONN_GIO17 23
CPLD.CONN_GIO67 23
CPLD.CONN_GIO31 23
CPLD.CONN_GIO64 23
CPLD.CONN_GIO61 23
CPLD.CONN_GIO59 23
CPLD.CONN_GIO57 23
CPLD.CONN_GIO32 23
D
MH2
R132
23 R1_GIO33
D
VCC_1V8
MH1
MH1
VCC_1V8
J19
HEADER 15X2
HEADER 15X2
BAT_VIN
VCC_5V
BAT_VIN
BLM41P750SPT
BL_6V8_RTN
BL_6V8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
6 VDOUT_VSYNC
6 VDOUT_HSYNC
6 VDOUT_VCLK
R138
R140
R142
9 SPI1_SDENA0
9 SPI1_SDO
9 SPI1_SCLK
MH1
L79
C
33
33
33
J18
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
LCD_3V3
LCD_5V
NO-POP
R420
C
VDOUT_LCD_OE 6
VDOUT_FIELD 6,20
R521
R522
VDOUT_EXTCLK 6,20
I2C_DATA 9,20,28,32,34,35,36,37,39,44
I2C_SCLK 9,20,28,32,34,35,36,37,39,44
0
0
R423
MH2
0
R137
9 SPI1_SDI
15V_LCD
33
HEADER 15X2
B
B
C380
NO-POP
VCC_3V3
R1_GIO33
R1_GIO33
VDOUT_FIELD
YOUT3
YOUT4
YOUT5
YOUT6
YOUT7
B0
B1
B2
B3
B4
B5
B6
B7
SPI1_SDI
SPI1_CLK
VDOUT_VCLK
COUT0
COUT1
COUT2
COUT3
COUT4
G0
G1
G2
G3
G4
G5
G6
G7
SPI1_SDENA0
G1_GIO30
COUT5
COUT6
COUT7
YOUT0
YOUT1
YOUT2
LCD_5V
R129
20K
VCC_5V
U32
23 LCD_OE_5V
R411
NO-POP
R128
100K
L34
4
VIN
VOUT2
3
5
ON/OFF VOUT1
2
6
R1/C1
1
R2
DD_5V
C107
BLM41P750SPT
C381
+
.1uF
100uF
R412
0
FDC6331L
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
A-41
Size: B
VIDEO DAUGHTER CARD OUTPUT
DWG NO
4
3
2
Revision:
C
510842-0001
Date: Monday, April 13, 2009
5
A
DM365 Evaluation Module
Sheet
1
40 o f
53
Spectrum Digital, Inc
R0
R1
R2
R3
R4
R5
R6
R7
4
3
2
1
D8
23 GIO_DILC_DOCK_DET
DOCK_DET
1SS355
PWR_VIN
VCC_5V
PWR_VIN
VCC_3V3
D7
D
PWR_VIN
R459
D
1M
R447
NO-POP
100K
R147
2M
CAM_PWR_DET
3
23 GIO_DILC_CAM_PWR_DET
CAM_PWR
2
1
Q6
DTC114EUA
C413
NO-POP
R450
3.3K
R451
3.3K
MP1
VCC_3V3
R452
3 .3K
C
23 SPI2_SCLK_DILC
23 SPI2_SDO_DILC
23 SPI2_SDI_DILC
SB
OP_SERIAL
R458
220
R457
220
R456
220
VCC_3V3
12 LINEOUT
LINEOUT
R455
0
BAT_CHG
R446
100K
10K
R460
C D1
C D2
1
AVJDET
3
23 GIO_DILC_AVJDET
TP53
Q5
TEST POINT
2 AVJ_DET
1
TP54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C
MOLEX FPC 20pin 52745-2096
J24
DTC114EUA
B
MP2
1
B
TEST POINT
R453
23 GIO_DILC_CHG_CTL
0
CHG_CTL
R454
100K
23 GIO_DILC_DRV_VBUS1
VCC_3V3
R445
3
10K
VBUS1
2
Q4
DTC114EUA
1
DM365 EVM Technical Reference
R444
100K
23 GIO_DILC_VBUS_DET
SPECTRUM DIGITAL INCORPORATED
A
Title:
7 TV_OUT
Page Contents:
Size: B
DILC HOST CONNECTOR
DWG NO
4
3
2
Revision:
C
510842-0001
Date: Monday, April 13, 2009
5
A
DM365 Evaluation Module
Sheet
1
41 o f
53
Spectrum Digital, Inc
A-42
5
5
4
3
2
1
VCC_3V3
VCC_3V3
R415
10K
R414
10K
C38
U10
0.1uF
D
SEL_ENET_IO0
SEL_ENET_IO1
21 SEL_ENET_IO0
21 SEL_ENET_IO1
9
9
9
9
9
9
CPU.TXCLK
CPU.TXD0
CPU.TXD1
CPU.TXD2
CPU.TXD3
CPU.TX_EN
R47
360
9 CPU.MDC
1
56
55
VCC.1
17
S0
S1
S2
2
4
6
9
11
13
15
18
21
23
25
27
1A1
2A1
3A1
4A1
5A1
6A1
7A1
8A1
9A1
10A1
11A1
12A1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
54
52
50
47
45
43
41
39
36
34
32
30
3
5
7
10
12
14
16
20
22
24
26
28
1A2
2A2
3A2
4A2
5A2
6A2
7A2
8A2
9A2
10A2
11A2
12A2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
53
51
48
46
44
42
40
37
35
33
31
29
GND.1
GND.2
GND.3
GND.4
8
19
38
49
D
EPHY.TXCLK 43
EPHY.TXD0 43
EPHY.TXD1 43
EPHY.TXD2 43
EPHY.TXD3 43
EPHY.TX_EN 43
EPHY.MDC 43
EPHY.MDIO 43
9 CPU.MDIO
C
CPU_GPIO16
CPU_GPIO11
CPU_GPIO12
CPU_GPIO13
CPU_GPIO14
CPU_GPIO17
21
21
21
21
21
21
S2
0
0
0
0
1
1
1
1
CPU_GPIO1 21
CPU_GPIO2 21
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
A1
Z
B1
B2
Z
Z
Z
B1
B2
A2
Z
Z
Z
B1
B2
Z
B2
B1
FUNCTION
DISCONNECT
A1 TO B1
A1 TO B2
A2 TO B1
A2 TO B2
DISCONNECT
A1 TO B1 A2 TO B2
A1 TO B2 A2 TO B1
C
SN74CBTLV16212DGGR
VCC_3V3
C186
U37
0.1uF
SEL_ENET_IO0
SEL_ENET_IO1
S0
S1
S2
2
4
6
9
11
13
15
18
21
23
25
27
3
5
7
10
12
14
16
20
22
24
26
28
B
9 CPU.COL
9 CPU.CRS
9 CPU.RXD0
9 CPU.RXD1
9 CPU.RXD2
9 CPU.RXD3
9 CPU.RX_DV
9 CPU.RX_ER
9 CPU.RX_CLK
R236
A
360
A-43
VCC.1
17
1A1
2A1
3A1
4A1
5A1
6A1
7A1
8A1
9A1
10A1
11A1
12A1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
54
52
50
47
45
43
41
39
36
34
32
30
1A2
2A2
3A2
4A2
5A2
6A2
7A2
8A2
9A2
10A2
11A2
12A2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
53
51
48
46
44
42
40
37
35
33
31
29
GND.1
GND.2
GND.3
GND.4
8
19
38
49
B
EPHY.COL 43
EPHY.CRS 43
EPHY.RXD0 43
EPHY.RXD1 43
EPHY.RXD2 43
EPHY.RXD3 43
EPHY.RX_DV 43
EPHY.RX_ER 43
EPHY.RX_CLK 43
CPU_GPIO15 21
CPU_GPIO3 21
CPU_GPIO7 21
CPU_GPIO8 21
CPU_GPIO9 21
CPU_GPIO10 21
CPU_GPIO5 21
CPU_GPIO4 21
CPU_GPIO6 21
SPECTRUM DIGITAL INCORPORATED
Page Contents:
ETHERNET MUXES
Size: B
DWG NO
Date:
4
3
2
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
SN74CBTLV16212DGGR
5
A
DM365 Evaluation Module
Title:
1
42 o f
53
Spectrum Digital, Inc
1
56
55
4
3
PHY_1V8
2
1
VDD_1V8RX
VDD_3V3A
SILKSCREEN:
ETHERNET
VCC_3V3
+ C18
VDD_3V3A
4.7uF
C143
0.1uF
c402-25
C12
4.7uF
C1206-40X70
C140
0.1uF
c402-25
C10
4.7uF
C1206-40X70
C8
P2
0.1uF
42 EPHY.TX_EN
R202
NO-POP
R201
NO-POP
C
R215
10K
R216
NO-POP
R17
10K
R20
NO-POP
R14
10K
R21
NO-POP
R217
10K
R208
NO-POP
R16
10K
47
R3
49.9
12
11
10
9
EPHY.LED2
C20
4.7uF
C1206-40X70
Differential Pair
15
17
18
19
20
TX_CLK/REF_CLK
TXD0
TXD1
TXD2
TXD3
TX+
41
TX-
40
16
14
TX_EN
TX_ER
RX+
33
RX-
32
RJ45 HALO HFJ11-2450E-L21
LED2LED2+
LED1LED1+
7
8
NC1
GND
1
4
2
TXD+
TXD-CT
TXD-
3
5
6
RXD+
RXD-CT
RXD-
D
C3
1000pF 2kV
GND_E_ENET
GND_E_ENET
Differential Pair
FXSD/FXEN
34
NC1
NC2
42
43
REXT
37
21
22
6
5
4
3
9
11
LED0/TEST
COL/RMII
CRS/RMII_BTB
LED1/SPD100
RXD0/PHYAD4
RXD1/PHYAD3
LED2/DUPLEX
RXD2/PHYAD2
RXD3/PHYAD1 LED3/NWAYEN
RX_DV/CRSDV/PCS_LPBK
RX_ER/ISO
26
10
RX_CLK
R195
R15
EPHY.LED0
R2
49.9
SH1
SH2
MH1
MH2
31
38
C148
0.1uF
c402-25
VDDPLL
22
EPHY.TXCLK
EPHY.TXD0
EPHY.TXD1
EPHY.TXD2
EPHY.TXD3
VDDRX
VDDRCV
R209
42
42
42
42
42
VDDIO1
VDDIO2
U5
13
VDD_1V8PLL
7
24
D
C11
4.7uF
C1206-40X70
VDDC1
C139
0.1uF
c402-25
SH1
SH2
MH1
MH2
C149
0.1uF
c402-25
VCC_3V3
NO-POP
R4
49.9
NO-POP
R196
C
R5
49.9
VDD_3V3A
6.65K
C9
RN25
RPACK8-33
1
2
3
4
5
6
7
8
42 EPHY.COL
42 EPHY.CRS
42 EPHY.RXD0
42 EPHY.RXD1
42 EPHY.RXD2
42 EPHY.RXD3
42 EPHY.RX_DV
42 EPHY.RX_ER
16
15
14
13
12
11
10
9
PH YAD4
PH YAD3
PH YAD2
PH YAD1
R214
R224
10K
R223
10K
R220
10K
10
R222
10K
B
42 EPHY.RX_CLK
2
MDC
1
MDIO
INT#/PHYAD0
48
RESET#
30
PD#
DM365 EVM Technical Reference
R212
EPHY.LED0
330
EPHY.LED2
0.1uF
28
R193
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
R207
R153
R206
NO-POP
NO-POP
NO-POP
29
VCC_3V3
R211
XI
46
XO
45
10K
R156
NO-POP
B
C150
U6
.1uF
1
EN
2
GND
VCC
4
OUT
3 R210
R203
22
R154
NO-POP
R204
25MHz
GND1
GND2
GND3
GND4
GND5
GND6
GND7
8
12
23
35
36
39
44
VCC_3V3
330
27
VCC_3V3
25
42 EPHY.MDC
R194
R155
NO-POP
NO-POP
L4
NO-POP
BLM21PG221SN1D
KS8001L
L42
1.5K
BLM21PG221SN1D
R205
NO-POP
42 EPHY.MDIO
GND_E_ENET
EPHY.INTERRUPTn
VCC_3V3
VCC_3V3
L5
VDD_3V3A
BLM21PG221SN1D
SPECTRUM DIGITAL INCORPORATED
A
TP7
TP-30
A
PHY_1V8
R197
10K
R192
NO-POP
VDD_1V8PLL
L49
BLM21PG221SN1D
DM365 Evaluation Module
Title:
Page Contents:
ETHERNET PHY
Size: B
DWG NO
VDD_1V8RX
21 ENET_RESETn
L6
Date:
5
4
3
Revision:
C
510842-0001
BLM21PG221SN1D
2
Monday, April 13, 2009
Sheet
1
43 o f
53
Spectrum Digital, Inc
A-44
5
5
4
3
2
1
MSP430_3V3
MSP430_3V3
MSP430_3V3
C414
U50
R463
100
0
R471
20K
5
1
R470
R506
14 MSP430_PWCTR_OUT1
0
MP430_IO5
R472
10K
C415
TP63
D
0.1uF
4
3
0.1uF
VDD
6
CT
RESET
1
MR
GND
2
SENSE1
ALT_POWERUP_RESET
ALT_POWERUP_RESET 14
D
TPS3808G09DBVRG4
Reset Threhold 0.84 Volts
R464
220
1
TP62
VCC_5V
MSP430_3V3
U36
1
3
2
VIN
EN
VOUT
6
FB
NR
5
4
GND
MSP430_3V3
MSP430_3V3
R185
51K
TPS79301-DBV
TP71
TEST POINT
+
C121
10uF 6.3V
1
C126
0.1uF
R505
10k
SW22
C
A
A1
R187
30.1K
VCC_3V3
B
B1
C417
10pF
C418
10pF
C
3
2
PUSHBUTTON SW
R176
10K
4
1
Y4
32.768KHz
21 MSP430_INT
MSP430_3V3
MSP430_3V3
VCC_3V3
U2
R151
100
U1
R161
10K
TP61
TEST POINT
MP430_IO0
1
3
1
2
B
+
TSOP34840
C1
10uF 6.3V
TP60
TEST POINT
TP6
TEST POINT
TP55
TEST POINT
1
VCC.1
2
P1.0/TACLK/ACLK/A0+
3
P1.1/TA0/A0-/A4+
4
P1.2/TA1/A1+/A4-
1
MP430_IO1
5
P1.3/VREF/A1-
1
MP430_IO2
6
P1.4/SMCLK/A2+/TCK
1
MP430_IO5
7
P1.5/TA0/A2-/SCLK/TMS
R163
47K
VSS
14
XIN/P2.6/TA1
13
XOUT/P2.7
12
TEST/SBWTCK
11
RST/NMI/SBWTDIO
10
P1.7/A3-/SDI/SDA/TDO/TDI
9
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
8
HEADER 7X2
2
4
6
8
10
12
14
430_TDO/TDI
VCC_TOOL
VCC_MSP
XOUT
TEST/VPP
ACLK
ACLKEN
TCLKEN
TDO/TDI
TDI/VPP
TMS
TCK
GND
RST/NMI
NC1
430_TDO/TDI
1
3
5
7
9
11
13
R152
330
B
C117
0.001uF
J3
SPY-BY-WIRE INTERFACE
MSP430F2013IPW
22 MP430_IO2
9,20,28,32,34,35,36,37,39,40 I2C_SCLK
R507
0
9,20,28,32,34,35,36,37,39,40 I2C_DATA
R512
0
SPECTRUM DIGITAL INCORPORATED
A
A-45
Page Contents:
MSP430 & IR INTERFACE
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
44 o f
53
Spectrum Digital, Inc
22 MP430_IO1
R419
4
3
SW6
C386
100pF
A
A1
SW7
B
B1
SW8
A
A1
PUSHBUTTON SW
B
B1
R430
A
A1
A
A1
D
SW13
A
A1
PUSHBUTTON SW
B
B1
A
A1
PUSHBUTTON SW
R416
1.5K
B
B1
PUSHBUTTON SW
R431
1.5K
R429
1.5K
0
C
SW14
C409
100pF
A
A1
SW15
B
B1
A
A1
PUSHBUTTON SW
SW16
B
B1
SW17
A
A1
PUSHBUTTON SW
R428
1.5K
R449
R418
1.5K
SW12
B
B1
R417
1.5K
3 KEY_B3
B
B1
PUSHBUTTON SW
R403
1.5K
SW11
B
B1
PUSHBUTTON SW
R437
A
A1
PUSHBUTTON SW
R405
1.5K
SW10
3 KEY_B2
B
B1
0
C405
100pF
C
1
SW9
A
A1
PUSHBUTTON SW
R407
1.5K
D
3 KEY_B1
2
0
B
B1
A
A1
PUSHBUTTON SW
R439
1.5K
B
B1
PUSHBUTTON SW
R438
1.5K
R436
1.5K
0
SW18
C412
100pF
B
A
A1
SW19
B
B1
A
A1
PUSHBUTTON SW
SW20
B
B1
SW21
A
A1
PUSHBUTTON SW
B
B1
A
A1
PUSHBUTTON SW
B
B1
B
PUSHBUTTON SW
VCC_3V3
R443
1.5K
R442
1.5K
R441
1.5K
R448
1.5K
R440
15K
VCC_3V3
KEY_A3 3
DM365 EVM Technical Reference
R410
15K
C411
100pF
VCC_3V3
KEY_A2 3
R404
15K
C379
100pF
VCC_3V3
KEY_A1 3
R406
15K
A
SPECTRUM DIGITAL INCORPORATED
C377
100pF
KEY_A0 3
C378
100pF
Page Contents:
SWITCHES
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
45 o f
53
Spectrum Digital, Inc
A-46
5
3 KEY_B0
5
4
3
2
1
VCC_3V3
D
D
R388
330
R387
330
R386
330
R385
330
R384
330
R383
330
R382
330
R381
330
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
LED
LED
LED
LED
LED
LED
LED
LED
C
C
23
LED0
23
LED1
23
LED2
23
LED3
22
LED4
22
LED5
22
LED6
22
LED7
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
B
B
R213
10K
SW3
A
A1
B
B1
33
R221
R219
0
PB_SWITCH 21
PUSHBUTTON SW
C154
A
SPECTRUM DIGITAL INCORPORATED
1uF
A-47
Page Contents:
LEDS
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
46 o f
53
Spectrum Digital, Inc
VCC_3V3
4
3
2
1
1
Vvo_bt = 1 + ( R33/R29_R28) *1.25
BHT1
BA2032SM
2
D
C32
D
R28
75K
27pF
VCC_VR0
R479
R33
392K
R29
0
130K
R22
33
R24
C419
2.2uF
499
VCC_5V
VIN_MAIN
L16
BLM41P750SPT
L13
1
2
3
4
4.7uH
C25
2.2uF
VR0
VOUT
VO1R8
VO1R2
12
11
10
9
V_CTRL
PWMON
CS
XRESET
C
VO_BT
SW
PGND
AGND
D2
MBR0530T1
U9
PWRPAD
VBAT
FB
FBG
VBK
17
16
15
14
13
1V8_BB_UP
C182
2.2uF
TPS65510_PGND
5
6
7
8
C183
2.2uF
TPS65510_AGND
1V2_BB_UP
C
C26
2.2uF
R25
10K
R26
10K
TPS65510
TP10
4
3
1
C24
2.2uF
2
ON
SW23
DIP_SWITCH_2
1
R30
0
1
2
TEST POINT
TPS65510_XRESET 14
TPS65510_CS 14
B
B
R525
100K
DM365 EVM Technical Reference
PL1
1
R526
100K
PL2
2
PLANE LINK
TPS65510_AGND
1
2
PLANE LINK
TPS65510_PGND
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
POWER SUPPLY TPS65510
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
47 o f
53
Spectrum Digital, Inc
A-48
5
5
4
3
2
1
VCC1_IN
NO-POP
VCC2_IN
VOUT5_TPS65530
D
R55
21,51 SEL_EXTRA_3
L15
R49
+
412K
VOUT2_TPS65530
D
GND_PCTL
G
BSS138
GND_PCTL
10K
R54
S
R249
21,51 CPU_VSEL1
C42
120pF
100K
R252
825K
R254
180K
VOUT3_TPS65530
+
R229
C35
22uF
475K
L11
4.7uH
C179
VCC_1V2 VOUT8_TPS65530
L57
NO-POP
R234
221K
GND_PCTL
3.3uH
L18
BLM41P750SPT
BLM41P750SPT
VOUT4_TPS65530
3
BLM41P750SPT
4
Q1A
VEC2611
22
HEADER 3
R40
2
0
25
26
27
28
29
30
31
32
33
34
35
36
C
1
VCC_3V3
VOUT8_TPS65530
C174
NO-POP
R38
C187
C175
+
0
1uF
22pF
R37
392K
R36
200K
C29
33uF
R35
21 CPLD_B-ADJ
VCC7_IN
R237
10
10K
L10
PGND3
SW8LD
LL8
SW8HD
PS
FB8
FBG7/8
B-ADJ
FBC
CIN
FBV
SW7
VCC2
REF
AGND
S/S
EN7
XSLEEP
ENAFE
FB4
VOUT4
SW4I
PGND4
SW4S
12
11
10
9
8
7
6
5
4
3
2
1
C214
2.2uF
C56
BL_6V8_RTN
B
BLM41P750SPT
C
GND_PCTL
EN7
R256
R261
82K
+
L19
21
ENAFE 21
332K
R60
10K
R58
100K
R59
10K
C58
47uF
4.7uH
GND_PCTL GND_PCTL
GND_PCTL GND_PCTL
15uH
VOUT4_TPS65530
C155
10uF
1
D3
BL_6V8
TP65
TEST POINT
CPU_VCC_3V3
L63
14,51,52 PWCTR_OUT1
0.1uF
+
TP64
TEST POINT
VOUT2_TPS65530
BLM41P750SPT
PGND5/7
SW5
SWOUT
VCC5
FB5
VCC6
SW6
FB6
S/S56
EN56
SEQ56
VCC4
PWR_PAD
C22
22uF
37
38
39
40
41
42
43
44
45
46
47
48
49
+
CPU_VCC_1V8
L54
U14
TPS65530/1RSL
SW3S
VCC3
FB3
FB1
PGND1
SW1
VCC1
FB2
VOUT2
SW2I
PGND2
SW2S
R226
8
7
L8
VOUT3_TPS65530
0
24
23
22
21
20
19
18
17
16
15
14
13
R39
6
5
Q1B
VEC2611
4.7uH
AFE_3V3
L65
C30
22uF
J27
+
MTR_3V3
L51
+
VCC5_IN
C23
22uF
D
BLM41P750SPT
VOUT1_TPS65530
GND_PCTL
1
2
3
VCC_CCD_N7V5
L64
+
C45
47uF
GND_PCTL
VOUT6_TPS65530
C57
22uF
C37
10uF
VCC3_IN
R263
NO-POP
BLM41P750SPT
+
C43
22uF
+
R48
100K
Q2
D
4.7uH
S
R264
NO-POP
VCC_CCD15V5
L14
VOUT1_TPS65530
Q3
NO-POP/BSS138
NO-POP G
R260
MBR0530T1
R34
680K
R230
100K
C177
SEQ56 21
EN56 21
0.1uF
VCC_5V
1
C159
10uF
VCC5_IN
C176
NO-POP
L61
B
VCC1_IN
+
R251
10K
BLM41P750SPT
R253
10K
VCC2_IN
L66
BLM41P750SPT
L56
BLM41P750SPT
VOUT5_TPS65530
PL3
VCC3_IN
+
C39
22uF
D4
MBR0530T1
L12
15uH
1
VCC4_IN
+
C162
22uF
GND_PCTL
+
R232
560K
C178
3.3uF
L67
R52
VCC6_IN
R51
82.5K
A
GND_PCTL
BLM41P750SPT
VCC5_IN
13.7K
L60
BLM41P750SPT
VOUT6_TPS65530
VCC6_IN
SPECTRUM DIGITAL INCORPORATED
VCC4_IN
R231
40.2K
+
GND_PCTL
2
PLANE LINK
L17
15uH
D5
MBR0530T1
L62
BLM41P750SPT
A
DM365 Evaluation Module
Title:
VCC7_IN
C41
22uF
+
C50
22uF
A-49
GND_PCTL
C202
0.1uF
+
C46
1uF
C217
22uF
L7
Page Contents:
POWER SUPPLY TPS65550
Size: B
DWG NO
BLM41P750SPT
Revision:
C
510842-0001
GND_PCTL
Date:
5
4
3
2
Sheet
Monday, April 13, 2009
1
48 o f
53
Spectrum Digital, Inc
GND_PCTL
4
3
2
1
21 ENABLE_LCD_15V
D
D
R143
10K
VCC_5V
C114
10uF
R144
0
2
VIN
6
EN
7
FSW
3
SS
4
GND
SW
L35
10
4.7uH
15V_LCD
L
1
OUT
9
FB
5
PGND
8
11
C408
47nF
TPS61080
PWRPAD
+
U34
R432
+
100
R139
560K 1%
R1
R1 = R2( ( VOUT/1.229) - 1 )
R2
C110
10uF
C111
33pF
R427
49.9K 1%
R1 = 49.9k( ( 15/1.229) - 1 )
R1 = 49.9k * (
C
R1 = 559K
11.205 )
C
-> 560K
LCD_3V3
B
B
VCC_5V
U31
TPS74701
L33
L32
1
2
IN1
IN2
4
BIAS
BLM41P750SPT
C103
2.2uF
10
9
PG
3
SS
FB
8
5
EN
GND
6
C376
5.6pF
10uF
BLM41P750SPT
R121
4.99K
PP1
7
C104
R127
15.8K
VOUT = 0.8 * ( 1+R401/R402 )
11
DM365 EVM Technical Reference
C375
0.001uF
VOUT2
VOUT1
23 ENABLE_LCD_3V3
R402
10K
SPECTRUM DIGITAL INCORPORATED
A
Page Contents:
POWER SUPPLY
Size: B
DWG NO
Date:
5
4
3
2
A
DM365 Evaluation Module
Title:
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
49 o f
53
Spectrum Digital, Inc
A-50
5
5
4
3
2
CPU_VCC_1V8
1
L87
1
VCC_1V8
L86
2
1
NO-POP
2
BLM41P750SPT
VCC_CPLD_1V8
L85
PLACE L87 BY DM365 AREA
1
D
2
D
BLM41P750SPT
VCC_DEC_1V8
TP58
L83
BLM41P750SPT
TP-60
C99
10uF
R119
15.8K
VCC_5V
C374
0.1uF
U30
C105
10uF
5
6
1IN_1
1IN_2
4
1EN
1RESET
VCC_5V
C
C106
10uF
3
1GND
11
12
2IN_1
2IN_2
10
1OUT_1
1OUT_2
1FB/SENSE
23
24
25
2RESET
22
2OUT_1
2OUT_2
2SENSE
17
18
19
NC.15
NC.16
NC.20
NC.21
NC.26
NC.27
15
16
20
21
26
27
R490
10K
TP56
TP-60
1
2
7
8
13
14
NC.1
NC.2
NC.7
NC.8
NC.13
NC.14
THERMAL_PAD
VCC_5V
2GND
R119 = ( 1.8/1.1834 -1) X R118
R118
30.1K
R119 = 0.52 X R118
TP59
TP-60
VCC_DEC_3V3
C
L84
2EN
9
R119 = ( VOUT/VREF-1) X R118
28
BLM41P750SPT
C100
10uF
C373
0.1uF
29
TPS767D301
D
CPU_VCC_3V3
R489
Q7
G
R409
NO-POP
S
B
1K
BSS138
B
R487
10K
VCC_5V
D
CPU_VCC_3V3
R491
A
R408
NO-POP
Q8
SPECTRUM DIGITAL INCORPORATED
A
1K
S
G
BSS138
DM365 Evaluation Module
Page Contents:
DECODER 3V3,1V8 POWER
Size: B
DWG NO
R488
10K
A-51
Title:
Date:
5
4
3
2
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
50 o f
53
Spectrum Digital, Inc
R492
10K
TP57
TP-60
4
3
2
1
PLACE L89 BY DM365
VCC_1V2
D
VCC_5V
U41
D
TPS74701
L88
L89
1
2
BLM41P750SPT
C422
2.2uF
IN1
IN2
VOUT2
VOUT1
10
9
4
BIAS
PG
3
7
SS
FB
8
5
EN
GND
6
C424
5.6pF
10uF
NO-POP
PP1
C423
0.001uF
C425
R493
2499 1%
VOUT = 0.8 * ( 1+R401/R402 )
11
14,48,52 PWCTR_OUT1
R494
10K
C
C
R495
4.99K
NO-POP
D
R500
21,48 SEL_EXTRA_3
R499
Q11
NO-POP/BSS138
G
NO-POP
S
R501
NO-POP
13.5K 1%
D
R496
Q10
G
B
R503
10K
S
21,48 CPU_VSEL1
BSS138
B
R498
NO-POP
DM365 EVM Technical Reference
SPECTRUM DIGITAL INCORPORATED
A
Title:
DM365 Evaluation Module
Page Contents:
ALTERNATE CPU POWER
Size: B
DWG NO
Date:
5
4
3
2
A
Revision:
C
510842-0001
Monday, April 13, 2009
Sheet
1
51 o f
53
Spectrum Digital, Inc
A-52
5
5
4
3
2
TP67
1
SPARE
TP-60
D
C431
10uF
R508
15.8K
VCC_5V
D
C427
0.1uF
U42
C428
10uF
5
6
1IN_1
1IN_2
4
1EN
VCC_5V
C
TP69
TP-60
28
1OUT_1
1OUT_2
1FB/SENSE
23
24
25
3
1GND
11
12
2IN_1
2IN_2
2RESET
22
10
2EN
2OUT_1
2OUT_2
2SENSE
17
18
19
NC.15
NC.16
NC.20
NC.21
NC.26
NC.27
15
16
20
21
26
27
9
2GND
1
2
7
8
13
14
NC.1
NC.2
NC.7
NC.8
NC.13
NC.14
THERMAL_PAD
C429
10uF
1RESET
R119 = ( VOUT/VREF-1) X R118
R119 = ( 1.8/1.1834 -1) X R118
R509
30.1K
TP68
TP-60
R119 = 0.52 X R118
VCC_3V3
C430
10uF
C426
0.1uF
L91
BLM41P750SPT
L92
BLM41P750SPT
C
29
TPS767D301
R510
10K
VCC_5V
R504
10K
B
B
R502
Q9
R511
NO-POP
G
1K
S
14,48,51 PWCTR_OUT1
BSS138
R497
10K
SPECTRUM DIGITAL INCORPORATED
A
A-53
Title:
DM365 Evaluation Module
Page Contents:
ALTERNATE 3V3 POWER
Size: B
DWG NO
Date:
5
4
3
2
A
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
52 o f
53
Spectrum Digital, Inc
D
TP70
TP-60
4
D
2
1
TP5
TP-30
F1
1
SILKSCREEN:
5V IN
3
2
D
VCC_5V
F_4.0A
J7
CENTER
SHUNT
SLEEVE
NO-POP
R199
R189
220
2.5 MM JACK
RASM712
D1
SMCJ6A
+
C15
47uF
DS1
GREEN
C
C
B
B
DM365 EVM Technical Reference
TP40
TP-60
TP1
TP-60
TP2
TP-60
TP52
TP-60
TP51 TP41
TP-60 TP-60
GND Test Points
SPECTRUM DIGITAL INCORPORATED
A
Title:
DM365 Evaluation Module
Page Contents:
POWER INPUT
Size: B
DWG NO
Date:
5
4
3
2
A
Revision:
C
510842-0001
Sheet
Monday, April 13, 2009
1
53 o f
53
Spectrum Digital, Inc
A-54
5
Appendix B
Mechanical Information
This appendix contains the mechanical information about the DM365
EVM produced by Spectrum Digital.
B-1
THIS DRAWING IS NOT TO SCALE
Spectrum Digital, Inc
B-2
DM365 EVM Technical Reference
Printed in U.S.A., April 2009
510845-0001 Rev A
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement