Modicon Ladder Logic Block Library User Guide Volume 4

Modicon Ladder Logic Block Library User Guide Volume 4
Modicon
Ladder Logic Block
Library User Guide
Volume 4
840 USE 101 00
043505766.81
4/2006
This document provided by Barr-Thorp Electric Co., Inc. 800-473-9123
www.barr-thorp.com
ii
This document provided by Barr-Thorp Electric Co., Inc. 800-473-9123
www.barr-thorp.com
Table of Contents
Safety Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii
About the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
Part I General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 1
Ladder Logic Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Segments and Networks in Ladder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
How a PLC Solves Ladder Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ladder Logic Elements and Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2
Memory Allocation in a PLC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State RAM Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State RAM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The I/O Map Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
16
18
20
22
26
Ladder Logic Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Translating Ladder Logic Elements in the System Memory Database . . . . . . . . 28
Translating DX Instructions in the System Memory Database . . . . . . . . . . . . . . 30
Opcode Defaults for Loadables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter Assignment of Instuctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Chapter 5
Instruction Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ASCII Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Counters and Timers Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Fast I/O Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Loadable DX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Matrix Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Skips/Specials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Coils, Contacts and Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 6
Equation Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Equation Network Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Mathematical Equations in Equation Networks . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Mathematical Operations in Equation Networks . . . . . . . . . . . . . . . . . . . . . . . . . 59
Mathematical Functions in Equation Networks . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Data Conversions in an Equation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Roundoff Differences in PLCs without a Math Coprocessor . . . . . . . . . . . . . . . . 68
Benchmark Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 7
Closed Loop Control / Analog Values . . . . . . . . . . . . . . . . . . . 71
Closed Loop Control / Analog Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PCFL Subfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
A PID Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PID2 Level Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Chapter 8
Formatting Messages for ASCII READ/WRIT Operations . . . 83
Formatting Messages for ASCII READ/WRIT Operations . . . . . . . . . . . . . . . . . . 84
Format Specifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Special Set-up Considerations for Control/Monitor
Signals Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Chapter 9
Coils, Contacts and Interconnects. . . . . . . . . . . . . . . . . . . . . . 91
Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Contacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Interconnects (Shorts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 10
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Chapter 11
Subroutine Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Chapter 12
Installation of DX Loadables . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Part II Instruction Descriptions (A to D) . . . . . . . . . . . . . . . . . 103
Chapter 13
1X3X - Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Short Description: 1X3X - Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Representation: 1X3X - Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Chapter 14
AD16: Ad 16 Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Representation: AD16 - 16-bit Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 15
ADD: Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Representation: ADD - Single Precision Add . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Chapter 16
AND: Logical And . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Representation: AND - Logical And . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Chapter 17
BCD: Binary to Binary Code . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Representation: BCD - Binary Coded Decimal Conversion . . . . . . . . . . . . . . . 125
Chapter 18
BLKM: Block Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Representation: BLKM - Block Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 19
BLKT: Block to Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Representation: BLKT - Block-to-Table Move. . . . . . . . . . . . . . . . . . . . . . . . . . 133
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Chapter 20
BMDI: Block Move with Interrupts Disabled . . . . . . . . . . . . . 135
Short Description: BMDI - Block Move Interrupts Disabled. . . . . . . . . . . . . . . . 136
Representation: BMDI - Block Move Interrupts Disabled . . . . . . . . . . . . . . . . . 137
Chapter 21
BROT: Bit Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Representation: BROT - Bit Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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Chapter 22
CALL: Activate Immediate or Deferred DX Function . . . . . . 143
Short Description: CALL - Activate Immediate or Deferred DX Function. . . . . . 144
Representation: CALL - Activate Immediate DX Function . . . . . . . . . . . . . . . . . 145
Representation: CALL - Activate Deferred DX Function . . . . . . . . . . . . . . . . . . 148
Chapter 23
CANT - Interpret Coils, Contacts, Timers, Counters,
and the SUB Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Short Description: CANT - Interpret Coils, Contacts, Timers,
Counters, and the SUB Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Representation: CANT - Interpret Coils, Contacts, Timers,
Counters, and the SUB Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Parameter Description: CANT - Interpret Coils, Contacts, Timers,
Counters, and the SUB Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Chapter 24
CHS: Configure Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . 157
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Representation: CHS - Configure Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . 159
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Chapter 25
CKSM: Check Sum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Representation: CKSM - Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Chapter 26
CMPR: Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Representation: CMPR - Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Chapter 27
Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Short Description: Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
General Usage Guidelines: Coils. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 28
COMM - ASCII Communications Function . . . . . . . . . . . . . . 175
Short Description: COMM - ASCII Communications Block . . . . . . . . . . . . . . . . 176
Representation: COMM - ASCII Communications Function . . . . . . . . . . . . . . . 177
Chapter 29
COMP: Complement a Matrix . . . . . . . . . . . . . . . . . . . . . . . . . 179
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Representation: COMP - Logical Compliment . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Chapter 30
Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Short Description: Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Representation: Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
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Chapter 31
CONV - Convert Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Short Description: CONV - Convert Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Representation: CONV - Convert Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Chapter 32
CTIF - Counter, Timer, and Interrupt Function. . . . . . . . . . . . 193
Short Description: CTIF - Counter, Timer, and Interrupt Function . . . . . . . . . . 194
Representation: CTIF - Counter, Timer, Interrupt Function. . . . . . . . . . . . . . . . 195
Parameter Description: CTIF - Register Usage Table (Top Node) . . . . . . . . . . 196
Chapter 33
DCTR: Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Representation: DCTR - Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Chapter 34
DIOH: Distributed I/O Health . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Representation: DIOH - Distributed I/O Health . . . . . . . . . . . . . . . . . . . . . . . . . 209
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Chapter 35
DISA - Disabled Discrete Monitor. . . . . . . . . . . . . . . . . . . . . . 213
Short Description: DISA - Disabled Discrete Monitor . . . . . . . . . . . . . . . . . . . . 214
Representation: DISA - Disabled Discrete Monitor . . . . . . . . . . . . . . . . . . . . . . 215
Chapter 36
DIV: Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Representation: DIV - Single Precision Division . . . . . . . . . . . . . . . . . . . . . . . . 219
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 37
DLOG: Data Logging for PCMCIA Read/Write Support. . . . . 223
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: DLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Time Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 38
224
225
226
228
DMTH - Double Precision Math . . . . . . . . . . . . . . . . . . . . . . . . 229
Short Description: DMTH - Double Precision Math Addition, Subtraction, Multiplication, and Division. . . . . . . . . . . . . . . . . . . . . . . 230
Representation: DMTH - Double Precision Math Addition, Subtraction, Multiplication, and Division. . . . . . . . . . . . . . . . . . . . . . . 231
Chapter 39
DRUM: DRUM Sequencer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Representation: DRUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
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Chapter 40
DV16: Divide 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Representation: DV16 - 16-bit Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Part III Instruction Descriptions (E) . . . . . . . . . . . . . . . . . . . . . . 249
Chapter 41
EARS - Event/Alarm Recording System . . . . . . . . . . . . . . . . 251
Short Description: EARS - Event/Alarm Recording System . . . . . . . . . . . . . . . 252
Representation: EARS - Event/Alarm Recording System . . . . . . . . . . . . . . . . . 253
Parameter Description: EARS - Event/Alarm Recording System . . . . . . . . . . . 255
Chapter 42
EMTH: Extended Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Representation: EMTH - Extended Math Functions . . . . . . . . . . . . . . . . . . . . . 261
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Floating Point EMTH Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Chapter 43
EMTH-ADDDP: Double Precision Addition . . . . . . . . . . . . . . 265
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Representation: EMTH - ADDDP - Double Precision Math - Addition . . . . . . . . 267
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Chapter 44
EMTH-ADDFP: Floating Point Addition . . . . . . . . . . . . . . . . . 271
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Representation: EMTH - ADDFP - Floating Point Math - Addition. . . . . . . . . . . 273
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Chapter 45
EMTH-ADDIF: Integer + Floating Point Addition. . . . . . . . . . 275
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Representation: EMTH - ADDIF - Integer + Floating Point Addition . . . . . . . . . 277
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Chapter 46
EMTH-ANLOG: Base 10 Antilogarithm . . . . . . . . . . . . . . . . . 279
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Representation: EMTH - ANLOG - integer Base 10 Antilogarithm . . . . . . . . . . 281
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Chapter 47
EMTH-ARCOS: Floating Point Arc Cosine
of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Representation: EMTH - ARCOS - Floating Point Math Arc Cosine of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
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Chapter 48
EMTH-ARSIN: Floating Point
Arcsine of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . 291
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Representation: EMTH - ARSIN Arcsine of an Angle (in Radians). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Chapter 49
EMTH-ARTAN: Floating Point Arc
Tangent of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . 295
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Representation: Floating Point Math - Arc Tangent
of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Chapter 50
EMTH-CHSIN: Changing the Sign of a
Floating Point Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Representation: EMTH - CHSIN - Change the Sign of a
Floating Point Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Chapter 51
EMTH-CMPFP: Floating Point Comparison . . . . . . . . . . . . . . 307
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Representation: EMTH - CMFPF - Floating Point Math Comparison . . . . . . . . 309
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Chapter 52
EMTH-CMPIF: Integer-Floating Point Comparison . . . . . . . . 313
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Representation: EMTH - CMPIF - Floating Point Math Integer/Floating Point Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Chapter 53
EMTH-CNVDR: Floating Point Conversion
of Degrees to Radians . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Representation: EMTH - CNVDR - Conversion of
Degrees to Radians. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Chapter 54
EMTH-CNVFI: Floating Point to Integer Conversion . . . . . . . 325
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: EMTH - CNVFI - Floating Point to
Integer Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Runtime Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
326
327
329
330
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Chapter 55
EMTH-CNVIF: Integer-to-Floating Point Conversion . . . . . . 331
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Representation: EMTH - CNVIF - Integer to Floating Point Conversion . . . . . . 333
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Runtime Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Chapter 56
EMTH-CNVRD: Floating Point Conversion
of Radians to Degrees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Representation: EMTH - CNVRD - Conversion of Radians to Degrees . . . . . . 339
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Chapter 57
EMTH-COS: Floating Point Cosine of
an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Representation: EMTH - COS - Cosine of an Angle (in Radians) . . . . . . . . . . . 345
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Chapter 58
EMTH-DIVDP: Double Precision Division . . . . . . . . . . . . . . . 347
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Representation: EMTH - DIVDP - Double Precision Math - Division . . . . . . . . . 349
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Runtime Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Chapter 59
EMTH-DIVFI: Floating Point Divided by Integer . . . . . . . . . . 353
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Representation: EMTH - DIVFI - Floating Point Divided by Integer. . . . . . . . . . 355
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Chapter 60
EMTH-DIVFP: Floating Point Division . . . . . . . . . . . . . . . . . . 357
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Representation: EMTH - DIVFP - Floating Point Division . . . . . . . . . . . . . . . . . 359
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Chapter 61
EMTH-DIVIF: Integer Divided by Floating Point . . . . . . . . . . 361
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Representation: EMTH - DIVIF - Integer Divided by Floating Point. . . . . . . . . . 363
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Chapter 62
EMTH-ERLOG: Floating Point Error Report Log. . . . . . . . . . 365
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Representation: EMTH - ERLOG - Floating Point Math Error Report Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
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Chapter 63
EMTH-EXP: Floating Point Exponential Function . . . . . . . . . 371
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Representation: EMTH - EXP - Floating Point Math Exponential Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Chapter 64
EMTH-LNFP: Floating Point Natural Logarithm. . . . . . . . . . . 377
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Representation: EMTH - LNFP - Natural Logarithm . . . . . . . . . . . . . . . . . . . . . 379
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Chapter 65
EMTH-LOG: Base 10 Logarithm . . . . . . . . . . . . . . . . . . . . . . . 383
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Representation: EMTH - LOG - Integer Math - Base 10 Logarithm . . . . . . . . . 385
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Chapter 66
EMTH-LOGFP: Floating Point Common Logarithm. . . . . . . . 389
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Representation: EMTH - LOGFP - Common Logarithm . . . . . . . . . . . . . . . . . . 391
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Chapter 67
EMTH-MULDP: Double Precision Multiplication . . . . . . . . . . 395
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Representation: EMTH - MULDP Double Precision Math - Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Chapter 68
EMTH-MULFP: Floating Point Multiplication . . . . . . . . . . . . . 401
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Representation: EMTH - MULFP - Floating Point - Multiplication . . . . . . . . . . . 403
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Chapter 69
EMTH-MULIF: Integer x Floating Point Multiplication . . . . . . 405
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Representation: EMTH - MULIF - Integer Multiplied by Floating Point . . . . . . . 407
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Chapter 70
EMTH-PI: Load the Floating Point Value of "Pi" . . . . . . . . . . 411
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Representation: EMTH - PI - Floating Point Math Load the Floating Point Value of PI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
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Chapter 71
EMTH-POW: Raising a Floating Point
Number to an Integer Power . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Representation: EMTH - POW - Raising a Floating
Point Number to an Integer Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Chapter 72
EMTH-SINE: Floating Point Sine
of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Representation: EMTH - SINE - Floating Point Math Sine of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Chapter 73
EMTH-SQRFP: Floating Point Square Root. . . . . . . . . . . . . . 429
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Representation: EMTH - SQRFP - Square Root . . . . . . . . . . . . . . . . . . . . . . . . 431
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Chapter 74
EMTH-SQRT: Floating Point Square Root . . . . . . . . . . . . . . . 435
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Representation: EMTH - SQRT - Square Root . . . . . . . . . . . . . . . . . . . . . . . . . 437
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Chapter 75
EMTH-SQRTP: Process Square Root. . . . . . . . . . . . . . . . . . . 441
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Representation: EMTH - SQRTP - Double Precision Math Process Square Root. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Chapter 76
EMTH-SUBDP: Double Precision Subtraction . . . . . . . . . . . 447
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Representation: EMTH - SUBDP - Double Precision Math - Subtraction . . . . . 449
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Chapter 77
EMTH-SUBFI: Floating Point - Integer Subtraction . . . . . . . 453
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Representation: EMTH - SUBFI - Floating Point minus Integer. . . . . . . . . . . . . 455
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Chapter 78
EMTH-SUBFP: Floating Point Subtraction . . . . . . . . . . . . . . 457
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Representation: EMTH - SUBFP - Floating Point - Subtraction. . . . . . . . . . . . . 459
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
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Chapter 79
EMTH-SUBIF: Integer - Floating Point Subtraction . . . . . . . . 461
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Representation: EMTH - SUBIF - Integer minus Floating Point . . . . . . . . . . . . 463
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Chapter 80
EMTH-TAN: Floating Point
Tangent of an Angle (in Radians) . . . . . . . . . . . . . . . . . . . . . . 465
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Representation: EMTH - TAN - Tangent of an Angle (in Radians) . . . . . . . . . . 467
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Chapter 81
ESI: Support of the ESI Module. . . . . . . . . . . . . . . . . . . . . . . . 469
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ ASCII Message (Subfunction 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE ASCII Message (Subfunction 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GET DATA (Subfunction 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PUT DATA (Subfunction 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABORT (Middle Input ON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 82
470
471
472
475
479
480
482
486
487
EUCA: Engineering Unit Conversion and Alarms . . . . . . . . . 489
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: EUCA - Engineering Unit and Alarm. . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
490
491
492
494
Part IV Instruction Descriptions (F to N) . . . . . . . . . . . . . . . . . 501
Chapter 83
FIN: First In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Representation: FIN - First in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Chapter 84
FOUT: First Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Representation: FOUT - First Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Chapter 85
FTOI: Floating Point to Integer . . . . . . . . . . . . . . . . . . . . . . . . 513
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Representation: FTOI - Floating Point to Integer Conversion . . . . . . . . . . . . . . 515
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Chapter 86
GD92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . 517
Short Description: GD92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . 518
Representation: GD92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . 519
Parameter Description - Inputs: GD92 - Gas Flow Function Block . . . . . . . . . . 521
Parameter Description - Outputs: GD92 - Gas Flow Function Block . . . . . . . . . 528
Parameter Description - Optional Outputs: GD92 Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Chapter 87
GFNX AGA#3 ‘85 and NX19 ‘68 Gas Flow Function Block. . 531
Short Description: GFNX - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . 532
Representation: GFNX - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . 533
Parameter Description - Inputs: GFNX - Gas Flow Function Block . . . . . . . . . . 535
Parameter Description - Outputs: GFNX - Gas Flow Function Block . . . . . . . . 542
Parameter Description - Optional Outputs: GFNX Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Chapter 88
GG92 AGA #3 1992 Gross Method
Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Short Description: GG92 - Gas Flow Function Block. . . . . . . . . . . . . . . . . . . . . 546
Representation: GG92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . 547
Parameter Description - Inputs: GG92 - Gas Flow Function Block . . . . . . . . . . 549
Parameter Description - Outputs: GG92 - Gas Flow Function Block. . . . . . . . . 555
Parameter Description - Optional Outputs: GG92 - Gas Flow Function Block . 556
Chapter 89
GM92 AGA #3 and #8 1992 Detail Method
Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Short Description: GM92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . 558
Representation: GM92 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . . 559
Parameter Description - Inputs: GM92 - Gas Flow Function Block . . . . . . . . . . 561
Parameter Description - Outputs: GM92 - Gas Flow Function Block. . . . . . . . . 568
Parameter Description - Optional Outputs: GM92 - Gas Flow Function Block . 569
Chapter 90
G392 AGA #3 1992 Gas Flow Function Block . . . . . . . . . . . . 571
Short Description: G392 - Gas Flow Function Block . . . . . . . . . . . . . . . . . . . . . 572
Representation: G392 - Gas Flow Function Block. . . . . . . . . . . . . . . . . . . . . . . 573
Parameter Description - Inputs: G392 - Gas Flow Function Block . . . . . . . . . . 575
Parameter Description - Outputs: G392 - Gas Flow Function Block . . . . . . . . . 580
Parameter Description - Optional Outputs: G392 - Gas Flow Function Block . . 581
Chapter 91
HLTH: History and Status Matrices . . . . . . . . . . . . . . . . . . . . 583
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Representation: HLTH - System Health. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Parameter Description Top Node (History Matrix) . . . . . . . . . . . . . . . . . . . . . . . 587
Parameter Description Middle Node (Status Matrix) . . . . . . . . . . . . . . . . . . . . . 592
Parameter Description Bottom Node (Length). . . . . . . . . . . . . . . . . . . . . . . . . . 596
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Chapter 92
HSBY - Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Short Description: HSBY - Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: HSBY - Hot Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description Top Node: HSBY - Hot Standby . . . . . . . . . . . . . . . . . .
Parameter Description Middle Node: HSBY - Hot Standby. . . . . . . . . . . . . . . .
Chapter 93
598
599
601
602
IBKR: Indirect Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Representation: IBKR - Indirect Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Chapter 94
IBKW: Indirect Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Representation: IBKW - Indirect Block Write. . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Chapter 95
ICMP: Input Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: ICMP - Input Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cascaded DRUM/ICMP Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 96
612
613
614
616
ID: Interrupt Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Short Description: ID - Interrupt Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Representation: ID - Interrupt Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Parameter Description: ID - Interrupt Disable . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Chapter 97
IE: Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Short Description: IE - Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Representation: IE - Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Parameter Description: IE - Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Chapter 98
IMIO: Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Short Description: IMIO - Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: IMIO - Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description: IMIO - Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Time Error Handling: IMIO - Immediate I/O . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 99
626
627
628
630
IMOD: Interrupt Module Instruction . . . . . . . . . . . . . . . . . . . . 631
Short Description: IMOD - Interrupt Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Representation: IMOD - Interrupt Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Parameter Description: IMOD - Interrupt Module . . . . . . . . . . . . . . . . . . . . . . . 635
Chapter 100
ITMR: Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Short Description: ITMR - Interval Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . 640
Representation: ITMR - Interval Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 641
Parameter Description: ITMR - Interval Timer Interrupt . . . . . . . . . . . . . . . . . . 643
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Chapter 101
ITOF: Integer to Floating Point . . . . . . . . . . . . . . . . . . . . . . . . 645
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Representation: ITOF - integer to Floating Point Conversion . . . . . . . . . . . . . . 647
Chapter 102
JSR: Jump to Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Representation: JSR - Jump to Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Chapter 103
LAB: Label for a Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Representation: LAB - Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Chapter 104
LOAD: Load Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Representation: LOAD - Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Chapter 105
MAP 3: MAP Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Representation: MAP 3 - Map Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Chapter 106
MATH - Integer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Short Description: MATH - Integer Operations Decimal Square Root, Process Square Root,
Logarithm (base 10), and Antilogarithm (base 10) . . . . . . . . . . . . . . . . . . . . . . 670
Representation: MATH - Integer Operations Decimal Square Root, Process Square Root,
Logarithm (base 10), and Antilogarithm (base 10) . . . . . . . . . . . . . . . . . . . . . . 671
Chapter 107
MBIT: Modify Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Representation: MBIT - Logical Bit Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Chapter 108
MBUS: MBUS Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Representation: MBUS - Modbus II Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
The MBUS Get Statistics Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Chapter 109
MRTM: Multi-Register Transfer Module . . . . . . . . . . . . . . . . . 691
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Representation: MRTM - Multi-Register Transfer Module . . . . . . . . . . . . . . . . . 693
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
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Chapter 110
MSPX (Seriplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Short Description: MSPX (Seriplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Representation: MSPX (Seriplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Chapter 111
MSTR: Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
984LL MSTR Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Get Local Statistics MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Local Statistics MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Global Data MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Global Data MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Get Remote Statistics MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Remote Statistics MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peer Cop Health MSTR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Option Module MSTR Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read CTE (Config Extension Table) MSTR Operation . . . . . . . . . . . . . . . . . . .
Write CTE (Config Extension Table) MSTR Operation . . . . . . . . . . . . . . . . . . .
Modbus Plus Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP/IP Ethernet Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modbus Plus and SY/MAX Ethernet Error Codes . . . . . . . . . . . . . . . . . . . . . . .
SY/MAX-specific Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCP/IP Ethernet Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTE Error Codes for SY/MAX and TCP/IP Ethernet. . . . . . . . . . . . . . . . . . . . .
Chapter 112
703
704
707
711
713
715
717
719
720
721
723
725
728
729
731
733
738
739
740
742
744
747
MU16: Multiply 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Representation: MU16 - 16-Bit Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Chapter 113
MUL: Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Representation: MUL - Single Precision Multiplication . . . . . . . . . . . . . . . . . . . 753
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Chapter 114
NBIT: Bit Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Representation: NBIT - Normal Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Chapter 115
NCBT: Normally Closed Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Representation: NCBT - Bit Normally Closed . . . . . . . . . . . . . . . . . . . . . . . . . . 761
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Chapter 116
NOBT: Normally Open Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
Representation: NOBT - Bit Normally Open . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Chapter 117
NOL: Network Option Module for Lonworks . . . . . . . . . . . . . 767
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
Representation: NOL - Network Option Module for Lonworks. . . . . . . . . . . . . . 769
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Part V Instruction Descriptions (O to Q) . . . . . . . . . . . . . . . . . . 773
Chapter 118
OR: Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Representation: OR - Logical Or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Chapter 119
PCFL: Process Control Function Library . . . . . . . . . . . . . . . 781
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Representation: PCFL - Process Control Function Library . . . . . . . . . . . . . . . . 783
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Chapter 120
PCFL-AIN: Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Representation: PCFL - AIN - Convert Inputs to
Scaled Engineering Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Chapter 121
PCFL-ALARM: Central Alarm Handler . . . . . . . . . . . . . . . . . . 793
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Representation: PCFL - ALRM - Central Alarm Handler for a P(v) Input. . . . . . 795
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Chapter 122
PCFL-AOUT: Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Representation: PCFL - AOUT - Convert Outputs to
Values in the 0 through 4095 Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Chapter 123
PCFL-AVER: Average Weighted Inputs Calculate . . . . . . . . 803
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Representation: PCFL - AVER - Average Weighted Inputs. . . . . . . . . . . . . . . . 805
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Chapter 124
PCFL-CALC: Calculated preset formula . . . . . . . . . . . . . . . . 809
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Representation: PCFL - CALC - Calculate Present Formula. . . . . . . . . . . . . . . 811
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
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Chapter 125
PCFL-DELAY: Time Delay Queue . . . . . . . . . . . . . . . . . . . . . . 815
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Representation: PCFL - DELY - Time Delay Queue . . . . . . . . . . . . . . . . . . . . . 817
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Chapter 126
PCFL-EQN: Formatted Equation Calculator. . . . . . . . . . . . . . 821
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Representation: PCFL - EQN - Formatted Equation Calculator . . . . . . . . . . . . 823
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Chapter 127
PCFL-INTEG: Integrate Input at Specified Interval . . . . . . . . 827
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Representation: PCFL - INTG - Integrate Input at Specified Interval . . . . . . . . 829
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Chapter 128
PCFL-KPID: Comprehensive ISA Non Interacting PID . . . . . 831
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Representation: PCFL - KPID - Comprehensive ISA NonInteracting Proportional-Integral-Derivative. . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Chapter 129
PCFL-LIMIT: Limiter for the Pv . . . . . . . . . . . . . . . . . . . . . . . . 837
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Representation: PCFL - LIMIT - Limiter for the P(v) . . . . . . . . . . . . . . . . . . . . . 839
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Chapter 130
PCFL-LIMV: Velocity Limiter for Changes in the Pv . . . . . . . 841
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Representation: PCFL - LIMV - Velocity Limiter for Changes in the P(v) . . . . . 843
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Chapter 131
PCFL-LKUP: Look-up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Representation: PCFL - LKUP - Look-up Table . . . . . . . . . . . . . . . . . . . . . . . . 847
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Chapter 132
PCFL-LLAG: First-order Lead/Lag Filter . . . . . . . . . . . . . . . . 851
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Representation: PCFL - LLAG - First-Order Lead/Lag Filter. . . . . . . . . . . . . . . 853
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
Chapter 133
PCFL-MODE: Put Input in Auto or Manual Mode . . . . . . . . . . 855
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Representation: PCFL - MODE - Put Input in Auto or Manual Mode . . . . . . . . 857
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
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Chapter 134
PCFL-ONOFF: ON/OFF Values for Deadband . . . . . . . . . . . . 859
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Representation: PCFL - ONOFF - Specifies
ON/OFF Values for Deadband. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Chapter 135
PCFL-PI: ISA Non Interacting PI . . . . . . . . . . . . . . . . . . . . . . . 865
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Representation: PCFL - PI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
Chapter 136
PCFL-PID: PID Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
Representation: PCFL - PID - Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Chapter 137
PCFL-RAMP: Ramp to Set Point at a Constant Rate . . . . . . 877
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Representation: PCFL - RAMP - Ramp to Set Point at Constant Rate . . . . . . . 879
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Chapter 138
PCFL-RATE: Derivative Rate Calculation
over a Specified Timeme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
Representation: PCFL - RATE - Derivative Rate
Calculation Over a Specified Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Chapter 139
PCFL-RATIO: Four Station Ratio Controller . . . . . . . . . . . . . 887
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Representation: PCFL - RATIO - Four-Station Ratio Controller . . . . . . . . . . . . 889
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Chapter 140
PCFL-RMPLN: Logarithmic Ramp to Set Point . . . . . . . . . . . 893
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Representation: PCFL - RMPLN - Logarithmic Ramp to Set Point . . . . . . . . . . 895
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Chapter 141
PCFL-SEL: Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
Representation: PCFL - SEL - High/Low/Average Input Selection . . . . . . . . . . 899
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Chapter 142
PCFL-TOTAL: Totalizer for Metering Flow . . . . . . . . . . . . . . 903
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Representation: PCFL - TOTAL - Totalizer for Metering Flow. . . . . . . . . . . . . . 905
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
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Chapter 143
PEER: PEER Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Representation: PEER - Modbus II Identical Transfer . . . . . . . . . . . . . . . . . . . 911
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Chapter 144
PID2: Proportional Integral Derivative . . . . . . . . . . . . . . . . . . 913
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Representation: PID2 - Proportional/Integral/Derivative . . . . . . . . . . . . . . . . . .
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
914
915
916
919
924
Part VI Instruction Descriptions (R to Z) . . . . . . . . . . . . . . . . . 927
Chapter 145
R --> T: Register to Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Representation: R o T - Register to Table Move . . . . . . . . . . . . . . . . . . . . . . . 931
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Chapter 146
RBIT: Reset Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
Representation: RBIT - Reset Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Chapter 147
READ: Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Representation: READ - Read ASCII Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Chapter 148
RET: Return from a Subroutine. . . . . . . . . . . . . . . . . . . . . . . . 943
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Representation: RET - Return to Scheduled Logic . . . . . . . . . . . . . . . . . . . . . . 945
Chapter 149
RTTI - Register to Input Table . . . . . . . . . . . . . . . . . . . . . . . . . 947
Short Description: RTTI - Register to Input Table . . . . . . . . . . . . . . . . . . . . . . . 948
Representation: RTTI - Register to Input Table . . . . . . . . . . . . . . . . . . . . . . . . 949
Chapter 150
RTTO - Register to Output Table. . . . . . . . . . . . . . . . . . . . . . . 951
Short Description: RTTO - Register to Output Table. . . . . . . . . . . . . . . . . . . . . 952
Representation: RTTO - Register to Output Table . . . . . . . . . . . . . . . . . . . . . . 953
Chapter 151
RTU - Remote Terminal Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Short Description: RTU - Remote Terminal Unit . . . . . . . . . . . . . . . . . . . . . . . . 956
Representation: RTU - Remote Terminal Unit . . . . . . . . . . . . . . . . . . . . . . . . . 957
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Chapter 152
SAVE: Save Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Representation: SAVE - Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Chapter 153
SBIT: Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
Representation: SBIT - Set Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Chapter 154
SCIF: Sequential Control Interfaces. . . . . . . . . . . . . . . . . . . . 969
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Representation: SCIF - Sequential Control Interface. . . . . . . . . . . . . . . . . . . . . 971
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Chapter 155
SENS: Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Representation: SENS - Logical Bit-Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Chapter 156
Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Short Description: Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Representation: Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Chapter 157
SKP - Skipping Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Short Description: SKP - Skipping Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Representation: SKP - Skipping Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Chapter 158
SRCH: Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Representation: SRCH - Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Chapter 159
STAT: Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Representation: STAT - Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Description of the Status Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Controller Status Words 1 - 11 for Quantum and Momentum . . . . . . . . . . . . . 1001
I/O Module Health Status Words 12 - 20 for Momentum . . . . . . . . . . . . . . . . . 1006
I/O Module Health Status Words 12 - 171 for Quantum . . . . . . . . . . . . . . . . . 1008
Communication Status Words 172 - 277 for Quantum . . . . . . . . . . . . . . . . . . 1010
Controller Status Words 1 - 11 for TSX Compact and Atrium . . . . . . . . . . . . . 1016
I/O Module Health Status Words 12 - 15 for TSX Compact. . . . . . . . . . . . . . . 1019
Global Health and Communications Retry
Status Words 182 ... 184 for TSX Compact. . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
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Chapter 160
SU16: Subtract 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Representation: SU16 - 16-bit Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Chapter 161
SUB: Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Representation: SUB - Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Chapter 162
SWAP - VME Bit Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Short Description: SWAP - VME Bit Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Representation: SWAP - VME Bit Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Chapter 163
TTR - Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Short Description: TTR - Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Representation: TTR - Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Chapter 164
T --> R Table to Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
Representation: T o R - Table to Register Move . . . . . . . . . . . . . . . . . . . . . . 1039
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Chapter 165
T --> T: Table to Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Representation: T o T - Table to Table Move . . . . . . . . . . . . . . . . . . . . . . . . 1045
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Chapter 166
T.01 Timer: One Hundredth Second Timer. . . . . . . . . . . . . . 1049
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
Representation: T.01 - One Hundredth of a Second Timer. . . . . . . . . . . . . . . 1051
Chapter 167
T0.1 Timer: One Tenth Second Timer . . . . . . . . . . . . . . . . . . 1053
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Representation: T0.1 - One Tenth of a Second Timer . . . . . . . . . . . . . . . . . . 1055
Chapter 168
T1.0 Timer: One Second Timer . . . . . . . . . . . . . . . . . . . . . . . 1057
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Representation: T1.0 - One Second Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Chapter 169
T1MS Timer: One Millisecond Timer. . . . . . . . . . . . . . . . . . . 1061
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Representation: T1MS - One Millisecond Timer . . . . . . . . . . . . . . . . . . . . . . . 1063
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Chapter 170
TBLK: Table to Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Representation: TBLK - Table-to-Block Move. . . . . . . . . . . . . . . . . . . . . . . . . 1069
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
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Chapter 171
TEST: Test of 2 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Representation: TEST - Test of 2 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Chapter 172
UCTR: Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Representation: UCTR - Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Chapter 173
VMER - VME Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Short Description: VMER - VME Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Representation: VMER - VME Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Parameter Description: VMER - VME Read . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Chapter 174
VMEW - VME Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Short Description: VMEW - VME Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Representation: VMEW - VME Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Parameter Description: VMEW - VME Write . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Chapter 175
WRIT: Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Representation: WRIT - Write ASCII Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Chapter 176
XMIT - Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
General Description: XMIT - Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
XMIT Modbus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Chapter 177
XMIT Communication Block . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Short Description: XMIT Communication Block . . . . . . . . . . . . . . . . . . . . . . . . 1106
Representation: XMIT Communication Block . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Parameter Description: Middle Node - Communication Control Table . . . . . . 1109
Parameter Description: XMIT Communication Block. . . . . . . . . . . . . . . . . . . . 1114
Parameter Description: XMIT Communications Block . . . . . . . . . . . . . . . . . . . 1116
Chapter 178
XMIT Port Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Short Description: XMIT Port Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Representation: XMIT Port Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Parameter Description: Middle Node - XMIT Conversion Block . . . . . . . . . . . 1121
Chapter 179
XMIT Conversion Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Short Description: XMIT Conversion Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Representation: XMIT Conversion Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Parameter Description: XMIT Conversion Block . . . . . . . . . . . . . . . . . . . . . . . 1129
Chapter 180
XMRD: Extended Memory Read . . . . . . . . . . . . . . . . . . . . . . 1133
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
Representation: XMRD - Extended Memory Read . . . . . . . . . . . . . . . . . . . . . 1135
Parameter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
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Chapter 181
XMWT: Extended Memory Write . . . . . . . . . . . . . . . . . . . . . . 1139
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Representation: XMWT - Extended Memory Write . . . . . . . . . . . . . . . . . . . . . 1141
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Chapter 182
XOR: Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Short Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Representation: XOR - Boolean Exclusive Or. . . . . . . . . . . . . . . . . . . . . . . . . 1147
Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
Appendices
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
Optimizing RIO Performance with the Segment Scheduler . . . . . . . . . . . . . . 1151
Appendix A
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
Optimizing RIO Peformance with the Segment Scheduler . . . . . . . . . . . . . . .
Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Measure Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximizing Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order of Solve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Segment Scheduler to Improve Critical I/O Throughput . . . . . . . . . . . .
Using Segment Scheduler to Improve System Performance . . . . . . . . . . . . .
Using Segment Scheduler to Improve Communication Port Servicing . . . . . .
Sweep Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1153
1154
1158
1159
1161
1162
1164
1165
1166
Glossary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxi
Index
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lv
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Safety Information
§
NOTICE
Read these instructions carefully, and look at the equipment to become familiar with
the device before trying to install, operate, or maintain it. The following special
messages may appear throughout this documentation or on the equipment to warn
of potential hazards or to call attention to information that clarifies or simplifies
a procedure.
The addition of this symbol to a Danger or Warning safety label indicates
that an electrical hazard exists, which will result in personal injury if the
instructions are not followed.
This is the safety alert symbol. It is used to alert you to potential personal
injury hazards. Obey all safety messages that follow this symbol to avoid
possible injury or death.
DANGER
DANGER indicates an imminently hazardous situation, which, if not avoided, will
result in death or serious injury.
WARNING
WARNING indicates a potentially hazardous situation, which, if not avoided, can result
in death, serious injury, or equipment damage.
CAUTION
CAUTION indicates a potentially hazardous situation, which, if not avoided, can result
in injury or equipment damage.
PLEASE NOTE
Electrical equipment should be installed, operated, serviced, and maintained only by
qualified personnel. No responsibility is assumed by Schneider Electric for any
consequences arising out of the use of this material.
© 2006 Schneider Electric. All Rights Reserved.
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Safety Information
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About the Book
At a Glance
Document Scope
This documentation will help you configure LL 984 instructions to any controller
using ProWorx NxT, ProWorx 32 or Modbus Plus. Examples in this book are used
with ProWorx 32. For LL 984 using Concept software, see Concept Block Library
LL984 (840USE49600).
Validity Note
The data and illustrations found in this book are not binding. We reserve the right to
modify our products in line with our policy of continuous product development. The
information in this document is subject to change without notice and should not be
construed as a commitment by Schneider Electric.
Related
Documents
Title of Documentation
Reference Number
Concept Block Library LL 984
840 USE 496
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About the Book
Product Related
Warnings
Schneider Electric assumes no responsibility for any errors that may appear in this
document. If you have any suggestions for improvements or amendments or have
found errors in this publication, please notify us.
No part of this document may be reproduced in any form or by any means, electronic
or mechanical, including photocopying, without express written permission of
Schneider Electric.
All pertinent state, regional, and local safety regulations must be observed when
installing and using this product. For reasons of safety and to ensure compliance
with documented system data, only the manufacturer should perform repairs to
components.
When controllers are used for applications with technical safety
requirements, please follow the relevant instructions.
Failure to use Schneider Electric software or approved software with our hardware
products may result in injury, harm, or improper operating results.
Failure to observe this product related warning can result in injury or
equipment damage.
User Comments
We welcome your comments about this document. You can reach us by e-mail at
[email protected]
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Instruction Descriptions (O to Q)
V
At a Glance
Introduction
In this part instruction descriptions are arranged alphabetically from O to Q.
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Instruction Descriptions (O to Q)
What's in
this Part?
This part contains the following chapters:
Chapter
Chapter Name
Page
118
OR: Logical OR
775
119
PCFL: Process Control Function Library
781
120
PCFL-AIN: Analog Input
787
121
PCFL-ALARM: Central Alarm Handler
793
122
PCFL-AOUT: Analog Output
799
123
PCFL-AVER: Average Weighted Inputs Calculate
803
124
PCFL-CALC: Calculated preset formula
809
125
PCFL-DELAY: Time Delay Queue
815
126
PCFL-EQN: Formatted Equation Calculator
821
127
PCFL-INTEG: Integrate Input at Specified Interval
827
128
PCFL-KPID: Comprehensive ISA Non Interacting PID
831
129
PCFL-LIMIT: Limiter for the Pv
837
130
PCFL-LIMV: Velocity Limiter for Changes in the Pv
841
131
PCFL-LKUP: Look-up Table
845
132
PCFL-LLAG: First-order Lead/Lag Filter
851
133
PCFL-MODE: Put Input in Auto or Manual Mode
855
134
PCFL-ONOFF: ON/OFF Values for Deadband
859
135
PCFL-PI: ISA Non Interacting PI
865
136
PCFL-PID: PID Algorithms
871
137
PCFL-RAMP: Ramp to Set Point at a Constant Rate
877
138
PCFL-RATE: Derivative Rate Calculation over a Specified
Timeme
883
139
PCFL-RATIO: Four Station Ratio Controller
887
140
PCFL-RMPLN: Logarithmic Ramp to Set Point
893
141
PCFL-SEL: Input Selection
897
142
PCFL-TOTAL: Totalizer for Metering Flow
903
143
PEER: PEER Transaction
909
144
PID2: Proportional Integral Derivative
913
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OR: Logical OR
118
At a Glance
Introduction
This chapter describes the instruction OR.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
776
Representation: OR - Logical Or
777
Parameter Description
779
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OR: Logical OR
Short Description
Function
Description
The OR instruction performs a Boolean OR operation on the bit patterns in the
source and destination matrices.
The ORed bit pattern is then posted in the destination matrix, overwriting its
previous contents.
source
bits
0
0
1
1
0
OR
OR
OR
OR
0
0
1
1
1
1
destination
bits
1
WARNING
Overriding of any disabled coils within the destination matrix
without enabling them
OR will override any disabled coils within the destination matrix without
enabling them. This can cause personal injury if a coil has disabled an operation
for maintenance or repair because the coil’s state can be changed by the
OR operation.
Failure to follow this instruction can result in death, serious injury, or
equipment damage.
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OR: Logical OR
Representation: OR - Logical Or
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source
matrix
Source matrix
destination
matrix
OR
Parameter
Description
Source bit: 0 0 1 1
Compare bit: 0 1 0 1
Result bit:
0111
Length: 1 to 100 registers
(16 to 1600 bits)
length
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
Initiates OR
source matrix
(top node)
0x, 1x, 3x,
4x
ANY_BIT
First reference in the source matrix.
destination matrix
(middle node)
0x, 4x
ANY_BIT
First reference in the destination matrix
length
(bottom node)
Top output
INT, UINT Matrix length, range: 1 ... 100.
0x
None
Echoes state of the top input
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OR: Logical OR
An OR Example
Whenever contact 10001 passes power, the source matrix formed by the bit pattern
in registers 40600 and 40601 is ORed with the destination matrix formed by the bit
pattern in registers 40606 and 40607. The ORed bit pattern is then copied into
registers 40606 and 40607, overwriting the original destination bit pattern.
source matrix
40600 = 1111111100000000 40601 = 1111111100000000
40600
10001
40606
OR
00002
Original destination matrix
40606 = 1111111111111111 40607 = 0000000000000000
ORed destination matrix
40606 = 1111111111111111 40607 = 1111111100000000
CAUTION
Outputs and coils cannot be turned off with the OR instruction.
Failure to follow this instruction can result in injury or equipment damage.
Note: If you want to retain the original destination bit pattern of registers 40606 and
40607, copy the information into another table using the BLKM instruction before
performing the OR operation.
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OR: Logical OR
Parameter Description
Matrix Length
(Bottom Node)
The integer entered in the bottom node specifies the matrix length, i.e. the number
of registers or 16-bit words in the two matrices. The matrix length can be in the range
1 ... 100. A length of 2 indicates that 32 bits in each matrix will be ORed.
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OR: Logical OR
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PCFL: Process Control
Function Library
119
At a Glance
Introduction
This chapter describes the instruction PCFL.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
782
Representation: PCFL - Process Control Function Library
783
Parameter Description
784
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PCFL: Process Control Function Library
Short Description
Function
Description
The PCFL instruction gives you access to a library of process control functions
utilizing analog values.
PCFL operations fall into three major categories.
Advanced Calculations
z Signal Processing
z Regulatory Control
z
A PCFL function is selected from a list of alphabetical subfunctions in a pulldown
menu in the panel software, and the subfunction is displayed in the top node of the
instruction (see p. 784 for a list of subfunctions and descriptions).
PCFL uses the same FP library as EMTH. If the PLC that you are using for PCFL
does not have the onboard 80x87 math coprocessor chip, calculations take a
comparatively long time to execute. PLCs with the math coprocessor can solve
PCFL calculations ten times faster than PLCs without the chip. Speed, however,
should not be an issue for most traditional process control applications where
solution times are measured in seconds, not milliseconds.
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PCFL: Process Control Function Library
Representation: PCFL - Process Control Function Library
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
function
ERROR
parameter
block
PCFL
Length: 1 - 255
length
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
function
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of process control function
An indicator for the selected PCFL library
function is specified in the top node.
(For more information, see p. 784.)
4x
length
(bottom node)
INT, UINT, First in a block of contiguous holding registers
WORD
where the parameters for the specified
subfunction are stored
INT, UINT Length of parameter block (depending on
selected subfunction
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
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PCFL: Process Control Function Library
Parameter Description
Function
(Top Node)
A subfunction for the selected PCFL library function is specified in the top node.
Operation
Subfunction Description
Advanced
AVER
Calculations CALC
Signal
Processing
Regulatory
Control
Timedependent
Operations
Average weighted inputs
no
Calculate preset formula
no
EQN
Formatted equation calculator
no
ALARM
Central alarm handler for a PV input
no
AIN
Convert inputs to scaled engineering units
no
AOUT
Convert outputs to values in the 0 ... 4095 range no
DELAY
Time delay queue
yes
LKUP
Look-up table
no
INTEG
Integrate input at specified interval
yes
LLAG
First-order lead/lag filter
yes
LIMIT
Limiter for the PV (low/low, low, high, high/high) no
LIMV
Velocity limiter for changes in the PV (low, high)
yes
MODE
Put input in auto or manual mode
no
RAMP
Ramp to set point at a constant rate
yes
RMPLN
Logarithmic ramp to set point (~2/3 closer to set
point for each time constant)
yes
RATE
Derivative rate calculation over a specified time
yes
SEL
High/low/average input selection
no
KPID
Comprehensive ISA non-interacting
proportional-integral-derivative (PID)
yes
ONOFF
Specifies ON/OFF values for deadband
no
PID
PID algorithms
yes
PI
ISA non-interacting PI (with halt/manual/auto
operation features)
yes
RATIO
Four-station ratio controller
no
TOTAL
Totalizer for metering flow
yes
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PCFL: Process Control Function Library
Advanced
Calculations
Advanced calculations are used for general mathematical purposes and are not
limited to process control applications. With advanced calculations, you can create
custom signal processing algorithms, derive states of the controlled process, derive
statistical measures of the process, etc.
Simple math routines have already been offered in the EMTH instruction. The
calculation capability included in PCFL is a textual equation calculator for writing
custom equations instead of programming a series of math operations one by one.
Signal
Processing
Signal processing functions are used to manipulate process and derived process
signals. They can do this in a variety of ways; they linearize, filter, delay, and
otherwise modify a signal. This category would include functions such as an Analog
Input/Output, Limiters, Lead/Lag, and Ramp generators.
Regulatory
Control
Regulatory functions perform closed loop control in a variety of applications.
Typically, this is a PID (proportional integral derivative) negative feedback control
loop. The PID functions in PCFL offer varying degrees of functionality. Function 75,
PID, has the same general functionality as the PID2 instruction but uses floating
point math and represents some options differently. PID is beneficial in cases where
PID2 is not suitable because of numerical concerns such as round-off.
For more information, see p. 73.
Parameter Block
(Middle Node)
The 4x register entered in the middle node is the first in a block of contiguous holding
register where the parameters for the specified PCFL operation are stored.
The ways that the various PCFL operations implement the parameter block are
described in the description of the various subfunctions (PCFL operations).
Within the parameter block of each PCFL function are two registers used for
input and output status.
Output Flags
In all PCFL functions, bits 12 ... 16 of the output status register define the following
standard output flags:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bit
Function
1 - 11
Not used
12
1 = Math error - invalid floating point or output
13
1 = Unknown PCFL function
14
not used
15
1 = Size of the allocated register table is too small
16
1 = Error has occurred - pass power to the bottom output
15
16
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PCFL: Process Control Function Library
For time-dependent PCFL functions, bits 9 and 11 are also used as follows:
1
Input Flags
2
3
4
5
6
7
8
9
10
11
12
13
14
Bit
Function
1-8
Not used
9
1 = Initialization working
10
Not used
11
1 = Illegal solution interval
12
1 = Math error - invalid floating point or output
13
1 = Unknown PCFL function
14
not used
15
1 = Size of the allocated register table is too small
16
1 = Error has occurred - pass power to the bottom output
15
16
In all PCFL functions, bits 1 and 3 of the input status register define the following
standard input flags:
1
Length
(Bottom Node)
2
3
4
5
6
7
8
9
10
11
12
Bit
Function
1
1 = Function initialization complete or in progress
0 = Initialize the function
2
not used
3
1 = Timer override
4 -16
not used
13
14
15
16
The integer value entered in the bottom node specifies the length, i.e. the number of
registers, of the PCFL parameter block. The maximum allowable length will vary
depending on the function you specify.
786
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PCFL-AIN: Analog Input
120
At a Glance
Introduction
This chapter describes the subfunction PCFL-AIN.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
788
Representation: PCFL - AIN - Convert Inputs to Scaled Engineering Units
789
Parameter Description
790
787
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PCFL-AIN: Analog Input
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The AIN function scales the raw input produced by analog input modules to
engineering values that can be used in the subsequent calculations.
Three scaling options are available.
z Auto input scaling
z Manual input scaling
z Implementing process square root on the input to linearize the signal
before scaling
788
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PCFL-AIN: Analog Input
Representation: PCFL - AIN - Convert Inputs to Scaled Engineering Units
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
AIN
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM Data Type
Reference
Meaning
Top input
0x, 1x
ON = enables specified process
control function
None
AIN
(top node)
parameter
block
(middle node)
Selection of the subfunction AIN
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information, see p. 791.
INT, UINT
Length of parameter block for subfunction AIN
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
789
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PCFL-AIN: Analog Input
Parameter Description
Mode of
Functioning
AIN supports the range resolutions for following device types:
Quantum Engineering Ranges
Resolution
Range: Valid
Range: Under
Range: Over
10 V
768 ... 64 768
767
64 769
16 768 ... 48 768
16 767
48 769
0 ... 10 V
0 ... 64 000
0
64 001
0 ... 5 V
0 ... 32 000
0
32 001
1 ... 5 V
6 400 ... 32 000
6 399
32 001
V
Quantum Thermocouple
Resolution
Range: Valid
TC degrees
-454 ... +3 308
TC 0.1 degrees -4 540 ... +32 767
TC Raw Units
0 ... 65 535
Quantum Voltmeter
Resolution
Range: Valid
Range: Under Range: Over
10 V
-10 000 ... +10 000
-10 001
+10 001
5V
-5 000 ... +5 000
-5 001
+5 001
0 ... 10 V
0 ... 10 000
0
10 001
0 ... 5 V
0 ... 5 000
0
5 001
1 ... 5 V
1 000 ... 5 000
999
5 001
790
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PCFL-AIN: Analog Input
Parameter Block
(Middle Node)
The length of the AIN parameter block is 14 registers.
Register
Content
Displayed
Input from a 3x register
First implied
Reserved
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Scale 100% engineering units
Sixth and seventh implied Scale 0% engineering units
Eighth and ninth implied
Manual input
10th and 11th implied
Auto input
12th and 13th implied
Output
Output Status
Bit
Function
1...5
Not used
6
1 = with TC PSQRT, invalid: in extrapolation range, PSQRT not used
7
1 = input out of range
8
1 = echo under range from input module
9
1 = echo over range from input module
10
1 = invalid output mode selected
11
1 = invalid Engineering Units
12 ... 16
Standard output bits (flags)
Bit
Function
1 ... 3
Standard input bits (flags)
4 ... 8
Ranges (see following tables)
9
1 = process square root on raw input
10
1 = manual scaling mode
0 = auto scaling mode
11
1 = extrapolate over-/under-range for auto mode
0 = clamp over-/under-range for auto mode
12 ... 16
Not used
Input Status
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PCFL-AIN: Analog Input
Quantum Engineering Ranges
Bit
4
5
6
7
8
Range
0
1
0
0
0
+/- 10V
0
1
0
0
1
+/- 5V
0
1
0
1
0
0 ... 10 V
0
1
0
1
1
0 ... 5 V
0
1
1
0
0
1 ... 5 V
Quantum Thermocouple
Bit
4
5
6
7
8
Range
0
1
1
0
1
TC degrees
0
1
1
1
0
TC 0.1 degrees
0
1
1
1
1
TC raw units
Quantum Voltmeter
Bit
4
5
6
7
8
Range
1
0
0
0
0
+/- 10V
1
0
0
1
0
+/- 5V
1
0
1
0
0
0 ... 10 V
1
0
1
1
0
0 ... 5 V
1
1
0
0
0
1 ... 5 V
Note: Bit 4 in this register is nonstandard use.
792
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PCFL-ALARM:
Central Alarm Handler
121
At a Glance
Introduction
This chapter describes the subfunction PCFL-Alarm.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
794
Representation: PCFL - ALRM - Central Alarm Handler for a P(v) Input
795
Parameter Description
796
793
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PCFL-ALARM: Central Alarm Handler
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The ALARM function gives you a central block for alarm handling where you can set
high (H), low (L), high high (HH), and low low (LL) limits on a process variable.
ALARM lets you specify
z A choice of normal or deviation operating mode
z Whether to use H/L or both H/L and HH/LL limits
z Whether or not to use deadband (DB) around the limits
794
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PCFL-ALARM: Central Alarm Handler
Representation: PCFL - ALRM - Central Alarm Handler for a P(v) Input
Symbol
Representation of the instruction
CONTROL INPUT
ALRM
OPERATION
SUCCESSFUL
ERROR
parameter
block
PCFL
#16
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ALRM
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction ALARM
4x
16
(bottom node)
INT, UINT, First in a block of contiguous holding registers
WORD
where the parameters for the specified
subfunction are stored
For more information, see p. 796.
INT, UINT
Length of parameter block for subfunction
ALARM (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
795
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PCFL-ALARM: Central Alarm Handler
Parameter Description
Mode of
Functioning
The following operating modes are available.
Mode
Meaning
Normal Operating ALARM operates directly on the input. Normal is the default condition
Mode
Deviation
Operating Mode
ALARM operates on the change between the current input and the
last input.
Deadband
When enabled, the DB option is incorporated into the HH/H/LL/L limits.
These calculated limits are inclusive of the more extreme range, e.g. if the
input has been in the high range, the output remains high and does not
transition when the input hits the calculated H limit.
Operations
A flag is set when the input or deviation equals or crosses the
corresponding limit. If the DB option is used, the HH, H, LL, L limits are
adjusted internally for crossed-limit checking and hysteresis.
Note: ALARM automatically tracks the last input, even when you specify normal
mode, to facilitate a smooth transition to deviation mode.
Parameter Block
(Middle Node)
The length of the ALARM parameter block is 16 registers.
Register
Content
Displayed and first implied Input registers
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
HH limit value
Sixth and seventh implied
H limit value
Eighth and ninth implied
L limit value
10th and 11th implied
LL limit value
12th and 13th implied
Deadband (DB) around limit
14th and 15th implied
Last input
796
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PCFL-ALARM: Central Alarm Handler
Output Status
Bit
Function
1 ... 4
Not used
5
1 = DB set to negative number
6
1 = deviation mode chosen with DB option
7
1 = LL crossed (x d LL
8
1 = L crossed (x d L or LL < x d L) with HH/LL option set
9
1 = H crossed (x t H or H d x < HH) with HH/LL option set
10
1 = HH crossed (x t HH)
11
1 = invalid limits specified
12 ... 16
Standard output bits (flags)
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = deviation mode
0 = normal mode
6
1 = both H/L and HH/LL limits apply
7
1 = DB enabled
8
1 = retain H/L flag when HH/LL limits crossed
9 ... 16
Not used
Input Status
797
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PCFL-ALARM: Central Alarm Handler
798
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PCFL-AOUT: Analog Output
122
At a Glance
Introduction
This chapter describes the subfunction PCFL-AOUT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
800
Representation: PCFL - AOUT - Convert Outputs to Values in the 0 through
4095 Range
801
Parameter Description
802
799
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PCFL-AOUT: Analog Output
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The AOUT function is an interface for calculated signals for output modules. It
converts the signal to a value in the range 0 ... 4 096.
Formula
Formula of the AOUT function:
u IN – LEU -
OUT = scale
----------------------------------------------- HEU – LEU The meaning of the elements:
Element
Meaning
HEU
High Engineering Unit
IN
Input
LEU
Low Engineering Unit
OUT
Output
scale
Scale
800
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PCFL-AOUT: Analog Output
Representation: PCFL - AOUT - Convert Outputs to Values in the 0
through 4095 Range
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
AOUT
ERROR
parameter
block
PCFL
#9
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
AOUT
(top node)
parameter
block
(middle node)
Selection of the subfunction AOUT
4x
9
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information, see p. 802.
INT, UINT
Length of parameter block for subfunction
AOUT (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
801
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PCFL-AOUT: Analog Output
Parameter Description
Parameter Block
(Middle Node)
The length of the AOUT parameter block is 9 registers.
Register
Content
Displayed and first implied
Input in engineering units
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
High engineering units
Sixth and seventh implied
Low engineering units
Eighth and ninth implied
Output
Output Status
Bit
Function
1 ... 7
Not used
8
1 = clamped low
9
1 = clamped high
10
not used
11
1 = invalid H/L limits
12 ... 16
Standard output bits (flags)
Input Status
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
802
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PCFL-AVER: Average Weighted
Inputs Calculate
123
At a Glance
Introduction
This chapter describes the subfunction PCFL-AVER.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
804
Representation: PCFL - AVER - Average Weighted Inputs
805
Parameter Description
806
803
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PCFL-AVER: Average Weighted Inputs Calculate
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Advanced Calculation.
The AVER function calculates the average of up to four weighted inputs.
Formula
Formula of the AVER function:
k + w 1 u In 1 + w 2 u In 2 + w 3 u In 3 + w 4 u In 4 RES = ---------------------------------------------------------------------------------------------------------------------------------------1 + w1 + w2 + w3 + w4
The meaning of the elements:
Element
Meaning
In1 ... In4
Inputs
k
Constant
RES
Result
w1 ... w4
Weights
804
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PCFL-AVER: Average Weighted Inputs Calculate
Representation: PCFL - AVER - Average Weighted Inputs
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
AVER
ERROR
parameter
block
PCFL
#24
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
AVER
(top node)
parameter
block
(middle node)
Selection of the subfunction AVER
4x
24
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information, see p. 806.
INT, UINT
Length of parameter block for subfunction
AVER (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
805
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PCFL-AVER: Average Weighted Inputs Calculate
Parameter Description
Parameter Block
(Middle Node)
The length of the AVER parameter block is 24 registers.
Register
Content
Displayed and first implied
reserved
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Value of In1
Sixth and seventh implied
Value of Inv2
Eighth and ninth implied
Value of In3
10th and 11th implied
Value of In4
12th and 13th implied
Value of k
14th and 15th implied
Value of wv1
16th and 17th implied
Value of wv2
18th and 19th implied
Value of wv3
20th and 21st implied
Value of wv4
22nd and 23rd implied
Value of result
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 9
Not used
10
1 = no inputs activated
11
1 = result negative
0 = result positive
12 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
806
16
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PCFL-AVER: Average Weighted Inputs Calculate
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = In4 and w4 are used
6
1 = In3 and w3 are used
7
1 = In2 and w2 are used
8
1 = In1 and w1 are used
9
1 = k is active
10 ... 16
Not used
9
10
11
12
13
14
15
16
A weight can be used only when its corresponding input is enabled, e.g. the 20th
and 21st implied registers (which contain the value of w4) can be used only when
the 10th and 11th implied registers (which contain In4) are enabled. The I in the
denominator is used only when the constant is enabled.
807
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PCFL-AVER: Average Weighted Inputs Calculate
808
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PCFL-CALC: Calculated
preset formula
124
At a Glance
Introduction
This chapter describes the subfunction PCFL-CALC.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
810
Representation: PCFL - CALC - Calculate Present Formula
811
Parameter Description
812
809
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PCFL-CALC: Calculated preset formula
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Advanced Calculation.
The CALC function calculates a preset formula with up to four inputs, each
characterized in a separate register of the parameter block.
810
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PCFL-CALC: Calculated preset formula
Representation: PCFL - CALC - Calculate Present Formula
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
CALC
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process
control function
CALC
(top node)
parameter
block
(middle node)
Selection of the subfunction CALC
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding
registers where the parameters for the
specified subfunction are stored
For more information, see p. 812.
INT, UINT
Length of parameter block for subfunction
CALC (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
811
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PCFL-CALC: Calculated preset formula
Parameter Description
Parameter Block
(Middle Node)
The length of the CALC parameter block is 14 registers.
Register
Content
Displayed and first implied
Reserved
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Value of input A
Sixth and seventh implied
Value of input B
Eighth and ninth implied
Value of input C
10th and 11th implied
Value of input D
12th and 13th implied
Value of the output
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1...10
Not used
11
1 = bad input code chosen
12 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 6
not used
7 ... 10
Formula Code
11 ... 16
Not used
812
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PCFL-CALC: Calculated preset formula
Formula Code
Bit
Formula Code
7
8
9
10
0
0
0
1
A u B – C u D
0
0
1
1
A u B e C u D
0
1
0
0
A e B u C u D
0
1
0
1
A u B u C e D
0
1
1
0
AuBuCuD
0
1
1
1
A+B+C+D
1
0
0
0
A u B C –D 1
0
0
1
A> B e C @
1
0
1
0
A u LN(B e C)
1
0
1
1
A – B – C – D e LN > A – B e C – D @
1
1
0
0
A e B
1
1
0
1
A –B e C – D D
–C e D 813
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PCFL-CALC: Calculated preset formula
814
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PCFL-DELAY: Time Delay Queue
125
At a Glance
Introduction
This chapter describes the subfunction PCFL-DELAY.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
816
Representation: PCFL - DELY - Time Delay Queue
817
Parameter Description
818
815
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PCFL-DELAY: Time Delay Queue
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The DELAY function can be used to build a series of readings for time-delay
compensation in the logic. Up to 10 sampling instances can be used to delay
an input.
All values are carried along in registers, where register x[0] contains the current
sampled input. The 10th delay period does not need to be stored. When the 10th
instance in the sequence takes place, the value in register x[9] can be moved
directly to the output
A DXDONE message is returned when the calculation is complete. The function can
be reset by toggling the first-scan bit.
816
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PCFL-DELAY: Time Delay Queue
Representation: PCFL - DELY - Time Delay Queue
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
DELY
ERROR
parameter
block
PCFL
#32
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
DELY
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction DELY
4x
32
(bottom node)
INT, UINT First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored For more information,
see p. 818.
INT, UINT Length of parameter block for subfunction DELY
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
817
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PCFL-DELAY: Time Delay Queue
Parameter Description
Parameter Block
(Middle Node)
The length of the DELAY parameter block is 32 registers.
Register
Content
Displayed and first implied Input at time n
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
x[0] delay
12th and 13th implied
x[1] delay
14th and 15th implied
x[2] delay
...
...
28th and 29th implied
x[9] delay
30th and 31st implied
Output registers
Output Status
1
2
3
4
5
6
7
8
9
10
Bit
Function
1...3
Not used
4
1 = k out of range
5 ... 8
Count of registers left to be initialized
9 ... 16
Standard output bits (flags)
11
12
13
14
15
818
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PCFL-DELAY: Time Delay Queue
Input Status
1
2
3
4
5
6
7
8
9
10
11
12
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 8
Time Delay d 10
9 ... 11
Echo number of registers left to be initialized
12 ... 16
Not used
13
14
15
16
819
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PCFL-DELAY: Time Delay Queue
820
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PCFL-EQN: Formatted
Equation Calculator
126
At a Glance
Introduction
This chapter describes the subfunction PCFL-EQN.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
822
Representation: PCFL - EQN - Formatted Equation Calculator
823
Parameter Description
824
821
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PCFL-EQN: Formatted Equation Calculator
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Advanced Calculation.
The EQN function is a formatted equation calculator. You must define the equation
in the parameter block with various codes that specify operators, input selection
and inputs.
EQN is used for equations that have four or fewer variables but do not fit into the
CALC format. It complements the CALC function by letting you input an equation
with floating point and integer inputs as well as operators.
822
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PCFL-EQN: Formatted Equation Calculator
Representation: PCFL - EQN - Formatted Equation Calculator
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
EQN
ERROR
parameter
block
PCFL
#64
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
EQN
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction EQN
4x
15 ... 64
(bottom node)
INT, UINT First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored. For more information,
see p. 824.
INT, UINT Length of parameter block for subfunction EQN
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
823
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PCFL-EQN: Formatted Equation Calculator
Parameter Description
Parameter Block
(Middle Node)
The length of the EQN parameter block can be as high as 64 registers.
Register
Content
Displayed and first implied
Reserved
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Variable A
Sixth and seventh implied
Variable B
Eighth and ninth implied
Variable C
10th and 11th implied
Variable D
12th and 13th implied
Output
14th implied
First formula code
15th implied
Second possible formula code
...
...
63rd implied
Last possible formula code
Output Status
1
2
3
4
5
6
7
8
9
Bit
Function
1
Stack error
2...3
Not used
4 ... 8
Code of last error logged
9
1 = bad operator selection code
10
1 = EQN not fully programmed
11
1 = bad input code chosen
12 ... 16
Standard output bits (flags)
10
11
12
13
14
15
824
16
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PCFL-EQN: Formatted Equation Calculator
Input Status
1
Formula Code
2
3
4
5
6
7
8
9
10
11
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = Degree/radian option for trigonometry
6 ... 8
not used
9 ... 16
Equation size for display in Concept
12
13
14
15
16
Each formula code in the EQN function defines either an input selection code or an
operator selection code.
Formula Code (Parameter Block)
1
2
3
4
5
6
7
8
9
Bit
Function
1 ... 4
Not used
5 ... 8
Definition of input selection
9 ... 11
Not used
12 ... 16
Definition of operator selection
10
11
12
13
14
15
16
Input Selection
Bit
Input Selection
5
6
7
8
0
0
0
0
Use operator selection
0
0
0
1
Float input
0
0
1
1
16-bit integer
1
0
0
0
Variable A
1
0
0
1
Variable B
1
0
1
0
Variable C
1
0
1
1
Variable D
825
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PCFL-EQN: Formatted Equation Calculator
Operator Selection
Bit
Operator Selection
12
13
14
15
16
0
0
0
0
0
No operation
0
0
0
0
1
Absolute value
0
0
0
1
0
Addition
0
0
0
1
1
Division
0
0
1
0
0
Exponent
0
0
1
1
1
LN (natural logarithm)
0
1
0
0
0
G (logarithm)
0
1
0
0
1
Multiplication
0
1
0
1
0
Negation
0
1
0
1
1
Power
0
1
1
0
0
Square root
0
1
1
0
1
Subtraction
0
1
1
1
0
Sine
0
1
1
1
1
Cosine
1
0
0
0
0
Tangent
1
0
0
0
1
Arcsine
1
0
0
1
0
Arccosine
1
0
0
1
1
Arctangent
826
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PCFL-INTEG: Integrate Input
at Specified Interval
127
At a Glance
Introduction
This chapter describes the subfunction PCFL-INTEG.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
828
Representation: PCFL - INTG - Integrate Input at Specified Interval
829
Parameter Description
830
827
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PCFL-INTEG: Integrate Input at Specified Interval
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The INTEG function is used to integrate over a specified time interval. No protection
against integral wind-up is provided in this function. INTEG is time-dependent, e.g.
if you are integrating at an input value of 1/sec, it matters whether it operates over
one second (in which case the result is 1) or over one minute (in which case the
result is 60).
You can set flags to either initialize or restart the function after an undetermined
down-time, and you can reset the integral sum if you wish. If you set the initialize
flag, you must specify a reset value (zero or the last output in case of power failure),
and calculations will be skipped for one sample.
The function returns a DXDONE message when the operation is complete.
828
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PCFL-INTEG: Integrate Input at Specified Interval
Representation: PCFL - INTG - Integrate Input at Specified Interval
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
INTG
ERROR
parameter
block
PCFL
#16
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
INTG
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction INTEG
4x
16
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored. For more information,
see p. 830.
INT, UINT
Length of parameter block for subfunction
INTEG (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
829
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PCFL-INTEG: Integrate Input at Specified Interval
Parameter Description
Parameter Block
(Middle Node)
The length of the INTEG parameter block is 16 registers.
Register
Content
Displayed and first implied
Current Input
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Last input
12th and 13th implied
Reset value
14th and 15th implied
Result
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1...8
Not used
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
Reset sum
6 ... 16
Not used
830
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PCFL-KPID: Comprehensive
ISA Non Interacting PID
128
At a Glance
Introduction
This chapter describes the subfunction PCFL-KPID.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
832
Representation: PCFL - KPID - Comprehensive ISA Non-Interacting
Proportional-Integral-Derivative
833
Parameter Description
834
831
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PCFL-KPID: Comprehensive ISA Non Interacting PID
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The KPID function offers a superset of the functionality of the PID function, with
additional features that include:
z A gain reduction zone
z A separate register for bumpless transfer when the integral term is not used
z A reset mode
z An external set point for cascade control
z Built-in velocity limiters for set point changes and changes to a manual output
z A variable derivative filter constant
z Optional expansion of anti-reset wind-up limits
832
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PCFL-KPID: Comprehensive ISA Non Interacting PID
Representation: PCFL - KPID - Comprehensive ISA Non-Interacting
Proportional-Integral-Derivative
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
KPID
ERROR
parameter
block
PCFL
#64
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control function
KPID
(top node)
parameter
block
(middle node)
Selection of the subfunction KPID
4x
64
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information, see p. 834.
INT, UINT
Length of parameter block for subfunction KPID
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
833
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PCFL-KPID: Comprehensive ISA Non Interacting PID
Parameter Description
Parameter Block
(Middle Node)
The length of the KPID parameter block is 64 registers.
Register
General
Parameters
Input
Parameters
Inputs
Content
Displayed and first implied Live input, x
Second implied
Output Status, Register 1
Third implied
Output Status, Register 2
Fourth implied
Reserved
Fifth implied
Input Status
Sixth and seventh implied
Proportional rate, KP
Eighth and ninth implied
Reset time, TI
10th and 11th implied
Derivative action time, TD
12th and 13th implied
Delay time constant, TD1
14th and 15th implied
Gain reduction zone, GRZ
16th and 17th implied
Gain reduction in GRZ, KGRZ
18th and 19th implied
Limit rise of manual set point value
20th and 21st implied
Limit rise of manual output
22nd and 23rd implied
High limit for Y
24th and 25th implied
Low limit for Y
26th and 27th implied
Expansion for anti-reset wind-up limits
28th and 29th implied
External set point for cascade
30th and 31st implied
Manual set point
32nd and 33rd implied
Manual Y
34th and 35th implied
Reset for Y
36th and 37th implied
Bias
834
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PCFL-KPID: Comprehensive ISA Non Interacting PID
Outputs
Timing
Information
Output
Register
Content
38th and 39th implied
Bumpless transfer register, BT
40th and 41st implied
Calculated control difference (error term), XD
42nd implied
Previous operating mode
43rd and 44th implied
Dt (in ms) since last solve
45th and 46th implied
Previous system deviation, XD_1
47th and 48th implied
Previous input, X_1
49th and 50th implied
Integral part for Y, YI
51st and 52nd implied
Differential part for Y, YD
53rd and 54th implied
Set point, SP
55th and 56th implied
Proportional part for Y, YP
57th implied
Previous operating status
58th implied
10 ms clock at time n
59th implied
Reserved
60th and 61th implied
Solution interval (in ms)
62th and 63th implied
Manipulated output variable, Y
Output Status,
Register 1
1
2
3
4
5
6
7
8
Bit
Function
1
Error
2
1 = low limit exceeded
3
1 = high limit exceeded
4
1 = Cascade mode selected
5
1 = Auto mode selected
6
1 = Halt mode selected
7
1 = Manual mode selected
8
1 = Reset mode selected
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
835
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PCFL-KPID: Comprehensive ISA Non Interacting PID
Output Status,
Register 2
1
2
3
4
5
6
7
8
Bit
Function
1...4
Not used
5
1 = Previous D mode selected
6
1 = Previous I mode selected
7
1 = Previous P mode selected
8
1 = Previous mode selected
9 ... 16
Not used
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = Reset mode
6
1 = Manual mode
7
1 = Halt mode
8
1 = Cascade mode
9
1 = Solve proportional algorithm
10
1 = Solve integral algorithm
11
1 = Solve derivative algorithm
12
1 = solve derivative algorithm based on x
0 = solve derivative algorithm based on xd
13
1 = anti--reset wind-up on YI only
0 = normal anti--reset wind-up
14
1 = disable bumpless transfer
0 = bumpless transfer
15
1 = Manual Y tracks Y
16
1 = reverse action for loop output
0 = direct action for loop output
836
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PCFL-LIMIT: Limiter for the Pv
129
At a Glance
Introduction
This chapter describes the subfunction PCFL-LIMIT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
838
Representation: PCFL - LIMIT - Limiter for the P(v)
839
Parameter Description
840
837
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PCFL-LIMIT: Limiter for the Pv
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The LIMIT function limits the input to a range between a specified high and low
value. If the high or low limit is reached, the function sets an H or L flag and clamps
the output.
LIMIT returns a DXDONE message when the operation is complete.
838
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PCFL-LIMIT: Limiter for the Pv
Representation: PCFL - LIMIT - Limiter for the P(v)
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
LIMIT
ERROR
parameter
block
PCFL
#9
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
LIMIT
(top node)
parameter
block
(middle node)
Selection of the subfunction LIMIT
4x
9
(bottom node)
INT, UINT
First in a block of contiguous holding
registers where the parameters for the
specified subfunction are stored. For more
information, see p. 840.
INT, UINT
Length of parameter block for subfunction
LIMIT (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
839
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PCFL-LIMIT: Limiter for the Pv
Parameter Description
Parameter Block
(Middle Node)
The length of the LIMIT parameter block is 9 registers.
Register
Content
Displayed and first implied
Current input
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Low limit
Sixth and seventh implied
High Limit
Eighth implied
Output register
Output Status
1
2
3
4
5
6
7
8
9
10
11
Bit
Function
1...8
Not used
9
1 = input < low limit
10
1 = input > high limit
11
1 = invalid high/low limits (e.g., low t high
12 ... 16
Standard output bits (flags)
12
13
14
15
16
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
9
10
11
840
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PCFL-LIMV: Velocity Limiter
for Changes in the Pv
130
At a Glance
Introduction
This chapter describes the subfunction PCFL-LIMV.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
842
Representation: PCFL - LIMV - Velocity Limiter for Changes in the P(v)
843
Parameter Description
844
841
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PCFL-LIMV: Velocity Limiter for Changes in the Pv
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The LIMV function limits the velocity of change in the input variable between a
specified high and low value. If the high or low limit is reached, the function sets an
H or L flag and clamps the output.
LIMV returns a DXDONE message when the operation is complete.
842
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PCFL-LIMV: Velocity Limiter for Changes in the Pv
Representation: PCFL - LIMV - Velocity Limiter for Changes in the P(v)
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
LIMV
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
LIMV
(top node)
parameter
block
(middle node)
Selection of the subfunction LIMV
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For expanded and detailed information
please see p. 844.)
INT, UINT
Length of parameter block for subfunction
LIMV (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
843
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PCFL-LIMV: Velocity Limiter for Changes in the Pv
Parameter Description
Parameter Block
(Middle Node)
The length of the LIMV parameter block is 14 registers.
Register
Content
Displayed and first implied
Input register
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Velocity limit / sec
12th and 13th implied
Result
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1...5
Not used
6
1 = negative velocity limit
7
1 = input < low limit
8
1 = input > high limit
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
844
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PCFL-LKUP: Look-up Table
131
At a Glance
Introduction
This chapter describes the subfunction PCFL-LKUP.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
846
Representation: PCFL - LKUP - Look-up Table
847
Parameter Description
848
845
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PCFL-LKUP: Look-up Table
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The LKUP function establishes a look-up table using a linear algorithm to interpolate
between points. LKUP can handle variable point intervals and variable numbers
of points.
846
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PCFL-LKUP: Look-up Table
Representation: PCFL - LKUP - Look-up Table
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
LKUP
ERROR
parameter
block
PCFL
#39
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
LKUP
(top node)
parameter
block
(middle node)
Selection of the subfunction LKUP
4x
39
(bottom node)
INT, UINT
First in a block of contiguous holding
registers where the parameters for the
specified subfunction are stored
(For more information, please see p. 849.)
INT, UINT
Length of parameter block for subfunction
LKUP (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
847
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PCFL-LKUP: Look-up Table
Parameter Description
Mode of
Functioning
The LKUP function establishes a look-up table using a linear algorithm to interpolate
between points. LKUP can handle variable point intervals and variable numbers
of points.
If the input (x) is outside the specified range of points, the output (y) is clamped to
the corresponding output y0 or yn. If the specified parameter block length is too
small or if the number of points is out of range, the function does not check the xn
because the information from that pointer is invalid.
Points to be interpolated are determined by a binary search algorithm starting near
the center of x data. The search is valid for x1 < x < xn. The variable x may occur
multiple times with the same value, the value chosen from the look-up table is the
first instance found.
For example, if the table is:
x
y
10.0
1.0
20.0
2.0
30.0
3.0
30.0
3.5
40.0
4.0
then an input of 30.0 finds the first instance of 30.0 and assigns 3.0 as the output.
An input of 31.0 would assign the value 3.55 as the output.
No sorting is done on the contents of the lookup table. Independent variable table
values should be entered in ascending order to prevent unreachable gaps in
the table.
The function returns a DXDONE message when the operation is complete.
848
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PCFL-LKUP: Look-up Table
Parameter Block
(Middle Node)
The length of the LKUP parameter block is 39 registers.
Register
Content
Displayed and first implied
Input
Second implied
Output status
Third implied
Input status
Fourth implied
Number of point pairs
Fifth and sixth implied
Point x1
Seventh and eighth implied
Point y1
Ninth and tenth implied
Point x2
11th and 12th implied
Point y2
...
...
33rd and 34th implied
Point x8
35th and 36th implied
Point y8
37th and 38th implied
Output
Output Status
1
2
3
4
5
6
7
8
9
10
11
Bit
Function
1 ... 9
Not used
10
1 = input clamped, i.e. out of table’s range
11
! = invalid number of points
12 ... 16
Standard output bits (flags)
12
13
14
15
16
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
9
10
11
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PCFL-LKUP: Look-up Table
850
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PCFL-LLAG: First-order
Lead/Lag Filter
132
At a Glance
Introduction
This chapter describes the subfunction PCFL-LLAG.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
852
Representation: PCFL - LLAG - First-Order Lead/Lag Filter
853
Parameter Description
854
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PCFL-LLAG: First-order Lead/Lag Filter
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The LLAG function provides dynamic compensation for a known disturbance. It
usually appears in a feed-forward algorithm or as a dynamic filter. LLAG passes the
input through a filter comprising a lead term (a numerator) and a lag term (a
denominator) in the frequency domain, then multiplies it by a gain. Lead, lag, gain,
and solution interval must be user-specified.
For best results, use lead and lag terms that are t 4 *'t. This will ensure sufficient
granularity in the output response.
LLAG returns a DXDONE message when the operation completes
852
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PCFL-LLAG: First-order Lead/Lag Filter
Representation: PCFL - LLAG - First-Order Lead/Lag Filter
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
LLAG
ERROR
parameter
block
PCFL
#20
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
LLAG
(top node)
parameter
block
(middle node)
Selection of the subfunction LLAG
4x
20
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For more information, please see p. 854.)
INT, UINT
Length of parameter block for subfunction
LLAG (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
853
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PCFL-LLAG: First-order Lead/Lag Filter
Parameter Description
Parameter Block
(Middle Node)
The length of the LLAG parameter block is 20 registers.
Register
Content
Displayed and first implied
Current Input
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Last input
12th and 13th implied
Lead term
14th and 15th implied
Lag term
16th and 17th implied
Filter gain
18th and 19th implied
Result
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1...8
Not used
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
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PCFL-MODE: Put Input in
Auto or Manual Mode
133
At a Glance
Introduction
This chapter describes the subfunction PCFL-MODE.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
856
Representation: PCFL - MODE - Put Input in Auto or Manual Mode
857
Parameter Description
858
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PCFL-MODE: Put Input in Auto or Manual Mode
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The MODE function sets up a manual or automatic station for enabling and disabling
data transfers to the next block. The function acts like a BLKM instruction, moving a
value to the output register.
In auto mode, the input is copied to the output. In manual mode, the output is
overwritten by a user entry.
MODE returns a DXDONE message when the operation completes.
856
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PCFL-MODE: Put Input in Auto or Manual Mode
Representation: PCFL - MODE - Put Input in Auto or Manual Mode
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
MODE
ERROR
parameter
block
PCFL
#8
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
MODE
(top node)
parameter
block
(middle node)
Selection of the subfunction MODE
4x
8
(bottom node)
INT, UINT
First in a block of contiguous holding
registers where the parameters for the
specified subfunction are stored
(For more information, please see p. 858.)
INT, UINT
Length of parameter block for subfunction
MODE (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
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PCFL-MODE: Put Input in Auto or Manual Mode
Parameter Description
Parameter Block
(Middle Node)
The length of the MODE parameter block is 8 registers.
Register
Content
Displayed and first implied
Input
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Manual input
Sixth and seventh implied
Output register
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 10
Not used
11
Echo mode:
1 = manual mode
0 = auto mode
12 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = manual mode
0 = auto mode
6 ... 16
Not used
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PCFL-ONOFF: ON/OFF
Values for Deadband
134
At a Glance
Introduction
This chapter describes the subfunction PCFL-ONOFF.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
860
Representation: PCFL - ONOFF - Specifies ON/OFF Values for Deadband
861
Parameter Description
862
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PCFL-ONOFF: ON/OFF Values for Deadband
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The ONOFF function is used to control the output signal between fully ON and fully
OFF conditions so that a user can manually force the output ON or OFF.
You can control the output via either a direct or reverse configuration:
Configuration IF Input...
Then Output...
Direct
< (SP - DB)
ON
> (SP + DB)
OFF
> (SP + DB)
ON
< (SP - DB)
OFF
Revers
Manual Override
Two bits in the input status register (the third implied register in the parameter block)
are used for manual override. When bit 6 is set to 1, manual mode is enforced. In
manual mode, a 0 in bit 7 forces the output OFF, and a 1 in bit 7 forces the output
ON. The state of bit 7 has meaning only in manual mode.
860
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PCFL-ONOFF: ON/OFF Values for Deadband
Representation: PCFL - ONOFF - Specifies ON/OFF Values for Deadband
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
ONOFF
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process
control function
ONOFF
(top node)
parameter
block
(middle node)
Selection of the subfunction ONOFF
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored. (For more information,
please see p. 862.)
INT, UINT
Length of parameter block for subfunction
ONOFF (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
861
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PCFL-ONOFF: ON/OFF Values for Deadband
Parameter Description
Parameter Block
(Middle Node)
The length of the ONOFF parameter block is 14 registers.
Register
Content
Displayed and first implied
Current Input
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Set point, SP
Sixth and seventh implied
Deadband (DB) around SP
Eighth and ninth implied
Fully ON (maximum output)
10th and 11th implied
Fully OFF (minimum output)
12th and 13th implied
Output, ON or OFF
Output Status
1
2
3
4
5
6
7
8
9
Bit
Function
1 ... 8
Not used
9
1 = DB set to negative number
10
Echo mode:
1 = manual override
0 = auto mode
11
1 = output set to ON
0 = output set to OFF
12 ... 16
Standard output bits (flags)
10
11
12
13
14
15
862
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PCFL-ONOFF: ON/OFF Values for Deadband
Input Status
1
2
3
4
5
6
7
8
9
10
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = reverse configuration
0 = direct configuration
6
1 = manual override
0 = auto mode
7
1 = force output ON in manual mode
0 = force output OFF in manual mode
8 ... 16
Not used
11
12
13
14
15
16
863
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PCFL-ONOFF: ON/OFF Values for Deadband
864
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PCFL-PI: ISA Non Interacting PI
135
At a Glance
Introduction
This chapter describes the subfunction PCFL-PI.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
866
Representation: PCFL - PI
867
Parameter Description
868
865
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PCFL-PI: ISA Non Interacting PI
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The PI function performs a simple proportional-integral operations using floating
point math. It features halt / manual / auto operation modes. It is similar to the PID
and KPID functions but does not contain as many options. It is available for higherspeed loops or inner loops in cascade strategies.
866
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PCFL-PI: ISA Non Interacting PI
Representation: PCFL - PI
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
PI
ERROR
parameter
block
PCFL
#36
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control function
PI
(top node)
parameter
block
(middle node)
Selection of the subfunction PI
4x
36
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored (For more information,
please see p. 868.)
INT, UINT
Length of parameter block for subfunction PI
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
867
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PCFL-PI: ISA Non Interacting PI
Parameter Description
Parameter Block
(Middle Node)
The length of the PI parameter block is 36 registers.
Register
General
Parameters
Inputs
Outputs
Timing
Information
Input
Parameters
Output
Content
Displayed and first implied Live input, x
Second implied
Output Status
Third implied
Error Word
Fourth implied
Reserved
Fifth implied
Input Status
Sixth and seventh implied
Set point, SP
Eighth and ninth implied
Manual output
10th and 11th implied
Calculated control difference (error), XD
12th implied
Previous operating mode
13th and 14th implied
Dt (in ms) since last solve
15th and 16th implied
Previous system deviation, XD_1
17th and 18th implied
Integral part of output Y
19th and 20th implied
Previous input, X_1
21st implied
Previous operating status
22nd implied
10 ms clock at time n
23rd implied
Reserved
24th and 25th implied
Solution interval (in ms)
26th and 27th implied
Proportional rate, KP
28th and 29th implied
Reset time, TI
30th and 31st implied
High limit on output Y
32nd and 33rd implied
Low limit on output Y
34th and 35th implied
Manipulated variable output, Y
868
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PCFL-PI: ISA Non Interacting PI
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1
Error
2
1 = low limit exceeded
3
1 = high limit exceeded
4 ... 8
Not used
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
15
16
Error Word
1
2
3
4
5
6
Bit
Function
1...11
Not used
12 ... 16
Error Description
7
8
Error Description
Bit
Meaning
12
13
14
15
16
1
0
1
1
0
Negative integral time constant
1
0
1
0
1
High/low limit error (low t high)
Input Status
1
2
3
4
5
6
7
8
9
Bit
Function
1 ... 4
Standard input bits (flags)
5
Not used
6
1 = Manual mode
7
1 = Halt mode
8 ... 15
Not used
16
1 = reverse action for loop output
0 = direct action for loop output
10
11
12
13
14
869
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PCFL-PI: ISA Non Interacting PI
870
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PCFL-PID: PID Algorithms
136
At a Glance
Introduction
This chapter describes the subfunction PCFL-PID.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
872
Representation: PCFL - PID - Algorithms
873
Parameter Description
874
871
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PCFL-PID: PID Algorithms
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The PID function performs ISA non-interacting proportional-integral-derivative (PID)
operations using floating point math. Because it uses FP math (unlike PID2), roundoff errors are negligible.
In the part "General Information" you will find A PID Example, p. 77.
872
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PCFL-PID: PID Algorithms
Representation: PCFL - PID - Algorithms
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
PID
ERROR
parameter
block
PCFL
#44
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
PID
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction PID
4x
44
(bottom node)
INT, UINT First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For more information, please see p. 874.)
INT, UINT Length of parameter block for subfunction PID
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
873
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PCFL-PID: PID Algorithms
Parameter Description
Parameter Block
(Middle Node)
The length of the KPID parameter block is 44 registers.
Register
Content
Displayed and first implied
Live input, x
Second implied
Output Status
Third implied
Error Word
Fourth implied
Reserved
Fifth implied
Input Status
Sixth and seventh implied
Set point, SP
Eighth and ninth implied
Manual output
10th and 11th implied
Summing junction, Bias
12th and 13th implied
Error, XD
14th implied
Previous operating mode
15th and 16th implied
Elapsed time (in ms) since last solve
17th and 18th implied
Previous system deviation, XD_1
19th and 20th implied
Previous input, X_1
21st and 22nd implied
Integral part of output Y, YI
23rd and 24th implied
Differential part of output Y, YD
25th and 26th implied
Proportional part of output Y, YP
27th implied
Previous operating status
Timing
Information
28th implied
Current time
29th implied
Reserved
Inputs
30th and 31st implied
Solution interval (in ms)
34th and 35th implied
Reset time, TI
36th and 37th implied
Derivative action time, TD
38th and 39th implied
High limit on output Y
40th and 41st implied
Low limit on output Y
42nd and 43rd implied
Manipulated control output, Y
General
Parameters
Inputs
Outputs
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PCFL-PID: PID Algorithms
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1
Error
2
1 = low limit exceeded
3
1 = high limit exceeded
4 ... 8
Not used
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Error Word
1
2
3
4
5
6
7
Bit
Function
1...11
Not used
12 ... 16
Error Description
8
Error Description
Bit
Meaning
12
13
14
15
16
1
0
1
1
1
Negative derivative time constant
1
0
1
1
0
Negative integral time constant
1
0
1
0
1
High/low limit error (low t high)
875
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PCFL-PID: PID Algorithms
Input Status
1
2
3
4
5
6
7
8
9
10
11
Bit
Function
1 ... 4
Standard input bits (flags)
5
Not used
6
1 = Manual mode
7
1 = Halt mode
8
Not used
9
1 = Solve proportional algorithm
10
1 = Solve integral algorithm
11
1 = Solve derivative algorithm
12
1 = solve derivative algorithm based on x
0 = solve derivative algorithm based on xd
13... 15
Not used
16
1 = reverse action for loop output
0 = direct action for loop output
12
13
14
15
876
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PCFL-RAMP: Ramp to Set
Point at a Constant Rate
137
At a Glance
Introduction
This chapter describes the subfunction PCFL-RAMP.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
878
Representation: PCFL - RAMP - Ramp to Set Point at Constant Rate
879
Parameter Description
880
877
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PCFL-RAMP: Ramp to Set Point at a Constant Rate
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The RAMP function allows you to ramp up linearly to a target set point at a specified
approach rate.
You need to specify:
z The target set point, in the same units as the contents of the input register are
specified
z The sampling rate
z A positive rate toward the target set point, negative rates are illegal
The direction of the ramp depends on the relationship between the target set point
and the input, i.e. if x < SP, the ramp is up; if x > SP, the ramp is down.
You may use a flag to initialize after an undetermined down-time. The function will
store a new sample, then wait for one cycle to collect the second sample.
Calculations will be skipped for one cycle and the output will be left as is, after which
the ramp will resume.
RAMP terminates when the entire ramping operation is complete (over multiple
scans) and returns a DXDONE message.
Starting the
Ramp
The following steps need to be done when starting the ramp (up/down) and each
and every time you need to start or restart the ramp.
Step
Action
1
Set bit 1 of the standard input bits to "1" (third implied register of the
parameter block).
2
Retoggle the top input (enable input) to the instruction. Ramp will now start to ramp
up/down from the initial value previously configured up/down to the previously
configured setpoint. Monitor the 12th implied register of the parameter block for
floating point value of the ramp value in progress.
878
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PCFL-RAMP: Ramp to Set Point at a Constant Rate
Representation: PCFL - RAMP - Ramp to Set Point at Constant Rate
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
RAMP
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control function
RAMP
(top node)
parameter
block
(middle node)
Selection of the subfunction RAMP
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For more information, please see p. 880.)
INT, UINT
Length of parameter block for subfunction
RAMP (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
879
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PCFL-RAMP: Ramp to Set Point at a Constant Rate
Parameter Description
Parameter Block
(Middle Node)
The length of the RAMP parameter block is 14 registers.
Register
Content
Displayed and first implied
Set point (Input)
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Rate of change (per second) toward set point
12th and 13th implied
Output
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Not used
5
1 = ramp rate is negative
6
1 = ramp complete
0 = ramp in progress
7
1 = ramping down
8
1 = ramping up
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
880
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PCFL-RAMP: Ramp to Set Point at a Constant Rate
Top Output
(Operation
Succesfull)
The top output of the PCFL subfunction RAMP goes active at each successive
discrete ramp step up/down. It happens so fast that it appears to be solidly on. This
top output should NOT be used as "Ramp done bit".
Bit 6 of the output status (second impied register of the parameter block) should be
monitored as "Ramp done bit".
881
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PCFL-RAMP: Ramp to Set Point at a Constant Rate
882
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PCFL-RATE: Derivative
Rate Calculation over a
Specified Timeme
138
At a Glance
Introduction
This chapter describes the subfunction PCFL-RATE.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
884
Representation: PCFL - RATE - Derivative Rate Calculation Over a
Specified Time
885
Parameter Description
886
883
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PCFL-RATE: Derivative Rate Calculation over a Specified Time
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The RATE function calculates the rate of change over the last two input values.
If you set an initialization flag, the function records a sample and sets the
appropriate flags.
If a divide-by-zero operation is attempted, the function returns a
DXERROR message.
It returns a DXDONE message when the operation completes successfully.
884
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PCFL-RATE: Derivative Rate Calculation over a Specified Time
Representation: PCFL - RATE - Derivative Rate Calculation
Over a Specified Time
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
RATE
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
RATE
(top node)
parameter
block
(middle node)
ON = enables specified process
control function
Selection of the subfunction RATE
4x
14
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For more information, please see p. 886.)
INT, UINT
Length of parameter block for subfunction
RATE (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
885
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PCFL-RATE: Derivative Rate Calculation over a Specified Time
Parameter Description
Parameter Block
(Middle Node)
The length of the RATE parameter block is 14 registers.
Register
Content
Displayed and first implied Current input
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Last input
12th and 13th implied
Result
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 8
Not used
9 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
886
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PCFL-RATIO: Four
Station Ratio Controller
139
At a Glance
Introduction
This chapter describes the subfunction PCFL-RATIO.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
888
Representation: PCFL - RATIO - Four-Station Ratio Controller
889
Parameter Description
890
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PCFL-RATIO: Four Station Ratio Controller
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The RATIO function provides a four-station ratio controller. Ratio control can be
used in applications where one or more raw ingredients are dependent on a primary
ingredient. The primary ingredient is measured, and the measurement is converted
to engineering units via an AIN function. The converted value is used to set the
target for the other ratioed inputs.
Outputs from the ratio controller can provide set points for other controllers.
They can also be used in an open loop structure for applications where feedback is
not required.
888
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PCFL-RATIO: Four Station Ratio Controller
Representation: PCFL - RATIO - Four-Station Ratio Controller
Symbol
Representation of the instruction
CONTROL INPUT
0PERATION SUCCESSFUL
RATIO
ERROR
parameter
block
PCFL
#20
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process
control function
RATIO
(top node)
parameter
block
(middle node)
Selection of the subfunction RATIO
4x
20
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information. please see p. 890.)
INT, UINT
Length of parameter block for subfunction
RATIO (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
889
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PCFL-RATIO: Four Station Ratio Controller
Parameter Description
Parameter Block
(Middle Node)
The length of the RATIO parameter block is 20 registers.
Register
Content
Displayed and first implied
Live input
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Ratio for input 1
Sixth and seventh implied
Ratio for input 2
Eighth and ninth implied
Ratio for input 3
10th and 11th implied
Ratio for input 4
12th and 13th implied
Output for input 1
14th and 15th implied
Output for input 2
16th and 17th implied
Output for input 3
18th and 19th implied
Output for input 4
Output Status
1
2
3
4
5
6
7
8
9
Bit
Function
1 ... 9
Not used
10
1 = parameter(s) out of range
11
1 = no inputs activated
12 ... 16
Standard output bits (flags)
10
11
12
13
14
15
890
16
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PCFL-RATIO: Four Station Ratio Controller
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
1= input 4 active
6
1= input 3 active
7
1= input 2 active
8
1= input 1 active
9 ... 16
Not used
9
10
11
12
13
14
15
16
891
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PCFL-RATIO: Four Station Ratio Controller
892
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PCFL-RMPLN: Logarithmic
Ramp to Set Point
140
At a Glance
Introduction
This chapter describes the subfunction PCFL-RMPLN.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
894
Representation: PCFL - RMPLN - Logarithmic Ramp to Set Point
895
Parameter Description
896
893
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PCFL-RMPLN: Logarithmic Ramp to Set Point
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The RMPLN function allows you to ramp up logarithmically to a target set point at a
specified approach rate. At each successive call, it calculates the output until it is
within a specified deadband (DB). DB is necessary because the incremental
distance the ramp crosses decreases with each solve.
You need to specify:
The target set point, in the same units as the contents of the input register are
specified
z The sampling rate
z The time constant used for the logarithmic ramp, which is the time it takes to
reach 63.2% of the new set point
z
For best results, use a t that is t4 *'t. This will ensure sufficient granularity in the
output response.
You may use a flag to initialize after an undetermined down-time. The function will
store a new sample, then wait for one cycle to collect the second sample.
Calculations will be skipped for one cycle and the output will be left as is, after which
the ramp will resume.
RMPLN terminates when the input reaches the target set point + the specified DB
and returns a DXDONE message.
894
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PCFL-RMPLN: Logarithmic Ramp to Set Point
Representation: PCFL - RMPLN - Logarithmic Ramp to Set Point
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
RMPLN
ERROR
parameter
block
PCFL
#16
Parameter
Description
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
RMPLN
(top node)
parameter
block
(middle node)
ON = enables specified process control function
Selection of the subfunction RMPLN
4x
16
(bottom node)
INT, UINT
First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
For more information, please see p. 896.)
INT, UINT
Length of parameter block for subfunction
RMPLN (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
895
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PCFL-RMPLN: Logarithmic Ramp to Set Point
Parameter Description
Parameter Block
(Middle Node)
The length of the RMPLN parameter block is 16 registers.
Register
Content
Displayed and first implied
Set point (Input)
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
10th and 11th implied
Time constant, W, (per second) of exponential ramp toward the
target set point
12th and 13th implied
DB (in engineering units)
14th and 15th implied
Output
Output Status
1
2
3
4
5
6
7
8
9
Bit
Function
1 ... 4
Not used
5
1 = DB or W set to negative units
6
1 = ramp complete
0 = ramp in progress
7
1 = ramping down
8
1 = ramping up
9 ... 16
Standard output bits (flags)
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5 ... 16
Not used
9
896
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PCFL-SEL: Input Selection
141
At a Glance
Introduction
This chapter describes the subfunction PCFL-SEL.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
898
Representation: PCFL - SEL - High/Low/Average Input Selection
899
Parameter Description
900
897
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PCFL-SEL: Input Selection
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Signal Processing.
The SEL function compares up to four inputs and makes a selection based upon
either the highest, lowest, or average value. You choose the inputs to be compared
and the comparison criterion. The output is a copy of the selected input.
SEL returns a DXDONE message when the operation is complete.
898
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PCFL-SEL: Input Selection
Representation: PCFL - SEL - High/Low/Average Input Selection
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
SEL
ERROR
parameter
block
PCFL
#14
Parameter
Description
Parameters
State RAM
Reference
Data
Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control function
SEL
(top node)
Selection of the subfunction SEL
4x
parameter
block
(middle node)
INT, UINT First in a block of contiguous holding registers
where the parameters for the specified
subfunction are stored
(For more information, please see p. 900.)
14
(bottom node)
INT, UINT Length of parameter block for subfunction SEL
(can not be changed)
Top output
0x
None
ON = operation successful
Bottom output 0x
None
ON = error
899
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PCFL-SEL: Input Selection
Parameter Description
Parameter Block
(Middle Node)
The length of the SEL parameter block is 14 registers.
Register
Content
Displayed and first implied
Reserved
Second implied
Output status
Third implied
Input status
Fourth and fifth implied
Input 1
Sixth and seventh implied
Input 2
Eighth and ninth implied
Input 3
10th and 11th implied
Input 4
12th and 13th implied
Output
Output Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 9
Not used
10
Invalid selection modes
11
No inputs selected
12 ... 16
Standard output bits (flags)
9
10
11
12
13
14
15
900
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PCFL-SEL: Input Selection
Input Status
1
2
3
4
5
6
7
8
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = enable input 1
0 = disable input 1
6
1 = enable input 2
0 = dyeable input 2
7
1 = enable input 3
0 = dyeable input 3
8
1 = enable input 4
0 = dyeable input 4
9 ... 10
Selection mode
11 ... 16
Not used
9
10
11
12
13
14
15
16
Selection mode
Bit
Meaning
9
10
0
0
Select average
0
1
Select high
1
0
Select low
1
1
reserved / invalid
901
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PCFL-SEL: Input Selection
902
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PCFL-TOTAL: Totalizer
for Metering Flow
142
At a Glance
Introduction
This chapter describes the subfunction PCFL-TOTAL.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
904
Representation: PCFL - TOTAL - Totalizer for Metering Flow
905
Parameter Description
906
903
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PCFL-TOTAL: Totalizer for Metering Flow
Short Description
Function
Description
Note: This instruction is a subfunction of the PCFL instruction. It belongs to the
category Regulatory Control.
The TOTAL function provides a material totalizer for batch processing reagents. The
input signal contains the units of weight or volume per unit of time. The totalizer
integrates the input over time.
The algorithm reports three outputs:
The integration sum
z The remainder left to meter in
z The valve output (in engineering units).
z
904
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PCFL-TOTAL: Totalizer for Metering Flow
Representation: PCFL - TOTAL - Totalizer for Metering Flow
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
TOTAL
ERROR
parameter
block
PCFL
#28
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables specified process control
function
TOTAL
(top node)
parameter
block
(middle node)
Selection of the subfunction TOTAL
4x
28
(bottom node)
INT, UINT
First in a block of contiguous holding
registers where the parameters for the
specified subfunction are stored
(For more information, please see p. 906.)
INT, UINT
Length of parameter block for subfunction
TOTAL (can not be changed)
Top output
0x
None
ON = operation successful
Bottom output
0x
None
ON = error
905
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PCFL-TOTAL: Totalizer for Metering Flow
Parameter Description
Mode of
Functioning
The function uses up to three different set points:
A trickle flow set point
z A target set point
z An auxiliary trickle flow set point
z
The target set point is for the full amount to be metered in. Here the output will be
turned OFF.
The trickle flow set point is the cut-off point when the output should be decreased
from full flow to a percentage of full flow so that the target set point is reached with
better granularity.
The auxiliary trickle flow set point is optional. It is used to gain another level of
granularity. If this set point is enabled, the output is reduced further to 10% of the
trickle output.
The totalizer works from zero as a base point. The set point must be a positive value
In normal operation, the valve output is set to 100% flow when the integrated value
is below the trickle flow set point. When the sum crosses the trickle flow set point,
the valve flow becomes a programmable percentage of full flow. When the sum
reaches the desired target set point, the valve output is set to 0% flow.
Set points can be relative or absolute. With a relative set point, the deviation
between the last summation and the set point is used. Otherwise, the summation is
used in absolute comparison to the set point.
There is a halt option to stop the system from integrating.
When the operation has finished, the output summation is retained for future use.
You have the option of clearing this sum. In some applications, it is important to save
the sum, e.g. if the meters or load cells cannot handle the full batch in one charge
and measurements are split up, if there are several tanks to fill for a batch and you
want to keep track of batch and production sums.
Parameter Block
(Middle Node)
The length of the TOTAL parameter block is 28 registers.
Register
Content
Displayed and first implied
Live input
Second implied
Output status
Third implied
Input status
Fourth implied
Time register
Fifth implied
Reserved
Sixth and seventh implied
't (in ms) since last solve
Eighth and ninth implied
Solution interval (in ms)
906
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PCFL-TOTAL: Totalizer for Metering Flow
Register
Content
10th and 11th implied
Last input, X_1
12th and 13th implied
Reset value
14th and 15th implied
Set point, target
16th and 17th implied
Set point, trickle flow
18th and 19th implied
% of full flow for trickle flow set point
20th and 21st implied
Full flow
22nd and 23rd implied
Remaining amount to SP
24th and 25th implied
Resulting sum
26th and 27th implied
Output for final control element
Output Status
1
2
3
4
5
6
7
8
9
10
11
12
Bit
Function
1 ... 2
Not used
3 ... 4
0 0 = OFF
0 1 = trickle flow
1 0 = full flow
5
1 = operation done
6
1 = totalizer running
7
1 = overshoot past set point by more than 5%
8
1 = parameter(s) out of range
9 ... 16
Standard output bits (flags)
13
14
15
16
907
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PCFL-TOTAL: Totalizer for Metering Flow
Input Status
1
2
3
4
5
6
7
8
9
10
Bit
Function
1 ... 4
Standard input bits (flags)
5
1 = reset sum
6
1 = halt integration
7
1 = deviation set point
0 = absolute set point
8
1 = use auxiliary trickle flow set point
9 ... 16
Not used
11
12
13
14
15
908
16
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PEER: PEER Transaction
143
At a Glance
Introduction
This chapter describes the instruction PEER.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
910
Representation: PEER - Modbus II Identical Transfer
911
Parameter Description
912
909
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PEER: PEER Transaction
Short Description
Function
Description
Note: This instruction is only available if you have unpacked and installed the DX
Loadables. For further information, see p. 101.
The S975 Modbus II Interface option modules use two loadable function blocks:
MBUS and PEER. The PEER instruction can initiate identical message transactions
with as many as 16 devices on Modbus II at one time. In a PEER transaction, you
may only write register data.
910
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PEER: PEER Transaction
Representation: PEER - Modbus II Identical Transfer
Symbol
Representation of the instruction
CONTROL INPUT
COMPLETE
control block
REPEAT
ACTIVE
data block
ERROR
PEER
Length: 1 - 249
Parameter
Description
length
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
Enable MBUS transaction
Middle input
0x, 1x
None
Repeat transaction in same scan
control block
(top node)
4x
INT, UINT, First of 19 contiguous registers in the PEER
WORD
control block (For more information, please
see p. 912.)
data block
(middle node)
4x
INT, UINT
First register in a data block to be transmitted
by the PEER function
INT, UINT
Length, i.e. the number of holding registers, of
the data block; range: 1 ... 249.
length
(bottom node)
Top output
0x
None
Transaction complete
Middle output
0x
None
Transaction in progress or new
transaction starting
Bottom output
0x
None
Error detected in transaction
911
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PEER: PEER Transaction
Parameter Description
Control Block
(Top Node)
The 4x register entered in the top node is the first of 19 contiguous registers in the
PEER control block.
Register
Function
Displayed
Indicates the status of the transactions at each device, the leftmost bit being
the status of device #1 and the rightmost bit the status of device #16: 0 =
OK, 1 = transaction error
First implied
Defines the reference to the first 4x register to be written to in the receiving
device; a 0 in this field is an invalid value and will produce an error (the
bottom output will go ON)
Second implied Time allowed for a transaction to be completed before an error is declared;
expressed as a multiple of 10 ms, e.g. 100 indicates 1,000 ms; the default
timeout is 250 ms
Third implied
The Modbus port 3 address of the first of the receiving devices; address
range: 1 ... 255 (0 = no transaction requested)
Fourth implied
The Modbus port 3 address of the second of the receiving devices; address
range: 1 ... 255 (0 = no transaction requested)
...
18th implied
...
The Modbus port 3 address of the 16th of the receiving devices (address
range: 1 ... 255)
912
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PID2: Proportional
Integral Derivative
144
At a Glance
Introduction
This chapter describes the instruction PID2.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
914
Representation: PID2 - Proportional/Integral/Derivative
915
Detailed Description
916
Parameter Description
919
Run Time Errors
924
913
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PID2: Proportional Integral Derivative
Short Description
Function
Description
The PID2 instruction implements an algorithm that performs proportional-integralderivative operations. The algorithm tunes the closed loop operation in a manner
similar to traditional pneumatic and analog electronic loop controllers. It uses a rate
gain limiting (RGL) filter on the PV as it is used for the derivative term only, thereby
filtering out higher-frequency PV noise sources (random and process generated).
Formula
Proportional Control
M V = K 1 E + bias
Proportional-Integral Control
MV
t
§
·
¨
= K 1 E + K 2 ³ E't¸
¨
¸
©
¹
0
Proportional-Integral-Derivative Control
MV
t
§
·
'PV
¨
= K 1 ¨ E + K 2 ³ E't + K 3 ------------¸¸
't
©
¹
0
914
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PID2: Proportional Integral Derivative
Representation: PID2 - Proportional/Integral/Derivative
Symbol
Representation of the instruction
MANUAL/AUTO
LOOP SOLUTION
source
INTEGRAL PRELOAD
HIGH ALARM
destination
Parameter
Description
DIRECT/REV. ACTION
PID2
Length: 1 - 255
solution
interval
LOW ALARM
Parameters
State RAM Reference Data Type Meaning
Top input
0x, 1x
None
0 = Manual mode
1 = Auto mode
Middle input
0x, 1x
None
0 = Integral preload OFF
1 = Integral preload ON
Bottom input
0x, 1x
None
0 = Output increases as E increases
1 = Output decreases as E decreases
source
(top node)
4x
INT, UINT First of 21 contiguous holding
registers in a source block. (For more
information, please see p. 919.)
destination
(middle node)
4x
INT, UINT First of nine contiguous holding
registers used for PID2 calculation.
Do not load anything in these
registers!. For more information,
please see p. 922.)
solution
interval
(bottom node)
INT, UINT Contains a number ranging from 1 ...
255, indicating how often the function
should be performed.
Top output
0x
None
1 = Invalid user parameter or Loop
ACTIVE but not being solved
Middle output
0x
None
1 = PV t high alarm limit
Bottom output
0x
None
1 = PV d low alarm limit
915
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PID2: Proportional Integral Derivative
Detailed Description
Block Diagram
+
Xn-1
Derivative
Contribution
Xn
Xn
+
(4y + 6)/8
+
PV
(4y + 6)/8
'Pv
-
'x
RGL
60(RGL - 1)K3
RGL Ts
Zn
4x13
+
SP
-
E
E
+
-
Proportional
Contribution
(4x1 - 4x2)
(4x11 - 4x12)
100
PB
x 4095
GE
+
Output
Clamp
+
Bias
4x8
Integral
Feedback
Mn-1
FIOC
4x16
M
+
Preload
Mode
TIOC
4x20
+
-
Qn
Integral
Clamp
Wn
+
-
In-1
In-1
4x17 4x2
4x18
Integral
Contribution
K2 T2
600000
Mn
In
'I
+
+
In
4y + 3, + 4, + 5
In
The elements in the block diagram have the following meaning:
Element
Meaning
E
Error, expressed in raw analog units
SP
Set point, in the range 0 ... 4095
PV
Process variable, in the range 0 ... 4095
x
Filtered PV
K2
Integral mode gain constant, expressed in 0.01 min-1
K3
Derivative mode gain constant, expressed in hundredths of a minute
916
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PID2: Proportional Integral Derivative
Element
Meaning
RGL
Rate gain limiting filter constant, in the range 2 ... 30
Ts
Solution time, expressed in hundredths of a second
PB
Proportional band, in the range 5 ... 500%
bias
Loop output bias factor, in the range 0 ... 4095
M
Loop output
GE
Gross error, the proportional-derivative contribution to the loop output
Z
Derivative mode contribution to GE
Qn
Unbiased loop output
F
Feedback value, in the range 0 ... 4095
I
Integral mode contribution to the loop output
Ilow
Anti-reset-windup low SP, in the range 0 ... 4095
Ihigh
Anti-reset-windup high SP, in the range 0 ... 4095
K1
100/PB
Note: The integral mode contribution calculation actually integrates the difference
of the output and the integral sum, this is effectively the same as integrating
the error.
Proportional
Control
With proportional-only control (P), you can calculate the manipulated variable by
multiplying error by a proportional constant, K1, then adding a bias. see p. 914.
However, process conditions in most applications are changed by other system
variables so that the bias does not remain constant; the result is offset error, where
PV is constantly offset from the SP. This condition limits the capability of
proportional-only control.
Note: The value in the integral term (in registers 4y + 3, 4y + 4, and 4y + 5) is
always used, even when the integral mode is not enabled. Using this value is
necessary to preserve bumpless transfer between modes. If you wish to disable
bumpless transfer, these three registers must be cleared.
In manual mode setpoint changes will not take effect unless the above three
registers are cleared and the mode is switched back to automatic. The transfer will
not be bumpless.
917
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PID2: Proportional Integral Derivative
ProportionalIntegral Control
To eliminate this offset error without forcing you to manually change the bias, an
integral function can be added to the control equation. see p. 914.
Proportional-integral control (PI) eliminates offset by integrating E as a function of
time. K1 is the integral constant expressed as rep/min. As long as E z 0, the
integrator increases (or decreases) its value, adjusting Mv. This continues until the
offset error is eliminated.
ProportionalIntegralDerivative
Control
You may want to add derivative functionality to the control equation to minimize the
effects of frequent load changes or to override the integral function in order to get to
the SP condition more quickly. see p. 914.
Example
An example to PID2 level control you will find in PID2 Level Control Example.
Proportional-integral-derivative (PID) control can be used to save energy in the
process or as a safety valve in the event of a sudden, unexpected change in process
flow. K3 is the derivative time constant expressed as min. DPV is the change in the
process variable over a time period of 't.
918
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PID2: Proportional Integral Derivative
Parameter Description
Source Block
(Top Node)
The 4x register entered in the top node is the first of 21 contiguous holding registers
in a source block. The contents of the fifth ... eighth implied registers determine
whether the operation will be P, PI, or PID:
Operation
Fifth Implied
Sixth Implied
P
ON
PI
ON
ON
PID
ON
ON
Seventh Implied Eighth Implied
ON
ON
The source block comprises the following register assignments:
Register
Name
Content
Displayed Scaled PV Loaded by the block each time it is scanned; a linear scaling is done
on register 4x + 13 using the high and low ranges from registers 4x
+ 11 and 4x + 12: Scaled PV = (4x13 / 4095) * (4x11 - 4x12) + 4x12
First
implied
SP
You must specify the set point in engineering units; the value must
be < value in the 11th implied register and > value in the 12th implied
register
Second
implied
Mv
Loaded by the block every time the loop is solved; it is clamped to a
range of 0 ... 4095, making the output compatible with an analog
output module; the manipulated variable register may be used for
further CPU calculations such as cascaded loops
Third
implied
High
Alarm
Limit
Load a value in this register to specify a high alarm for PV (at or
above SP); enter the value in engineering units within the range
specified in the 11th and 12th implied registers
Fourth
implied
Low Alarm Load a value in this register to specify a low alarm for PV (at or below
Limit
SP); enter the value in engineering units within the range specified
in the 11th and 12th implied registers
Fifth
implied
Proportion Load this register with the desired proportional constant in the range
al Band
5 ... 500; the smaller the number, the larger the proportional
contribution; a valid number is required in this register for PID2
to operate
Sixth
implied
Reset
Time
Constant
Load this register to add integral action to the calculation; enter a
value between 0000 ... 9999 to represent a range of 00.00 ... 99.99
repeats/min; the larger the number, the larger the integral
contribution; a value > 9999 stops the PID2 calculation
919
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PID2: Proportional Integral Derivative
Register
Name
Content
Seventh
implied
Rate Time Load this register to add derivative action to the calculation; enter a
Constant value between 0000 ... 9999 to represent a range of 00.00 ... 99.99
min; the larger the number, the larger the derivative contribution; a
value > 9999 stops the PID2 calculation
Eighth
implied
Bias
Load this register to add a bias to the output; the value must be
between 000 .... 4095, and added directly to Mv, whether the integral
term is enabled or not
Ninth
implied
High
Integral
Windup
Limit
Load this register with the upper limit of the output value (between 0
... 4095) where the anti-reset windup takes effect; the updating of the
integral sum is stopped if it goes above this value (this is normally
4095)
10th
implied
Low
Integral
Windup
Limit
Load this register with the lower limit of the output value (between 0
... 4095) where the anti-reset windup takes effect (this is normally 0)
11th
implied
High
Engineeri
ng Range
Load this register with the highest value for which the measurement
device is spanned, e.g. if a resistance temperature device ranges
from 0 ... 500 degrees C, the high engineering range value is 500;
the range must be given as a positive integer between 0001 ... 9999,
corresponding to the raw analog input 4095
12th
implied
Low
Engineeri
ng Range
Load this register with the lowest value for which the measurement
device is spanned; the range must be given as a positive integer
between 0 ... 9998, and it must be less than the value in the 11th
implied register; it corresponds to the raw analog input 0
13th
implied
Raw
Analog
Measurement
The logic program loads this register with PV; the measurement
must be scaled and linear in the range 0 ... 4095
14th
implied
Pointer to
Loop
Counter
Register
The value you load in this register points to the register that counts
the number of loops solved in each scan; the entry is determined by
discarding the most significant digit in the register where the
controller will count the loops solved/scan, e.g., if the PLC does the
count in register 41236, load 1236 into the 14th implied register; the
same value must be loaded into the 14th implied register in every
PID2 block in the logic program
15th
implied
Maximum Solved In a Scan: If the 14th implied register contains a non-zero
Number of value, you may load a value in this register to limit the number of
loops to be solved in one scan
Loops
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PID2: Proportional Integral Derivative
Register
Name
Content
16th
implied
Pointer To
Reset
Feedback
Input:
The value you load in this register points to the holding register that
contains the value of feedback (F); drop the 4 from the feedback
register and enter the remaining four digits in this register;
integration calculations depend on the F value being should F vary
from 0 ... 4095
17th
implied
Output
Clamp High
The value entered in this register determines the upper limit of Mv
(this is normally 4095)
18th
implied
Output
Clamp Low
The value entered in this register determines the lower limit of Mv
(this is normally 0)
19th
implied
Rate Gain
Limit
(RGL)
Constant
The value entered in this register determines the effective degree of
derivative filtering; the range is from 2 ... 30; the smaller the value,
the more filtering takes place
20th
implied
Pointer to
Integral
Preload
The value entered in this register points to the holding register
containing the track input (T) value; drop the 4 from the tracking
register and enter the remaining four digits in this register; the value
in the T register is connected to the input of the integral lag whenever
the auto bit and integral preload bit are both true
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PID2: Proportional Integral Derivative
Destination
(MIddle Node)
The 4y register entered in the middle node is the first of nine contiguous
holding register used for PID2 calculations. You do not need to load anything into
these registers:
Register
Name
Content
Displayed
Loop Status
Register
Twelve of the 16 bits in this register are used to define
loop status.
First implied
Error (E) Status Bits This register displays PID2 error codes.
Second
implied
Loop Timer
Register
This register stores the real-time clock reading on the
system clock each time the loop is solved: the
difference between the current clock value and the
value stored in the register is the elapsed time; if
elapsed time t solution interval (10 times the value
given in the bottom node of the PID2 block), then the
loop should be solved in this scan
Third implied
For Internal Use
Integral (integer portion)
Fourth implied For Internal Use
Integral-fraction 1 (1/3 000)
Fifth implied
For Internal Use
Integral-fraction 2 (1/600 000)
Sixth implied
Pv x 8 (Filtered)
This register stores the result of the filtered analog
input (from register 4x14) multiplied by 8; this value is
useful in derivative control operations
Seventh
implied
Absolute Value of E This register, which is updated after each loop
solution, contains the absolute value of (SP - PV); bit
8 in register 4y + 1 indicates the sign of E
Eighth implied For Internal Use
Current solution interval
Loop Status
Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Function
1
Top output status (Node lockout or parameter error
2
Middle output status (High alarm)
3
Bottom output status (Low alarm)
4
Loop in AUTO mode and time since last solution t solution interval
5
Wind-down mod (for REV B or higher)
6
Loop in AUTO mode but not being solved
7
4x14 register referenced by 4x15 is valid
8
Sign of E in 4y + 7:
z 0 = + (plus)
z 1 = - (minus)
922
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PID2: Proportional Integral Derivative
Bit
Function
9
Rev B or higher
10
Integral windup limit never set
11
Integral windup saturated
12
Negative values in the equation
13
Bottom input status (direct / reverse acting)
14
Middle input status (tracking mode)
z 1 = tracking
z 0 = no tracking
Solution Interval
(Bottom Node)
15
Top input status (MAN / AUTO)
16
Bit 16 is set after initial startup or installation of the loop. If you clear the bit, the
following actions take place in one scan:
z The loop status register 4y is reset
z The current value in the real-time clock is stored in the first implied register
(4y+1)
z Values in the third ... fifth registers (4y+2,3) are cleared
z The value in the13th implied register (4x+13) x 8 is stored in the sixth implied
register (4y+6)
z The seventh and eighth implied registers (4y+7,8) are cleared
The bottom node indicates that this is a PID2 function and contains a number
ranging from 1 ... 255, indicating how often the function should be performed. The
number represents a time value in tenths of a second, or example, the number 17
indicates that the PID function should be performed every 1.7 s.
923
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PID2: Proportional Integral Derivative
Run Time Errors
Error Status Bit
The first implied register of the destination contains the error status bits:
Code
Explanation
Check these Registers in the
Source Block (Top Node)
0000
No errors, all validations OK
None
0001
Scaled SP above 9999
First implied
0002
High alarm above 9999
Third implied
0003
Low alarm above 9999
Fourth implied
0004
Proportional band below 5
Fifth implied
0005
Proportional band above 500
Fifth implied
0006
Reset above 99.99 r/min
Sixth implied
0007
Rate above 99.99 min
Seventh implied
0008
Bias above 4095
Eighth implied
0009
High integral limit above 4095
Ninth implied
0010
Low integral limit above 4095
10th implied
0011
High engineering unit (E.U.) scale above 9999
11th implied
0012
Low E.U. scale above 9999
12th implied
0013
High E.U. below low E.U.
11th and 12th implied
0014
Scaled SP above high E.U.
First and 11th implied
0015
.Scaled SP below low E.U.
First and 12th implied
0016
Maximum loops/scan > 9999
Note: Activated by maximum loop feature, i.e.
only if 4x15 is not zero.
15th implied
0017
Reset feedback pointer out of range
16th implied
0018
High output clamp above 4095
17th implied
0019
Low output clamp above 4095
18th implied
0020
Low output clamp above high output clamp
17th and 18th implied
0021
RGL below 2
19th implied
0022
RGL above 30
19th implied
0023
Track F pointer out of range
Note: Activated only if the track feature is ON, i.e.
the middle input of the PID2 block is receiving
power while in AUTO mode.
20th implied with middle input
ON
924
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PID2: Proportional Integral Derivative
Code
Explanation
Check these Registers in the
Source Block (Top Node)
0024
Track F pointer is zero
20th implied with middle input
Note: Activated only if the track feature is ON, i.e. ON
the middle input of the PID2 block is receiving
power while in AUTO mode.
0025
None
Node locked out (short of scan time)
Note: Activated by maximum loop feature, i.e.
only if 4x15 is not zero.
Note: If lockout occurs often and the parameters
are all valid, increase the maximum number of
loops/scan. Lockout may also occur if the counting
registers in use are not cleared as required.
0026
Loop counter pointer is zero
Note: Activated by maximum loop feature, i.e.
only if 4x15 is not zero.
14th and 15th implied
0027
Loop counter pointer out of range
14th and 15th implied
925
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PID2: Proportional Integral Derivative
926
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Instruction Descriptions (R to Z)
VI
At a Glance
Introduction
In this part instruction descriptions are arranged alphabetically from R to Z.
What's in
this Part?
This part contains the following chapters:
Chapter
Chapter Name
Page
145
R --> T: Register to Table
929
146
RBIT: Reset Bit
933
147
READ: Read
937
148
RET: Return from a Subroutine
943
149
RTTI - Register to Input Table
947
150
RTTO - Register to Output Table
951
151
RTU - Remote Terminal Unit
955
152
SAVE: Save Flash
961
153
SBIT: Set Bit
965
154
SCIF: Sequential Control Interfaces
969
155
SENS: Sense
975
156
Shorts
979
157
SKP - Skipping Networks
983
158
SRCH: Search
987
159
STAT: Status
993
160
SU16: Subtract 16 Bit
1021
161
SUB: Subtraction
1025
162
SWAP - VME Bit Swap
1029
163
TTR - Table to Register
1033
164
T --> R Table to Register
1037
165
T --> T: Table to Table
1043
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Instruction Descriptions (R to Z)
Chapter
Chapter Name
Page
166
T.01 Timer: One Hundredth Second Timer
1049
167
T0.1 Timer: One Tenth Second Timer
1053
168
T1.0 Timer: One Second Timer
1057
169
T1MS Timer: One Millisecond Timer
1061
170
TBLK: Table to Block
1067
171
TEST: Test of 2 Values
1073
172
UCTR: Up Counter
1077
173
VMER - VME Read
1081
174
VMEW - VME Write
1085
175
WRIT: Write
1091
176
XMIT - Transmit
1097
177
XMIT Communication Block
1105
178
XMIT Port Status Block
1117
179
XMIT Conversion Block
1125
180
XMRD: Extended Memory Read
1133
181
XMWT: Extended Memory Write
1139
182
XOR: Exclusive OR
1145
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R --> T: Register to Table
145
At a Glance
Introduction
This chapter describes the instruction R o T.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
930
Representation: R o T - Register to Table Move
931
Parameter Description
932
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R --> T: Register to Table
Short Description
Function
Description
The RoT instruction copies the bit pattern of a register or of a string of contiguous
discretes stored in a word into a specific register located in a table. It can
accommodate the transfer of one register/word per scan.
930
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R --> T: Register to Table
Representation: R o T - Register to Table Move
Symbol
Representation of the instruction
CONTROL INPUT /
INCREASE POINTER
PREVENTS POINTER FROM
INCREASING
ACTIVE
source
POINTER = TABLE LENGTH
destination
pointer
RESET POINTER
RÆT
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Parameter
Description
table length
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = copies source data and increments the
pointer value
Middle input
0x, 1x
None
ON = freezes the pointer value
Bottom input
0x, 1x
None
ON = resets the pointer value to zero
source
(top node)
0x, 1x, 3x, 4x INT, UINT,
WORD
Source data to be copied in the current scan
destination
pointer
(middle node)
4x
INT, UINT
Destination table where source data will be
copied in the scan
INT, UINT
Number of registers in the destination table,
range: 1 ... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
table length
(bottom node)
Top output
0x
None
Echoes the state of the top input
Middle output
0x
None
ON = pointer value = table length (instruction
cannot increment any further)
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R --> T: Register to Table
Parameter Description
Top Input
The input to the top node initiates the DX move operation.
Middle Input
When the middle input goes ON, the current value stored in the destination pointer
register is frozen while the DX operation continues. This causes new data being
copied to the destination to overwrite the data copied on the previous scan.
Bottom Input
When the bottom input goes ON, the value in the destination pointer register is reset
to zero. This causes the next DX move operation to copy source data into the first
register in the destination table.
Source Data
(Top Node)
Destination
Pointer
(Middle Node)
When using register types 0x or 1x:
First 0x reference in a string of 16 contiguous coils or discrete outputs
z First 1x reference in a string of 16 discrete inputs
z
The 4x register entered in the middle node is a pointer to the destination table where
source data will be copied in the scan. The first register in the destination table is the
next contiguous 4x register following the pointer, i.e. if the pointer register is 400027,
then the destination table begins at register 400028.
The value posted in the pointer register indicates the register in the destination table
where the source data will be copied. A value of zero indicates that the source data
will be copied to the first register in the destination table; a value of 1 indicates that
the source data be copied to the second register in the destination table; etc.
Note: The value posted in the destination pointer register cannot be larger than the
table length integer specified in this node.
Outputs
RoT can produce two possible outputs, from the top and middle nodes. The state
of the output from the top node echoes the state of the top input. The output from
the middle node goes ON when the value in the destination pointer register equals
the specified table length. At this point, the instruction cannot increment any further.
932
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RBIT: Reset Bit
146
At a Glance
Introduction
This chapter describes the instruction RBIT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
934
Representation: RBIT - Reset Bit
935
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RBIT: Reset Bit
Short Description
Function
Description
The reset bit (RBIT) instruction lets you clear a latched-ON bit by powering the top
input. The bit remains cleared after power is removed from the input. This instruction
is designed to clear a bit set by the SBIT instruction.
Note: The RBIT instruction does not follow the same rules of network placement
as 0x-referenced coils do. An RBIT instruction cannot be placed in column 11 of a
network and it can be placed to the left of other logic nodes on the same rungs of
the ladder.
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RBIT: Reset Bit
Representation: RBIT - Reset Bit
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
register #
Bit number to reset
(1 - 16)
RBIT
bit #
(1 ... 16)
Parameter
Description
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = clears the specified bit to 0. The bit
remains cleared after power is removed
from the input
register #
(top node)
4x
WORD
Holding register whose bit pattern is being
controlled
INT, UINT
Indicates which one of the 16 bits is being
cleared
None
ON = the specified bit has been cleared to 0
bit #
(bottom node)
Top output
0x
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RBIT: Reset Bit
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READ: Read
147
At a Glance
Introduction
This chapter describes the instruction READ.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
938
Representation: READ - Read ASCII Port
939
Parameter Description
940
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READ: Read
Short Description
Function
Description
The READ instruction provides the ability to read data from an ASCII input device
(keyboard, bar code reader, etc.) into the PLC’s memory via its RIO network. The
connection to the ASCII device is made at an RIO interface.
In the process of handling the messaging operation, READ performs the
following functions:
z Verifies the lengths of variable data fields
z Verifies the correctness of the ASCII communication parameters, e.g. the port
number, the message number
z Performs error detection and recording
z Reports RIO interface status
READ requires two tables of registers: a destination table where retrieved variable
data (the message) is stored, and a control block where comm port and message
parameters are identified.
Further information about formatting messages you will find on p. 83.
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READ: Read
Representation: READ - Read ASCII Port
Symbol
Representation of the instruction
CONTROL
(off to on)
ACTIVE
control block
PAUSE OPERATION
ERROR (ONE SCAN)
destination
ABORT OPERATION
COMPLETE (ONE SCAN)
READ
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Parameter
Description
table length
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON = initiates a READ
Middle input
0x, 1x
None
ON = pauses READ operation
Bottom input
0x, 1x
None
ON = abort READ operation
control block
(top node)
4x
INT, UINT, Control block (first of seven contiguous
WORD
holding registers)
destination
(middle node)
4x
INT, UINT, Destination table
WORD
table length
(bottom node)
INT, UINT
Length of destination table (number of
registers where the message data will be
stored), range: 1 ... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Top output
0x
None
Echoes the state of the top input
Middle output
0x
None
ON = error in communication or operation has
timed out (for one scan)
Bottom output
0x
None
ON = READ complete (for one scan)
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READ: Read
Parameter Description
Control Block
(Top Node)
The 4x register entered in the top node is the first of seven contiguous holding
register in the control block.
Register
Definition
Displayed
Port number and error code
First implied
Message number
Second implied
Number of registers required to satisfy format
Third implied
Count of the number of registers transmitted thus far
Fourth implied
Status of the solve
Fifth implied
Reserved
Sixth implied
Checksum of registers 0 ... 5
Port Number and
Error Code
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bit
Function
1 ... 4
PLC error code
5
Not used
6
Input from the ASCII device not compatible with format
7
Input buffer overrun, data received too quickly at RIOP
8
USART error, bad byte received at RIOP
9
ASCII device off-line, check cabling
10
Illegal format, not received properly by RIOP
11
ASCII message terminated early (in keyboard mode
12 ... 16
Comm port # (1 ... 32)
15
940
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READ: Read
PLC Error Code
Bit
Destination
(Middle Node)
Meaning
1
2
3
4
0
0
0
1
Error in the input to RIOP from ASCII device
0
0
1
0
Exception response from RIOP, bad data
0
0
1
1
Sequenced number from RIOP differs from expected value
0
1
0
0
User register checksum error, often caused by altering
READ registers while the block is active
0
1
0
1
Invalid port or message number detected
0
1
1
0
User-initiated abort, bottom input energized
0
1
1
1
No response from drop, communication error
1
0
0
0
Node aborted because of SKP instruction
1
0
0
1
Message area scrambled, reload memory
1
0
1
0
Port not configured in the I/O map
1
0
1
2
Illegal ASCII request
1
1
0
0
Unknown response from ASCII port
1
1
0
1
Illegal ASCII element detected in user logic
1
1
1
1
RIOP in the PLC is down
The middle node contains the first 4x register in a destination table. Variable data in
a READ message are written into this table. The length of the table is defined in the
bottom node.
Consider this READ message:
please enter password:
(Embedded Text)
AAAAAAAAAA
(Variable Data)
Note: An ASCII READ message may contain the embedded text, placed inside
quotation marks, as well as the variable data in the format statement, i.e., the ASCII
message. The 10-character ASCII field AAAAAAAAAA is the variable data field;
variable data must be entered via an ASCII input device.
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READ: Read
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RET: Return from a Subroutine
148
At a Glance
Introduction
This chapter describes the instruction RET.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
944
Representation: RET - Return to Scheduled Logic
945
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RET: Return from a Subroutine
Short Description
Function
Description
The RET instruction may be used to conditionally return the logic scan to the node
immediately following the most recently executed JSR block. This instruction can be
implemented only from within the subroutine segment, the (unscheduled) last
segment in the user logic program.
Note: If a subroutine does not contain a RET block, either a LAB block or the endof-logic (whichever comes first) serves as the default return from the subroutine.
An example to the subroutine handling you will find on p. 99.
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RET: Return from a Subroutine
Representation: RET - Return to Scheduled Logic
Symbol
Representation of the instruction
RETURN TO PREVIOUS
LOGIC
ERROR
RET
00001
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = return to previous logic
ON returns the logic scan to the node
immediately following the most recently
executed JSR instruction or to the point where
the interrupt occurred in the logic scan.
INT, UINT
Constant value, can not be changed
None
ON = error in the specified subroutine
00001
Top output
0x
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RET: Return from a Subroutine
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RTTI - Register to Input Table
149
At A Glance
Introduction
This chapter describes the instruction RTTI.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: RTTI - Register to Input Table
948
Representation: RTTI - Register to Input Table
949
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RTTI - Register to Input Table
Short Description: RTTI - Register to Input Table
Function
Description
The Register to Input Table block is one of four 484-replacement instructions. It
copies the contents of an input register or a holding register to another input or
holding register. This destination register is pointed to by the input register implied
by the constant in the bottom node. Only one such operation can be accommodated
by the system in each scan.
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RTTI - Register to Input Table
Representation: RTTI - Register to Input Table
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source
ERROR
RTTI
destination
offset pointer
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
Control source
source
(top node)
3x, 4x
INT, UINT
The source node (top node) contains the
source register address. The data located in
the source register address will be copied to
the destination address, which is determined
by the destination offset pointer.
pointer
(bottom node)
(1 ... 254)
(801 ... 832)
INT, UINT
The pointer is a 3xxxx implied by a constant
(i.e. 00018 -> 30018) whose contents indicate
the destination. A value of 1 to 254 indicates a
holding register (40001 - 40254) and a value
of 801 to 832 indicates an input register
(30001 - 30032). If the value is outside this
range, the operation is not performed and the
ERROR rail is powered. Note the pointer's
value is NOT automatically increased.
Top output
0x
None
Echoes the value of the top input
Bottom output
0x
None
ON = error
Pointer value out of range
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RTTI - Register to Input Table
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RTTO - Register to Output Table
150
At A Glance
Introduction
This chapter describes the instruction RTTO.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: RTTO - Register to Output Table
952
Representation: RTTO - Register to Output Table
953
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RTTO - Register to Output Table
Short Description: RTTO - Register to Output Table
Function
Description
The Register to Output Table block is one of four 484-replacement instructions. It
copies the contents of an input register or a holding register to another input or
holding register. The holding register implied by the constant in the bottom node
points to this destination register. Only one such operation can be accommodated
by the system in each scan.
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RTTO - Register to Output Table
Representation: RTTO - Register to Output Table
Symbol
Representation of the instruction
CONTROL INPUT
COPY
source
ERROR
RTTO
destination
offset pointer
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
Control source
source
(top node)
3x, 4x
INT, UINT
The source node (top node) contains the source
register address. The data located in the source
register address will be copied to the destination
address, which is determined by the destination
offset pointer.
pointer
(1 ... 254)
INT, UINT
(bottom node) (801 ... 824)
The pointer is a 4xxxx implied by a constant (i.e.
00018 -> 40018) whose contents indicate the
destination. A value of 1 to 254 indicates a
holding register (40001 - 40254) and a value of
801 to 832 indicates an input register (30001 30032). If the value is outside this range, the
operation is not performed and the ERROR rail
is powered. Note that the pointer's value is NOT
automatically increased.
Top output
0x
None
Echoes the value of the top input
Bottom output 0x
None
ON = error
Pointer value out of range
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RTTO - Register to Output Table
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RTU - Remote Terminal Unit
151
At A Glance
Introduction
This chapter describes the instruction RTU.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: RTU - Remote Terminal Unit
956
Representation: RTU - Remote Terminal Unit
957
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RTU - Remote Terminal Unit
Short Description: RTU - Remote Terminal Unit
Function
Description
The MODBUS Remote Terminal Unit (RTU) block supports the following data
baud rates:
z
z
z
z
z
1200
2400
4800
9600
19200
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RTU - Remote Terminal Unit
Representation: RTU - Remote Terminal Unit
Parameter
Description
Register Entries
for Baud Rates
Description of the instructions parameters
Register
Function
4x
RTU revision number (read-only)
4x + 1
Fault status field (read-only)
4x + 2
Field not used
4x + 3
Set the Data Baud Rate register
For expanded and detailed information about the register entries for baud rates
please see the section below: Register Entries for Baud Rates.
4x + 4
Set the Data Bits register
For expanded and detailed information about the register entries for data bits
please see the section below: Register Entries for Data Bits
4x + 5
Parity register
4x + 6
Stop bit register
4x + 7
Field not used
4x + 8
Set the Command Word register
For expanded and detailed information about the register entries for command
words please see the section below: Register Entries for Command Words
The MODBUS Remote Terminal Unit (RTU) block supports the following data
baud rates:
z
z
z
z
z
1200
2400
4800
9600
19200
Below are the register entries for the supported data rates. To configure a data
rate, type the appropriate decimal number (for example 1200) in the data baud
rate register.
Register Entry
Baud Rate
1200
1200
2400
2400
4800
4800
9600
9600
19200
19200
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RTU - Remote Terminal Unit
Register Entries
for Data Bits
The RTU block supports data bits 7 and 8. Below are the possible register entries
for the data bits field:
Register Entry Data Bit Field
7
7
8
8
Modbus messages can be sent in Modbus RTU format or Modbus ASCII format.
If messages are sent in Modbus ASCII format, type 7 in the field.
z If messages are sent in Modbus RTU format, type 8.
z
If you're sending ASCII character messages, this register can be set to
7 or 8 data bits.
Register
Entries for
Command
Words
The RTU block interprets each bit of the command word as a function to implement
or perform. Below are the bit definitions for the command word register entries.
Register Entry Definitions
1 (msb)
Not used
2
Enable RTS/CTS control
3
Not used
4
Not used
5
Not used
6
Not used
7
Enable ASCII string messaging
8
Enable Modbus messaging
9
Not used
10
Not used
11
Not used
12
Not used
13
Not used
14
Hang up modem
15
Dial modem
16 (lsb)
Initialize modem
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RTU - Remote Terminal Unit
The following items provide expanded and detailed information about
Bits 2, 7, and 8.
z
z
z
Bit 2 – Enable request-to-send/clear-to-send (RTS/CTS) control
This bit should be set (or true) when a DCE that is connected to the PLC requires
hardware handshaking using RTS/CTS control.
This bit can be used in conjunction with the values contained in the (4xxxx ¸ 13)
start-of-transmission delay register and the (4xxxx + 13) end-of-transmission
delay register. Start-of-transmission delay keeps RTS asserted for 0-9999 ms
before the RTU block sends a message from the PLC port. After the RTU block
sends a message, end-of-transmission delay keeps RTS asserted for 0-9999 ms.
When end-of-transmission delay has expired, the RTU block de-asserts RTS.
Bit 7 – Enable ASCII string messaging
This bit should be set (or true) to send ASCII string messages form the PLC
communication Port #1.
The RTU block can send an ASCII string of up to 512 characters in length. Each
ASCII message must be programmed into contiguous 4x registers of the PLC.
Two characters per register are allowed.
Note: This ASCII message string should NOT be confused with a Modbus
message sent in ASCII format.
Bit 8 – Enable Modbus messaging
This bit should be set (or true) to send Modbus messages from the PLC
communication Port #1.
Modbus messages can be sent in RTU or ASCII formats.
z If sending Modbus messages in RTU format, set the data bits in the (4xxxx +
4) data bits register to 8.
z If sending Modbus message in ASCII format, set the data bits in the (4xxxx +
4) data bits register to 7.
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RTU - Remote Terminal Unit
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SAVE: Save Flash
152
At a Glance
Introduction
This chapter describes the instruction SAVE.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
962
Representation: SAVE - Save
963
Parameter Description
964
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SAVE: Save Flash
Short Description
Function
Description
Note: This instruction is available with the PLC family TSX Compact, with Quantum
CPUs 434 12/ 534 14 and Momentum CPUs CCC 960 x0/ 980 x0.
The SAVE instruction saves a block of 4x registers to state RAM where they are
protected from unauthorized modification.
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SAVE: Save Flash
Representation: SAVE - Save
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
register
1, 2, 3, 4
ERROR
SAVE not allowed
SAVE
length
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
Start SAVE operation: it should remain ON until
the operation has completed successfully or an
error has occurred.
register
(top node)
4x
INT, UINT,
WORD
First of max. 512 contiguous 4x registers to be
saved to state RAM
1, 2, 3, 4 (see
p. 964)
(middle node)
INT
Integer value, which defines the specific buffer
where the block of data is to be saved
length
(bottom node)
INT
Number of words to be saved, range: 1 ... 512
Top output
0x
None
ON = SAVE is active
Middle output
(see p. 964)
0x
None
ON = SAVE is not allowed
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SAVE: Save Flash
Parameter Description
1, 2, 3, 4
(Middle Node)
The middle node defines the specific buffer, within state RAM, where the block of
data is to be saved. Four 512 word buffers are allowed. Each buffer is defined by
placing its corresponding value in the middle node, that is, the value 1 represents
the first buffer, value 2 represents the second buffer and so on. The legal values are
1, 2, 3, and 4. When the PLC is started all four buffers are zeroed. Therefore, you
may not save data to the same buffer without first loading it with the instruction
LOAD (see p. 657). When this is attempted the middle output goes ON. In other
words, once a buffer is used, it may not be used again until the data has
been removed.
Middle Output
The output from the middle node goes ON when previously saved data has not been
accessed using the LOAD (see p. 657) instruction. This prevents inadvertent
overwriting of data in the SAVE buffer.
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SBIT: Set Bit
153
At a Glance
Introduction
This chapter describes the instruction SBIT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
966
Representation: SBIT - Set Bit
967
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SBIT: Set Bit
Short Description
Function
Description
The set bit (SBIT) instruction lets you set the state of the specified bit to ON (1)
by powering the top input.
Note: The SBIT instruction does not follow the same rules of network placement
as 0x-referenced coils do. An SBIT instruction cannot be placed in column 11 of a
network and it can be placed to the left of other logic nodes on the same rungs
of the ladder.
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SBIT: Set Bit
Representation: SBIT - Set Bit
Symbol
Representation of the instruction
ON SETS BIT TO 1
ACTIVE
register #
SBIT
bit #
(1 ... 16)
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = sets the specified bit to 1. The bit remains
set after power is removed from the input
register #
(top node)
4x
WORD
Holding register whose bit pattern is
being controlled
INT, UINT
Indicates which one of the 16 bits is being set
None
Goes ON, when the specified bit is set and
remains ON until it is cleared (via the RBIT
(see p. 933) instruction)
bit #
(bottom node)
Top output
0x
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SBIT: Set Bit
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SCIF: Sequential
Control Interfaces
154
At a Glance
Introduction
This chapter describes the instruction SCIF.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
970
Representation: SCIF - Sequential Control Interface
971
Parameter Description
973
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SCIF: Sequential Control Interfaces
Short Description
Function
Description
The SCIF instruction performs either a drum sequencing operation or an input
comparison (ICMP) using the data defined in the step data table.
The choice of operation is made by defining the value in the first register of the step
data table (see p. 973):
z 0 = drum mode:
The instruction controls outputs in the drum sequencing application.
z 1 = ICMP mode:
The instruction reads inputs to ensure that limit switches, proximity switches,
pushbuttons, etc. are properly positioned to allow drum outputs to be fired.
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SCIF: Sequential Control Interfaces
Representation: SCIF - Sequential Control Interface
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
step pointer
OPERATION SPECIFIC
OPERATION SPECIFIC
step data
table
RESET STEP POINTER
Length: 1 - 255
SCIF
ERROR
length
(1 ... 255)
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SCIF: Sequential Control Interfaces
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = initiates specified sequence control
operation
Middle input
0x, 1x
None
Drum mode: step pointer increments to the
next step
ICMP mode: compare status is shown at the
middle output
Bottom input
0x, 1x
None
Drum mode: ON = reset step pointer to 0
ICMP mode: not used
step pointer
(top node)
4x
INT, UINT
Number of the current step in the step
data table
step data table
(see p. 973)
(middle node)
4x
INT, UINT
First register in the step data table
(For expanded and detailed information
please see p. 973.)
INT, UINT
Number of application-specific registers used
in the step data table
length (see
p. 974)
(bottom node)
Top output
0x
None
Echoes state of the top input
Middle output
0x
None
Drum mode goes ON for the last step
Note: When using the middle output, be
aware that when integrating with other logic, if
the step pointer is zero and the middle input is
ON, then the middle output will also be ON.
This condition will cause the step pointer to be
one step out of sequence.
Bottom output
0x
None
ON = error is detected
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SCIF: Sequential Control Interfaces
Parameter Description
Step Data Table
(Middle Node)
The 4x register entered in the middle node is the first register in the step data table.
The first seven registers in the table hold constant and variable data required to
solve the instruction:
Register
Register Name
Description
Displayed
subfunction type
0 = drum mode; 1 = ICMP mode (entry of any other value in
this register will result in all outputs OFF)
First
implied
masked output
data
(in drum mode)
Loaded by SCIF each time the block is solved; the register
contains the contents of the current step data register
masked with the output mask register
raw input data
(in ICMP mode)
Loaded by the user from a group of sequential inputs to be
used by the block in the current step
Second
implied
current step data
Loaded by SCIF each time the block is solved; the
register contains data from the current step (pointed to by
the step pointer)
Third
implied
output mask
(in drum mode)
Loaded by the user before using the block, the contents will
not be altered during logic solving; contains a mask to be
applied to the data for each sequencer step
input mask
(in ICMP mode)
Loaded by the user before using the block, it contains a
mask to be ANDed with raw input data for each step,
masked bits will not be compared; the masked data are put
in the masked input data register
Fourth
implied
masked input data Loaded by SCIF each time the block is solved, it contains
(in ICMP mode)
the result of the ANDed input mask and raw input data
not used in
drum mode
Fifth
implied
compare status
(in ICMP mode)
Loaded by SCIF each time the block is solved, it contains
the result of an XOR of the masked input data and the
current step data; unmasked inputs that are not in the
correct logical state cause the associated register bit to go
to 1, non-zero bits cause a miscompare and turn ON the
middle output from the SCIF block
not used in
drum mode
Sixth
implied
start of data table
First of K registers in the table containing the user-specified
control data
Note: This and the rest of the registers represent
application-specific step data in the process being
controlled.
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SCIF: Sequential Control Interfaces
Length of Step
Data Table
(Bottom Node)
The integer value entered in the bottom node is the length, i.e. the number of
application-specific registers, used in the step data table. The length can range from
1 ... 255.
The total number of registers required in the step data table is the length + 7. The
length must be t the value placed in the steps used register in the middle node.
974
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SENS: Sense
155
At a Glance
Introduction
This chapter describes the instruction SENS.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
976
Representation: SENS - Logical Bit-Sense
977
Parameter Description
978
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SENS: Sense
Short Description
Function
Description
The SENS instruction examines and reports the sense (1 or 0) of a specific bit
location in a data matrix. One bit location is sensed per scan.
976
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SENS: Sense
Representation: SENS - Logical Bit-Sense
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
bit location
Pointer: (999 16-bit PLC)
(max) (9600 24-bit PLC)
INCREASE POINTER
SENSE BIT (ON/OFF)
data matrix
RESET POINTER
SENS
Matrix length (max)
255 Registers (4080 bits 16-bit PLC)
600 Registers (9600 bits 24-bit PLC)
Parameter
Description
ERROR
Operation not performed
Pointer > Matrix size
length
Description of the instruction’s parameters
Parameters
State RAM Data
Reference Type
Meaning
Top input
0x, 1x
None
ON = senses the bit location
Middle input
0x, 1x
None
Increment bit location by one on next scan
Bottom input
0x, 1x
None
Reset bit location to 1
bit location (see 3x, 4x
p. 978)
(top node)
WORD
Specific bit location to be sensed in the data matrix,
entered explicitly as an integer or stored in a
register; range: 1 ... 9600
Pointer: ( 999 16-bit PLC)
(max) (9900 24-bit PLC)
data matrix
(middle node)
BOOL,
WORD
First word or register in the data matrix
INT,
UINT
Matrix length max
255 Registers (4080 bits 16-bit PLC)
600 Registers (9600 bits 24-bit PLC)
0x, 4x
length (see
p. 978)
(bottom node)
Top output
0x
None
Echoes state of the top input
Middle output
0x
None
ON = bit sense is 1
OFF = bit sense is 0
Bottom output
0x
None
ON = error: bit location > matrix length
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SENS: Sense
Parameter Description
Bit Location
(Top Node)
Note: If the bit location is entered as an integer or in a 3x register, the instruction
will ignore the state of the middle and bottom inputs.
Matrix Length
(Bottom Node)
The integer value entered in the bottom node specifies a matrix length, i.e, the
number of 16-bit words or registers in the data matrix. The length can range from 1
... 600 in a 24-bit CPU, e.g, a matrix length of 200 indicates 3200 bit locations.
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Shorts
156
At A Glance
Introduction
This chapter describes the instruction element Shorts.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: Shorts
980
Representation: Shorts
981
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Shorts
Short Description: Shorts
Function
Description
Shorts are simply straight-line connections between contacts and/or instructions in
a ladder logic network. Vertical (|) and horizontal (—) shorts are used to make
connections between rows and columns of logic. To cancel a vertical short, use a
vertical open.
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Shorts
Representation: Shorts
Vertical Shorts
Connects contacts or instructions vertically in a network column, or node inputs and
outputs to create either/or conditions. When two contacts are connected by vertical
shorts, power is passed when one or both contacts receive power.
Horizontal
Shorts
Expands logic horizontally along a rung in a ladder logic network
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Shorts
982
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SKP - Skipping Networks
157
At A Glance
Introduction
This chapter describes the instruction SKP.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: SKP - Skipping Networks
984
Representation: SKP - Skipping Networks
985
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SKP - Skipping Networks
Short Description: SKP - Skipping Networks
Function
Description
The SKP instruction is a standard instruction in all PLCs. It should be used
with caution
The SKP instruction is used to reduce the scan time by not solving a portion of the
logic. The SKP instruction causes the logic scan to skip specified networks in
the program.
The SKP function can be used to
Bypass seldom used program sequences
z Create subroutines
z
The SKP instruction allows you to skip a specified number of networks in a ladder
logic program. When it is powered, the SKP operation is performed on every scan.
The remainder of the network in which the instruction appears counts as the first of
the specified number of networks to be skipped. The CPU continues to skip
networks until the total number of networks skipped equals the number specified in
the instruction block or until a segment boundary is reached. A SKP operation
cannot cross a segment boundary.
A SKP instruction can be activated only if you specify in the PLC set-up editor that
skips are allowed. SKP is a one-high nodal instruction.
WARNING
Skipped inputs and outputs
SKP is a dangerous instruction that should be used carefully. If inputs and outputs
that normally effect control are unintentionally skipped (or not skipped), the result
can create hazardous conditions for personnel and application equipment.
Failure to follow this instruction can result in death, serious injury, or
equipment damage.
CAUTION
Reading values while changing
Use 3xxxx and 4xxxx registers with caution. The processor can read the value
while it's changing.
Failure to follow this instruction can result in injury or equipment damage.
984
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SKP - Skipping Networks
Representation: SKP - Skipping Networks
Symbol
Representation of the instruction
CONTROL INPUT
SKP
# of networks
skipped
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
1x
None
ON initiates a skip network operation when it
passes power. A SKP operation is performed on
every scan while the input is ON
# of networks
skipped
(top node)
3x, 4x
INT, UINT
WORD
The value entered in the node specifies the
number of networks to be skipped.
The value can be
z Specified explicitly as an integer constant in
the range 1 through 999
z Stored in a 3xxxx input register
z Stored in a 4xxxx holding register
The node value includes the network that
contains the SKP instruction. The nodal regions
in the network where the SKP resides that have
not already been scanned will be skipped; this
counts as one of the networks specified to be
skipped. The CPU continues to skip networks
until the total number of networks skipped equals
the value specified.
985
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SKP - Skipping Networks
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SRCH: Search
158
At a Glance
Introduction
This chapter describes the instruction SRCH.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
988
Representation: SRCH - Search
989
Parameter Description
991
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SRCH: Search
Short Description
Function
Description
The SRCH instruction searches the registers in a source table for a specific
bit pattern.
988
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SRCH: Search
Representation: SRCH - Search
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source table
START SEARCH AT
POINTER REGISTER
MATCH FOUND
pointer
SRCH
Length: 1 - 100 registers
table length
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = initiates search
Middle input
0x, 1x
None
OFF = search from beginning
ON = search from last match
source table
(top node)
3x, 4x
INT, UINT,
WORD
Source table to be searched
pointer (see
p. 991)
(middle node)
4x
INT, UINT
Pointer into the source table
INT, UINT
Number of registers in the source table; range:
1 ... 100
table length
(bottom node)
Top output
0x
None
Echoes state of the top input
Middle output
0x
None
ON = match found
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SRCH: Search
A SRCH Example
In the following example, we search a source table that contains five registers
(40421 ... 40425) for a specific bit pattern. The pointer register (40430) indicates that
the desired bit pattern is stored in register 40431, and we see that the register
contains a bit value of 3333.
40430
40421
10001
10002
40430
40500
SRCH
00005
BLKM
0001
register
source table content
40421
40422
40423
40424
40425
= 1111
= 2222
= 3333
= 4444
= 5555
pointer
40430
register
content
40431
= 3333
00142
In each scan where P.T. contact 10001 transitions from OFF to ON, the source table
is searched for a bit pattern equivalent to the value 3333. when the math is found,
the middle output passes power to coil 00142.
If N.O. contact 10002 is OFF when the match is found at register 40423, the SRCH
instruction energizes coil 00142 for one scan, then starts the search again in the
next scan at the top of the source table (register 40421). If contact 10002 is ON, the
SRCH instruction energizes coil 00142 for one scan, then starts the search in
register 40424,
Because the top input is a P.T. contact, on any scan where power is not applied to
the top input the pointer value is cleared. We use a BLKM instruction here to sage
the pointer value to register 40500.
990
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SRCH: Search
Parameter Description
Pointer
(Middle Node)
The 4x register entered in the middle node is the pointer into the source table. It
points to the source register that contains the same value as the value stored in the
next contiguous register after the pointer, e.g. if the pointer register is 400015, then
register 400016 contains a value that the SRCH instruction will attempt to match in
source table.
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SRCH: Search
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STAT: Status
159
At a Glance
Introduction
This chapter describes the instruction STAT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
994
Representation: STAT - Status
995
Parameter Description
996
Description of the Status Table
997
Controller Status Words 1 - 11 for Quantum and Momentum
1001
I/O Module Health Status Words 12 - 20 for Momentum
1006
I/O Module Health Status Words 12 - 171 for Quantum
1008
Communication Status Words 172 - 277 for Quantum
1010
Controller Status Words 1 - 11 for TSX Compact and Atrium
1016
I/O Module Health Status Words 12 - 15 for TSX Compact
1019
Global Health and Communications Retry Status Words 182 ... 184 for
TSX Compact
1020
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STAT: Status
Short Description
Function
Description
The STAT instruction accesses a specified number of words in a status table (see
p. 997) in the PLC’s system memory. Here vital diagnostic information regarding the
health of the PLC and its remote I/O drops is posted.
This information includes:
PLC status
z Possible error conditions in the I/O modules
z Input-to-PLC-to-output communication status
z
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STAT: Status
Representation: STAT - Status
Symbol
Representation of the instruction
CONTROL DESTINATION
TOP INPUT
destination
STAT
length
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON = copies specified number of words from the
status table
destination (see 0x, 4x
p. 996)
(top node)
INT, UINT, First position in the destination block
BOOL,
WORD
length (see
p. 996)
(bottom node)
INT, UINT number of registers or 16-bit words in the
destination block
The integer value entered in the bottom node
specifies a matrix length - i.e., the number of 16bit words or registers in the data matrix. The
length can range from 1 through 255 in a 16-bit
CPU and from 1 through 600 in a 24-bit CPU—
e.g., a matrix length of 200 indicates 3200 bit
locations.
Note: If 0xxxx references are used as the
destination, they cannot be programmed as
coils, only as contacts referencing those coil
numbers. (For expanded and detailed
information regarding table length and PLCs
see p. 996.)
Top output
0x
None
ON = operation successful
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STAT: Status
Parameter Description
Mode of
Functioning
With the STAT instruction, you can copy some or all of the status words into a block
of registers or a block of contiguous discrete references.
The copy to the STAT block always begins with the first word in the table up to the
last word of interest to you. For example, if the status table is 277 words long and
you are interested only in the statistics provided in word 11, you need to copy only
words 1 ... 11 by specifying a length of 11 in the STAT instruction.
Destination
Block (Top Node)
The reference number entered in the top node is the first position in the destination
block, i.e. the block where the current words of interest from the status table will
be copied.
The number of holding registers or 16-bit words in the destination block is specified
in the bottom node (length).
Note: We recommend that you do not use discretes in the STAT destination node
because of the excessive number required to contain status information.
Length
(Bottom Node)
The integer value entered in the bottom node specifies the number of registers or
16-bit words in the destination block where the current status information will
be written.
The maximum allowable length will differ according to the type of PLC in use and the
type of I/O communications protocol employed.
z For a 984A, 984B, or 984X Chassis Mount PLC using the S901 RIO protocol the
available range of the system status table is 1 ... 75 words
z For PLCs with 16-bit CPUs using the S908 RIO protocol - for example the 38x,
48x, and 68x Slot Mount PLCs - the available range of the system status table is
1 ... 255
z For PLCs with 24-bit CPUs using the S908 RIO protocol - for example the 78x
Slot Mount PLCs, the Quantum PLCs - the available range of the system status
table is 1 ... 277
z For Compact-984 PLCs the available range of the system status table is 1 ... 184
z For Modicon Micro PLCs the available range of the system status table is 1 ... 56
996
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STAT: Status
Description of the Status Table
General
The STAT instruction is used to display the Status of Controller and I/O system for
Quantum (see p. 997), Atrium (see p. 1000), TSX Compact (see p. 1000) and
Momentum (see p. 999).
The first 11 status words are used by Quantum and Momentum in the same way and
by TSX Compact and Atrium in the same way. The following have a different
meaning for Quantum, TSX Compact and Momentum.
Quantum
Overview
The 277 words in the status table are organized in three sections:
z Controller Status (words 1 ... 11) (see p. 1001)
z I/O Module Health (words 12 ... 171) (see p. 1008)
z I/O Communications Health (words 172 ... 277) (see p. 1010)
Words of the status table:
Decimal Word Word Content
Hex Word
1
Controller Status
01
2
Hot Standby Status
02
3
Controller Status
03
4
RIO Status
04
5
Controller Stop State
06
6
Number of Ladder Logic Segments
06
7
End-of-logic (EOL) Pointer
07
8
RIO Redundancy and Timeout
08
9
ASCII Message Status
09
10
RUN/LOAD/DEBUG Status
0A
11
not used
0B
12
Drop 1, Rack 1
0C
13
Drop 1, Rack 2
0D
...
......
...
16
Drop 1, Rack 5
0F
17
Drop 2, Rack 1
10
18
Drop 2, Rack 2
11
...
......
...
171
Drop 32, Rack 5
AB
172
S908 Startup Error Code
AC
173
Cable A Errors
AD
174
Cable A Errors
AE
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STAT: Status
Decimal Word Word Content
Hex Word
175
Cable A Errors
AF
176
Cable B Errors
B0
178
Cable B Errors
B1
178
Cable B Errors
B2
179
Global Communication Errors
B3
180
Global Communication Errors
B4
181
Global Communication Errors
B5
182
Drop 1 Errors/Health Status and Retry Counters (in the TSX B6
Compact 984 Controllers) (First word)
183
Drop 1 Errors/Health Status and Retry Counters (in the TSX B7
Compact 984 Controllers) (Second word)
184
Drop 1 Errors/Health Status and Retry Counters (in the TSX B8
Compact 984 Controllers) (Third word)
185
Drop 2 Errors/Health Status and Retry Counters (in the TSX B9
Compact 984 Controllers) (First word)
...
......
...
275
Drop 32 Errors/Health Status and Retry Counters (in the
TSX Compact 984 Controllers) (First word)
113
276
Drop 32 Errors/Health Status and Retry Counters (in the
TSX Compact 984 Controllers) (Second word)
114
277
Drop 32 Errors/Health Status and Retry Counters (in the
TSX Compact 984 Controllers) (Third word)
115
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STAT: Status
Momentum
Overview
The 20 words in the status table are organized in two sections:
z Controller Status (words 1 ... 11) (see p. 1001)
z I/O Module Health (words 12 ... 20) (see p. 1006)
Words of the status table:
Decimal Word
Word Content
Hex Word
1
Controller Status
01
2
Hot Standby Status
02
3
Controller Status
03
4
RIO Status
04
5
Controller Stop State
06
6
Number of Ladder Logic Segments
06
7
End-of-logic (EOL) Pointer
07
8
RIO Redundancy and Timeout
08
9
ASCII Message Status
09
10
RUN/LOAD/DEBUG Status
0A
11
not used
0B
12
Local Momentum I/O Module Health
0C
13
I/O Bus Module Health
0D
14
I/O Bus Module Health
0E
15
I/O Bus Module Health
0F
16
I/O Bus Module Health
10
17
I/O Bus Module Health
11
18
I/O Bus Module Health
12
19
I/O Bus Module Health
13
20
I/O Bus Module Health
14
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STAT: Status
TSX Compact
and Atrium
Overview
The 184 words in the status table are organized in three sections:
z Controller Status (words 1 ... 11) (see p. 1016)
z I/O Module Health (words 12 ... 15) (see p. 1019)
z Not used (16 ... 181)
z Global Health and Communications retry status (words 182 ... 184) (see p. 1020)
Words of the status table:
Decimal Word
Word Content
Hex Word
1
CPU Status
01
2
not used
02
3
Controller Status
03
4
not used
04
5
CPU Stop State
06
6
Number of Ladder Logic Segments
06
7
End-of-logic (EOL) Pointer
07
8
not used
08
9
not used
09
10
RUN/LOAD/DEBUG Status
0A
11
not used
0B
12
I/O Health Status Rack 1
0C
13
I/O Health Status Rack 2
0D
14
I/O Health Status Rack 3
0E
15
I/O Health Status Rack 4
0F
16 ... 181
not used
10 ... B5
182
Health Status
B6
183
I/O Error Counter
B7
184
PAB Bus Retry Counter
B8
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STAT: Status
Controller Status Words 1 - 11 for Quantum and Momentum
Controller Status
(Word 1)
Word 1 displays the following aspects of the PLC status:
1
Hot Standby
Status (Word 2)
2
3
4
5
6
7
8
9
Bit
Function
1-5
Not used
6
1 = enable constant sweep
7
1 = enable single sweep delay
8
1 = 16 bit user logic
0 = 24 bit user logic
9
1 = AC power on
10
1 = RUN light OFF
11
1 = memory protect OFF
12
1 = battery failed
13 - 16
Not used
10
11
12
13
14
15
16
Word 2 displays the Hot Standby status for 984 PLCs that use S911/R911 Hot
Standby Modules:
1
2
3
4
5
6
7
8
9
10
11
Bit
Function
1
1 = S911/R911 present and healthy
2 - 10
Not used
11
0 = controller toggle set to A
1 = controller toggle set to B
12
0 = controllers have matching logic
1 = controllers do not have matching logic
13, 14
Remote system state:
0 1 = Off line (1 dec)
1 0 = primary (2 dec)
1 1 = standby (3 dec)
15, 16
Local system state:
0 1 = Off line (1 dec)
1 0 = primary (2 dec)
1 1 = standby (3 dec)
12
13
14
15
16
1001
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STAT: Status
Controller Status
(Word 3)
Word 3 displays more aspects of the controller status:
1
RIO Status
(Word 4)
2
3
4
5
6
7
8
9
10
Bit
Function
1
1 = first scan
2
1 = start command pending
3
1 = constant sweep time exceeded
4
1 = Existing DIM AWARENESS
5 - 12
Not used
13 - 16
Single sweeps
11
12
13
14
15
16
11
12
13
14
15
16
Word 4 is used for IOP information:
1
2
3
4
5
6
7
Bit
Function
1
1 = IOP bad
2
1 = IOP time out
3
1 = IOP loop back
4
1 = IOP memory failure
5 - 12
Not used
13 - 16
00 = IO did not respond
01 = no response
02 = failed loopback
8
9
10
1002
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STAT: Status
Controller Stop
State (Word 5)
CAUTION
Using a Quantum or 984-684E/785E PLC
If you are using a Quantum or 984-684E/785E PLC, bit 15 in word 5 is never set.
These PLCs can be started and run with coils disabled in RUN (optimized) mode.
Also all the bits in word 5 must be set to 0 when one of these PLCs is running.
Failure to follow this instruction can result in injury or equipment damage.
Word 5 displays the PLC’s stop state conditions:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Function
1
1 = peripheral port stop
2
Extended memory parity error (for chassis mount controllers) or traffic cop/S908 error
(for other controllers)
If the bit = 1 in a 984B controller, an error has been detected in extended memory;
the controller will run, but the error output will be ON for XMRD/XMWT functions
If the bit = 1 for any other controller than a chassis mount, then either a traffic cop
error has been detected or the S908 is missing from a multi-drop configuration.
3
1 = controller in DIM AWARENESS
4
1 = illegal peripheral intervention
5
1 = segment scheduler invalid
6
1 = start of node did not start segment
7
1 = state RAM test failed
8
1 = invalid traffic cop
9
1 = watchdog timer expired
10
1 = real time clock error
11
CPU logic solver failed (for chassis mount controllers) or Coil Use TABLE (for other
controllers) If the bit = 1 in a chassis mount controller, the internal diagnostics have
detected CPU failure.
If the bit = 1 in any controller other than a chassis mount, then the Coil Use Table does
not match the coils in user logic.
12
1 = IOP failure
13
1 = invalid node
14
1 = logic checksum
15
1 = coil disabled in RUN mode (see Caution below)
16
1 = bad config
1003
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STAT: Status
Controller Stop
State (Word 6)
Word 6 displays the number of segments in ladder logic; a binary number is shown:
1
Controller Stop
State (Word 7)
ASCII Message
Status (Word 9)
3
4
5
6
7
8
9
10
11
12
13
14
Bit
Function
1 - 16
Number of segments (expressed as a decimal number)
15
16
Word 7 displays the address of the end-of-logic (EOL) pointer:
1
RIO Redundancy
and Timeout
(Word 8)
2
2
3
4
5
6
7
Bit
Function
1 - 16
EOL pointer address
8
9
10
11
12
13
14
15
16
Word 8 uses its four least significant bits to display the remote I/O timeout constant:
1
2
3
4
5
6
7
Bit
Function
1 - 12
Not used
13 - 16
RIO timeout constant
8
9
10
11
12
13
14
15
16
Word 9 uses its four least significant bits to display ASCII message status:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Function
1 ... 12
Not used
13
1 = Mismatch between numbers of messages and pointers
14
1 = Invalid message pointer
15
1 = Invalid message
16
1 = Message checksum error
1004
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STAT: Status
RUN/LOAD/
DEBUG Status
(Word 10)
Word 11
Word 10 uses its two least significant bits to display RUN/LOAD/DEBUG status:
1
2
3
4
5
6
Bit
Function
1 ... 14
Not used
15, 15
0 0 = Debug (0 dec)
0 1 = Run (1 dec)
1 0 = Load (2 dec)
7
8
9
10
11
12
13
14
15
16
This word is not used.
1005
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STAT: Status
I/O Module Health Status Words 12 - 20 for Momentum
I/O Module
Health Status
Status words 12 ... 20 display I/O module health status.
Local Momentum
I/O Module
Health
Word 12 displays the Local Momentum I/O Module health:
1 word is reserved for each of up to 1 Local drop, 8 words are used to represent the
health of up to 128 I/O Bus Modules
Momentum I/O
Bus Module
Health
1
2
3
4
5
6
Bit
Function
1
1 = Local Module
2 - 16
Not used
7
8
9
10
11
12
13
14
15
16
Word 13 through 20 display the health status for Momentum I/O Bus Modules as
follows:
Word
I/O Bus Modules
13
1 ... 16
14
17 ... 32
15
33 ... 48
16
49 ... 64
17
65 ... 80
18
81 ... 96
19
97 ... 112
20
113 ... 128
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STAT: Status
Each Word display the Momentum I/O Bus Module health as follows:
1
2
3
4
5
Bit
Function
1
1 = Module 1
2
1 = Module 2
3
1 = Module 3
4
1 = Module 4
5
1 = Module 5
6
1 = Module 6
7
1 = Module 7
8
1 = Module 8
9
1 = Module 9
10
1 = Module 10
11
1 = Module 11
12
1 = Module 12
13
1 = Module 13
14
1 = Module 14
15
1 = Module 15
16
1 = Module 16
6
7
8
9
10
11
12
13
14
15
16
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STAT: Status
I/O Module Health Status Words 12 - 171 for Quantum
RIO Status
Words
Status words 12 ... 20 display I/O module health status.
Five words are reserved for each of up to 32 drops, one word for each of up to five
possible racks (I/O housings) in each drop. Each rack may contain up to 11 I/O
modules; bits 1 ... 11 in each word represent the health of the associated I/O
module in each rack.
1
2
3
4
5
Bit
Function
1
1 = Slot 1
2
1 = Slot 2
3
1 = Slot 3
4
1 = Slot 4
5
1 = Slot 5
6
1 = Slot 6
7
1 = Slot 7
8
1 = Slot 8
9
1 = Slot 9
10
1 = Slot 10
11
1 = Slot 11
12
1 = Slot 12
13
1 = Slot 13
14
1 = Slot 14
15
1 = Slot 15
16
1 = Slot 16
6
7
8
9
10
11
12
13
14
15
16
Four conditions must be met before an I/O module can indicate good health:
z The slot must be traffic copped
z The slot must contain a module with the correct personality
z Valid communications must exist between the module and the RIO interface at
remote drops
z Valid communications must exist between the RIO interface at each remote drop
and the I/O processor in the controller
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STAT: Status
Status Words for
the MMI Operator
Panels
The status of the 32 Element Pushbutton Panels and PanelMate units on an RIO
network can also be monitored with an I/O health status word. The Pushbutton
Panels occupy slot 4 in an I/O rack and can be monitored at bit 4 of the appropriate
status word. A PanelMate on RIO occupies slot 1 in rack 1 of the drop and can be
monitored at bit 1 of the first status word for the drop.
Note: The ASCII Keypad’s communication status can be monitored with the error
codes in the ASCII READ/WRIT blocks.
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STAT: Status
Communication Status Words 172 - 277 for Quantum
DIO Status
Status words 172 ... 277 contain the I/O system communication status. Words 172
... 181 are global status words. Among the remaining 96 words, three words are
dedicated to each of up to 32 drops, depending on the type of PLC.
Word 172 stores the Quantum Startup Error Code. This word is always 0 when the
system is running. If an error occurs, the controller does not start-it generates a stop
state code of 10 (word 5 (see p. 1003)).
Quantum Start-up Error Codes
Code
Error
Meaning (Where the error has occurred)
01
BADTCLEN
Traffic Cop length
02
BADLNKNUM
Remote I/O link number
03
BADNUMDPS
Number of drops in Traffic Cop
04
BADTCSUM
Traffic Cop checksum
10
BADDDLEN
Drop descriptor length
11
BADDRPNUM
I/O drop number
12
BADHUPTIM
Drop holdup time
13
BADASCNUM
ASCII port number
14
BADNUMODS
Number of modules in drop
15
PRECONDRP
Drop already configured
16
PRECONPRT
Port already configured
17
TOOMNYOUT
More than 1024 output points
18
TOOMNYINS
More than 1024 input points
20
BADSLTNUM
Module slot address
21
BADRCKNUM
Module rack address
22
BADOUTBC
Number of output bytes
23
BADINBC
Number of input bytes
25
BADRF1MAP
First reference number
26
BADRF2MAP
Second reference number
27
NOBYTES
No input or output bytes
28
BADDISMAP
Discrete not on 16-bit boundary
30
BADODDOUT
Unpaired odd output module
31
BADODDIN
Unpaired odd input module
32
BADODDREF
Unmatched odd module reference
33
BAD3X1XRF
1x reference after 3x register
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STAT: Status
Status of Cable A
Code
Error
Meaning (Where the error has occurred)
34
BADDMYMOD
Dummy module reference already used
35
NOT3XDMY
3x module not a dummy
36
NOT4XDMY
4x module not a dummy
40
DMYREAL1X
Dummy, then real 1x module
41
REALDMY1X
Real, then dummy 1x module
42
DMYREAL3X
Dummy, then real 3x module
43
REALDMY3X
Real, then dummy 3x module
Words 173 ... 175 are Cable A error words:
Word 173
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Bit
Function
1 ... 8
Counts framing errors
9 ... 16
Counts DMA receiver overruns
Word 174
1
2
3
4
5
6
7
8
Bit
Function
1 ... 8
Counts receiver errors
9 ... 16
Counts bad drop receptions
Word 175
1
2
3
4
5
6
7
Bit
Function
1
1 = Short frame
2
1 = No end-of- frame
3 ... 12
Not used
13
1 = CRC error
14
1 = Alignment error
15
1 =Overrun error
16
Not used
8
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STAT: Status
Status of Cable B
Words 176 ... 178 are Cable A error words:
Word 176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Bit
Function
1 ... 8
Counts framing errors
9 ... 16
Counts DMA receiver overruns
Word 177
1
2
3
4
5
6
7
8
Bit
Function
1 ... 8
Counts receiver errors
9 -...16
Counts bad drop receptions
Word 178
1
2
3
4
5
6
7
Bit
Function
1
1 = Short frame
2
1 = No end-of- frame
3 ... 12
Not used
13
1 = CRC error
14
1 = Alignment error
15
1 =Overrun error
16
Not used
8
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STAT: Status
Status of Global
Communication
(Words
179 ... 181)
Word 179 displays global communication status:
1
2
3
4
5
6
7
8
Bit
Function
1
1 = Comm health
2
1 = Cable A status
3
1 = Cable B status
4
Not used
5 ... 8
Lost communication counter
9 ... 16
Cumulative retry counter
9
10
11
12
13
14
15
16
15
16
15
16
Word 180 is the global cumulative error counter for Cable A:
1
2
3
4
5
6
7
Bit
Function
1 ... 8
Counts detected errors
9 ... 162
Counts No responses
8
9
10
11
12
13
14
Word 181 is the global cumulative error counter for Cable B:
1
2
3
4
5
6
7
Bit
Function
1 ... 8
Counts detected errors
9 ... 162
Counts No responses
8
9
10
11
12
13
14
1013
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STAT: Status
Status of Remote
I/O (Words
182 ... 277)
Words 182 ... 277 are used to describe remote I/O drop status; three status words
are used for each drop.
The first word in each group of three displays communication status for the
appropriate drop:
1
2
3
4
5
6
7
8
Bit
Function
1
1 = Communication health
2
1 = Cable A status
3
1 = Cable B status
4
Not used
5 ... 8
Lost communication counter
9 ... 16
Cumulative retry counter
9
10
11
12
13
14
15
16
The second word in each group of three is the drop cumulative error counter on
Cable A for the appropriate drop:
1
2
3
4
5
6
7
8
9
10
Bit
Function
1 ... 8
At least one error in words 173 ...175
9 ... 162
Counts No responses
11
12
13
14
15
16
The third word in each group of three is the drop cumulative error counter on Cable
B for the appropriate drop:
1
2
3
4
5
6
7
8
9
10
Bit
Function
1 ... 8
At least one error in words 176 ...178
9 ... 162
Counts No responses
11
12
13
14
15
16
Note: For PLCs where drop 1 is reserved for local I/O, status words 182 ... 184 are
used as follows:
1014
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STAT: Status
Word 182 displays local drop status:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Function
1
1 = All modules healthy
2 ... 8
Always 0
9 ... 162
Number of times a module has been seen as unhealthy; counter rolls over at 255
Word 183 is a 16-bit error counter, which indicates the number of times a module
has been accessed and found to be unhealthy. Rolls over at 65535.
Word 184 is a 16-bit error counter, which indicates the number of times a
communication error occurred while accessing an I/O module. Rolls over at 65535.
1015
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STAT: Status
Controller Status Words 1 - 11 for TSX Compact and Atrium
CPU Status
(Word 1)
Word 1 displays the following aspects of the CPU status:
1
2
3
4
5
6
7
8
9
Bit
Function
1-5
Not used
6
1 = enable constant sweep
7
1 = enable single sweep delay
8
1 = 16 bit user logic
0 = 24 bit user logic
9
1 = AC power on
10
1 = RUN light OFF
11
1 = memory protect OFF
12
1 = battery failed
13 - 16
Not used
10
11
Word 2
This word is not used.
Controller Status
(Word 3)
Word 3 displays aspects of the controller status:
1
Word 4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
12
13
14
15
16
Bit
Function
1
1 = first scan
2
1 = start command pending
3
1 = scan time has exceed constant scan target
4
1 = existing DIM AWARENESS
5 - 12
Not used
13 - 16
Single sweeps
This word is not used.
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STAT: Status
CPU Stop State
(Word 5)
Word 5 displays the CPU’s stop state conditions:
1
Number of
Segments
in program
(Word 6)
2
3
4
5
6
7
8
9
10
11
12
13
14
Bit
Function
1
1 = peripheral port stop
2
1 = XMEM parity error
3
1 = DIM AWARENESS
4
1 = illegal peripheral intervention
5
1 = invalid segment scheduler
6
1 = no start-of-network (SON) at the start of a segment
7
1 = state RAM test failed
8
1 = no end of logic (EOL), (bad Tcop)
9
1 = watch dog timer has expired
10
1 = real time clock error
11
1 = CPU failure
12
Not used
13
1 = invalid node in ladder logic
14
1 = logic checksum error
1
1 = coil disabled in RUN mode
16
1 = bad PLC setup
15
16
Word 6 displays the number of segments in ladder logic; a binary number is shown.
This word is confirmed during power up to be the number of EOS (DOIO) nodes plus
1 (for the end of logic nodes), if untrue, a stop code is set, causing the run light to
be off:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Function
1 - 16
Number of segments in the current ladder logic program (expressed as a decimal
number)
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STAT: Status
Address of the
End of Logic
Pointer (Word 7)
Word 7 displays the address of the end-of-logic (EOL) pointer:
1
2
3
4
5
6
7
Bit
Function
1 - 16
EOL pointer address
8
9
10
11
12
13
14
15
16
Word 8, Word 9
These words are not used.
RUN/LOAD/
DEBUG Status
(Word 10)
Word 10 uses its two least significant bits to display RUN/LOAD/DEBUG status:
Word 11
1
2
3
4
5
6
7
Bit
Function
1 ... 14
Not used
15, 16
0 0 = Debug (0 dec)
0 1 = Run (1 dec)
1 0 = Load (2 dec)
8
9
10
11
12
13
14
15
16
This word is not used.
1018
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STAT: Status
I/O Module Health Status Words 12 - 15 for TSX Compact
TSX Compact I/O
Module Health
Words 12 ... 15 are used to display the health of the A120 I/O modules in the
four racks:
Word
Rack No.
12
1
13
2
14
3
15
4
Each word contains the health status of up to five A120 I/O modules. The most
significant (left-most) bit represents the health of the module in Slot 1 of the rack:
1
2
3
4
Bit
Function
1
1 = Slot 1
2
1 = Slot 2
3
1 = Slot 3
4
1 = Slot 4
5
1 = Slot 5
6 ... 16
Not used
5
6
7
8
9
10
11
12
13
14
15
16
If a module is I/O Mapped and ACTIVE, the bit will have a value of "1". If a module
is inactive or not I/O Mapped, the bit will have a value of "0".
Note: Slots 1 and 2 in Rack 1 (Word 12) are not used because the controller itself
uses those two slots.
1019
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STAT: Status
Global Health and Communications Retry Status Words 182 ...
184 for TSX Compact
Overview
There are three words that contain health and communication information on the
installed I/O modules. If monitored with the Stat block, they are found in Words 182
through 184. This requires that the length of the Stat block is a minimum of 184
(Words 16 through 181 are not used).
Words 16 ... 181
These words are not used.
Health Status
(Word 182)
Word 182 increments each time a module becomes bad. After a module becomes
bad, this counter does not increment again until that module becomes good and
then bad again.
1
2
3
4
5
6
7
8
9
10
Bit
Function
1
1 = All modules healthy
2 ... 9
Not used
10 ... 16
"Module went unhealthy" counter
11
12
13
14
15
16
I/O Error
Counter
(Word 183)
This counter is similar to the above counter, except this word increments every scan
that a module remains in the bad state.
PAB Bus Retry
Counter
(Word 184)
Diagnostics are performed on the communications through the bus. This word
should normally be all zeroes. If after 5 retries, a bus error is still detected, the
controller will stop and error code 10 will be displayed. An error could occur if there
is a short in the backplane or from noise. The counter rolls over while running. If the
retries are less than 5, no bus error is detected.
1020
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SU16: Subtract 16 Bit
160
At a Glance
Introduction
This chapter describes the instruction SU16.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1022
Representation: SU16 - 16-bit Subtraction
1023
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SU16: Subtract 16 Bit
Short Description
Function
Description
The SU16 instruction performs a signed or unsigned 16-bit subtraction (value 1 value 2) on the top and middle node values, then posts the signed or unsigned
difference in a 4x holding register in the bottom node.
1022
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SU16: Subtract 16 Bit
Representation: SU16 - 16-bit Subtraction
Symbol
Representation of the instruction
CONTROL INPUT
TOP VALUE > MIDDLE VALUE
(+ result)
Value 1
Max. Value
65535
Value 2
TOP VALUE = MIDDLE VALUE
(zero result)
SU16
TOP VALUE < MIDDLE VALUE
(- result)
Max. Value
65535
SIGNED
difference
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON = enables value 1 - value 2
Bottom input
0x, 1x
None
ON = signed operation
OFF = unsigned operation
value 1
(top node)
3x, 4x
INT, UINT
Minuend, can be displayed explicitly as an
integer (range 1 ... 65 535) or stored in a register
value 2
(middle node)
3x, 4x
INT, UINT
Subtrahend, can be displayed explicitly as an
integer (range 1 ... 65 535) or stored in a register
difference
(bottom node)
4x
INT, UINT
Difference
Top output
0x
None
ON = value 1 > value 2
Middle output
0x
None
ON = value 1 = value 2
Bottom output
0x
None
ON = value 1 < value 2
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SU16: Subtract 16 Bit
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SUB: Subtraction
161
At a Glance
Introduction
This chapter describes the instruction SUB.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1026
Representation: SUB - Subtraction
1027
1025
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SUB: Subtraction
Short Description
Function
Description
The SUB instruction performs a signed or unsigned 16-bit subtraction (value 1 value 2) on the top and middle node values, then posts the signed or unsigned
difference in a 4x holding register in the bottom node.
Note: SUB is often used as a comparator where the state of the outputs identifies
whether value 1 is greater than, equal to, or less than value 2.
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SUB: Subtraction
Representation: SUB - Subtraction
Symbol
Representation of the instruction
CONTROL INPUT
Parameter
Description
value 1
TOP VALUE > MIDDLE VALUE
(+ result)
Max.
999 16-bit PLC
9999 24-bit PLC
65535-785L
value 2
TOP VALUE = MIDDLE VALUE
(zero result)
Max.
999 16-bit PLC
9999 24-bit PLC
65535-785L
SUB
TOP VLUE < MIDDLE VALUE
(- result)
difference
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = enables value 1 - value 2
value 1
(top node)
3x, 4x
INT, UINT
Minuend, can be displayed explicitly as an
integer or stored in a register
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535-785L
value 2
(middle node)
3x, 4x
INT, UINT
Subtrahend, can be displayed explicitly as
an integer or stored in a register
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535-785L
difference
(bottom node)
4x
INT, UINT
Difference
Top output
0x
None
ON = value 1 > value 2
Middle output
0x
None
ON = value 1 = value 2
Bottom output
0x
None
ON = value 1 < value 2
1027
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SUB: Subtraction
1028
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SWAP - VME Bit Swap
162
At A Glance
Introduction
This chapter describes the instruction SWAP.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: SWAP - VME Bit Swap
1030
Representation: SWAP - VME Bit Swap
1031
1029
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SWAP - VME Bit Swap
Short Description: SWAP - VME Bit Swap
Function
Description
The SWAP block allows the user to issue one of three different swap commands:
Swap high and low bits of a 16-bit word.
z Swap high and low words of a 32-bit double word.
z Swap (reverse) bits within a register's low byte.
z
Note: Available only on the Quantum VME-424/X controller.
1030
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SWAP - VME Bit Swap
Representation: SWAP - VME Bit Swap
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
value
ERROR
register
COMPLETE
SWAP
# of registers
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON enables SWAP operation
INT, UINT,
WORD
Contains a constant from 1 to 3, which
specifies what type of swap to perform:
1. Swap high and low bits of a 16-bit word.
2. Swap high and low words of a 32-bit
double word.
3. Swap (reverse) bits within a register's
low byte.
INT, UINT,
WORD
Contains the register on which the swap is
to be performed
INT, UINT,
WORD
Contains a constant that indicates how
many registers are to be swapped, starting
with the source register.
value
(top node)
register
(middle node)
3x, 4x
# of registers
(bottom node)
Top output
0x
None
Echoes the state of the top input
Middle output
0x
None
Error
Bottom output
0x
None
Swap completed successfully
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SWAP - VME Bit Swap
1032
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TTR - Table to Register
163
At A Glance
Introduction
This chapter describes the instruction TTR.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: TTR - Table to Register
1034
Representation: TTR - Table to Register
1035
1033
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TTR - Table to Register
Short Description: TTR - Table to Register
Function
Description
The Table to Register block is one of four 484-replacement instructions.
It copies the contents of a source (input or holding) register to a holding register
implied by the constant in the bottom node. This source register is pointed to by the
input or holding register specified in the top node. Only one such operation can be
accommodated by the system in each scan.
Note: Available only on the 984-351 and 984-455.
1034
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TTR - Table to Register
Representation: TTR - Table to Register
Symbol
Representation of the instruction
CONTROL INPUT
COPY
source
ERROR
TTR
destination
offset pointer
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
Control source
source
(top node)
3x, 4x
INT, UINT
The source node (top node) contains the
source register address. The data located in
the source register address will be copied to
the destination address, which is determined
by the destination offset pointer.
destination
(bottom node)
(1 ... 254)
(801 ... 824)
INT, UINT
The pointer is a 3xxxx or 4xxxx whose
contents indicate the source. A value of 1 to
254 indicates a holding register (40001 40254) and a value of 801 to 832 indicates an
input register (30001 - 30032). If the value is
outside this range, the operation is not
performed and the ERROR rail is powered.
Top output
0x
None
Passes power when top input receives power
Bottom output
0x
None
Pointer value out of range
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TTR - Table to Register
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T --> R Table to Register
164
At a Glance
Introduction
This chapter describes the instruction ToR.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1038
Representation: T o R - Table to Register Move
1039
Parameter Description
1041
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T --> R: Table to Register
Short Description
Function
Description
The ToR instruction copies the bit pattern of a register or 16 contiguous discretes
in a table to a specific holding register. It can accommodate the transfer of one
register per scan. It has three control inputs and produces two possible outputs.
1038
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T --> R: Table to Register
Representation: T o R - Table to Register Move
Symbol
Representation of the instruction
CONTROL INPUT/INCREASE POINTER
source table
ACTIVE
PREVENTS POINTER
FROM INCREASING
pointer
POINTER = TABLE LENGTH
RESET POINTER
T ÆR
Table length
Max. 255 16-bit PLC
999 24-bit PLC
table length
1039
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T --> R: Table to Register
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM Reference Data Type Meaning
Top input
0x, 1x
None
ON = copies source data and
increments the pointer value
Middle input 0x, 1x
(see p. 1041)
None
ON = freezes the pointer value
Bottom input 0x, 1x
(see p. 1041)
None
ON = resets the pointer value to zero
source table
(top node)
0x, 1x, 3x, 4x
INT, UINT, First register or discrete reference in
WORD
the source table. A register or string of
contiguous discretes from this table will
be copied in a scan.
pointer (see
p. 1041)
(middle
node)
4x
INT, UINT
Pointer to the destination where the
source data will be copied
INT, UINT
Length of the source table: number of
registers that may be copied; range: 1
... 999
Length:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
0x
None
Echoes the state of the top input
Middle output 0x
None
ON = pointer value = table length
(instruction cannot increment
any further)
table length
(bottom
node)
Top output
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T --> R: Table to Register
Parameter Description
Middle Input
When the middle input goes ON, the current value stored in the pointer register is
frozen while the DX operation continues. This causes the same table data to be
written to the destination register on each scan.
Bottom Input
When the bottom input goes ON, the value in the pointer is reset to zero. This causes
the next DX move operation to copy the first destination register in the table.
Pointer
(Middle Node)
The 4x register entered in the middle node is a pointer to the destination where the
source data will be copied. The destination register is the next contiguous 4x register
after the pointer. For example, if the middle node displays a pointer of 400100, then
the destination register for the ToR copy is 400101.
The value stored in the pointer register indicates which register in the source table
will be copied to the destination register in the current scan. A value of 0 in the
pointer indicates that the bit pattern in the first register of the source table will be
copied to the destination; a value of 1 in the pointer register indicates that the bit
pattern in the second register of the source table will be copied to the destination
register; etc.
1041
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T --> R: Table to Register
1042
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T --> T: Table to Table
165
At a Glance
Introduction
This chapter describes the instruction ToT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1044
Representation: T o T - Table to Table Move
1045
Parameter Description
1047
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T --> T: Table to Table
Short Description
Function
Description
The ToT instruction copies the bit pattern of a register or of 16 discretes from a
position within one table to an equivalent position in another table of registers. It can
accommodate the transfer of one register per scan. It has three control inputs and
produces two possible outputs.
1044
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T --> T: Table to Table
Representation: T o T - Table to Table Move
Symbol
Representation of the instruction
CONTROL INPUT/INCREASE POINTER
source table
ACTIVE
PREVENTS POINTER
FROM INCREASING
pointer
POINTER = TABLE LENGTH
RESET POINTER
Table length
Max. 255 16-bit PLC
999 24-bit PLC
65535 *PLC
TÆT
table length
*Available on the following
z E685/785 PLCs
z L785 PLCs
z Quantum Series PLCs
1045
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T --> T: Table to Table
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = copies source data and
increments the pointer value
Middle input
(see p. 1047)
0x, 1x
None
ON = freezes the pointer value
Bottom input
(see p. 1047)
0x, 1x
None
ON = resets the pointer value to zero
source table
(top node)
0x, 1x, 3x, 4x
INT, UINT,
WORD
First register or discrete reference in
the source table. A register or string
of contiguous discretes from this
table will be copied in a scan.
pointer (see
p. 1047)
(middle node)
4x
INT, UINT
Pointer into both the source and
destination table
INT, UINT
Length of the source and the
destination table (must be equal in
length)
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
table length
(bottom node)
Top output
0x
None
Echoes the state of the top input
Middle output
0x
None
ON = pointer value = table length
(instruction cannot increment any
further)
1046
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T --> T: Table to Table
Parameter Description
Middle Input
When the input to the middle node goes ON, the current value stored in the pointer
register is frozen while the DX operation continues. This causes new data being
copied to the destination to overwrite the data copied on the previous scan.
Bottom Input
When the input to the bottom node goes ON, the value in the pointer register is reset
to zero. This causes the next DX move operation to copy source data into the first
register in the destination table.
Pointer
(Middle Node)
The 4x register entered in the middle node is a pointer into both the source and
destination tables, indicating where the data will be copied from and to in the current
scan. The first register in the destination table is the next contiguous 4x register
following the pointer. For example, if the middle node displays a a pointer reference
of 400100, then the first register in the destination table is 400101.
The value stored in the pointer register indicates which register in the source table
will be copied to which register in the destination table. Since the length of the two
tables is equal and ToT copy is to the equivalent register in the destination table,
the current value in the pointer register also indicates which register in the
destination table the source data will be copied to.
A value of 0 in the pointer register indicates that the bit pattern in the first register of
the source table will be copied to the first register of the destination table; a value of
1 in the pointer register indicates that the bit pattern in the second register of the
source table will be copied to the second register of the destination register; etc.
1047
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T --> T: Table to Table
1048
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T.01 Timer: One
Hundredth Second Timer
166
At a Glance
Introduction
This chapter describes the instruction T.01 Timer.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1050
Representation: T.01 - One Hundredth of a Second Timer
1051
1049
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T.01 Timer: One Hundredth Second Timer
Short Description
Function
Description
The T.01 instruction measures time in hundredth of a second intervals. It can be
used for timing an event or creating a delay. T.01 has two control inputs and can
produce one of two possible outputs.
1050
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T.01 Timer: One Hundredth Second Timer
Representation: T.01 - One Hundredth of a Second Timer
Symbol
Representation of the instruction
CONTROL INPUT
Max. 999 16-bit PLC
9999 24-bit PLC
65535 - 785L
TIMER = PRESET
timer preset
ENABLE/RESET
TIMER < PRESET
T.01
accumulated
time
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
OFF o ON = initiates the timer operation: time
accumulates in hundredths-of-a-second when
top and bottom input are ON
Bottom input
0x, 1x
None
OFF = accumulated time reset to 0
ON = timer accumulating
timer preset
(top node)
3x, 4x
INT, UINT
Preset value (number of hundredth-of-asecond increments), can be displayed
explicitly as an integer or stored in a register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated
time
(bottom node)
4x
INT, UINT
Accumulated time count in hundredth-of-asecond increments.
Top output
0x
None
ON = accumulated time = timer preset
Bottom output
0x
None
ON = accumulated time < timer preset
1051
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T.01 Timer: One Hundredth Second Timer
1052
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T0.1 Timer: One Tenth
Second Timer
167
At a Glance
Introduction
This chapter describes the instruction T0.1 Timer.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1054
Representation: T0.1 - One Tenth of a Second Timer
1055
1053
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T0.1 Timer: One Tenth Second Timer
Short Description
Function
Description
The T0.1 instruction measures time in tenth-of-a-second increments. It can be used
for timing an event or creating a delay. T0.1 has two control inputs and can produce
one of two possible outputs.
Note: If you cascade T0.1 timers with presets of 1, the timers will time-out together;
to avoid this problem, change the presets to 10 and substitute a T.01 timer (see
p. 1049).
1054
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T0.1 Timer: One Tenth Second Timer
Representation: T0.1 - One Tenth of a Second Timer
Symbol
Representation of the instruction
CONTROL INPUT
Max. 999 16-bit PLC
9999 24-bit PLC
65535 - 785L
TIMER = PRESET
timer preset
ENABLE/RESET
TIMER < PRESET
T0.1
accumulated
time
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
OFF o ON = initiates the timer operation:
time accumulates in tenth-of-a-second
when top and bottom input are ON
Bottom input
0x, 1x
None
OFF = accumulated time reset to 0
ON = timer accumulating
timer preset
(top node)
3x, 4x
INT, UINT
Preset value (number of tenth-of-a-second
increments), can be displayed explicitly as
an integer or stored in a register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated
time
(bottom node)
4x
INT, UINT
Accumulated time count in tenth-of-asecond increments.
Top output
0x
None
ON = accumulated time = timer preset
Bottom output
0x
None
ON = accumulated time < timer preset
1055
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T0.1 Timer: One Tenth Second Timer
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T1.0 Timer: One Second Timer
168
At a Glance
Introduction
This chapter describes the instruction T1.0 Timer.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1058
Representation: T1.0 - One Second Timer
1059
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T1.0 Timer: One Second Timer
Short Description
Function
Description
The T1.0 timer instruction measures time in one-second increments. It can be used
for timing an event or creating a delay. T1.0 has two control inputs and can produce
one of two possible outputs.
Note: If you cascade T1.0 timers with presets of 1, the timers will time-out together;
to avoid this problem, change the presets to 10 and substitute a T0.1 timer (see
p. 1053).
1058
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T1.0 Timer: One Second Timer
Representation: T1.0 - One Second Timer
Symbol
Representation of the instruction
CONTROL INPUT
Max. 999 16-bit PLC
9999 24-bit PLC
65535 - 785L
TIMER = PRESET
timer preset
ENABLE / RESET
TIMER < PRESET
T1.0
accumulated
time
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM Reference
Data Type
Meaning
Top input
0x, 1x
None
OFF o ON = initiates the timer
operation: time accumulates in
seconds when top and bottom
input are ON
Bottom input
0x, 1x
None
OFF = accumulated time reset to 0
ON = timer accumulating
timer preset
(top node)
3x, 4x
INT, UINT
Preset value (number of one
second increments), can be
displayed explicitly as an integer or
stored in a register
Range:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated
time
(bottom node)
4x
INT, UINT
Accumulated time count in onesecond increments.
Top output
0x
None
ON = accumulated time =
timer preset
Bottom output
0x
None
ON = accumulated time <
timer preset
1059
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T1.0 Timer: One Second Timer
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T1MS Timer: One
Millisecond Timer
169
At a Glance
Introduction
This chapter describes the instruction T1MS Timer.
What's in
this Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1062
Representation: T1MS - One Millisecond Timer
1063
Example
1064
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T1MS Timer: One Millisecond Timer
Short Description
Function
Description
The T1MS timer instruction measures time in one-millisecond increments. It can be
used for timing an event or creating a delay.
Note: The T1MS instruction is available only on the B984-102, the Micro 311, 411,
512, and 612, and the Quantum 424 02.
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T1MS Timer: One Millisecond Timer
Representation: T1MS - One Millisecond Timer
Symbol
Representation of the instruction
CONTROL INPUT
TIMER = PRESET
timer preset
Preset value
Max. 999 (in ms.)
ENABLE/RESET
TIMER < PRESET
accumulated
time
T1MS
#1
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON = initiates the timer operation: time
accumulates in milliseconds when top and
middle input are ON
Middle input
0x, 1x
None
OFF = accumulated time reset to 0
ON = timer accumulating
timer preset
(top node)
3x, 4x
INT, UINT
Preset value (number of millisecond increments
the timer can accumulate), can be displayed
explicitly as an integer (range 1 ... 999) or stored
in a register
accumulated
time
(middle node)
4x
INT, UINT
Accumulated time count in millisecond
increments.
INT, UINT
Constant value of #1
#1
(bottom node)
Top output
0x
None
ON = accumulated time = timer preset
Middle output
0x
None
ON = accumulated time < timer preset
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T1MS Timer: One Millisecond Timer
Example
A Millisecond
Timer Example
Here is the ladder logic for a real-time clock with millisecond accuracy:
100
000001
400055
10
T1MS
UCTR
400054
000002
000001
1
60
000003
UCTR
400053
60
000002
000004
UCTR
400052
24
000003
000005
UCTR
400051
000004
000005
The T1MS instruction is programmed to pass power at 100 ms intervals; it is
followed by a cascade of four up-counters (see p. 1077) that store the time
respectively in hundredth-of-a-second units, tenth-of-a-second units, one- second
units, one-minute units, and one-hour units.
When logic solving begins, the accumulated time value begins incrementing in
register 40055 of the T1MS block. After 100 one-ms increments, the top output
passes power and energizes coil 00001. At this point, the value in register 40055 in
the timer is reset to 0. The accumulated count value in register 40054 in the first
UCTR block increments by 1, indicating that 100 ms have passed. Because the
accumulated time count in T1MS no longer equals the timer preset, the timer begins
to re-accumulate time in ms.
When the accumulated count in register 40054 of the first UCTR instruction
increments to 10, the top output from that instruction block passes power and
energizes coil 00002. The value in register 40054 then resets to 0, and the
accumulated count in register 40053 of the second UCTR block increments by 1.
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T1MS Timer: One Millisecond Timer
As the times accumulate in each counter, the time of day can be read in five holding
registers as follows:
Register
Unit of Time
Valid Range
40055
Thousandths-of-a-second
0 ... 100
40054
Tenths-of-a-second
0 ... 10
40053
Seconds
0 ... 60
40052
Minutes
0 ... 60
40051
Hours
0 ... 24
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T1MS Timer: One Millisecond Timer
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TBLK: Table to Block
170
At a Glance
Introduction
This chapter describes the instruction TBLK.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1068
Representation: TBLK - Table-to-Block Move
1069
Parameter Description
1071
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TBLK: Table to Block
Short Description
Function
Description
The TBLK (table-to-block) instruction combines the functions of ToR (see p. 1037)
and the BLKM (see p. 127) in a single instruction. In one scan, it can copy up to 100
contiguous 4x registers from a table to a destination block. The destination block is
of a fixed length. The block of registers being copied from the source table is of the
same length, but the overall length of the source table is limited only by the number
of registers in your system configuration.
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TBLK: Table to Block
Representation: TBLK - Table-to-Block Move
Symbol
Representation of the instruction
CONTROL INPUT
OPERATION SUCCESSFUL
source table
HOLD POINTER
ERROR
pointer
RESET POINTER
TBLK
block length
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = initiates move operation
Middle input
(see p. 1071)
0x, 1x
None
ON = hold pointer - The inputs to the middle
and bottom node can be used to control the
value in the pointer so that size of the source
table can be controlled.
Important: You should use external logic in
conjunction with the middle or bottom input to
confine the value in the destination pointer to
a safe range. When the input to the middle
node is ON, the value in the pointer register is
frozen while the TBLK operation continues.
This causes the same source data block to be
copied to the destination table on each scan.
Bottom input
(see p. 1071)
0x, 1x
None
ON = reset pointer to zero
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TBLK: Table to Block
Parameters
State RAM
Reference
Data Type
Meaning
source table
(see p. 1071)
(top node)
4x
INT, UINT,
WORD
First holding register in the source table
The 4xxxx register entered in the top node is
the first holding register in the source table.
Note: The source table is segmented into a
series of register blocks, each of which is the
same length as the destination block.
Therefore, the size of the source table is a
multiple of the length of the destination block,
but its overall size is not specifically defined in
the instruction. If left uncontrolled, the source
table could consume all the 4xxxx registers
available in the PLC configuration.
pointer (see
p. 1071)
(middle node)
4x
INT, UINT
Pointer to the source block, destination block
INT, UINT
Number of registers of the destination block
and of the blocks within the source table;
range: 1 ... 100
block length
(bottom node)
Top output
0x
None
ON = move successful
Middle output
0x
None
ON = error / move not possible
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TBLK: Table to Block
Parameter Description
Middle Input
When the middle input is ON, the value in the pointer register is frozen while the
TBLK operation continues. This causes the same source data block to be copied to
the destination table on each scan.
Bottom Input
When the bottom input is ON, the pointer value is reset to zero. This causes the
TBLK operation to copy data from the first block of registers in the source table.
CAUTION
Confine the value in the destination pointer to a safe range.
You should use external logic in conjunction with the middle and the bottom inputs
to confine the value in the destination pointer to a safe range.
Failure to follow this instruction can result in injury or equipment damage.
Source Table
(Top Node)
The 4x register entered in the top node is the first holding register in the source table.
Note: The source table is segmented into a series of register blocks, each of which
is the same length as the destination block. Therefore, the size of the source table
is a multiple of the length of the destination block, but its overall size is not
specifically defined in the instruction. If left uncontrolled, the source table could
consume all the 4x registers available in the PLC configuration.
Pointer
(Middle Node)
The 4x register entered in the middle node is the pointer to the source block. The
first register in the destination block is the next contiguous register after the pointer.
For example, if the pointer is register 400107, then the first register in the destination
block is 400108.
The value stored in the pointer indicates which block of data from the source table
will be copied to the destination block. This value specifies a block number within the
source table.
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TBLK: Table to Block
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TEST: Test of 2 Values
171
At a Glance
Introduction
This chapter describes the instruction TEST.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1074
Representation: TEST - Test of 2 Values
1075
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TEST: Test of 2 Values
Short Description
Function
Description
The TEST instruction compares the signed or unsigned size of the 16-bit values in
the top and middle nodes and describes the relationship via the block outputs.
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TEST: Test of 2 Values
Representation: TEST - Test of 2 Values
Symbol
Representation of the instruction
CONTROL INPUT
TOP VALUE > MIDDLE VALUE
value 1
Max. value: 65535
TOP VALUE = MIDDLE VALUE
value 2
Max. value: 65535
SIGNED
TOP VALUE < MIDDLE VALUE
TEST
#1
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = compares value 1 and value 2
Bottom input
0x, 1x
None
ON = signed operation
OFF = unsigned operation
value 1
(top node)
3x, 4x
INT, UINT
Value 1, can be displayed explicitly as an
integer (range 1 ... 65 535) or stored in a
register
value 2
(middle node)
3x, 4x
INT, UINT
Value 2, can be displayed explicitly as an
integer (range 1 ... 65 535) or stored in a
register
INT, UINT
Constant value, cannot be changed
1
(bottom node)
Top output
0x
None
ON = value 1 > value 2
Middle output
0x
None
ON = value 1 = value 2
Bottom output
0x
None
ON = value 1 < value 2
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TEST: Test of 2 Values
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UCTR: Up Counter
172
At a Glance
Introduction
This chapter describes the instruction UCTR.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1078
Representation: UCTR - Up Counter
1079
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UCTR: Up Counter
Short Description
Function
Description
The UCTR instruction counts control input transitions from OFF to ON up from zero
to a counter preset value.
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UCTR: Up Counter
Representation: UCTR - Up Counter
Symbol
Representation of the instruction
CONTROL
Preset Value: 999 16-bit PLC
(max)
9999 24-bit PLC
65535 - *PLC
ENABLE/RESET COUNT
VALUE
counter preset
UCTR
OUTPUT CONDITION
UCTR: count = preset
OUTPUT CONDITION
UCTR: count < preset
accumulated
count
*Available on the following
z E685/785 PLCs
z L785 PLCs
z Quantum Series PLCs
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
OFF o ON = initiates the counter operation
Bottom input
0x, 1x
None
OFF = reset accumulator to 0
ON = counter accumulating
counter preset
(top node)
3x, 4x
INT, UINT
Preset value, can be displayed explicitly as
an integer or stored in a register
Preset value:
Max. 255 16-bit PLC
Max. 999 24-bit PLC
Max. 65535 785L
accumulated
count
(bottom node)
4x
INT, UINT
Count value (actual value); which
increments by one on each transition from
OFF to ON of the top input until it reaches
the specified counter preset value.
Top output
0x
None
ON = accumulated count = counter preset
Bottom output
0x
None
ON = accumulated count < counter preset
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UCTR: Up Counter
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VMER - VME Read
173
At A Glance
Introduction
This chapter describes the instruction VMER.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: VMER - VME Read
1082
Representation: VMER - VME Read
1083
Parameter Description: VMER - VME Read
1084
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VMER - VME Read
Short Description: VMER - VME Read
Function
Description
The VME Read block allows the user to read data from devices on the VME bus. If
Byte Swap is active, the high byte is exchanged with the low byte of a word after it
is read from the VME bus. If Word Swap is enabled, the upper word is exchanged
with the lower word of a double after it is read. An error will occur if both inputs are
enabled at once.
Note: Available only on the Quantum VME-424/X controller.
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VMER - VME Read
Representation: VMER - VME Read
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
register
BYTE SWAP
ERROR
pointer
WORD SWAP
COMPLETE
VMER
value
(1 ... 255)
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON enables read
Middle input
0x, 1x
None
ON = byte swap
Bottom input
0x, 1x
None
ON = word swap
register
(top node)
4x
INT, UINT, There are five control registers in the top node.
WORD
They are allotted as follows:
4x - VME Address modifier code (39, 3A, 3D, 3E,
29, or 2D 4x+1 to 4x+4 - The VME Control Block
(For expanded and detailed information please
see p. 1084.)
pointer
4x
(middle node)
INT, UINT A pointer to the first destination register.
WORD
(For expanded and detailed information please
see p. 1084.)
value
(bottom node)
INT, UINT A constant specifying the number of destination
WORD
registers to which data is transferred. This
constant can be from 1 to 255.
Top output
0x
None
ON when the top input receives power
Middle output 0x
None
ON When an error occurs
Bottom output 0x
None
On when the read is complete
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VMER - VME Read
Parameter Description: VMER - VME Read
VME Control
Block
Error Code
Status
This is the VME control block.
Register
Description
Displayed
VME Address modifier code
First implied
Error code status
Please see Error Code Status Table
Second implied
Length of data to be read/written
Third implied
VME Device address (low byte)
Fourth implied
VME Device address (high byte)
This is the Error Code Status table.
Error
Description
01
Bad word count. Must be an even number of words
02
Bad length, greater than 255
03
Bad data length. Length was 0 or greater than 255
04
Bad address modifier in first control block
05
Bad command in top node of SWAP block
06
Bad VME bus interface
07
VME bus address doesn’t exist
08
VME 486 timeout
09
ME bus interface has not been configured
10
Both BYTE and WORD swap inputs have been selected
11
Match the type implied by the AM code (A16 or A2)
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VMEW - VME Write
174
At A Glance
Introduction
This chapter describes the instruction VMEW.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: VMEW - VME Write
1086
Representation: VMEW - VME Write
1087
Parameter Description: VMEW - VME Write
1089
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VMEW - VME Write
Short Description: VMEW - VME Write
Function
Description
The VME Write block allows the user to write data to devices on the VME bus. If
BYTE SWAP is active, the high byte is exchanged with the low byte of a word before
it is written to the VME bus. If WORD SWAP is active, the upper word is exchanged
with the lower word of a double before it is written. An error will occur if both inputs
are enabled at once.
Note: Available only on the Quantum VME-424/X controller.
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VMEW - VME Write
Representation: VMEW - VME Write
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
register
BYTE SWAP
ERROR
pointer
WORD SWAP
VMEW
COMPLETE
value
(1 ... 255)
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VMEW - VME Write
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON enables read
Middle input
0x, 1x
None
ON = byte swap
Bottom input
0x, 1x
None
ON = word swap
register
(top node)
4x
INT, UINT
WORD
There are five control registers in the top
node. They are allotted as follows:
4x - High Byte: VME Address modifier code
(39, 3A, 3D, 3E, 29, or 2D
4x - Low Byte: Data bus size
4x + 1 to 4x + 4 - The VME Control Block
(For expanded and detailed information
please see p. 1089.)
pointer
(middle node)
3x, 4x
INT, UINT
WORD
A pointer to the first destination register.
(For expanded and detailed information
please see p. 1089.)
INT, UINT
WORD
A constant specifying the number of
destination registers to which data is
transferred. This can be from 1 to 255.
value
(bottom node)
Top output
0x
None
ON when the top input receives power
Passes power when top input receives power
Middle output
0x
None
ON when an error occurs
Bottom output
0x
None
ON when write is complete
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VMEW - VME Write
Parameter Description: VMEW - VME Write
VME Control
Block
This is the VME control block.
Register
Description
Displayed
VME Address modifier code
First implied
Error code status
Please see Error Code Status Table
Second implied Length of data to be read/written
Error Code
Status
Third implied
VME Device address (low byte)
Fourth implied
VME Device address (high byte)
This is the Error Code Status table.
Error
Description
01
Bad word count. Must be an even number of words
02
Bad length, greater than 255
03
Bad data length. Length was 0 or greater than 255
04
Bad address modifier in first control block
05
Bad command in top node of SWAP block
06
Bad VME bus interface
07
VME bus address doesn’t exist
08
VME 486 timeout
09
ME bus interface has not been configured
10
Both BYTE and WORD swap inputs have been selected
11
Match the type implied by the AM code (A16 or A2)
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VMEW - VME Write
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WRIT: Write
175
At a Glance
Introduction
This chapter describes the instruction WRIT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1092
Representation: WRIT - Write ASCII Port
1093
Parameter Description
1094
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WRIT: Write
Short Description
Function
Description
The WRIT instruction sends a message from the PLC over the RIO communications
link to an ASCII display (screen, printer, etc.).
In the process of sending the messaging operation, WRIT performs the
following functions:
z Verifies the correctness of the ASCII communication parameters, e.g. the port
number, the message number
z Verifies the lengths of variable data fields
z Performs error detection and recording
z Reports RIO interface status
WRIT requires two tables of registers: a source table where variable data (the
message) is copied, and a control block where comm port and message parameters
are identified.
Further information about formatting messages you will find on p. 83.
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WRIT: Write
Representation: WRIT - Write ASCII Port
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source
PAUSE OPERATION
ERROR (ONE SCAN)
control
block
ABORT OPERATION
COMPLETE (ONE SCAN)
WRIT
Table length
Max. 255
Parameter
Description
table length
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON = initiates a WRIT
Middle input
0x, 1x
None
ON = pauses WRIT operation
Bottom input
0x, 1x
None
ON = abort WRIT operation
source (see
p. 1094)
(top node)
3x, 4x
INT, UINT, Source table
WORD
control block
(see p. 1094)
(middle node)
4x
INT, UINT, ASCII Control block (first of seven contiguous
WORD
holding registers)
(For expanded and detailed information please
see p. 1094.)
table length
(bottom node)
INT, UINT
Length of source table (number of registers
where the message data will be stored), range:
1 ... 255
Top output
0x
None
Echoes the state of the top input
Middle output
0x
None
ON = error in communication or operation has
timed out (for one scan)
Bottom output
0x
None
ON = WRIT complete (for one scan)
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WRIT: Write
Parameter Description
Source Table
(Top Node)
The top node contains the first 3x or 4x register in a source table whose length is
specified in the bottom node. This table contains the data required to fill the variable
field in a message.
Consider the following WRIT message
vessel #1 temperature is:
III
The 3-character ASCII field III is the variable data field; variable data are loaded,
typically via DX moves, into a table of variable field data.
Control Block
(Middle Node)
The 4x register entered in the middle node is the first of seven contiguous holding
register in the control block.
Register
Definition
Displayed
Port Number and Error Code, p. 1095
First implied
Message number
Second implied Number of registers required to satisfy format
Third implied
Count of the number of registers transmitted thus far
Fourth implied
Status of the solve
Fifth implied
Reserved
Sixth implied
Checksum of registers 0 ... 5
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WRIT: Write
Port Number and
Error Code
Port Number and Error Code
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit
Function
1 ... 4
PLC error code (see table below)
5
Not used
6
Input from the ASCII device not compatible with format
7
Input buffer overrun, data received too quickly at RIOP
8
USART error, bad byte received at RIOP
9
Illegal format, not received properly by RIOP
10
ASCII device off-line, check cabling
11
ASCII message terminated early (in keyboard mode
12 ... 16
Comm port # (1 ... 32)
PLC Error Code
Bit
Meaning
1
2
3
4
0
0
0
1
Error in the input to RIOP from ASCII device
0
0
1
0
Exception response from RIOP, bad data
0
0
1
1
Sequenced number from RIOP differs from expected value
0
1
0
0
User register checksum error, often caused by altering
READ registers while the block is active
0
1
0
1
Invalid port or message number detected
0
1
1
0
User-initiated abort, bottom input energized
0
1
1
1
No response from drop, communication error
1
0
0
0
Node aborted because of SKP instruction
1
0
0
1
Message area scrambled, reload memory
1
0
1
0
Port not configured in the I/O map
1
0
1
1
Illegal ASCII request
1
1
0
0
Unknown response from ASCII port
1
1
0
1
Illegal ASCII element detected in user logic
1
1
1
1
RIOP in the PLC is down
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WRIT: Write
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XMIT - Transmit
176
At A Glance
Introduction
This chapter describes the instruction XMIT - Transmit.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
General Description: XMIT - Transmit
1098
XMIT Modbus Functions
1099
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XMIT - Transmit
General Description: XMIT - Transmit
Overview
The XMIT (Transmit) function block sends Modbus messages from a "master" PLC
to multiple slave PLCs or sends ASCII character strings from the PLC's Modbus
slave port#1 or port#2 to ASCII printers and terminals. XMIT sends these messages
over telephone dial up modems, radio modems, or simply direct connection.
For more detailed information on the XMIT function block, see p. 1099.
XMIT comes with three modes: communication, port status, and conversion.
These modes are described in the following sections.
z
z
z
XMIT Communication Block, p. 1105
XMIT Port Status Block, p. 1117
XMIT Conversion Block, p. 1125
XMIT performs general ASCII input functions in the communication mode including
simple ASCII and terminated ASCII. You may use an additional XMIT block for
reporting port status information into registers while another XMIT block performs
the ASCII communication function. You may import and export ASCII or binary data
into your PLC and convert it into various binary data or ASCII to send to DCE
devices based upon the needs of your application.
The block has built in diagnostics, which ensure no other XMIT blocks are active in
the PLC. Within the XMIT block a control table allows you to control the
communications link between the PLC and Data Communication Equipment (DCE)
devices attached to Modbus port #1 or port#2 of the PLC. The XMIT block does not
activate the port LED when it's transmitting data.
Note: The Modbus protocol is a "master/slave" protocol and designed to have only
one master when polling multiple slaves. Therefore, when using the XMIT block in
a network with multiple masters, contention resolution, and collision avoidance is
your responsibility and may easily be addressed through ladder
logic programming.
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XMIT - Transmit
XMIT Modbus Functions
At a Glance
The XMIT function block supports the following Modbus function codes:.
z
z
z
z
01 ... 06
08
15 and 16
20 and 21
For Modbus messages, the MSG_OUT array has to contain the Modbus definition
table. The Modbus definition table for Modbus function code: 01, 02, 03, 04, 05, 06,
15 and 16 is five registers long and you must set XMIT_SET.MessageLen to 5 for
successful XMIT operation. The Modbus definition table is shown in the table below
Modbus
Function
Codes 01...06
For Modbus messages, the MSG_OUT array has to contain the Modbus definition
table. The Modbus definition table for Modbus function code: 01, 02, 03, 04, 05, 06,
15 and 16 is five registers long and you must set XMIT_SET.MessageLen to 5 for
successful XMIT operation. The Modbus definition table is shown in the table below
Modbus Definition Table Function Codes (01 ... 06, 15 and 16)
Content
Description
XMIT supports the following function codes:
Modbus
01 = Read multiple coils (0x)
function code
(MSG_OUT[1]) 02 = Read multiple discrete inputs (1x)
03 = Read multiple holding registers (4x)
04= Read multiple input registers (3x)
05 = Write single coil (0x)
06 = Write single holding registers (4x)
15 = Write multiple coils (0x)
16 = Write multiple holding registers (4x)
Quantity
Enter the amount of data you want written to the slave PLC or read from the
(MSG_OUT[2]) slave PLC. For example, enter 100 to read 100 holding registers from the
slave PLC or enter 32 to write 32 coils to a slave PLC. There is a size
limitation on quantity that is dependent on the PLC model. Refer to
Appendix A for complete details on limits.
Enter the slave Modbus PLC address. Typically the Modbus address range
Slave PLC
is 1 ... 247. To send a Modbus message to multiple PLCs, enter 0 for the
address
(MSG_OUT[3]) slave PLC address. This is referred to as Broadcast Mode. Broadcast Mode
only supports Modbus function codes that writes data from the master PLC
to slave PLCs. Broadcast Mode does NOT support Modbus function codes
that read data from slave PLCs.
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XMIT - Transmit
Content
Description
Slave PLC data For a read command, the slave PLC data area is the source of the data. For
area
a write command, the slave PLC data area is the destination for the data.
(MSG_OUT[4]) For example, when you want to read coils (00300 ... 00500) from a slave
PLC, enter 300 in this field. When you want to write data from a master PLC
and place it into register (40100) of a slave PLC, enter 100 in this field.
Depending on the type of Modbus command (write or read), the source and
destination data areas must be as defined in the Source and Destination
Data Areas table below.
For a read command, the master PLC data area is the destination for the
Master PLC
data returned by the slave. For a write command, the master PLC data area
data area
(MSG_OUT[5]) is the source of the data. For example, when you want to write coils (00016
... 00032) located in the master PLC to a slave PLC, enter 16 in the field.
When you want to read input registers (30001 ... 30100) from a slave PLC
and place the data into the master PLC data area (40100 ... 40199), enter
100 in this field. Depending on the type of Modbus command (write or read),
the source and destination data areas must be as defined in the Source and
Destination Data Areas table below.
Source and Destination Data Areas for Function Codes (01 ... 06, 15 and 16)
Function Code
Master PLC Data Area
Slave PLC Data Area
03 (Read multiple 4x)
4x (destination)
4x (source)
04 (Read multiple 3x)
4x (destination)
3x (source)
01 (Read multiple 0x)
0x (destination)
0x (source)
02 (Read multiple 1x)
0x (destination)
1x (source)
16 (Write multiple 4x)
4x (source)
4x (destination)
15 (Write multiple 0x)
0x (source)
0x (destination)
05 (Write single 0x)
0x (source)
0x (destination)
06 (Write single 4x)
4x (source)
4x (destination)
When you want to send 20 Modbus messages out of the PLC, you must transfer 20
Modbus definition tables one after another into MSG_OUT after each successful
operation of XMIT, or you may program 20 separate XMIT blocks and then activate
them one at a time through user logic.
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XMIT - Transmit
Modbus
Function
Code (08)
The Modbus definition table for Modbus function code: 08 is five registers long and
you must you must set XMIT_SET.MessageLen to 5 for For Modbus messages, the
MSG_OUT array has to contain the Modbus definition successful XMIT operation.
The Modbus definition table is shown in the table below.
Modbus Definition Table Function Codes (08)
Content
Description
Modbus function XMIT supports the following function code: 08 = Diagnostics
code
(MSG_OUT[1])
Diagnostics
(MSG_OUT[2])
Enter the diagnostics subfunction code decimal value in this filed to
perform the specific diagnostics function desired. The following diagnostic
subfunctions are supported:
Code
Description
00
Return query data
01
Restart comm option
02
Return diagnostic register
03
Change ASCII input delimiter
04
Force listen only mode
05 ... 09 Reserved
10
Clear counters (& diagnostics registers in 384, 484)
11
Return bus messages count
12
Return bus comm error count
13
Return bus exception error count
14 ... 15 Not supported
16
Return slave NAK count
17
Return slave busy count
18
Return bus Char overrun count
19 ... 21 Not supported
Slave PLC
address
(MSG_OUT[3])
Enter the slave Modbus PLC address. Typically the Modbus address
range is 1 ... 247. Function code 8 dose NOT support Broadcast Mode
(Address 0)
Diagnostics
function data
field content
(MSG_OUT[4])
You must enter the decimal value needed for the data area of the specific
diagnostic subfunction. For subfunctions 02, 04, 10, 11, 12, 13, 16, 17 and
18 this value is automatically set to zero. For subfunctions 00, 01, and 03
you must enter the desired data field value. For more details, refer to
Modicon Modbus Protocol Reference Guide (PI-MBUS-300).
Master PLC data For all subfunctions, the master PLC data area is the destination for the
data returned by the slave. You must specify a 4x register that marks the
area
(MSG_OUT[5]) beginning of the data area where the returned data is placed. For example,
to place the data into the master PLC data area starting at (40100), enter
100 in this field. Subfunction 04 does NOT return a response.
For more details, refer to Modicon Modbus Protocol Reference Guide (PIMBUS-300).
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XMIT - Transmit
Modbus
Function Codes
(20, 21)
For Modbus messages, the MSG_OUT array has to contain the Modbus definition
table. The Modbus definition table for Modbus function codes: 20 and 21 is six
registers long and you must you must set XMIT_SET.MessageLen to 6 for
successful XMIT operation. The Modbus definition table is shown in the table below.
Modbus Definition Table Function Codes (20, 21)
Content
Description
Modbus function
XMIT supports the following function codes: 20 = Read general
code (MSG_OUT[1]) reference (6x) 21 = Write general reference (6x)
Quantity
(MSG_OUT[2])
Enter the amount of data you want written to the slave PLC or read
from the slave PLC. For example, enter 100 to read 100 holding
registers from the slave PLC or enter 32 to write 32 coils to a slave
PLC. There is a size limitation on quantity that is dependent on the
PLC model. Refer to Appendix A for complete details on limits.
Slave PLC address
(MSG_OUT[3])
Enter the slave Modbus PLC address. Typically the Modbus address
range is 1 ... 247. Function code 20 and 21 do NOT support Broadcast
Mode (Address 0).
Slave PLC data area For a read command, the slave PLC data area is the source of the
(MSG_OUT[4])
data. For a write command, the slave PLC data area is the destination
for the data. For example, when you want to read registers (600300 ...
600399) from a slave PLC, enter 300 in this field. When you want to
write data from a master PLC and place it into register (600100) of a
slave PLC, enter 100 in this field. Depending on the type of Modbus
command (write or read), the source and destination data areas must
be as defined in the Source and Destination Data Areas table below.
The lowest extended register is addressed as register "zero" (600000).
The lowest holding register is addressed as register "one" (400001).
Master PLC data
For a read command, the master PLC data area is the destination for
area (MSG_OUT[5]) the data returned by the slave. For a write command, the master PLC
data area is the source of the data. For example, when you want to
write registers (40016 ... 40032) located in the master PLC to 6x
registers in a slave PLC, enter 16 in the filed. When you want to read
6x registers (600001 ... 600100) from a slave PLC and place the data
into the master PLC data area (40100 ... 40199), enter 100 in this field.
Depending on the type of Modbus command (write or read), the
source and destination data areas must be as defined in the Source
and Destination Data Areas table below. The lowest extended register
is addressed as register "zero" (600000). The lowest holding register
is addressed as register "one" (400001).
File number
(MSG_OUT[6])
Enter the file number for the 6x registers to be written to or read from.
(1 ... 10) depending on the size of the extended register data area.
600001 is 60001 file 1 and 690001 is 60001 file 10 as viewed by the
Reference Data Editor.
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XMIT - Transmit
Source and Destination Data Areas for Function Codes (20, 21)
Function Code
Master PLC Data Area Slave PLC Data Area
20 (Read general reference 6x)
4x (destination)
6x (source)
21 (Write general reference 6x)
4x (source)
6x (destination)
When you want to send 20 Modbus messages out of the PLC, you must transfer 20
Modbus definition tables one after another into MSG_OUT after each successful
operation of XMIT, or you may program 20 separate XMIT blocks and then activate
them one at a time through user logic.
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XMIT - Transmit
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XMIT Communication Block
177
At A Glance
Introduction
This chapter describes the instruction XMIT Communication Block.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: XMIT Communication Block
1106
Representation: XMIT Communication Block
1107
Parameter Description: Middle Node - Communication Control Table
1109
Parameter Description: XMIT Communication Block
1114
Parameter Description: XMIT Communications Block
1116
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XMIT Communication Block
Short Description: XMIT Communication Block
Function
Description
The purpose of the XMIT communication block is to receive and transmit ASCII
messages and Modbus Master messages using your PLC ports.
The XMIT instruction block will not operate correctly if:
The NSUP and XMIT loadables are not installed
z The NSUP loadable is installed after the XMIT loadable
z The NSUP and XMIT loadables are installed in a Quantum PLC with an out-ofdate executive (older than version 2.10 or 2.12)
z
For an overview of the XMIT instruction please see p. 1098.
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XMIT Communication Block
Representation: XMIT Communication Block
Symbol
Representation of the instruction
START
OPERATION IS ACTIVE
port
#0001
or
#0002
ABORT
OPERATION TERMINATED UNSUCCESSFULLY
register
OPERATION
SUCCESSFUL
XMIT
constant =
#0016
Parameter
Description
Description of the instruction’s parameters
Parameters State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON begins an XMIT operation and START
should remain ON until the operation has
completed successfully or an error has occurred.
Middle input 0x, 1x
None
ON aborts any active XMIT operation and forces
the port to slave mode. The abort code (121) is
placed into the fault status register. The port
remains closed as long as this input is ON.
Note: To reset an XMIT fault and clear the fault
register, the top input must go OFF for at least
one PLC scan.
port #0001
or #0002
(top node)
INT, UINT,
WORD
The top node must contain one of the following
constants either (#0001) to select PLC port #1, or
(#0002) to select PLC port #2.
Note: The loadable version DOES accept 4xxxx
registers in the top node, whereas the built-in
does NOT.
4x
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XMIT Communication Block
Parameters State RAM
Reference
register
(middle
node)
4x
#0016
(bottom
node)
Data Type
Meaning
INT, UINT,
WORD
The 4xxxx register entered in the middle node is
the first in a group of sixteen (16) contiguous
holding registers that comprise the control block,
as shown in the Communication Control Table.
(For expanded and detailed information on this
node please see p. 1109 in the Parameter
Description: Middle Node - XMIT Communication
Block.)
Important: DO NOT modify the address in the
middle node of the XMIT block or delete the
address from the block while the program is
active. This action locks up the port preventing
communications.
INT, UINT,
WORD
The bottom node must contain a constant equal
to (#0016). This is the number of registers used
by the XMIT instruction.
Top output
0x
None
ON while an XMIT operation in progress.
Passes power while an XMIT operation is in
progress.
Middle
output
0x
None
ON when XMIT has detected an error or was
issued an abort. Passes power when XMIT has
detected an error or when an XMIT operation
was aborted.
Bottom
output
0x
None
ON for one scan only when an XMIT operation
has been successfully completed. Passes power
when an XMIT operation has been successfully
completed.
Note: The START input must remain ON until the
OPERATION SUCCESSFUL has turned OFF.
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XMIT Communication Block
Parameter Description: Middle Node - Communication Control Table
Communication
Control Table
This table represents the first in a group of 16 contiguous holding registers that
comprise the control block.
Register
Name
Description
No Valid Entries
4xxxx
Revision
Number
Displays the current revision number of XMIT
block.
This number is automatically loaded by the
block and the block over writes any other
number entered into this register.
Read Only
4xxxx + 1
Fault
Status
This field displays a fault code generated by the Read Only
XMIT port status block. (For expanded and
detailed information please see p. 1114 in the
Parameter Description: XMIT Communication
Block section).
4xxxx + 2
Available
to User
The XMIT block does not use this register.
However, it may be used in ladder logic as a
pointer. An efficient way to use the XMIT block
is to place a pointer value of a TBLK instruction
into this register.
4xxxx + 3
Data Rate
XMIT supports the following data rates: 50, 75, Read/Write
110, 134, 150, 300, 600, 1200, 1800, 2000,
2400, 3600, 4800, 7200, 9600 and 19200.
To configure a data rate, enter its decimal
number into this field. When an invalid data rate
is entered, the block displays an illegal
configuration error (error code 127) in the Fault
Status (4xxxx + 1) register.
4xxxx + 4
Data Bits
XMIT supports the following data bits: 7 and 8. Read/Write
To configure a data bit size, enter its decimal
number into this register.
Note: Modbus messages may be sent in ASCII
mode or RTU mode. ASCII mode requires 7
data bits, while RTU mode requires 8 data bits.
When sending ASCII character message you
may use either 7 or 8 data bits. When an invalid
data bit is entered, the block displays an illegal
configuration error (error code 127) in the Fault
Status (4xxxx + 1) register.
Read/Write
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XMIT Communication Block
Register
Name
Description
No Valid Entries
4xxxx + 5
Parity Bits
XMIT supports the following parity: none, odd
and even. Enter a decimal of either: 0 = no
parity, 1 = odd parity, or 2 = even parity. When
an invalid parity is entered, the block displays
an illegal configuration error (error code 127) in
the Fault Status (4xxxx + 1) register.
Read/Write
4xxxx + 6
Stop Bits
XMIT supports one or two stop bits. Enter a
decimal of either: 1 = one stop bit, or 2 = two
stop bits. When an invalid stop bit is entered,
the block displays an illegal configuration error
(error code 127) in the Fault Status (4xxxx + 1)
register.
Read/Write
4xxxx + 7
Available
to User
The XMIT block does not use this register.
However, it may be used in ladder logic as a
pointer. An efficient way to use the XMIT block
is to place a pointer value of a TBLK instruction
into this register.
Read/Write
4xxxx + 8
Read/Write
Command (16-digit binary number)
Word
The XMIT interprets each bit of the command
word as a function to perform. If bit 7 and 8 are
on simultaneously or if any two or more of bits
13, 14, 15 or 16 are on simultaneously or if bit 7
is not on when bits 13, 14, 15, or 16 are on error
129 will be generated.
For expanded and detailed information please
see p. 1116 in the Parameter Description: XMIT
Communications Block section.
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XMIT Communication Block
Register
Name
Description
No Valid Entries
4xxxx + 9
Message
Pointer
Word
Read/Write
(message pointer)
Values are limited by the range of 4x registers
configured.
The message table consists of either
z ASCII characters
For ASCII character strings, the pointer is
the register offset to the first register of the
ASCII character string. Each register holds
up to two ASCII characters. Each ASCII
string may be up to 1024 characters in
length. For example, when you want to send
10 ASCII messages out of the PLC, you
must program 10 ASCII characters strings
into 4xxxx registers of the PLC and then
through ladder logic set the pointer to the
start of each message after each successful
operation of XMIT.
z Modbus Function Codes
For expanded and detailed information
please see p. 1099
Enter a pointer that points to the beginning of
the message table.
4xxxx + 10 Message
Length
Read/Write
(0 - 512)
Enter the length of the current message. When
XMIT is sending Modbus messages for function
codes 01, 02, 03, 04, 05, 06, 08, 15 and 16, the
length of the message is automatically set to
five. When XMIT is receiving Terminated ASCII
input the length of the message must be set to
five or an error results. When XMIT is sending
Modbus messages for function codes twenty
and twenty- -one, the length of the message is
automatically set to six. When XMIT is sending
ASCII messages, the length may be 1 through
1024 ASCII characters per message.
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XMIT Communication Block
Register
Name
4xxxx + 11 Response
Timeout
(ms)
Description
No Valid Entries
Read/Write
(0 - 65535 milliseconds)
Enter the time value in milliseconds (ms) to
determine how long XMIT waits for a valid
response message from a slave device (PLC,
modem, etc.). In addition, the time applies to
ASCII transmissions and flow control
operations. When the response message is not
completely formed within this specified time,
XMIT issues a fault. The valid range is 0 through
65535 ms. The timeout is initiated after the last
character in the message is sent.
Read/Write
4xxxx + 12 Retry Limit (0 - 65535 milliseconds)
Enter the quantity of retries to determine how
many times XMIT sends a message to get a
valid response from a slave device (PLC,
modem, etc.). When the response message is
not completely formed within this specified time,
XMIT issues a fault and a fault code. The valid
range is 0 ... 65535 # of retries. This field is used
in conjunction with response time-out (4xxxx +
11).
4xxxx + 13 Start of
Transmissi
on Delay
(ms)
Read/Write
(0 - 65535 milliseconds)
Enter the time value in milliseconds (ms) when
RTS/CTS control is enabled, to determine how
long XMIT waits after CTS is received before it
transmits a message out of the PLC port #1.
Also, you may use this register even when RTS/
CTS is NOT in control. In this situation, the
entered time value determines how long XMIT
waits before it sends a message out of the PLC
port #1. You may use this as a pre message
delay timer. The valid range is 0 through 65535
ms.
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XMIT Communication Block
Register
Name
Description
No Valid Entries
4xxxx + 14 End of
Transmissi
on Delay
(ms)
(0 - 65535 milliseconds)
To determine how long XMIT keeps an RTS
assertion once the message is sent out of the
PLC port #1, enter the time value in
milliseconds (ms) when RTS/CTS control is
enabled, After the time expires, XMIT ends the
RTS assertion. Also, you may use this register
even when RTS/CTS is NOT in control. In this
situation, the entered time value determines
how long XMIT waits after it sends a message
out of the PLC port #1. You may use this as a
post message delay timer. The valid range is 0
through 65535 ms.
Read/Write
4xxxx + 15 Current
Retry
The value displayed here indicates the current
number of retry attempts made by the XMIT
block
Read Only
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XMIT Communication Block
Parameter Description: XMIT Communication Block
Fault
Status Table
The following is a list of the fault codes generated by the XMIT port status block
(4x + 1).
Fault Code
Fault Description
1
Modbus exception -- Illegal function
2
Modbus exception -- Illegal data address
3
Modbus exception -- Illegal data value
4
Modbus exception -- Slave device failure
5
Modbus exception -- Acknowledge
6
Modbus exception -- Slave device busy
7
Modbus exception -- Negative acknowledge
8
Modbus exception -- Memory parity error
9 through 99 Reserved
100
Slave PLC data area cannot equal zero
101
Master PLC data area cannot equal zero
102
Coil (0x) not configured
103
Holding register (4xxxx) not configured
104
Data length cannot equal zero
105
Pointer to message table cannot equal zero
106
Pointer to message table is outside the range of configured holding registers
(4xxxx)
107
Transmit message timeout
(This error is generated when the UART cannot complete a transmission in 10
seconds or less. This error bypasses the retry counter and will activate the
error output on the first error.)
108
Undefined error
109
Modem returned ERROR
110
Modem returned NO CARRIER
111
Modem returned NO DIALTONE
112
Modem returned BUSY
113
Invalid LRC checksum from the slave PLC
114
Invalid CRC checksum from the slave PLC
115
Invalid Modbus function code
116
Modbus response message time-out
117
Modem reply timeout
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XMIT Communication Block
Fault Code
Fault Description
118
XMIT could not gain access to PLC communications port #1 or port #2
119
XMIT could not enable PLC port receiver
120
XMIT could not set PLC UART
121
User issued an abort command
122
Top node of XMIT not equal to zero, one or two
123
Bottom node of XMIT is not equal to seven, eight or sixteen
124
Undefined internal state
125
Broadcast mode not allowed with this Modbus function code
126
DCE did not assert CTS
127
Illegal configuration (data rate, data bits, parity, or stop bits)
128
Unexpected response received from Modbus slave
129
Illegal command word setting
130
Command word changed while active
131
Invalid character count
132
Invalid register block
133
ASCII input FIFO overflow error
134
Invalid number of start characters or termination characters
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XMIT Communication Block
Parameter Description: XMIT Communications Block
Command Word
Communication
Functions Table
This table describes the function performed as XMIT interprets each bit of the
command word.
(4x + 8) Command
Word Function
Command word bits Command word bits that
that must be set to 1 must be set to 0
Terminated ASCII input (Bit 5=1)
2,3,9,10,11,12
6,7,8,13,14,15,16
Simple ASCII input (Bit 6=1)
2,3,9,10,11,12
5,7,8,13,14,15,16
Simple ASCII output (Bit 7=1)
2,3,9,10,11,12
5,6,8,13,14,15,16
Modem output (Bit 7=1)
2,3,13,14,15,16
5,6,8,9,10,11,12
(plus one, but ONLY one, of the
following bits is set to 1:
13,14,15 or 16, while the other
three bits must be set to 0)
Modbus master messaging output
(Bit 8=1)
2,3
5,6,7,9,10,11,12,13,14,15,16
Enable ASCII receive input FIFO
ONLY (Bit 9=1)
2,3,10,11,12
5,6,7,8,13,14,15,16
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XMIT Port Status Block
178
At A Glance
Introduction
This chapter describes the instruction XMIT Port Status Block.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: XMIT Port Status Block
1118
Representation: XMIT Port Status Block
1119
Parameter Description: Middle Node - XMIT Conversion Block
1121
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XMIT Port Status Block
Short Description: XMIT Port Status Block
Function
Description
The XMIT port status block shows the current port status, Modbus slave activity,
ASCII input FIFO and flow control information that may be used in ladder logic for
some applications. The XMIT port status block is totally passive. It does not take,
release, or control the PLC port.
For an overview of the XMIT instruction please see p. 1098.
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XMIT Port Status Block
Representation: XMIT Port Status Block
Symbol
Representation of the instruction
START
port
#0001
or
#0002
register
OPERATION
TERMINATED
UNSUCCESSFULLY
OPERTION SUCCESSFUL
XMIT
constant =
#0007
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XMIT Port Status Block
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type Meaning
Top input
0x, 1x
None
ON begins an XMIT operation and it should
remain ON until the operation has completed
successfully or an error has occurred.
port #0001 or
#0002
(top node)
4x
INT, UINT
WORD
Must contain one of the following constants
either (#0001) to select PLC port #1, or
(#0002) to select PLC port #2.
Note: The loadable version DOES accept
4xxxx registers in the top node, whereas the
built-in does NOT.
register
(middle node)
4x
INT, UINT, The 4xxxx register entered in the middle node
WORD
is the first in a group of seven (7) contiguous
holding registers that comprise the port status
display block, as shown on p. 1121 in the
Parameter Description: Middle Node - XMIT
Conversion Block section.
Important: DO NOT modify the address in the
middle node of the XMIT block or delete the
address from the block while the block is
active. This action locks up the port preventing
communications.
constant =
#0007
(bottom node)
INT, UINT, Must contain a constant equal to (#0007). This
WORD
is the number of registers used by the XMIT
port status instruction.
Middle output
0x
None
ON when XMIT has detected an error or was
issued an abort.
Bottom output
0x
None
ON when an XMIT operation has been
successfully completed.
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XMIT Port Status Block
Parameter Description: Middle Node - XMIT Conversion Block
Explanation of
This Section
This section expands and details information relevant to the middle node. There are
six (6) units in this section.
z
z
z
z
z
z
Port Status
Display Table
Port Status Display Table
Fault Code Generation Table
Status Generation Table
Port Ownership Table
Input FIFO Status Table
Input FIFO Length Table
This table represents the first in a group of seven (7) contiguous holding registers
that comprise the port status block.
Register
Name
Description
No Valid Entries
4xxxx
Revision
Number
Displays the current revision number of XMIT
block. This number is automatically loaded by the
block and the block over writes any other number
entered into this register.
Read Only
4xxxx + 1 Fault
Status
This field displays a fault code generated by the
XMIT port status block. (For expanded and
detailed information please see the Fault Code
Generation Table below.)
Read Only
4xxxx + 2 Slave
login
status/
Slave port
active
status
This register displays the status of two items
Read Only
generated by the XMIT port status block.
The two items are the slave login status and the
slave port active status. Ladder logic may be able
to use this information to reduce or avoid collisions
on a multi master Modbus network. (For expanded
and detailed information please see the Status
Generation Table below.
4xxxx + 3 Slave
transactio
n counter
This register displays the number of slave
transactions generated by the XMIT port status
block. The counter increases every time the PLC
Modbus slave port receives another command
from the Modbus master. Ladder logic may be
able to use this information to reduce or avoid
collisions on a multi master Modbus network.
4xxxx + 4 Port State
This register displays ownership of the port and its Read Only
state. It is generated by the XMIT port status block.
(For expanded and detailed information please
see the Port Ownership Table below.)
Read Only
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XMIT Port Status Block
Register
Name
Description
No Valid Entries
4xxxx + 5 Input FIFO The register displays the status of seven items
status bits related to the input FIFO. It is generated by the
XMIT port status block. (For expanded and
detailed information please see the Input FIFO
Table below.)
Read Only
4xxxx + 6 Input FIFO This register displays the current number of
Read Only
length
characters present in the ASCII input FIFO. The
register may contain other values based on the
state of the input FIFO and if the length is empty or
overflowing. It is generated by the XMIT port
status block. (For expanded and detailed
information please see the Input FIFO Length
Table below.
Fault Code
Generation Table
Status
Generation Table
This table describes the fault codes generated by the XMIT port status block in the
(4x + 1) register.
Fault Code
Fault Description
118
XMIT could not gain access to PLC communications port #1 or port #2.
122
Top node of XMIT not equal to zero, one or two.
123
Bottom node of XMIT is not equal to seven, eight or sixteen.
This table describes the slave login status and the slave port active status generated
by the XMIT port status block for the (4x + 2) register.
(4x + 2 high byte)
Slave Login Status
(4x + 2 low byte)
Slave Port Active Status
Yes - When a programming
device is currently logged ON to
this PLC slave port.
Yes - When observed port is owned by the PLC and
currently receiving a Mod-bus command or transmitting a
Mod-bus response.
No - When a programming device No - When observed port is NOT owned by the PLC and
is currently NOT logged ON to this currently receiving Mod-bus command or transmitting a
Mod-bus response.
PLC slave port.
Note: A Modbus master can send
commands but, not be logged ON
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XMIT Port Status Block
Port Ownership
Table
nput FIFO
Status Table
Input FIFO
Length Table
This table describes the port’s ownership and state for the (4x + 4) register.
Owns Port Active State
Value
PLC
PLC Modbus slave
0
XMIT
Tone dial modem
1
XMIT
Hang up modem
2
XMIT
Modbus messaging
3
XMIT
Simple ASCII output
4
XMIT
Pulse dial modem
5
XMIT
Initialize modem
6
XMIT
Simple ASCII input
7
XMIT
Terminated ASCII input
8
XMIT
ASCII input FIFO is ON, but no XMIT function is active
9
This table describes the status bits related to the input FIFO for the (4x + 5) register.
Bit #
Definition
Yes / 1
No / 0
1-3
Reserved
4
Port owned by ...
XMIT
PLC
5-7
Reserved
8
ASCII output
transmission ...
Blocked by receiving device
Unblocked by receiving
device
9
ASCII input received ... New character
No new character
10
ASCII input FIFO is ...
Empty
Not empty
11
ASCII input FIFO is ...
Overflowing (error)
Not overflowing (error)
12
ASCII input FIFO is ...
On
Off
13 - 15
Reserved
16
ASCII input reception ... XMIT blocked sending
device
XMIT unblocked sending
device
This table describes the current number of characters present in the ASCII input
FIFO for the (4x + 6) register.
WHEN Input FIFO
THEN Length
= OFF
=0
= ON and Empty
=0
= ON and Overflowing = 512
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XMIT Port Status Block
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XMIT Conversion Block
179
At A Glance
Introduction
This chapter describes the instruction XMIT Conversion Block.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description: XMIT Conversion Block
1126
Representation: XMIT Conversion Block
1127
Parameter Description: XMIT Conversion Block
1129
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XMIT Conversion Block
Short Description: XMIT Conversion Block
Function
Description
The purpose of the XMIT conversion block is to take data and convert it into other
usable forms based upon your application needs. The convert block performs
eleven (11) different functions or options. Some functions include ASCII to binary,
integer to ASCII, byte swapping, searching ASCII strings, and others. This block
allows internal conversions using 4xxxx source blocks to 4xxxx destination blocks.
For an overview of the XMIT instruction please see p. 1098.
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XMIT Conversion Block
Representation: XMIT Conversion Block
Symbol
Representation of the instruction
START
constant
#0001
register
OPERATION
TERMINATED
UNSUCCESSFULLY
OPERTION SUCCESSFUL
XMIT
constant =
#0008
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XMIT Conversion Block
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON begins an XMIT operation and it should
remain ON until the operation has
completed successfully or an error
has occurred.
Note: To reset an XMIT fault and clear the
fault register, the top input must go OFF for
at least one PLC scan.
constant #0001
(top node)
4x
INT, UINT
WORD
The top node must contain a constant
(#0000) since conversions do not deal with
the PLC’s port. The loadable version DOES
accept 4xxxx registers in the top node,
whereas the built-in does NOT.
register
(middle node)
4x
INT, UINT,
WORD
The 4xxxx register entered in the middle
node is the first in a group of eight (8)
contiguous holding registers that comprise
the control block, as shown on p. 1129
found in the Parameter Description: XMIT
Conversion Block section.
Important: DO NOT modify the address in
the middle node of the XMIT block or delete
the address from the program while the
block is active. This action locks up the port
preventing communications.
INT, UINT,
WORD
The bottom node must contain a constant
equal to (#0008). This is the number of
registers used by the XMIT conversion
instruction.
constant =
#0008
(bottom node)
Middle output
0x
None
ON when XMIT has detected an error or
was issued an abort.
Bottom output
0x
None
ON when an XMIT operation has been
successfully completed.
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XMIT Conversion Block
Parameter Description: XMIT Conversion Block
Explanation of
This Section
This section expands and details information relevant to the middle node. There are
four (4) units in this section.
z
z
z
z
Conversion
Block Control
Table
Conversion Block Control Table
Fault Code Generation Table
Data Conversion Control Bits Table
Data Conversion Opcodes Table
This table represents the first in a group of eight (8) contiguous holding registers that
comprise the port status block.
Register
Name
Description
No Valid
Entries
4xxxx
XMIT Revision
Number
Displays the current revision number of XMIT Read Only
block. This number is automatically loaded by
the block and the block over writes any other
number entered into this register.
4xxxx + 1
Fault Status
This field displays a fault code generated by
the XMIT port status block. (For expanded
and detailed information please see the Fault
Code Generation Table below.)
Read Only
4xxxx + 2
Available to User
0 (May be used as pointers for instructions
such as TBLK.)
The XMIT conversion block does not use this
register. However, it may be used in ladder
logic as a pointer. An efficient way to use the
XMIT block is to place a pointer value of a
TBLK instruction into this register.
Read/Write
4xxxx + 3
Data Conversion
Control Bits
This 16 bit word relates to the Data
Conversion (4xxxx + 3) word. These bits
provide additional control options based on
which of the eleven conversions you select.
(For expanded and detailed information
please see Data Conversion Control Bits
Table below.
Read/Write
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XMIT Conversion Block
Fault Code
Generation Table
Register
Name
Description
No Valid
Entries
4xxxx + 4
Data Conversion
Opcodes
Read/Write
Select the type of conversion you want to
perform from the list of eleven options listed in
the Data Conversion Opcodes Table below.
After picking the type of conversion refer to
Data Conversion Control Bits (4xxxx + 4) and
the Data Conversion Control Bits Table for
additional control options that relate to the
specific conversion type selected.
4xxxx + 5
Source Register
Enter the 4xxxx register desired.
This is the first register in the source block
that is read. Ensure you select where you
want the READ to begin (high or low byte).
Read/Write
4xxxx + 6
Destination
Register
Enter the 4xxxx register desired.
This is the first register in the source block
that is read. Ensure you select where you
want the READ to begin (high or low byte).
The selection beside this register in the DX
zoom is the same as bit16 in (4xxxx + 3).
Read/Write
4xxxx + 7
ASCII String
Character Count
Enter the search area. This register defines
the search area.
When either automatic advance source (Bit
13) or automatic advance destination (Bit 14)
are ON and no ASCII character is detected,
the block automatically adjusts the character
count.
Read/Write
This table describes the fault codes generated by the XMIT conversion block in the
(4x + 1) register.
Fault Code
Fault Description
122
Top node of XMIT is not equal to zero, one or two
123
Bottom node of XMIT is not equal to seven, eight or sixteen
131
Invalid character count
135
Invalid destination register block
136
Invalid source register block
137
No ASCII number present
138
Multiple sign characters present
139
Numerical overflow detected
140
String mismatch error
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XMIT Conversion Block
Data Conversion
Control Bits
Table
Fault Code
Fault Description
141
String not found
142
Invalid error check detected
143
Invalid conversion opcode
This table describes the control options available based upon the conversion
selected in the (4x + 3) register.
Bit #
Definition
1=
0=
2
CRC 16 seed
0x0000
0xFFFF
3
Error check type
LRC 8
CRC 16
4
Error check
Validate
Append
7
Conversion case
Upper to Lower
Lower to Upper
8
Case sensitivity
No
Yes
9
Format leading
Zeros
Blanks
10
Output format
Fixed
Variable
11
Conversion type
Unsigned
Signed
12
Conversion word
32-bit
16-bit
13
Automatic advance source pointer (points Yes
to the next character after the last
character purged)
No
14
Automatic advance destination pointer
(points to the next character after the last
character purged)
Yes
No
15
Begin reading ASCII at source
beginning with ...
Low byte
High byte
(normal)
16
Begin saving ASCII at destination
beginning with ...
Low byte
High byte
(normal)
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XMIT Conversion Block
Data Conversion
Opcodes Table
This table describes the eleven (11) functions or options for performing conversions
using the data conversion opcodes in the (4x + 4) register.
Opcode
Action
Data Type
(4xxxx block
Illegal opcode
Displayed when illegal
opcode is detected.
Not applicable
(1 Hex) Received ASCII decimal
character string
Converted to
16-bit or 32-bit signed or
unsigned binary integer
(2 Hex) Received ASCII hex
character string
Converted to
16-bit or 32-bit unsigned
binary integer
(3 Hex) Received ASCII hex
character string
Converted to
16-bit unsigned binary integer
array
(4 Hex) 16-bit or 32-bit signed or
unsigned integer
Converted to
ASCII decimal character
string for transmission
(5 Hex) 16-bit or 32-bit unsigned
binary integer
Converted to
ASCII hex character string for
transmission
(6 Hex) 16-bit unsigned integer
array
Converted to
ASCII hex character string for
transmission
(7 Hex) High and low bytes from
saved ASCII source register block
Swapped to
ASCII destination register
block
(8 Hex) ASCII string from source
register block
Copied to
ASCII destination register
block with or without case
conversion
(9 Hex) ASCII source register block Compared to
ASCII string defined in
destination register block with
or without case sensitivity
(10 Hex) ASCII source register
block
Search for
ASCII string defined in
destination block with or
without case sensitivity
(11 Hex) Error check 8-bit LRC or
16-bit CRC
Validated or Appended ASCII string in source
on
register block
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XMRD: Extended Memory Read
180
At a Glance
Introduction
This chapter describes the instruction XMRD.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1134
Representation: XMRD - Extended Memory Read
1135
Parameter Description
1136
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XMRD: Extended Memory Read
Short Description
Function
Description
The XMRD instruction is used to copy a table of 6x extended memory registers to a
table of 4x holding registers in state RAM.
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XMRD: Extended Memory Read
Representation: XMRD - Extended Memory Read
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
control block
ENABLE CLEAR OFFSET
ERROR
destination
COMPLETE (ONE SCAN)
ENABLE ABORT IF ERROR
XMRD
#1
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = activates read operation
Middle input
0x, 1x
None
OFF = clears offset to 0
ON = does not clear offset
Bottom input
0x, 1x
None
OFF = abort on error
ON = do not abort on error
control block
(see p. 1136)
(top node)
4x
INT, UINT,
WORD
First of six contiguous holding
registers in the extended memory
(For expanded and detailed
information please see p. 1136.)
destination
(middle node)
4x
INT, UINT,
WORD
The first 4x holding register in a
table of registers that receive the
transferred data from the 6x
extended memory storage registers
INT, UINT
Contains the constant value 1,
which cannot be changed
1
(bottom node)
Top output
0x
None
Read transfer active
Middle output
0x
None
Error condition detected
Bottom output
0x
None
ON = operation complete
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XMRD: Extended Memory Read
Parameter Description
Control Block
(Top Node)
The 4x register entered in the top node is the first of six contiguous holding registers
in the extended memory control block.
Reference
Register Name Description
Displayed
status word
Contains the diagnostic information about extended
memory (see p. 1137)
First implied
file number
Specifies which of the extended memory files is currently in
use (range: 1 ... 10)
Second
implied
start address
Specifies which 6x storage register in the current file is the
starting address; 0 = 60000, 9999 = 69999
Third
implied
count
Specifies the number of registers to be read or written in a
scan when the appropriate function block is powered; range:
0 ... 9999, not to exceed number specified in max registers
(fifth implied)
Fourth
implied
offset
Keeps a running total of the number of registers transferred
thus far
Fifth implied
max registers
Specifies the maximum number of registers that may be
transferred when the function block is powered (range: 0 ...
9999)
If you are in multi-scan mode, these six registers should be unique to this
function block.
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XMRD: Extended Memory Read
Status Word of
the Control Block
Status Word of the Control Block
1
2
3
4
5
6
7
8
9
10
Bit
Function
1
1 = power-up diagnostic error
2
1 = parity error in extended memory
3
1 = extended memory does not exist
4
0 = transfer not running
1 = busy
5
0 = transfer in progress
1 = transfer complete
6
1 = file boundary crossed
7
1 = offset parameter too large
8-9
Not used
10
1 = nonexistent state RAM
11
Not used
12
1 = maximum registers parameter error
13
1 = offset parameter error
14
1 = count parameter error
15
1 = starting address parameter error
16
1 = file number parameter error
11
12
13
14
15
16
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XMRD: Extended Memory Read
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XMWT: Extended Memory Write
181
At a Glance
Introduction
This chapter describes the instruction XMWT.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1140
Representation: XMWT - Extended Memory Write
1141
Parameter Description
1142
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XMWT: Extended Memory Write
Short Description
Function
Description
The XMWT instruction is used to write data from a block of input registers or holding
registers in state RAM to a block of 6x registers in an extended memory file.
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XMWT: Extended Memory Write
Representation: XMWT - Extended Memory Write
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source
ENABLE CLEAR OFFSET
ERROR
control block
ENABLE ABORT IF ERROR
COMPLETE (ONE SCAN)
XMWT
1
Parameter
Description
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
ON = activates write operation
Middle input
0x, 1x
None
OFF = clears offset to 0
ON = does not clear offset
Bottom input
0x, 1x
None
OFF = abort on error
ON = do not abort on error
source
(top node)
3x, 4x
INT, UINT,
WORD
The first 3x or 4x register in a block of
contiguous source registers, i.e. input or
holding registers, whose contents will be
written to 6x extended memory registers
control block
(see p. 1142)
(middle node)
4x
INT, UINT,
WORD
First of six contiguous holding registers in
the extended memory
(For expanded and detailed information
please see p. 1142.)
INT, UINT
Contains the constant value 1, which
cannot be changed
1
(bottom node)
Top output
0x
None
Write transfer active
Middle output
0x
None
Error condition detected
Bottom output
0x
None
ON = operation complete
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XMWT: Extended Memory Write
Parameter Description
Control Block
(Middle Node)
The 4x register entered in the middle node is the first of six contiguous holding
registers in the extended memory control block.
Reference
Register Name Description
Displayed
status word
Contains the diagnostic information about extended
memory (see p. 1143)
First implied
file number
Specifies which of the extended memory files is currently
in use (range: 1 ... 10)
Second implied
start address
Specifies which 6x storage register in the current file is
the starting address; 0 = 60000, 9999 = 69999
Third implied
count
Specifies the number of registers to be read or written in
a scan when the appropriate function block is powered;
range: 0 ... 9999, not to exceed number specified in max
registers (fifth implied)
Fourth implied
offset
Keeps a running total of the number of registers
transferred thus far
Fifth implied
max registers
Specifies the maximum number of registers that may be
transferred when the function block is powered (range: 0
... 9999)
If you are in multi-scan mode, these six registers should be unique to this
function block.
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XMWT: Extended Memory Write
Status Word of
the Control Block
Status Word of the Control Block
1
2
3
4
5
6
7
8
9
10
11
Bit
Function
1
1 = power-up diagnostic error
2
1 = parity error in extended memory
3
1 = extended memory does not exist
4
0 = transfer not running
1 = busy
5
0 = transfer in progress
1 = transfer complete
6
1 = file boundary crossed
7
1 = offset parameter too large
8-9
Not used
10
1 = nonexistent state RAM
11
Not used
12
1 = maximum registers parameter error
13
1 = offset parameter error
14
1 = count parameter error
15
1 = starting address parameter error
16
1 = file number parameter error
12
13
14
15
16
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XMWT: Extended Memory Write
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XOR: Exclusive OR
182
At a Glance
Introduction
This chapter describes the instruction XOR.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Short Description
1146
Representation: XOR - Boolean Exclusive Or
1147
Parameter Description
1149
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XOR: Exclusive OR
Short Description
Function
Description
The XOR instruction performs a Boolean Exclusive OR operation on the bit patterns
in the source and destination matrices.
The XORed bit pattern is then posted in the destination matrix, overwriting its
previous contents:
source
bits
0
0
1
1
0
XOR
XOR
XOR
XOR
0
0
1
1
0
1
destination
bits
1
WARNING
XOR will override any disabled coils within the destination matrix without
enabling them.
This can cause personal injury if a coil has disabled an operation for maintenance
or repair because the coil’s state can be changed by the XOR operation.
Failure to follow this instruction can result in death, serious injury, or
equipment damage.
1146
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XOR: Exclusive OR
Representation: XOR - Boolean Exclusive Or
Symbol
Representation of the instruction
CONTROL INPUT
ACTIVE
source matrix
destination
matrix
MATRIX SIZE
XOR
Length: 1 - 100 registers
(16 - 1600 bits)
Parameter
Description
length
Description of the instruction’s parameters
Parameters
State RAM
Reference
Data Type
Meaning
Top input
0x, 1x
None
Initiates XOR
source matrix
(top node)
0x, 1x, 3x, 4x
BOOL,
WORD
First reference in the source matrix
destination matrix
(middle node)
0x, 4x
BOOL,
WORD
First reference in the destination matrix
INT, UINT
Matrix length; range 1 ... 100 registers.
None
Echoes state of the top input
length
(bottom node)
Top output
0x
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XOR: Exclusive OR
An XOR Example
When contact 10001 passes power, the source matrix formed by the bit pattern in
registers 40600 and 40601 is XORed with the destination matrix formed by the bit
pattern in registers 40608 and 40609, overwriting the original destination bit pattern.
source matrix
40600 = 1111111100000000 40601 = 1111111100000000
40600
10001
40608
XOR
00002
Original destination matrix
40608 = 1111111111111111 40609 = 0000000000000000
XORed destination matrix
40608 = 0000000011111111 40609 = 1111111100000000
Note: If you want to reatin the original destination bit pattern of registers 40608 and
40609, copy the information into another table using a BLKIM before performing
the XOR operation.
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XOR: Exclusive OR
Parameter Description
Matrix Length
(Bottom Node)
The integer entered in the bottom node specifies the matrix length, i.e. the number
of registers or 16-bit words in the two matrices. The matrix length can be in the range
1 ... 100. A length of 2 indicates that 32 bits in each matrix will be XORed.
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XOR: Exclusive OR
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Appendices
Optimizing RIO Performance with the Segment Scheduler
Purpose
This section shows you how to optimize your RIO using the segment scheduler.
What's in this
Appendix?
The appendix contains the following chapters:
Chapter
A
Chapter Name
Page
Appendix A
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Appendices
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Appendix A
A
Optimizing RIO Peformance with the Segment Scheduler
Purpose
This appendix shows you how to optimize RIO performance using the
segment scheduler.
What's in this
Chapter?
This chapter contains the following topics:
Topic
Page
Scan Time
1154
How to Measure Scan Time
1158
Maximizing Throughput
1159
Order of Solve
1161
Using Segment Scheduler to Improve Critical I/O Throughput
1162
Using Segment Scheduler to Improve System Performance
1164
Using Segment Scheduler to Improve Communication Port Servicing
1165
Sweep Functions
1166
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Appendices
Scan Time
Overview
The time it takes the PLC to solve the logic program and update the physical system
is called scan time . It comprises the time it takes the PLC to:
Logic Solve Time
z
Solve all scheduled logic ie..logic solve time
z
Service the I/O drops
z
Service the communication ports and option processors
z
Execute intersegment transfer (IST) and system diagnostics
Logic solve time is the time it takes the CPU to solve the elements and instructions
used in the logic program. It is a part of the total scan time that is independent of I/
O service time and system overhead time. Logic solve time is measured in ms/K
words of user logic. Various PLC models have different logic solve times, as
shown below:
Logic Solve Time PLC Models
PLC Types
0.75 ms/Kwords
984A, 984B, 984X
Chassis-mount
1.0 ms/Kwords
E984-685/-785, L984-785
Slot-mount
CPU11302, CPU11303, CPU21304
Quantum Series
AT-984, MC-984
Hosr -based
0984-780/-785
Slot-mount
Q984
Host-based
0984-685
Slot-mount
2.5 ms/Kwords
110CPU51x and 110CPU61x
Micro
3.0 ms/Kwords
984-385, 984-485, 984-680
Slot mount
4.25 ms/Kwords
984-A12x, 984-A13x, 984-A14x
Compact
110CPU311 and 110CPU411
Micro
984-380/-381, 984-480
Slot-mount
1.5 ms/Kwords
2.0 ms/Kwords
5.0 ms/Kwords
The following illustration shows how logic solve time fits in the overall scan
time function:
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Appendices
Segment 1
Service
Outputs
Read
Inputs
IST
Segment 2
= Logic Solve Time
Service
Outputs
= Other Elements of
Scan Time
One Scan
Read
Inputs
IST
Segment 3
Service
Outputs
Read
Inputs
IST
Overhead
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Appendices
Servicing the I/O
In order to handle system throughput efficiently, the PLC coordinates the solution of
logic segments via its CPU and the servicing of I/O drops via its I/O processor.
Typically a logic segment is coordinated with a particular I/O drop—for example, the
logic networks in segment 2 correspond to the real-world I/O points at drop 2. Inputs
are read during the previous segment and outputs are written during the
subsequent segment.
This method of I/O servicing assures that the most recent input status is available
for logic solve and that outputs are written as soon as possible after logic solve. It
ensures predictability between the PLC and the process it is controlling.
Segment 1
Service
Outputs
Read
Drop 2
Inputs
IST
Segment 2
= I/O Service Time
for Drop 2
Service
Outputs
= Other Elements of
Scan Time
Read
Inputs
One Scan
IST
Segment 3
Service
Drop 2
Outputs
Read
Inputs
IST
Overhead
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Appendices
Overhead
An intersegment transfer (IST) occurs between each segment. At this time, the I/O
processor and the state RAM exchange data; previous inputs are transferred to
state RAM and the next outputs are transferred to the I/O processor. The logic scan
and I/O servicing for each segment are coordinated in this fashion. Using direct
memory access (DMA), ISTs typically take less than 1 ms/segment.
At the end of each scan, input messages to the Modbus communication ports are
serviced. The maximum time allotted for comm port servicing is 2.5 ms/scan; typical
servicing times are less than 1 ms/scan. If the PLC is using any option processors
(C986 Coprocessors or D908 Distributed Communications Processors), they are
also serviced at the end of each scan and typically require less than 1 ms/scan.
System diagnostics take from 1 ... 2 ms/scan to run, depending on PLC type.
Segment 1
Service
Outputs
Read
Inputs
IST
Segment 2
= Overhead
Support Time
Service
Outputs
= Other Elements of
Scan Time
One Scan
Read
Inputs
IST
Segment 3
Service
Outputs
Read
Inputs
IST
Overhead
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Appendices
How to Measure Scan Time
Overview
The following ladder logic circuit can be used in your application program to evaluate
system scan time:
UCTR
T.01
DIV
The up-counter counts 1000 scans as it transitions 500 times. When the counter has
transitioned 500 times, the T.01 timer turns OFF and stores the number of
hundredths of seconds it has taken for the counter to transition 500 times (1000
scans) in register 40003.
The value stored in 40002/40003 in the DIV block is then divided by 100 and the
result—which represents logic solve time in ms is stored in register 40005.
Note: 10001 is controlled via a DISABLE or a hard-wired input; ifyou are running
the program in optimized mode, a hard-wired input isrequired to toggle 10001.
Note: The maximum amount of time allowed for a scan is 250 ms; if the scan has
not completed in that amount of time, a watchdog timer in the CPU stops the
application and sends a timeout error message to the programming panel display.
The maximum limit on scan time protects the PLC from entering into an
infinite loop.
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Appendices
Maximizing Throughput
Overview
The PLC architecture simultaneously solves logic and services I/O drops to optimize
system throughput. Throughput is the time it takes for a signal received at a field
sensing device to be sent as an input to the PLC, processed in ladder logic, and
returned as an output signal to a field working device. Throughput time may be
longer or shorter than a single scan; it gives you a realistic measure of the system’s
actual performance.
The Ideal
Throughput
Situation
If the default segment scheduler is in place, the system automatically solves the
logic starting at segment 1 and moving sequentially through segment n. Throughput
is optimized when logic referring to real-world I/O is contained in the segment that
corresponds to that I/O drop.For instance, if you are using I/O in drop 1 of a threedrop system to control a pushbutton that starts a motor, the ideal condition is for
logic segment 1 to contain all the appropriate logic:
PLC
10001
I/O
Drop1
Segment 1
10001
00001
00001
I/O
Drop2
I/O
Drop3
When all logic segments are coordinated with all physical I/O drops in this manner,
the throughput for a given logic segment can be less than one scan. Here is how it
can be traced in our scan time model:
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Appendices
Segment 1
Service
Drop 3
Outputs
Read
Inputs
IST
Segment 2
Service
Outputs
Event A
Read
Drop 3
Inputs
Scan 1
IST
Segment 3
Event B
Service
Outputs
Event C
Read
Inputs
Event D
IST
Overhead
Segment 1
Event E
Service
Drop 3
Outputs
Scan 2
Read
Inputs
The model tracks throughput for drop 3. Throughput in this best case example is
about 75% of total scan time. Five benchmark events are shown:
z
Event A, where the inputs from drop 3 are available to the I/O processor.
z
Event B, where the I/O processor transfers data to state RAM.
z
Event C, where the segment 3 logic networks are solved.
z
Event D, where data is transferred from state RAM to the I/O processor
z
Event E, where the output data is written to the input modules at drop 3
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Appendices
Order of Solve
Overview
You specify the number of segments and I/O drops with the configurator editor in
your panel software package. The default order-of-solve condition is segment 1
through segment n consecutively and continuously, once per scan, with the
corresponding I/O drops serviced in like order. You are able to change the order of
solve using the segment scheduler editor in your panel software package.
There may be times when you can modify the order of solve to improve overall
system performance. The segment scheduler can be used effectively to:
z
Improve throughput for critical I/O
z
Improve overall system performance
z
Optimize the servicing of communication ports
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Appendices
Using Segment Scheduler to Improve Critical I/O Throughput
Overview
Suppose that your logic program is three segments long and that segment 3
contains logic that is critical to your application, for example, monitoring a proximity
switch to verify part presence. Segments 1 and 2 are running noncritical logic such
as part count analysis and statistic gathering. The program is running in the standard
order-of-solve mode, and you are finding that the PLC is not able to read critical
inputs with the frequency desired, thereby causing unacceptable system delay.
Using the segment scheduler editor, you can improve the throughput for the
critical I/O at drop 3 by scheduling segment 3 to be solved two (or more) times in the
same scan
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Appendices
Here is an example of a rescheduled logic program, again using our
scan time model:
Segment 1
Service
Drop 3
Outputs
Read
Drop 3
Inputs
IST
Segment 3
Service
Drop 1
Outputs
Read
Drop 2
Inputs
One Scan
IST
Segment 2
Service
Drop 3
Outputs
Read
Drop 3
Inputs
IST
Segment 3
Service
Drop 2
Outputs
Overhead
Read
Drop 1
Inputs
IST
Overhead
By rescheduling the order-of-solve table, you actually increase the scan time, but
more importantly you improve throughput for the critical I/O supported by logic in
segment 3. Throughput is the better measure of system performance.
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Appendices
Using Segment Scheduler to Improve System Performance
Overview
When certain areas of a ladder logic program do not need to be solved continually
on every scan. For example, an alarm handling routine, a data analysis routine, or
some diagnostic message routines can be designated as controlled segments by
the segment scheduler editor. Based on the status of an I/O or internal reference, a
controlled segment may be scheduled to be skipped, thereby reducing scan time
and improving overall system throughput.
For example, suppose that you have some alarm handling logic in segment 2 of a
three-segment logic program. You can use the segment scheduler editor to control
segment 2 based on the status of a coil 00056—if the coil is ON, segment 2 logic will
be activated in the scan, and if the coil is OFF the segment will not be solved in
the scan.
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Appendices
Using Segment Scheduler to Improve Communication Port Servicing
Overview
When you find that the frequency of standard end-of-scan servicing of
communication ports, option processors, or system diagnostics is inadequate for
your application requirements, you can increase service frequency by inserting one
or more reset watchdog timer routines in the order-of-solve table. Each time this
routine is encountered by the CPU, it causes all communication ports to be serviced
and causes the system diagnostics to be run.
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Appendices
Sweep Functions
Overview
Sweep functions allow you to scan a logic program at fixed intervals. They do not
make the PLC solve logic faster or terminate scans prematurely.
Constant Sweep
Constant Sweep allows you to set target scan times from 10 ... 200 ms (in multiples
of 10). A target scan time is the time between the start of one scan and the start of
the next; it is not the time between the end of one scan and the beginning of the next.
Constant Sweep is useful in applications where data must be sampled at constant
time intervals. If a Constant Sweep is invoked with a time lapse smaller than the
actual scan time, the time lapse is ignored and the system uses its own normal scan
rate. The Constant Sweep target scan time encompasses logic solving, I/O and
Modbus port servicing, and system diagnostics. If you set a target scan of 40 ms and
the logic solving, I/O servicing, and diagnostics require only 30 ms, the PLC will wait
10 ms on each scan.
Single Sweep
The Single Sweep function allows your PLC to execute a fixed number of scans
(from 1 ... 15) and then to stop solving logic but continue servicing I/O. This function
is useful for diagnostic work; it allows solved logic, moved data, and performed
calculations to be examined for errors.
WARNING
The Single Sweep function should not be used to debug controls on machine tools,
processes, or material handling systems when they are active. Once a specified
number of scans has been solved, all outputs are frozen in their last state. Since
no logic solving is taking place, the PLCignores all input information. This can result
in unsafe, hazardous, and destructive operation of the machine or process
connected to the PLC.
Failure to follow this instruction can result in death, serious injury, or
equipment damage.
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Glossary
A
active window
The window, which is currently selected. Only one window can be active at any one
given time. When a window is active, the heading changes color, in order to
distinguish it from other windows. Unselected windows are inactive.
Actual parameter
Currently connected Input/Output parameters.
Addresses
(Direct) addresses are memory areas on the PLC. These are found in the State RAM
and can be assigned input/output modules.
The display/input of direct addresses is possible in the following formats:
z Standard format (400001)
z Separator format (4:00001)
z Compact format (4:1)
z IEC format (QW1)
ANL_IN
ANL_IN stands for the data type "Analog Input" and is used for processing analog
values. The 3x References of the configured analog input module, which is specified
in the I/O component list is automatically assigned the data type and should
therefore only be occupied by Unlocated variables.
ANL_OUT
ANL_OUT stands for the data type "Analog Output" and is used for processing
analog values. The 4x-References of the configured analog output module, which is
specified in the I/O component list is automatically assigned the data type and
should therefore only be occupied by Unlocated variables.
ANY
In the existing version "ANY" covers the elementary data types BOOL, BYTE, DINT,
INT, REAL, UDINT, UINT, TIME and WORD and therefore derived data types.
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Glossary
ANY_BIT
In the existing version, "ANY_BIT" covers the data types BOOL, BYTE and WORD.
ANY_ELEM
In the existing version "ANY_ELEM" covers the elementary data types BOOL,
BYTE, DINT, INT, REAL, UDINT, UINT, TIME and WORD.
ANY_INT
In the existing version, "ANY_INT" covers the data types DINT, INT, UDINT and
UINT.
ANY_NUM
In the existing version, "ANY_NUM" covers the data types DINT, INT, REAL, UDINT
and UINT.
ANY_REAL
In the existing version "ANY_REAL" covers the data type REAL.
Application
window
The window, which contains the working area, the menu bar and the tool bar for the
application. The name of the application appears in the heading. An application
window can contain several document windows. In Concept the application window
corresponds to a Project.
Argument
Synonymous with Actual parameters.
ASCII mode
American Standard Code for Information Interchange. The ASCII mode is used for
communication with various host devices. ASCII works with 7 data bits.
Atrium
The PC based controller is located on a standard AT board, and can be operated
within a host computer in an ISA bus slot. The module occupies a motherboard
(requires SA85 driver) with two slots for PC104 daughter boards. From this, a
PC104 daughter board is used as a CPU and the others for INTERBUS control.
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Glossary
B
Back up data file
(Concept EFB)
The back up file is a copy of the last Source files. The name of this back up file is
"backup??.c" (it is accepted that there are no more than 100 copies of the source
files. The first back up file is called "backup00.c". If changes have been made on the
Definition file, which do not create any changes to the interface in the EFB, there is
no need to create a back up file by editing the source files (ObjectsoSource). If a
back up file can be assigned, the name of the source file can be given.
Base 16 literals
Base 16 literals function as the input of whole number values in the hexadecimal
system. The base must be denoted by the prefix 16#. The values may not be
preceded by signs (+/-). Single underline signs ( _ ) between figures are not
significant.
Example
16#F_F or 16#FF (decimal 255)
16#E_0 or 16#E0 (decimal 224)
Base 8 literal
Base 8 literals function as the input of whole number values in the octal system. The
base must be denoted by the prefix 3.63kg. The values may not be preceded by
signs (+/-). Single underline signs ( _ ) between figures are not significant.
Example
8#3_1111 or 8#377 (decimal 255)
8#34_1111 or 8#340 (decimal 224)
Basis 2 literals
Base 2 literals function as the input of whole number values in the dual system. The
base must be denoted by the prefix 0.91kg. The values may not be preceded by
signs (+/-). Single underline signs ( _ ) between figures are not significant.
Example
2#1111_1111 or 2#11111111 (decimal 255)
2#1110_1111 or 2#11100000 (decimal 224)
Binary
connections
Connections between outputs and inputs of FFBs of data type BOOL.
Bit sequence
A data element, which is made up from one or more bits.
BOOL
BOOL stands for the data type "Boolean". The length of the data elements is 1 bit
(in the memory contained in 1 byte). The range of values for variables of this type is
0 (FALSE) and 1 (TRUE).
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Glossary
Bridge
A bridge serves to connect networks. It enables communication between nodes on
the two networks. Each network has its own token rotation sequence – the token is
not deployed via bridges.
BYTE
BYTE stands for the data type "Bit sequence 8". The input appears as Base 2 literal,
Base 8 literal or Base 1 16 literal. The length of the data element is 8 bit. A numerical
range of values cannot be assigned to this data type.
C
Cache
The cache is a temporary memory for cut or copied objects. These objects can be
inserted into sections. The old content in the cache is overwritten for each new Cut
or Copy.
Call up
The operation, by which the execution of an operation is initiated.
Coil
A coil is a LD element, which transfers (without alteration) the status of the horizontal
link on the left side to the horizontal link on the right side. In this way, the status is
saved in the associated Variable/ direct address.
Compact format
(4:1)
The first figure (the Reference) is separated from the following address with a colon
(:), where the leading zero are not entered in the address.
Connection
A check or flow of data connection between graphic objects (e.g. steps in the SFC
editor, Function blocks in the FBD editor) within a section, is graphically shown as a
line.
Constants
Constants are Unlocated variables, which are assigned a value that cannot be
altered from the program logic (write protected).
Contact
A contact is a LD element, which transfers a horizontal connection status onto the
right side. This status is from the Boolean AND- operation of the horizontal
connection status on the left side with the status of the associated Variables/direct
Address. A contact does not alter the value of the associated variables
/direct address.
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Glossary
D
Data transfer
settings
Settings, which determine how information from the programming device is
transferred to the PLC.
Data types
The overview shows the hierarchy of data types, as they are used with inputs and
outputs of Functions and Function blocks. Generic data types are denoted by the
prefix "ANY".
z ANY_ELEM
z ANY_NUM
ANY_REAL (REAL)
ANY_INT (DINT, INT, UDINT, UINT)
z ANY_BIT (BOOL, BYTE, WORD)
z TIME
z System data types (IEC extensions)
z Derived (from "ANY" data types)
DCP I/O station
With a Distributed Control Processor (D908) a remote network can be set up with a
parent PLC. When using a D908 with remote PLC, the parent PLC views the remote
PLC as a remote I/O station. The D908 and the remote PLC communicate via the
system bus, which results in high performance, with minimum effect on the cycle
time. The data exchange between the D908 and the parent PLC takes place at 1.5
Megabits per second via the remote I/O bus. A parent PLC can support up to 31
(Address 2-32) D908 processors.
DDE (Dynamic
Data Exchange)
The DDE interface enables a dynamic data exchange between two programs under
Windows. The DDE interface can be used in the extended monitor to call up its own
display applications. With this interface, the user (i.e. the DDE client) can not only
read data from the extended monitor (DDE server), but also write data onto the PLC
via the server. Data can therefore be altered directly in the PLC, while it monitors
and analyzes the results. When using this interface, the user is able to make their
own "Graphic-Tool", "Face Plate" or "Tuning Tool", and integrate this into the
system. The tools can be written in any DDE supporting language, e.g. Visual Basic
and Visual-C++. The tools are called up, when the one of the buttons in the dialog
box extended monitor uses Concept Graphic Tool: Signals of a projection can be
displayed as timing diagrams via the DDE connection between Concept and
Concept Graphic Tool.
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Glossary
Decentral
Network (DIO)
A remote programming in Modbus Plus network enables maximum data transfer
performance and no specific requests on the links. The programming of a remote
net is easy. To set up the net, no additional ladder diagram logic is needed. Via
corresponding entries into the Peer Cop processor all data transfer requests
are met.
Declaration
Mechanism for determining the definition of a Language element. A declaration
normally covers the connection of an Identifier with a language element and the
assignment of attributes such as Data types and algorithms.
Definition data
file (Concept
EFB)
The definition file contains general descriptive information about the selected FFB
and its formal parameters.
Derived data type
Derived data types are types of data, which are derived from the Elementary data
types and/or other derived data types. The definition of the derived data types
appears in the data type editor in Concept.
Distinctions are made between global data types and local data types.
Derived Function
Block (DFB)
A derived function block represents the Call up of a derived function block type.
Details of the graphic form of call up can be found in the definition " Function block
(Item)". Contrary to calling up EFB types, calling up DFB types is denoted by double
vertical lines on the left and right side of the rectangular block symbol.
The body of a derived function block type is designed using FBD language, but only
in the current version of the programming system. Other IEC languages cannot yet
be used for defining DFB types, nor can derived functions be defined in the current
version. Distinctions are made between local and global DFBs.
DINT
DINT stands for the data type "double integer". The input appears as Integer literal,
Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element is 32
bit. The range of values for variables of this data type is from –2 exp (31) to 2 exp
(31) –1.
Direct display
A method of displaying variables in the PLC program, from which the assignment of
configured memory can be directly and indirectly derived from the physical memory.
Document
window
A window within an Application window. Several document windows can be opened
at the same time in an application window. However, only one document window
can be active. Document windows in Concept are, for example, sections, the
message window, the reference data editor and the PLC configuration.
Dummy
An empty data file, which consists of a text header with general file information, i.e.
author, date of creation, EFB identifier etc. The user must complete this dummy file
with additional entries.
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Glossary
DX Zoom
This property enables connection to a programming object to observe and, if
necessary, change its data value.
E
Elementary
functions/
function blocks
(EFB)
Identifier for Functions or Function blocks, whose type definitions are not formulated
in one of the IEC languages, i.e. whose bodies, for example, cannot be modified with
the DFB Editor (Concept-DFB). EFB types are programmed in "C" and mounted via
Libraries in precompiled form.
EN / ENO (Enable
/ Error display)
If the value of EN is "0" when the FFB is called up, the algorithms defined by the FFB
are not executed and all outputs contain the previous value. The value of ENO is
automatically set to "0" in this case. If the value of EN is "1" when the FFB is called
up, the algorithms defined by the FFB are executed. After the error free execution of
the algorithms, the ENO value is automatically set to "1". If an error occurs during
the execution of the algorithm, ENO is automatically set to "0". The output behavior
of the FFB depends whether the FFBs are called up without EN/ENO or with EN=1.
If the EN/ENO display is enabled, the EN input must be active. Otherwise, the FFB
is not executed. The projection of EN and ENO is enabled/disabled in the block
properties dialog box. The dialog box is called up via the menu commands Objects
oProperties... or via a double click on the FFB.
Error
When processing a FFB or a Step an error is detected (e.g. unauthorized input value
or a time error), an error message appears, which can be viewed with the menu
command OnlineoEvent display... . With FFBs the ENO output is set to "0".
Evaluation
The process, by which a value for a Function or for the outputs of a Function block
during the Program execution is transmitted.
Expression
Expressions consist of operators and operands.
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Glossary
F
FFB (functions/
function blocks)
Collective term for EFB (elementary functions/function blocks) and DFB (derived
function blocks)
Field variables
Variables, one of which is assigned, with the assistance of the key word ARRAY
(field), a defined Derived data type. A field is a collection of data elements of the
same Data type.
FIR filter
Finite Impulse Response Filter
Formal
parameters
Input/Output parameters, which are used within the logic of a FFB and led out of the
FFB as inputs/outputs.
Function (FUNC)
A Program organization unit, which exactly supplies a data element when executing.
A function has no internal status information. Multiple call ups of the same function
with the same input parameter values always supply the same output values.
Details of the graphic form of function call up can be found in the definition " Function
block (Item)". In contrast to the call up of function blocks, the function call ups only
have one unnamed output, whose name is the name of the function itself. In FBD
each call up is denoted by a unique number over the graphic block; this number is
automatically generated and cannot be altered.
Function block
(item) (FB)
A function block is a Program organization unit, which correspondingly calculates
the functionality values, defined in the function block type description, for the output
and internal variables, when it is called up as a certain item. All output values and
internal variables of a certain function block item remain as a call up of the function
block until the next. Multiple call up of the same function block item with the
same arguments (Input parameter values) supply generally supply the same
output value(s).
Each function block item is displayed graphically by a rectangular block symbol. The
name of the function block type is located on the top center within the rectangle. The
name of the function block item is located also at the top, but on the outside of the
rectangle. An instance is automatically generated when creating, which can
however be altered manually, if required. Inputs are displayed on the left side and
outputs on the right of the block. The names of the formal input/output parameters
are displayed within the rectangle in the corresponding places.
The above description of the graphic presentation is principally applicable to
Function call ups and to DFB call ups. Differences are described in the
corresponding definitions.
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Glossary
Function block
dialog (FBD)
One or more sections, which contain graphically displayed networks from Functions,
Function blocks and Connections.
Function block
type
A language element, consisting of: 1. the definition of a data structure, subdivided
into input, output and internal variables, 2. A set of operations, which is used with
the elements of the data structure, when a function block type instance is called up.
This set of operations can be formulated either in one of the IEC languages
(DFB type) or in "C" (EFB type). A function block type can be instanced (called up)
several times.
Function counter
The function counter serves as a unique identifier for the function in a Program or
DFB. The function counter cannot be edited and is automatically assigned. The
function counter always has the structure: .n.m
n = Section number (number running)
m = Number of the FFB object in the section (number running)
G
Generic data
type
A Data type, which stands in for several other data types.
Generic literal
If the Data type of a literal is not relevant, simply enter the value for the literal. In this
case Concept automatically assigns the literal to a suitable data type.
Global derived
data types
Global Derived data types are available in every Concept project and are contained
in the DFB directory directly under the Concept directory.
Global DFBs
Global DFBs are available in every Concept project and are contained in the DFB
directory directly under the Concept directory.
Global macros
Global Macros are available in every Concept project and are contained in the DFB
directory directly under the Concept directory.
Groups (EFBs)
Some EFB libraries (e.g. the IEC library) are subdivided into groups. This facilitates
the search for FFBs, especially in extensive libraries.
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Glossary
I
I/O component
list
The I/O and expert assemblies of the various CPUs are configured in the I/O
component list.
IEC 61131-3
International norm: Programmable controllers – part 3: Programming languages.
IEC format (QW1)
In the place of the address stands an IEC identifier, followed by a five figure address:
%0x12345 = %Q12345
z %1x12345 = %I12345
z %3x12345 = %IW12345
z %4x12345 = %QW12345
z
IEC name
conventions
(identifier)
An identifier is a sequence of letters, figures, and underscores, which must start with
a letter or underscores (e.g. name of a function block type, of an item or section).
Letters from national sets of characters (e.g. ö,ü, é, õ) can be used, taken from
project and DFB names.
Underscores are significant in identifiers; e.g. "A_BCD" and "AB_CD" are
interpreted as different identifiers. Several leading and multiple underscores are not
authorized consecutively.
Identifiers are not permitted to contain space characters. Upper and/or lower case
is not significant; e.g. "ABCD" and "abcd" are interpreted as the same identifier.
Identifiers are not permitted to be Key words.
IIR filter
Infinite Impulse Response Filter
Initial step
(starting step)
The first step in a chain. In each chain, an initial step must be defined. The chain is
started with the initial step when first called up.
Initial value
The allocated value of one of the variables when starting the program. The value
assignment appears in the form of a Literal.
Input bits (1x
references)
The 1/0 status of input bits is controlled via the process data, which reaches the CPU
from an entry device.
Note: The x, which comes after the first figure of the reference type, represents a
five figure storage location in the application data store, i.e. if the reference 100201
signifies an input bit in the address 201 of the State RAM.
Input parameters
(Input)
When calling up a FFB the associated Argument is transferred.
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Glossary
Input words (3x
references)
An input word contains information, which come from an external source and are
represented by a 16 bit figure. A 3x register can also contain 16 sequential input bits,
which were read into the register in binary or BCD (binary coded decimal) format.
Note: The x, which comes after the first figure of the reference type, represents a
five figure storage location in the user data store, i.e. if the reference 300201
signifies a 16 bit input word in the address 201 of the State RAM.
Instantiation
The generation of an Item.
Instruction (IL)
Instructions are "commands" of the IL programming language. Each operation
begins on a new line and is succeeded by an operator (with modifier if needed) and,
if necessary for each relevant operation, by one or more operands. If several
operands are used, they are separated by commas. A tag can stand before the
instruction, which is followed by a colon. The commentary must, if available, be the
last element in the line.
Instruction
(LL984)
When programming electric controllers, the task of implementing operational coded
instructions in the form of picture objects, which are divided into recognizable
contact forms, must be executed. The designed program objects are, on the user
level, converted to computer useable OP codes during the loading process. The OP
codes are deciphered in the CPU and processed by the controller’s firmware
functions so that the desired controller is implemented.
Instruction list
(IL)
IL is a text language according to IEC 1131, in which operations, e.g. conditional/
unconditional call up of Function blocks and Functions, conditional/unconditional
jumps etc. are displayed through instructions.
INT
INT stands for the data type "whole number". The input appears as Integer literal,
Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element is 16
bit. The range of values for variables of this data type is from –2 exp (15) to 2 exp
(15) –1.
Integer literals
Integer literals function as the input of whole number values in the decimal system.
The values may be preceded by the signs (+/-). Single underline signs ( _ ) between
figures are not significant.
Example
-12, 0, 123_456, +986
INTERBUS (PCP)
To use the INTERBUS PCP channel and the INTERBUS process data
preprocessing (PDP), the new I/O station type INTERBUS (PCP) is led into the
Concept configurator. This I/O station type is assigned fixed to the INTERBUS
connection module 180-CRP-660-01.
The 180-CRP-660-01 differs from the 180-CRP-660-00 only by a clearly larger I/O
area in the state RAM of the controller.
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Glossary
Item name
An Identifier, which belongs to a certain Function block item. The item name serves
as a unique identifier for the function block in a program organization unit. The item
name is automatically generated, but can be edited. The item name must be unique
throughout the Program organization unit, and no distinction is made between
upper/lower case. If the given name already exists, a warning is given and another
name must be selected. The item name must conform to the IEC name conventions,
otherwise an error message appears. The automatically generated instance name
always has the structure: FBI_n_m
FBI = Function block item
n = Section number (number running)
m = Number of the FFB object in the section (number running)
J
Jump
Element of the SFC language. Jumps are used to jump over areas of the chain.
K
Key words
Key words are unique combinations of figures, which are used as special syntactic
elements, as is defined in appendix B of the IEC 1131-3. All key words, which are
used in the IEC 1131-3 and in Concept, are listed in appendix C of the IEC 1131-3.
These listed keywords cannot be used for any other purpose, i.e. not as variable
names, section names, item names etc.
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Glossary
L
Ladder Diagram
(LD)
Ladder Diagram is a graphic programming language according to IEC1131, which
optically orientates itself to the "rung" of a relay ladder diagram.
Ladder Logic 984
(LL)
In the terms Ladder Logic and Ladder Diagram, the word Ladder refers to execution.
In contrast to a diagram, a ladder logic is used by engineers to draw up a circuit (with
assistance from electrical symbols),which should chart the cycle of events and not
the existing wires, which connect the parts together. A usual user interface for
controlling the action by automated devices permits ladder logic interfaces, so that
when implementing a control system, engineers do not have to learn any new
programming languages, with which they are not conversant.
The structure of the actual ladder logic enables electrical elements to be linked in a
way that generates a control output, which is dependant upon a configured flow of
power through the electrical objects used, which displays the previously demanded
condition of a physical electric appliance.
In simple form, the user interface is one of the video displays used by the PLC
programming application, which establishes a vertical and horizontal grid, in which
the programming objects are arranged. The logic is powered from the left side of the
grid, and by connecting activated objects the electricity flows from left to right.
Landscape
format
Landscape format means that the page is wider than it is long when looking
at the printed text.
Language
element
Each basic element in one of the IEC programming languages, e.g. a Step in SFC,
a Function block item in FBD or the Start value of a variable.
Library
Collection of software objects, which are provided for reuse when programming new
projects, or even when building new libraries. Examples are the Elementary function
block types libraries.
EFB libraries can be subdivided into Groups.
Literals
Literals serve to directly supply values to inputs of FFBs, transition conditions etc.
These values cannot be overwritten by the program logic (write protected). In this
way, generic and standardized literals are differentiated.
Furthermore literals serve to assign a Constant a value or a Variable an Initial value.
The input appears as Base 2 literal, Base 8 literal, Base 16 literal, Integer literal, Real
literal or Real literal with exponent.
Local derived
data types
Local derived data types are only available in a single Concept project and its local
DFBs and are contained in the DFB directory under the project directory.
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Glossary
Local DFBs
Local DFBs are only available in a single Concept project and are contained in the
DFB directory under the project directory.
Local link
The local network link is the network, which links the local nodes with other nodes
either directly or via a bus amplifier.
Local macros
Local Macros are only available in a single Concept project and are contained in the
DFB directory under the project directory.
Local network
nodes
The local node is the one, which is projected evenly.
Located variable
Located variables are assigned a state RAM address (reference addresses 0x,1x,
3x, 4x). The value of these variables is saved in the state RAM and can be altered
online with the reference data editor. These variables can be addressed by symbolic
names or the reference addresses.
Collective PLC inputs and outputs are connected to the state RAM. The program
access to the peripheral signals, which are connected to the PLC, appears only via
located variables. PLC access from external sides via Modbus or Modbus plus
interfaces, i.e. from visualizing systems, are likewise possible via located variables.
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Glossary
M
Macro
Macros are created with help from the software Concept DFB.
Macros function to duplicate frequently used sections and networks (including the
logic, variables, and variable declaration).
Distinctions are made between local and global macros.
Macros have the following properties:
z Macros can only be created in the programming languages FBD and LD.
z Macros only contain one single section.
z Macros can contain any complex section.
z From a program technical point of view, there is no differentiation between an
instanced macro, i.e. a macro inserted into a section, and a conventionally
created macro.
z Calling up DFBs in a macro
z Variable declaration
z Use of macro-own data structures
z Automatic acceptance of the variables declared in the macro
z Initial value for variables
z Multiple instancing of a macro in the whole program with different variables
z The section name, the variable name and the data structure name can contain up
to 10 different exchange markings (@0 to @9).
MMI
Man Machine Interface
Multi element
variables
Variables, one of which is assigned a Derived data type defined with STRUCT or
ARRAY.
Distinctions are made between Field variables and structured variables.
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Glossary
N
Network
A network is the connection of devices to a common data path, which communicate
with each other via a common protocol.
Network node
A node is a device with an address (164) on the Modbus Plus network.
Node address
The node address serves a unique identifier for the network in the routing path. The
address is set directly on the node, e.g. with a rotary switch on the back of the
module.
O
Operand
An operand is a Literal, a Variable, a Function call up or an Expression.
Operator
An operator is a symbol for an arithmetic or Boolean operation to be executed.
Output
parameters
(Output)
A parameter, with which the result(s) of the Evaluation of a FFB are returned.
Output/discretes
(0x references)
An output/marker bit can be used to control real output data via an output unit of the
control system, or to define one or more outputs in the state RAM. Note: The x,
which comes after the first figure of the reference type, represents a five figure
storage location in the application data store, i.e. if the reference 000201 signifies
an output or marker bit in the address 201 of the State RAM.
Output/marker
words (4x
references)
An output/marker word can be used to save numerical data (binary or decimal) in
the State RAM, or also to send data from the CPU to an output unit in the control
system. Note: The x, which comes after the first figure of the reference type,
represents a five figure storage location in the application data store, i.e. if the
reference 400201 signifies a 16 bit output or marker word in the address 201 of the
State RAM.
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Glossary
P
Peer processor
The peer processor processes the token run and the flow of data between the
Modbus Plus network and the PLC application logic.
PLC
Programmable controller
Program
The uppermost Program organization unit. A program is closed and loaded onto a
single PLC.
Program cycle
A program cycle consists of reading in the inputs, processing the program logic and
the output of the outputs.
Program
organization unit
A Function, a Function block, or a Program. This term can refer to either a Type or
an Item.
Programming
device
Hardware and software, which supports programming, configuring, testing,
implementing and error searching in PLC applications as well as in remote system
applications, to enable source documentation and archiving. The programming
device could also be used for process visualization.
Programming
redundancy
system (Hot
Standby)
A redundancy system consists of two identically configured PLC devices, which
communicate with each other via redundancy processors. In the case of the primary
PLC failing, the secondary PLC takes over the control checks. Under normal
conditions the secondary PLC does not take over any controlling functions, but
instead checks the status information, to detect mistakes.
Project
General identification of the uppermost level of a software tree structure, which
specifies the parent project name of a PLC application. After specifying the project
name, the system configuration and control program can be saved under this name.
All data, which results during the creation of the configuration and the program,
belongs to this parent project for this special automation.
General identification for the complete set of programming and configuring
information in the Project data bank, which displays the source code that describes
the automation of a system.
Project data bank
The data bank in the Programming device, which contains the projection
information for a Project.
Prototype data
file (Concept
EFB)
The prototype data file contains all prototypes of the assigned functions. Further, if
available, a type definition of the internal status structure is given.
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Glossary
R
REAL
REAL stands for the data type "real". The input appears as Real literal or as Real
literal with exponent. The length of the data element is 32 bit. The value range for
variables of this data type reaches from 8.43E-37 to 3.36E+38.
Note: Depending on the mathematic processor type of the CPU, various areas
within this valid value range cannot be represented. This is valid for values nearing
ZERO and for values nearing INFINITY. In these cases, a number value is not
shown in animation, instead NAN (Not A Number) oder INF (INFinite).
Real literal
Real literals function as the input of real values in the decimal system. Real literals
are denoted by the input of the decimal point. The values may be preceded by the
signs (+/-). Single underline signs ( _ ) between figures are not significant.
Example
-12.0, 0.0, +0.456, 3.14159_26
Real literal with
exponent
Real literals with exponent function as the input of real values in the decimal system.
Real literals with exponent are denoted by the input of the decimal point. The
exponent sets the key potency, by which the preceding number is multiplied to get
to the value to be displayed. The basis may be preceded by a negative sign (-). The
exponent may be preceded by a positive or negative sign (+/-). Single underline
signs ( _ ) between figures are not significant. (Only between numbers, not before
or after the decimal poiont and not before or after "E", "E+" or "E-")
Example
-1.34E-12 or -1.34e-12
1.0E+6 or 1.0e+6
1.234E6 or 1.234e6
Reference
Each direct address is a reference, which starts with an ID, specifying whether it
concerns an input or an output and whether it concerns a bit or a word. References,
which start with the code 6, display the register in the extended memory of the state
RAM.
0x area = Discrete outputs
1x area = Input bits
3x area = Input words
4x area = Output bits/Marker words
6x area = Register in the extended memory
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Glossary
Note: The x, which comes after the first figure of each reference type, represents
a five figure storage location in the application data store, i.e. if the reference
400201 signifies a 16 bit output or marker word in the address 201 of the State
RAM.
Register in the
extended
memory (6x
reference)
6x references are marker words in the extended memory of the PLC. Only LL984
user programs and CPU 213 04 or CPU 424 02 can be used.
RIO (Remote I/O)
Remote I/O provides a physical location of the I/O coordinate setting device in
relation to the processor to be controlled. Remote inputs/outputs are connected to
the consumer control via a wired communication cable.
RP (PROFIBUS)
RP = Remote Peripheral
RTU mode
Remote Terminal Unit
The RTU mode is used for communication between the PLC and an IBM compatible
personal computer. RTU works with 8 data bits.
Rum-time error
Error, which occurs during program processing on the PLC, with SFC objects (i.e.
steps) or FFBs. These are, for example, over-runs of value ranges with figures, or
time errors with steps.
S
SA85 module
The SA85 module is a Modbus Plus adapter for an IBM-AT or compatible computer.
Section
A section can be used, for example, to describe the functioning method of a
technological unit, such as a motor.
A Program or DFB consist of one or more sections. Sections can be programmed
with the IEC programming languages FBD and SFC. Only one of the named
programming languages can be used within a section.
Each section has its own Document window in Concept. For reasons of clarity, it is
recommended to subdivide a very large section into several small ones. The scroll
bar serves to assist scrolling in a section.
Separator format
(4:00001)
The first figure (the Reference) is separated from the ensuing five figure address by
a colon (:).
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Glossary
Sequence
language (SFC)
The SFC Language elements enable the subdivision of a PLC program organizational unit in a number of Steps and Transitions, which are connected horizontally
by aligned Connections. A number of actions belong to each step, and a transition
condition is linked to a transition.
Serial ports
With serial ports (COM) the information is transferred bit by bit.
Source code data
file (Concept
EFB)
The source code data file is a usual C++ source file. After execution of the menu
command LibraryoGenerate data files this file contains an EFB code framework,
in which a specific code must be entered for the selected EFB. To do this, click on
the menu command ObjectsoSource.
Standard format
(400001)
The five figure address is located directly after the first figure (the reference).
Standardized
literals
If the data type for the literal is to be automatically determined, use the following
construction: ’Data type name’#’Literal value’.
Example
INT#15 (Data type: Integer, value: 15),
BYTE#00001111 (data type: Byte, value: 00001111)
REAL#23.0 (Data type: Real, value: 23.0)
For the assignment of REAL data types, there is also the possibility to enter the
value in the following way: 23.0.
Entering a comma will automatically assign the data type REAL.
State RAM
The state RAM is the storage for all sizes, which are addressed in the user program
via References (Direct display). For example, input bits, discretes, input words, and
discrete words are located in the state RAM.
Statement (ST)
Instructions are "commands" of the ST programming language. Instructions must be
terminated with semicolons. Several instructions (separated by semi-colons) can
occupy the same line.
Status bits
There is a status bit for every node with a global input or specific input/output of Peer
Cop data. If a defined group of data was successfully transferred within the set time
out, the corresponding status bit is set to 1. Alternatively, this bit is set to 0 and all
data belonging to this group (of 0) is deleted.
Step
SFC Language element: Situations, in which the Program behavior follows in
relation to the inputs and outputs of the same operations, which are defined by the
associated actions of the step.
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Glossary
Step name
The step name functions as the unique flag of a step in a Program organization unit.
The step name is automatically generated, but can be edited. The step name must
be unique throughout the whole program organization unit, otherwise an Error
message appears.
The automatically generated step name always has the structure: S_n_m
S = Step
n = Section number (number running)
m = Number of steps in the section (number running)
Structured text
(ST)
ST is a text language according to IEC 1131, in which operations, e.g. call up of
Function blocks and Functions, conditional execution of instructions, repetition of
instructions etc. are displayed through instructions.
Structured
variables
Variables, one of which is assigned a Derived data type defined with STRUCT
(structure).
A structure is a collection of data elements with generally differing data types (
Elementary data types and/or derived data types).
SY/MAX
In Quantum control devices, Concept closes the mounting on the I/O population SY/
MAX I/O modules for RIO control via the Quantum PLC with on. The SY/MAX
remote subrack has a remote I/O adapter in slot 1, which communicates via a
Modicon S908 R I/O system. The SY/MAX I/O modules are performed when
highlighting and including in the I/O population of the Concept configuration.
Symbol (Icon)
Graphic display of various objects in Windows, e.g. drives, user programs and
Document windows.
T
Template data
file (Concept
EFB)
The template data file is an ASCII data file with a layout information for the Concept
FBD editor, and the parameters for code generation.
TIME
TIME stands for the data type "Time span". The input appears as Time span literal.
The length of the data element is 32 bit. The value range for variables of this type
stretches from 0 to 2exp(32)-1. The unit for the data type TIME is 1 ms.
Time span
literals
Permitted units for time spans (TIME) are days (D), hours (H), minutes (M), seconds
(S) and milliseconds (MS) or a combination thereof. The time span must be denoted
by the prefix t#, T#, time# or TIME#. An "overrun" of the highest ranking unit is
permitted, i.e. the input T#25H15M is permitted.
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Glossary
Example
t#14MS, T#14.7S, time#18M, TIME#19.9H, t#20.4D, T#25H15M,
time#5D14H12M18S3.5MS
Token
The network "Token" controls the temporary property of the transfer rights via a
single node. The token runs through the node in a circulating (rising) address
sequence. All nodes track the Token run through and can contain all possible data
sent with it.
Traffic Cop
The Traffic Cop is a component list, which is compiled from the user component list.
The Traffic Cop is managed in the PLC and in addition contains the user component
list e.g. Status information of the I/O stations and modules.
Transition
The condition with which the control of one or more Previous steps transfers to one
or more ensuing steps along a directional Link.
U
UDEFB
User defined elementary functions/function blocks
Functions or Function blocks, which were created in the programming language C,
and are available in Concept Libraries.
UDINT
UDINT stands for the data type "unsigned double integer". The input appears as
Integer literal, Base 2 literal, Base 8 literal or Base 16 literal. The length of the data
element is 32 bit. The value range for variables of this type stretches from 0 to
2exp(32)-1.
UINT
UINT stands for the data type "unsigned integer". The input appears as Integer
literal, Base 2 literal, Base 8 literal or Base 16 literal. The length of the data element
is 16 bit. The value range for variables of this type stretches from 0 to (2exp16)-1.
Unlocated
variable
Unlocated variables are not assigned any state RAM addresses. They therefore do
not occupy any state RAM addresses. The value of these variables is saved in the
system and can be altered with the reference data editor. These variables are only
addressed by symbolic names.
Signals requiring no peripheral access, e.g. intermediate results, system tags etc,
should primarily be declared as unlocated variables.
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Glossary
V
Variables
Variables function as a data exchange within sections between several sections and
between the Program and the PLC.
Variables consist of at least a variable name and a Data type.
Should a variable be assigned a direct Address (Reference), it is referred to as a
Located variable. Should a variable not be assigned a direct address, it is referred
to as an unlocated variable. If the variable is assigned a Derived data type, it is
referred to as a Multi-element variable.
Otherwise there are Constants and Literals.
Vertical format
Vertical format means that the page is higher than it is wide when looking at the
printed text.
W
Warning
When processing a FFB or a Step a critical status is detected (e.g. critical input value
or a time out), a warning appears, which can be viewed with the menu command
OnlineoEvent display... . With FFBs the ENO output remains at "1".
WORD
WORD stands for the data type "Bit sequence 16". The input appears as Base 2
literal, Base 8 literal or Base 1 16 literal. The length of the data element is 16 bit. A
numerical range of values cannot be assigned to this data type.
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Glossary
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This document provided by Barr-Thorp Electric Co., Inc. 800-473-9123
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B
AC
Index
Numerics
3x or 4x register
entering in mathematical equation, 57
assignment operator, 59
Average Weighted Inputs Calculate, 803
B
A
ABS, 64
AD16, 109
ADD, 113
Add 16 Bit, 109
Addition, 113
AD16, 109
ADD, 113
Advanced Calculations, 782
algebraic expression
equation network, 54
algebraic notation
equation network, 51
Analog Input, 787
Analog Output, 799
Analog Values, 71
AND, 117
ARCCOS, 64
ARCSIN, 64
ARCTAN, 64
argument
equation network, 64
limits, 65
arithmetic operator, 59
ASCII Functions
READ, 937
WRIT, 1091
Base 10 Antilogarithm, 279
Base 10 Logarithm, 383
BCD, 123
benchmark performance
equation network, 69
Binary to Binary Code, 123
Bit Control, 755
Bit pattern comparison
CMPR, 167
Bit Rotate, 139
bitwise operator, 59
BLKM, 127
BLKT, 131
Block Move, 127
Block Move with Interrupts Disabled, 135
Block to Table, 131
BMDI, 135
boolean, 56
BROT, 139
C
Calculated preset formula, 809
Central Alarm Handler, 793
Changing the Sign of a Floating Point
Number, 301
Check Sum, 163
lv
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Index
CHS, 157
CKSM, 163
Closed Loop Control, 71
CMPR, 167
coil
equation network, 53
error messages, 53
Coils, 91
Communications
MSTR, 701
COMP, 179
Compare Register, 167
Complement a Matrix, 179
Comprehensive ISA Non Interacting PID,
831
conditional expression
equation network, 51, 61
conditional operator, 59
Configure Hot Standby, 157
constant
equation network, 51
constant data
floating point, 57
long (32-bit), 57
LSB (least signifcant byte), 57
mathematical equation, 57
Contacts, 91
Convertion
BCD to binary, 123
binary to BCD, 123
COS, 64
COSD, 64
Counters / Timers
T.01 Timer, 1049
T0.1 Timer, 1053
T1.0 Timer, 1057
T1MS Timer, 1061
UCTR, 1077
Counters/Timers
DCTR, 203
creating equation network, 52
D
data
mathematical equation, 56
data conversions
equation network, 66
Data Logging for PCMCIA Read/Write
Support, 223
DCTR, 203
Derivative Rate Calculation over a Specified
Time, 883
DIOH, 207
discrete reference
mathematical equation, 56
Distributed I/O Health, 207
DIV, 217
Divide, 217
Divide 16 Bit, 243
DLOG, 223
Double Precision Addition, 265
Double Precision Division, 347
Double Precision Multiplication, 395
Double Precision Subtraction, 447
Down Counter, 203
DRUM, 237
DRUM Sequencer, 237
DV16, 243
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Index
E
EMTH, 259
EMTH Subfunction
EMTH-ADDDP, 265
EMTH-ADDFP, 271, 275
EMTH-ANLOG, 279
EMTH-ARCOS, 285
EMTH-ARSIN, 291
EMTH-ARTAN, 295
EMTH-CHSIN, 301
EMTH-CMPFP, 307
EMTH-CMPIF, 313
EMTH-CNVDR, 319
EMTH-CNVFI, 325
EMTH-CNVIF, 331
EMTH-CNVRD, 337
EMTH-COS, 343
EMTH-DIVDP, 347
EMTH-DIVFI, 353
EMTH-DIVFP, 357
EMTH-DIVIF, 361
EMTH-ERLOG, 365
EMTH-EXP, 371
EMTH-LNFP, 377
EMTH-LOG, 383
EMTH-LOGFP, 389
EMTH-MULDP, 395
EMTH-MULFP, 401
EMTH-MULIF, 405
EMTH-PI, 411
EMTH-POW, 417
EMTH-SINE, 423
EMTH-SQRFP, 429
EMTH-SQRT, 435
EMTH-SQRTP, 441
EMTH-SUBDP, 447
EMTH-SUBFI, 453
EMTH-SUBFP, 457
EMTH-SUBIF, 461
EMTH-TAN, 465
EMTH-ADDDP, 265
EMTH-ADDFP, 271
EMTH-ADDIF, 275
EMTH-ANLOG, 279
EMTH-ARCOS, 285
EMTH-ARSIN, 291
EMTH-ARTAN, 295
EMTH-CHSIN, 301
EMTH-CMPFP, 307
EMTH-CMPIF, 313
EMTH-CNVDR, 319
EMTH-CNVFI, 325
EMTH-CNVIF, 331
EMTH-CNVRD, 337
EMTH-COS, 343
EMTH-DIVDP, 347
EMTH-DIVFI, 353
EMTH-DIVFP, 357
EMTH-DIVIF, 361
EMTH-ERLOG, 365
EMTH-EXP, 371
EMTH-LNFP, 377
EMTH-LOG, 383
EMTH-LOGFP, 389
EMTHMULDP, 395
EMTH-MULFP, 401
EMTH-MULIF, 405
EMTH-PI, 411
EMTH-POW, 417
EMTH-SINE, 423
EMTH-SQRFP, 429
EMTH-SQRT, 435
EMTH-SQRTP, 441
EMTH-SUBDP, 447
EMTH-SUBFI, 453
EMTH-SUBFP, 457
EMTH-SUBIF, 461
EMTH-TAN, 465
enable contact
horizontal open, 53
horizontal short, 53
normally closed, 53
normally open, 53
Engineering Unit Conversion
and Alarms, 489
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Index
equation network
ABS, 64
algebraic expression, 54
algebraic notation, 51
ARCCOS, 64
ARCSIN, 64
ARCTAN, 64
argument, 64
argument limits, 65
arithmetic operator, 59
assignment operator, 59
benchmark performance, 69
bitwise operator, 59
conditional expression, 51, 61
conditional operator, 59
constant, 51
content, 54
COS, 64
COSD, 64
creating, 52
data conversions, 66
enable contact, 53
entering function, 64
entering parentheses, 63
EXP, 64
exponentiation operator, 59
FIX, 64
FLOAT, 64
group expressions in nested layers of
parentheses, 51
LN, 64
LOG, 64
logic editor, 51
logical expression, 51
math operator, 51
mathematical, 55
mathematical function, 64
mathematical operation, 59
nested parentheses, 63
operator precedence, 62
output coil, 53
overview, 51
parentheses, 59, 63
relational operator, 59
result, 54
roundoff differences, 68
SIN, 64
SIND, 64
single expression, 61
size, 54
SQRT, 64
TAN, 64
TAND, 64
unary operator, 59
variable, 51
words consumed, 54
ESI, 469
EUCA, 489
Exclusive OR, 1145
EXP, 64
exponential notation
mathematical equation, 58
exponentiation operator, 59
expression
equation network, 61
Extended Math, 259
Extended Memory Read, 1133
Extended Memory Write, 1139
lviii
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Index
F
Fast I/O Instructions
BMDI, 135
ID, 617
IE, 621
IMIO, 625
IMOD, 631
ITMR, 639
FIN, 503
First In, 503
First Out, 507
First-order Lead/Lag Filter, 851
FIX, 64
FLOAT, 64
Floating Point - Integer Subtraction, 453
Floating Point Addition, 271
Floating Point Arc Cosine of an Angle (in
Radians), 285
Floating Point Arc Tangent of an Angle (in
Radians), 295
Floating Point Arcsine of an Angle (in
Radians), 291
Floating Point Common Logarithm, 389
Floating Point Comparison, 307
Floating Point Conversion of Degrees to
Radians, 319
Floating Point Conversion of Radians to
Degrees, 337
Floating Point Cosine of an Angle (in
Radians), 343
Floating Point Divided by Integer, 353
Floating Point Division, 357
Floating Point Error Report Log, 365
Floating Point Exponential Function, 371
Floating Point Multiplication, 401
Floating Point Natural Logarithm, 377
Floating Point Sine of an Angle
(in Radians), 423
Floating Point Square Root, 429, 435
Floating Point Subtraction, 457
Floating Point Tangent of an Angle (in
Radians), 465
Floating Point to Integer, 513
Floating Point to Integer Conversion, 325
floating point variable, 56
Formatted Equation Calculator, 821
Formatting Messages, 83
Four Station Ratio Controller, 887
FOUT, 507
FTOI, 513
function
ABS, 64
ARCCOS, 64
ARCSIN, 64
ARCTAN, 64
argument, 64
argument limits, 65
COS, 64
COSD, 64
entering in equation network, 64
EXP, 64
FIX, 64
FLOAT, 64
LN, 64
LOG, 64
SIN, 64
SIND, 64
SQRT, 64
TAN, 64
TAND, 64
G
group expressions in nested layers of
parentheses
equation network, 51
H
History and Status Matrices, 583
HLTH, 583
horizontal open
equation network, 53
horizontal short
equation network, 53
Hot standby
CHS, 157
lix
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Index
I
IBKR, 603
IBKW, 607
ICMP, 611
ID, 617
IE, 621
IMIO, 625
Immediate I/O, 625
IMOD, 631
Indirect Block Read, 603
Indirect Block Write, 607
infix notation
equation network, 52
Input Compare, 611
Input Selection, 897
Installation of DX Loadables, 101
Instruction
Coils, Contacts and Interconnects, 91
Instruction Groups, 37
ASCII Communication Instructions, 39
Coils, Contacts and Interconnects, 50
Counters and Timers Instructions, 40
Fast I/O Instructions, 41
Loadable DX, 42
Math Instructions, 43
Matrix Instructions, 45
Miscellaneous, 46
Move Instructions, 47
Overview, 38
Skips/Specials, 48
Special Instructions, 49
Integer - Floating Point Subtraction, 461
Integer + Floating Point Addition, 275
Integer Divided by Floating Point, 361
Integer to Floating Point, 645
Integer x Floating Point Multiplication, 405
Integer-Floating Point Comparison, 313
Integer-to-Floating Point Conversion, 331
Integrate Input at Specified Interval, 827
Interconnects, 91
Interrupt Disable, 617
Interrupt Enable, 621
Interrupt Handling, 97
Interrupt Module Instruction, 631
Interrupt Timer, 639
ISA Non Interacting PI, 865
ITMR, 639
ITOF, 645
J
JSR, 649
Jump to Subroutine, 649
L
LAB, 653
Label for a Subroutine, 653
Limiter for the Pv, 837
lx
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This document provided by Barr-Thorp Electric Co., Inc. 800-473-9123
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Index
LL984
AD16, 109
ADD, 113
AND, 117
BCD, 123
BLKM, 127
BLKT, 131
BMDI, 135
BROT, 139
CHS, 157
CKSM, 163
Closed Loop Control / Analog Values, 71
CMPR, 167
Coils, Contacts and Interconnects, 91
COMP, 179
DCTR, 203
DIOH, 207
DIV, 217
DLOG, 223
DRUM, 237
DV16, 243
EMTH, 259
EMTH-ADDDP, 265
EMTH-ADDFP, 271
EMTH-ADDIF, 275
EMTH-ANLOG, 279
EMTH-ARCOS, 285
EMTH-ARSIN, 291
EMTH-ARTAN, 295
EMTH-CHSIN, 301
EMTH-CMPFP, 307
EMTH-CMPIF, 313
EMTH-CNVDR, 319
EMTH-CNVFI, 325
EMTH-CNVIF, 331
EMTH-CNVRD, 337
EMTH-COS, 343
EMTH-DIVDP, 347
EMTH-DIVFI, 353
EMTH-DIVFP, 357
EMTH-DIVIF, 361
EMTH-ERLOG, 365
EMTH-EXP, 371
EMTH-LNFP, 377
EMTH-LOG, 383
EMTH-LOGFP, 389
EMTH-MULDP, 395
EMTH-MULFP, 401
EMTH-MULIF, 405
EMTH-PI, 411
EMTH-POW, 417
EMTH-SINE, 423
EMTH-SQRFP, 429
EMTH-SQRT, 435
EMTH-SQRTP, 441
EMTH-SUBDP, 447
EMTH-SUBFI, 453
EMTH-SUBFP, 457
EMTH-SUBIF, 461
EMTH-TAN, 465
ESI, 469
EUCA, 489
FIN, 503
Formatting Messages for ASCII READ/
lxi
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Index
WRIT Operations, 83
FOUT, 507
FTOI, 513
HLTH, 583
IBKR, 603
IBKW, 607
ICMP, 611
ID, 617
IE, 621
IMIO, 625
IMOD, 631
Interrupt Handling, 97
ITMR, 639
ITOF, 645
JSR, 649
LAB, 653
LOAD, 657
MAP 3, 661
MBIT, 677
MBUS, 681
MRTM, 691
MSTR, 701
MU16, 747
MUL, 751
NBIT, 755
NCBT, 759
NOBT, 763
NOL, 767
OR, 775
PCFL, 781
PCFL-AIN, 787
PCFL-ALARM, 793
PCFL-AOUT, 799
PCFL-AVER, 803
PCFL-CALC, 809
PCFL-DELAY, 815
PCFL-EQN, 821
PCFL-INTEG, 827
PCFL-KPID, 831
PCFL-LIMIT, 837
PCFL-LIMV, 841
PCFL-LKUP, 845
PCFL-LLAG, 851
PCFL-MODE, 855
PCFL-ONOFF, 859
PCFL-PI, 865
PCFL-PID, 871
PCFL-RAMP, 877
PCFL-RATE, 883
PCFL-RATIO, 887
PCFL-RMPLN, 893
PCFL-SEL, 897
PCFL-TOTAL, 903
PEER, 909
PID2, 913
R --> T, 929
RBIT, 933
READ, 937
RET, 943
SAVE, 961
SBIT, 965
SCIF, 969
SENS, 975
SRCH, 987
STAT, 993
SU16, 1021
SUB, 1025
Subroutine Handling, 99
T.01 Timer, 1049
T-->R, 1037
T-->T, 1043
T0.1 Timer, 1053
T1.0 Timer, 1057
T1MS Timer, 1061
TBLK, 1067
TEST, 1073
UCTR, 1077
WRIT, 1091
XMRD, 1133
XMWT, 1139
XOR, 1145
LN, 64
LOAD, 657
Load Flash, 657
Load the Floating Point Value of "Pi", 411
lxii
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www.barr-thorp.com
Index
Loadable DX
CHS, 157
DRUM, 237
ESI, 469
EUCA, 489
HLTH, 583
ICMP, 611
Installation, 101
MAP 3, 661
MBUS, 681
MRTM, 691
NOL, 767
PEER, 909
LOG, 64
Logarithmic Ramp to Set Point, 893
logic editor
equation network, 51, 52
Logical And, 117
logical expression
equation network, 51
Logical OR, 775
Look-up Table, 845
LSB (least significant byte)
constant data, 57
M
MAP 3, 661
MAP Transaction, 661
Master, 701
Math
AD16, 109
ADD, 113
BCD, 123
DIV, 217
DV16, 243
FTOI, 513
ITOF, 645
MU16, 747
MUL, 751
SU16, 1021
SUB, 1025
TEST, 1073
math coprocessor
roundoff differences, 68
math operator
equation network, 51
mathematical equation
constant data, 57
exponential notation, 58
values and data types, 55
mathematical function
ABS, 64
ARCCOS, 64
ARCSIN, 64
ARCTAN, 64
argument, 64
argument limits, 65
COS, 64
COSD, 64
entering in equation network, 64
equation network, 64
EXP, 64
FIX, 64
FLOAT, 64
LN, 64
LOG, 64
SIN, 64
SIND, 64
SQRT, 64
TAN, 64
TAND, 64
mathematical operation
arithmetic operator, 59
assignment operator, 59
bitwise operator, 59
conditional operator, 59
equation network, 59
exponentiation operator, 59
parentheses, 59
relational operator, 59
unary operator, 59
lxiii
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Index
Matrix
AND, 117
BROT, 139
CMPR, 167
COMP, 179
MBIT, 677
NBIT, 755
NCBT, 759, 763
OR, 775
RBIT, 933
SBIT, 965
SENS, 975
XOR, 1145
MBIT, 677
MBUS, 681
MBUS Transaction, 681
Miscellaneous
CKSM, 163
DLOG, 223
EMTH, 259
EMTH-ADDDP, 265
EMTH-ADDFP, 271
EMTH-ADDIF, 275
EMTH-ANLOG, 279
EMTH-ARCOS, 285, 343
EMTH-ARSIN, 291
EMTH-ARTAN, 295
EMTH-CHSIN, 301
EMTH-CMPFP, 307
EMTH-CMPIF, 313
EMTH-CNVDR, 319
EMTH-CNVFI, 325
EMTH-CNVIF, 331
EMTH-CNVRD, 337
EMTH-DIVDP, 347
EMTH-DIVFI, 353
EMTH-DIVFP, 357
EMTH-DIVIF, 361
EMTH-ERLOG, 365
EMTH-EXP, 371
EMTH-LNFP, 377
EMTH-LOG, 383
EMTH-LOGFP, 389
EMTH-MULDP, 395
EMTH-MULFP, 401
EMTH-MULIF, 405
EMTH-PI, 411
EMTH-POW, 417
EMTH-SINE, 423
EMTH-SQRFP, 429
EMTH-SQRT, 435
EMTH-SQRTP, 441
EMTH-SUBDP, 447
EMTH-SUBFI, 453
EMTH-SUBFP, 457
EMTH-SUBIF, 461
EMTH-TAN, 465
LOAD, 657
MSTR, 701
SAVE, 961
SCIF, 969
XMRD, 1133
lxiv
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Index
XMWT, 1139
mixed data types
equation network, 66
Modbus Functions, 1099
Modbus Plus
MSTR, 701
Modbus Plus Network Statistics
MSTR, 732
Modify Bit, 677
Move
BLKM, 127
BLKT, 131
FIN, 503
FOUT, 507
IBKR, 603
IBKW, 607
R --> T, 929
SRCH, 987
T-->R, 1037
T-->T, 1043
TBLK, 1067
MRTM, 691
MSTR, 701
Clear Local Statistics, 716
Clear Remote Statistics, 722
CTE Error Codes for SY/MAX and TCP/
IP Ethernet, 746
Get Local Statistics, 714
Get Remote Statistics, 720
Modbus Plus and SY/MAX Ethernet
Error Codes, 739
Modbus Plus Network Statistics, 732
Peer Cop Health, 724
Read CTE (Config Extension Table), 728
Read Global Data, 719
Reset Option Module, 727
SY/MAX-specific Error Codes, 741
TCP/IP Ethernet Error Codes, 743
TCP/IP Ethernet Statistics, 737
Write CTE (Config Extension Table), 730
Write Global Data, 718
MU16, 747
MUL, 751
Multiply, 751
Multiply 16 Bit, 747
Multi-Register Transfer Module, 691
N
NBIT, 755
NCBT, 759
nested layer
parentheses, 51
nested parentheses
equation network, 63
Network Option Module for Lonworks, 767
NOBT, 763
NOL, 767
Normally Closed Bit, 759
normally closed contact
equation network, 53
Normally Open Bit, 763
normally open contact
equation network, 53
O
ON/OFF Values for Deadband, 859
One Hundredth Second Timer, 1049
One Millisecond Timer, 1061
One Second Timer, 1057
One Tenth Second Timer, 1053
operator combinations
equation network, 66
operator precedence
equation network, 62
OR, 775
output coil
equation network, 53
P
parentheses
entering in equation network, 63
equation network, 51
nested, 63
nested layer, 51
using in equation network, 63
PCFL, 781
PCFL Subfunctions
General, 73
PCFL-AIN, 787
PCFL-ALARM, 793
lxv
043505766 4/2006
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www.barr-thorp.com
Index
PCFL-AOUT, 799
PCFL-AVER, 803
PCFL-CALC, 809
PCFL-DELAY, 815
PCFL-EQN, 821
PCFL-INTEG, 827
PCFL-KPID, 831
PCFL-LIMIT, 837
PCFL-LIMV, 841
PCFL-LKUP, 845
PCFL-LLAG, 851
PCFL-MODE, 855
PCFL-ONOFF, 859
PCFL-PI, 865
PCFL-PID, 871
PCFL-RAMP, 877
PCFL-RATE, 883
PCFL-RATIO, 887
PCFL-RMPLN, 893
PCFL-SEL, 897
PCFL-Subfunction
PCFL-AIN, 787
PCFL-ALARM, 793
PCFL-AOUT, 799
PCFL-AVER, 803
PCFL-CALC, 809
PCFL-DELAY, 815
PCFL-EQN, 821
PCFL-INTEG, 827
PCFL-KPID, 831
PCFL-LIMIT, 837
PCFL-LIMV, 841
PCFL-LKUP, 845
PCFL-LLAG, 851
PCFL-MODE, 855
PCFL-ONOFF, 859
PCFL-PI, 865
PCFL-PID, 871
PCFL-RAMP, 877
PCFL-RATE, 883
PCFL-RATIO, 887
PCFL-RMPLN, 893
PCFL-SEL, 897
PCFL-TOTAL, 903
PCFL-TOTAL, 903
PEER, 909
PEER Transaction, 909
PID Algorithms, 871
PID Example, 77
PID2, 913
PID2 Level Control Example, 80
PLCs
roundoff differences, 68
scan time, 69
precedence
equation network, 62
Process Control Function Library, 781
Process Square Root, 441
Process Variable, 72
Proportional Integral Derivative, 913
Put Input in Auto or Manual Mode, 855
Q
Quantum PLCs
roundoff differences, 68
R
R --> T, 929
Raising a Floating Point Number to an
Integer Power, 417
Ramp to Set Point at a Constant Rate, 877
RBIT, 933
READ, 937
MSTR, 712
Read, 937
READ/WRIT Operations, 83
Register to Table, 929
registers consumed
mathematical equation, 56
Regulatory Control, 782
relational operator, 59
Reset Bit, 933
result
equation network, 54
RET, 943
Return from a Subroutine, 943
roundoff differences
equation network, 68
lxvi
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Index
S
SAVE, 961
Save Flash, 961
SBIT, 965
SCIF, 969
Search, 987
SENS, 975
Sense, 975
Sequential Control Interfaces, 969
Set Bit, 965
Set Point Vaiable, 72
signed 16-bit variable, 56
signed long (32-bit) variable, 56
SIN, 64
SIND, 64
single expression
equation network, 61
Skips / Specials
RET, 943
Skips/Specials
JSR, 649
LAB, 653
Special
DIOH, 207
PCFL, 781
PCFL-, 799
PCFL-AIN, 787
PCFL-ALARM, 793
PCFL-AVER, 803
PCFL-CALC, 809
PCFL-DELAY, 815
PCFL-EQN, 821
PCFL-KPID, 831
PCFL-LIMIT, 837
PCFL-LIMV, 841
PCFL-LKUP, 845
PCFL-LLAG, 851
PCFL-MODE, 855
PCFL-ONOFF, 859
PCFL-PI, 865
PCFL-PID, 871
PCFL-RAMP, 877
PCFL-RATE, 883
PCFL-RATIO, 887
PCFL-RMPLN, 893
PCFL-SEL, 897
PCFL-TOTAL, 903
PCPCFL-INTEGFL, 827
PID2, 913
STAT, 993
SQRT, 64
SRCH, 987
STAT, 993
Status, 993
SU16, 1021
SUB, 1025
Subroutine Handling, 99
Subtract 16 Bit, 1021
Subtraction, 1025
Support of the ESI Module, 469
lxvii
043505766 4/2006
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Index
T
T.01 Timer, 1049
T-->R, 1037
T-->T, 1043
T0.1 Timer, 1053
T1.0 Timer, 1057
T1MS Timer, 1061
Table to Block, 1067
Table to Register, 1037
Table to Table, 1043
TAN, 64
TAND, 64
TBLK, 1067
TCP/IP Ethernet Statistics
MSTR, 737
TEST, 1073
Test of 2 Values, 1073
Time Delay Queue, 815
Totalizer for Metering Flow, 903
WRIT, 1091
Write, 1091
MSTR, 710
X
XMRD, 1133
XMWT, 1139
XOR, 1145
U
UCTR, 1077
unary operator, 59
unsigned 16-bit variable, 56
unsigned long (32-bit) variable, 56
Up Counter, 1077
V
values and data types
mathematical equation, 55
variable
equation network, 51
variable data
mathematical equation, 56
Velocity Limiter for Changes in the Pv, 841
W
word
maximum in an equation network, 54
words consumed
constant data, 57
mathematical equation, 56
lxviii
043505766 4/2006
This document provided by Barr-Thorp Electric Co., Inc. 800-473-9123
www.barr-thorp.com
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