datasheet for PUMA68S4000X by Apta Group

datasheet for PUMA68S4000X by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
128K x 32 SRAM MODULE
PUMA 68S4000X - 12/15/20/25
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191)
2590997
Description
Issue 1.5 : December 1998
Features
The PUMA68S4000X is a 4Mbit CMOS High Speed
Static RAM organised as 128K x 32 in a JEDEC 68
pin surface mount PLCC, available with access
times of 15ns, 20ns, or 25ns. The output width is user
configurable as 8 , 16 or 32 bits using four Chip
Selects (CS1~4).
The device features low power standby, multiple
ground pins for maximum noise immunity and TTL
compatible inputs and outputs. The PUMA
68S4000X offers a dramatic space saving
advantage over four standard 128Kx8 devices. A low
power standby option with 2V data retention mode is
available.
• JEDEC 68 'J' leaded plastic surface mount Substrate
• Upgradeable footprint.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power
Low Power Standby
-L Version
(32-BIT)
(TTL)
(CMOS)
4.40 W (Max)
1.32 W (Max)
44 mW (Max)
• Fully Static operation.
• Multiple ground pins for maximum noise immunity.
• Single 5V±10% Power supply.
Pin Definition
D16
NC
NC
CS4
CS3
CS2
CS1
NC
VCC
NC
NC
OE
WE
A16
A15
A14
D15
Block Diagram
• Very Fast Access Times of 12/15/20/25 ns.
A0-A16
OE
WE
9
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
D17
D18
D19
VSS
D20
D21
D22
D23
VCC
D24
D25
D26
D27
VSS
D28
D29
D30
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
16
PUMA 68S4000X
17
VIEW
18
55
54
53
52
19
FROM
51
20
ABOVE
50
21
49
22
48
23
47
24
46
25
45
26
44
Pin Functions
Address Inputs
A0 - A16
Data Input/Output
D0 - D31
Chip Select
CS1~4
Write Enable
WE
Output Enable
OE
No Connect
NC
Power (+5V)
VCC
Ground
D31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
D0
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
D14
D13
D12
VSS
D11
D10
D9
D8
VCC
D7
D6
D5
D4
VSS
D3
D2
D1
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to GND
Power Dissipation
Storage Temperature
DC Output Current
VT
-0.3 to +7.0
V
PT
4.0
W
°
TSTG -55 to +125
C
I OUT
80
mA
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Max Terminal Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
min
typ
max
VCC
VTERM
VIH
VIL (1)
TA
TAI
4.5
-0.3
2.2
-0.3
0
-40
5.0
-
5.5
7.0
Vcc+0.3
0.8
70
85
Units
V
V
V
V
°
C
°
C ( Suffix I )
Notes: (1) Pulse width: -3.0V for less than 5ns.
DC Electrical Characteristics (VCC=5V±10%,TA=-40°C to +85°C)
Parameter
Symbol Test Condition
Input Leakage Current
Output Leakage Current
ILI1
ILO
VIN=0V to VCC
VI/O=0V to VCC
min
typ
max
Unit
-20
-40
-
20
40
µA
µA
Operating Supply Current(2) 32 bit ICC32
16 bit ICC16
8 bit ICC8
CS(1)=VIL, II/O=0mA, f=fmax
As above.
As above.
-
-
840
540
400
mA
mA
mA
Standby Supply Current
(TTL) ISB
-L Version (CMOS) ISB1
CS(1)=VIH, f=fmax, VIN=VILor VIH
CS≥VCC-0.2V, 0.2V≥VIN≥VCC-0.2V,f=0
-
-
260
8
mA
mA
2.4
-
0.4
-
V
V
Output Voltage Low
Output Voltage High
VOL
VOH
IOL = 8.0mA,VCC=Min
IOH = -4.0mA,VCC=Min
Notes: (1) CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit
mode.
(2) At f=fmax address and data inputs are cycling at max frequency.
Capacitance (VCC=5V, TA=25°C, F=1Mhz)
Parameter
Input Capacitance Address,OE,WE
Output Capacitance 8-bit mode (worst case)
Symbol
CIN1
CI/O
Test Condition
VIN =0V
VI/O=0V
Note: These parameters are calculated, not measured.
2
min
typ
max
Unit
-
-
34
42
pF
pF
PUMA 68S4000X - 12/15/20/25
ISSUE 1.5 : December 1998
AC Test Conditions
Output Load
*Input pulse levels: 0.0V to 3.0V
I/O Pin
166 Ω
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
1.76V
30pF
*Vcc=5V±10%
*PUMA module is tested in 32 bit mode.
Operation Truth Table
CS1 CS2 CS3 CS4
L
H
H
H
L
H
L
L
H
H
H
L
H
L
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
X
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
X
H
H
H
H
L
H
L
L
H
H
H
L
H
L
L
X
H
OE
WE
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
SUPPLY CURRENT
ICC8
ICC8
ICC8
ICC8
ICC16
ICC16
ICC32
ICC8
ICC8
ICC8
ICC8
ICC16
ICC16
ICC32
ICC32/ICC16/ICC8
ISB,ISB1
MODE
Write D0~7
Write D8~15
Write D16~23
Write D24~31
Write D0~15
Write D16~31
Write D0~31
Read D0~7
Read D8~15
Read D16~23
Read D24~31
Read D0~15
Read D16~31
Read D0~31
D0~31 High-Z
D0~31 Standby
Notes : H = VIH : L =VIL : X = VIH or VIL
Low Vcc Data Retention Characteristics - L version only
Parameter
Symbol
Test Condition
min
typ
max
Unit
VCC for Data Retention
Data Retention Current
Data Retention Time
Operation Recovery Time
VDR
ICCDR1(1)
tCDR
tR
CS=VCC-0.2V
VCC = 2.0V, CS > VCC-0.2V, VIN >0V
2.0
See Retention Waveform
See Retention Waveform
0
tRC
-
2.2
-
V
mA
ns
ns
3
-
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
AC OPERATING CONDITIONS
Read Cycle
Parameter
12
max
min
15
max
min
20
max
min
25
max
Symbol
min
Units
Read Cycle Time
tRC
12
-
15
-
20
-
25
-
ns
Address Access Time
tAA
-
12
-
15
-
20
-
25
ns
Chip Select Access Time
tACS
-
12
-
15
-
20
-
25
ns
Output Enable to Output Valid
tOE
-
7
-
8
-
10
-
13
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Output in Low Z
tCLZ
2
-
2
-
3
-
3
-
ns
Output Enable to Output in Low Z
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Deselection to Output in High Z
tCHZ
0
6
0
8
0
9
0
10
ns
Output Disable to Output in High Z
tOHZ
0
5
0
7
0
8
0
10
ns
Symbol
min
Write Cycle Time
tWC
12
-
15
-
20
-
25
-
ns
Chip Selection to End of Write
tCW
10
-
12
-
15
-
20
-
ns
Address Valid to End of Write
tAW
10
-
12
-
15
-
20
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
tWP
10
-
12
-
15
-
20
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Data to Write Time Overlap
tDW
7
-
9
-
12
-
15
-
ns
Output Active from End of Write
tOW
0
-
0
-
0
-
0
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
0
-
ns
Write to Output High Z
tWHZ
6
-
-
7
-
10
-
12
ns
Write Cycle
Parameter
12
max
4
min
15
max
min
20
max
min
25
max Units
PUMA 68S4000X - 12/15/20/25
ISSUE 1.5 : December 1998
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE
t OH
t OLZ
CS1~4
t ACS
Don't
care.
t OHZ (3)
t CLZ (4,5)
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW
t CW
CS1~4
Don't
Care
WE
t OHZ(3,9)
tOW
t WP(2)
High-Z
Dout
t DW
Din
High-Z
t DH
Data Valid
5
(8)
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
t AS(6)
t CW
t WR(7)
CS1~4
t AW
t WP(2)
WE
tOH
t WHZ(3,9)
t OW
High-Z
Dout
t DW
(8)
(4)
Don't
Care
t DH
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS1~4 and WE low.
(3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes.
(7) CS1~4 or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
t CDR
tR
2.2V
2.2V
V DR
CS1~4
CS1~4 > Vcc -0.2V
0V
6
PUMA 68S4000X - 12/15/20/25
Package Information
ISSUE 1.5 : December 1998
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.40 (1.000)
24.89 (0.980)
1.27
(0.050) Typ.
0.43
(0.017) Typ.
24.13 (0.950)
23.11 (0.910)
5.08 (0.200)
Max.
1.02 (0.040)
Typ.
Ordering Information
PUMA 68S4000XLI - 15
Speed
12
15
20
25
=
=
=
=
12 ns
15 ns
20 ns
25 ns
Temp. range/screening
Blank
I
=
=
Commercial Temperature
Industrial Temperature
Power Consumption
Blank
L
=
=
Standard
Low Power
Pinout Configuration
X
=
Industry Standard Pinout
S4000
=
128K x 32 SRAM
configurable as 256K x
16 and 512K x 8
PUMA 68
=
68 pin "J" Leaded PLCC
Memory Organisation
Package
7
ISSUE 1.5 : December 1998
PUMA 68S4000X - 12/15/20/25
Soldering Recommendations.
Bake.
As specified on product packaging.
If not specified HMP Ltd. recommend a minimum bake of 6 hours duration @ 125OC, if parts have
been exposed to the atmosphere for 24 hours or more.
Soldering.
Must not exceed,
VPR 215 - 219OC, 60 secs.
IR / Convection
Ramp Rate 6OC/sec max.
Temp maintained at 125OC,120 secs max.
Temp exceeding 183OC, 120 - 180 secs.
Time at max. temp. 10 - 40 secs.
Max temp. 220 +5/-0OC
Ramp down -6OC/sec max.
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
8
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