a 200 MHz Clock Generator PLL ADF4001

a 200 MHz Clock Generator PLL ADF4001
a
200 MHz Clock Generator PLL
ADF4001
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
ADF4001
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CP
CHARGE
PUMP
R COUNTER
LATCH
DATA
24-BIT
INPUT REGISTER
22
FUNCTION
LATCH
LE
CPI3 CPI2
SDOUT
CPI1 CPI6 CPI5
CPI4
N COUNTER
LATCH
HIGH Z
AVDD
13
MUXOUT
MUX
RFINA
13-BIT
N COUNTER
RFINB
SDOUT
M3
REV. B
CURRENT
SETTING 2
CURRENT
SETTING 1
LOCK DETECT
CLK
CE
AGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
M2
M1
DGND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© 2013 Analog Devices, Inc. All rights reserved.
ADF4001–SPECIFICATIONS1 (AV
DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =
CPGND = 0 V; RSET = 4.7 k; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)
Parameter
B Version
Unit
RF CHARACTERISTICS (3 V)
RF Input Frequency
RF Input Sensitivity
5/165
–10/0
MHz min/max
dBm min/max
10/200
20/200
MHz min/max
MHz min/max
5/104
MHz min/max
REFIN Input Sensitivity2
–5
dBm min
REFIN Input Capacitance
REFIN Input Current
10
± 100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency3
55
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD – 0.4
0.4
V min
V max
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V
5.5
0.4
1
mA max
mA max
µA typ
4.5 mA typical
TA = 25°C
–161
–153
dBc/Hz typ
dBc/Hz typ
–99
dBc/Hz typ
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCXO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
–90/–95
dBc typ/dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
RF CHARACTERISTICS (5 V)
RF Input Frequency
REFIN CHARACTERISTICS
REFIN Input Frequency
POWER SUPPLIES
AVDD
DVDD
VP
IDD4 (AIDD + DIDD)
ADF4001
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor5
Phase Noise Performance6
200 MHz Output7
Spurious Signals
200 MHz Output7
Test Conditions/Comments
See Figure 3 for Input Circuit
–5/0 dBm min/max
–10/0 dBm min/max
See Figure 2 for Input Circuit
For f < 5 MHz, Use DC-Coupled Square Wave
(0 to VDD)
AC-Coupled. When DC-Coupled:
0 to VDD Max (CMOS Compatible)
Programmable: See Table V
With RSET = 4.7 kΩ
With RSET = 4.7 kΩ
See Table V
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
IOH = 500 µA
IOL = 500 µA
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7
fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
–2–
REV. B
ADF4001
TIMING CHARACTERISTICS (AV
DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V;
RSET = 4.7 k; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)
Parameter
Limit at
TMIN to TMAX
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t3
t4
CLOCK
t1
DATA
DB20
(MSB)
t2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
LFCSP θJA Thermal Impedance (Paddle Soldered) . . 122°C/W
LFCSP θJA Thermal Impedance (Paddle Not Soldered) 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25°C, unless otherwise noted.)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±600 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . 150°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = AGND = DGND = 0 V.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
ADF4001
16 VP
15 DVDD
3
AGND
4
ADF4001
14 MUXOUT
RFINB
5
TOP VIEW
(Not to Scale)
RFINA 6
CPGND
AGND
AGND
RFINB
RFINA
13 LE
12 DATA
11 CLK
10 CE
9
DGND
NOTES
1. TRANSISTOR COUNT 6425 (CMOS)
AND 50 (BIPOLAR).
ADF4001
TOP VIEW
(Not to Scale)
15
14
13
12
11
MUXOUT
LE
DATA
CLK
CE
AVDD 6
7
AVDD
REFIN 8
DGND 9
DGND 10
7
REFIN 8
1
2
3
4
5
NOTES
1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
2. CONNECT EXPOSED PAD TO AGND.
02569-004
CPGND
AVDD
20
19
18
17
16
1
CP 2
02569-003
RSET
CP
RSET
VP
DVDD
DVDD
PIN CONFIGURATIONS
LFCSP
TSSOP
Table 1. Pin Function Descriptions
TSSOP
Pin No.
1
LFCSP
Pin No.
19
Mnemonic
RSET
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship
between ICP and RSET is
I CP MAX 
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
6
7
5
6, 7
RFINA
AVDD
8
8
REFIN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DVDD
16
18
VP
N/A
EP
EPAD
23.5
RSET
So, with RSET = 4.7 kΩ, ICP MAX = 5 mA.
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter which,
in turn, drives the external VCO or VCXO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AVDD must have the
same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DVDD must be the
same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems
where VDD is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
range of up to 5 V.
Exposed Pad. The exposed pad should be connected to AGND.
Rev. B | Page 4
Typical Performance Characteristics–ADF4001
10dB/DIVISION
–40
0
RL = –40dBc/Hz
rms NOISE = 0.229 DEGREES
–50
0.229 rms
–5
PHASE NOISE – dBc/Hz
–60
AMPLITUDE – dBm
–10
–15
TA = +85C
–20
TA = +25C
–25
–70
–80
–90
–100
–110
–120
–30
–130
TA = –40C
–140
100
–35
50
0
100
150
FREQUENCY – MHz
200
250
TPC 1. Input Sensitivity, VDD = 3.3 V, 100 pF on RFIN
1k
10k
100k
FREQUENCY OFFSET FROM 200MHz CARRIER – Hz
TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)
0
0
–10
–5
–20
OUTPUT POWER – dB
AMPLITUDE – dBm
1M
–10
–15
–20
REFERENCE LEVEL =
–5.7dBm
–30
–40
VDD = 3V, VP = 5V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 300Hz
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2 SECONDS
AVERAGES = 20
–50
–60
–70
–92.3dBc
–80
–25
–90
–30
–100
5
0
10
15
FREQUENCY – MHz
20
25
–200kHz
0
OUTPUT POWER – dB
–20
REFERENCE LEVEL =
–5.7dBm
–30
–40
VDD = 3V, VP = 5V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 26
–50
–60
–70
–99.2dBc/Hz
–80
–90
–100
–2kHz
–1kHz
200MHz
1kHz
2kHz
0
TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)
REV. B
200MHz
100kHz
200kHz
0
TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)
TPC 2. Input Sensitivity, VDD = 3.3 V, 100 pF on RFIN
–10
–100kHz
–5–
ADF4001
FROM
N COUNTER LATCH
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
13-BIT N
COUNTER
FROM RF
INPUT STAGE
TO PFD
Figure 4. N Counter
POWER-DOWN
CONTROL
R Counter
NC
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
100k⍀
SW2
REFIN
NC
BUFFER
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
TO
R COUNTER
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that no
dead zone is in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the reference counter
latch, ABP2 and ABP1, control the width of the pulse (see
Table III).
SW1
SW3
NO
Figure 2. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N counter buffer.
VP
HI
1.6V
BIAS
GENERATOR
D1
Q1
CHARGE
PUMP
UP
U1
R DIVIDER
CLR1
AVDD
2k⍀
2k⍀
DELAY
CP
U3
RFINA
RFINB
HI
AGND
N DIVIDER
D2
Q2
DOWN
U2
CLR2
Figure 3. RF Input Stage
CPGND
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
R DIVIDER
N DIVIDER
N and R Relationship
The N counter with the R counter make it possible to generate
output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
fVCO = N R × f REFIN
MUXOUT AND LOCK DETECT
fVCO is the output frequency of the external voltage cotrolled
oscillator (VCO).
The output multiplexer on the ADF4001 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
N is the preset divide ratio of the binary 13-bit counter
(1 to 8,191).
fREFIN is the external reference frequency oscillator.
R is the preset divide ratio of the binary 14-bit programmable
reference counter (1 to 16,383).
–6–
REV. B
ADF4001
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.
DVDD
ANALOG LOCK DETECT
INPUT SHIFT REGISTER
DIGITAL LOCK DETECT
CONTROL
MUX
The ADF4001 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a summary of how the latches are programmed.
MUXOUT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
DGND
Figure 6. MUXOUT Circuit
Table I. C2, C1 Truth Table
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to 0, digital
lock detect is set high when the phase error on three consecutive
phase detector cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
C2
Control Bits
C1
0
0
1
1
Data Latch
0
1
0
1
R Counter
N Counter
Function Latch
Initialization Latch
Table II. ADF4001 Family Latch Summary
LOCK
DETECT
PRECISION
REFERENCE COUNTER LATCH
RESERVED
DB23 DB22
X
X
TEST
MODE
BITS
DB21
DB20
DB19
X
LDP
T2
ANTIBACKLASH
WIDTH
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
T1
ABP2
ABP1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
DB3
DB2
DB1
DB0
R2
R1
C2 (0) C1 (0)
N COUNTER LATCH
RESERVED
CP
GAIN
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
G1
N13
N12
N11
N10
N9
N8
X
X
13-BIT N COUNTER
DB14
N7
DB13
N6
CONTROL
BITS
RESERVED
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
N5
N4
N3
N2
N1
X
X
X
X
X
X
C2 (0) C1 (1)
CONTROL
BITS
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
FUNCTION LATCH
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
CONTROL
BITS
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
DB0
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
INITIALIZATION LATCH
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (1)
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
X = DON’T CARE
REV. B
–7–
MUXOUT
CONTROL
DB0
ADF4001
LOCK
DETECT
PRECISION
Table III. Reference Counter Latch Map
RESERVED
DB23 DB22
X
X
ANTIBACKLASH
WIDTH
TEST
MODE
BITS
DB21
DB20
DB19
X
LDP
T2
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
T1
ABP2
ABP1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
DB3
DB2
DB1
DB0
R2
R1
C2 (0) C1 (0)
X = DON’T CARE
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
0
1
1
0
.
.
.
0
1
0
1
0
.
.
.
0
1
2
3
4
.
.
.
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
2.9ns
1.3ns
6.0ns
2.9ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP
OPERATION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
–8–
REV. B
ADF4001
RESERVED
CP GAIN
Table IV. N Counter Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
G1
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
X
X
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
C2 (0)
C1 (1)
X = DON’T CARE
N13
N12
N11
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
1
1
1
1
1
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
0
0
0
1
1
0
1
1
N3
N2
N1
N COUNTER DIVIDE RATIO
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
0
1
1
0
.
.
.
0
1
0
1
0
.
.
.
0
1
2
3
4
.
.
.
8188
1
..........
1
0
1
8189
1
..........
1
1
0
8190
1
..........
1
1
1
8191
OPERATION
CHARGE PUMP CURRENT SETTING
1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON’T CARE BITS.
REV. B
CONTROL
BITS
RESERVED
13-BIT N COUNTER
–9–
ADF4001
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
Table V. Function Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB0
X = DON’T CARE
F2
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
F3
CHARGE PUMP OUTPUT
0
NORMAL
1
THREE-STATE
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TC4
TC3
TC2
TC1
TIMEOUT
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
CPI6
CPI5
CP14
CPI3
CPI2
CPI1
2.7k
4.7k
10k
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.088
2.176
3.264
4.352
5.44
6.528
7.616
8.704
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
0.294
0.588
0.882
1.176
1.47
1.764
2.058
2.352
F1
0
1
COUNTER
OPERATION
NORMAL
R, N COUNTER
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
AVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ICP (mA)
CE PIN
PD2
PD1
MODE
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
–10–
REV. B
ADF4001
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
Table VI. Initialization Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (1)
X
X
CURRENT
SETTING
1
CURRENT
SETTING
2
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB0
X = DON’T CARE
F2
0
1
REV. B
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
CP14
CPI1
2.7k⍀
4.7k⍀
10k⍀
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.088
2.176
3.264
4.352
5.44
6.528
7.616
8.704
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
0.294
0.588
0.882
1.176
1.47
1.764
2.058
2.352
ICP (mA)
CE PIN
PD2
PD1
MODE
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
THREE-STATE
F5
TC1
CPI5
NORMAL
1
X
0
1
TC2
CPI2
CHARGE PUMP OUTPUT
0
0
1
1
TC3
CPI6
F3
F4
TC4
CPI3
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
–11–
F1
0
1
COUNTER
OPERATION
NORMAL
R, N COUNTER
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
AVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ADF4001
FUNCTION LATCH
Fastlock Mode 1
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming
the function latch.
The charge pump current is switched to the contents of Current
Setting 2.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the A, B counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit needs to be disabled,
and the N counter resumes counting in close alignment with the
R counter. (The maximum error is one prescaler cycle.)
The device enters fastlock by having a 1 written to the CP gain
bit in the N counter latch. The device exits fastlock by having a
0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain bit
in the N counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period determined
by the value in TC4–TC1, the CP gain bit in the N counter latch
is automatically reset to 0 and the device reverts to normal mode
instead of fastlock. See Table V for the timeout periods.
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4001 family provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
Timer Counter Control
In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the
condition that PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into Bit
PD1 (on condition that a 1 has also been loaded to PD2), the
device will go into power-down on the occurrence of the next
charge pump event.
When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated power-down), the
following events occur:
The user has the option of programming two charge pump
currents. The intent is that the Current Setting 1 is used when
the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed). The normal sequence of events is as follows.
The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the function latch. The truth
table is given in Table V.
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
Now, when the user wishes to program a new output frequency,
they can simply program the N counter latch with new value for N.
At the same time, they can set the CP gain bit to a 1, which sets
the charge pump with the value in CPI6–CPI4 for a period of
time determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time, the CP gain bit in the N counter latch is reset to 0 and
is now ready for the next time that the user wishes to change the
frequency.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RFIN input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4001. Table V shows the truth table.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
Fastlock Enable Bit
Charge Pump Currents
DB9 of the function latch is the fastlock enable bit. Only when
this is 1 is fastlock enabled.
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
MUXOUT Control
Fastlock Mode Bit
DB10 of the function latch is the fastlock mode bit. When fastlock
is enabled, this bit determines which fastlock mode is used. If the
fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock
mode bit is 1, fastlock mode 2 is selected.
PD Polarity
This bit sets the PD polarity bit (see Table V).
CP Three-State
This bit sets the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP
output is enabled.
–12–
REV. B
ADF4001
INITIALIZATION LATCH
Counter Reset Method
When C2, C1 = 1, 1, the initialization latch is programmed.
This is essentially the same as the function latch (programmed
when C2, C1 = 1, 0).
Apply VDD.
However, when the initialization latch is programmed, there is
an additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at a load point when
the N counter data is latched, and the device will begin counting
in close phase alignment.
Do an R counter load (00 in 2 LSBs).
If the latch is programmed for synchronous power-down (the CE
pin is high; PD1 bit is high; and PD2 bit is low), the internal
pulse also triggers this power-down. The oscillator input
buffer is unaffected by the internal reset pulse, so close phase
alignment is maintained when counting resumes.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump but does not trigger synchronous
power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply VDD.
Program the initialization latch (11 in 2 LSB of input word). Make
sure that F1 bit is programmed to 0.
Do a function latch load (10 in 2 LSBs). As part of this, load 1
to the F1 bit. This enables the counter reset.
Do an N counter load (01 in 2 LSBs).
Do a function latch load (10 in 2 LSBs). As part of this, load 0
to the F1 bit. This disables the counter reset.
APPLICATION
Extremely Stable, Low Jitter Reference Clock for GSM Base
Station Transmitter
Figure 7 shows the ADF4001 being used with a VCXO to produce an extremely stable, low jitter reference clock for a GSM
base station local oscillator (LO).
13MHz
SYSTEM
CLOCK
1
13MHz
R DIVIDER
CHARGE
PUMP
PFD
Do an R load (00 in 2 LSBs).
CP
LOOP
FILTER
VCXO
1
Do an N load (01 in 2 LSBs).
RFIN
N DIVIDER
When the initialization latch is loaded, the following occurs:
ADF4001
1. The function latch contents are loaded.
2. An internal pulse resets the R, N, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler band gap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.
CE Pin Method
Apply VDD.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the N counter latch (01).
Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
REFIN CP
VCO
RFIN
ADF4110
ADF4111
ADF4112
ADF4113
RFINA
Figure 7. Low Jitter, Stable Clock Source for GSM Base
Station Local Oscillator Circuit
The system reference signal is applied to the circuit at REFIN.
Typical GSM systems would have a very stable OCXO as the
clock source for the entire base station. However, distribution of
this signal around the base station makes it susceptible to
noise and spurious pickup. It is also open to pulling from the
various loads it may need to drive.
The charge pump output of the ADF4001 (Pin 2 of the TSSOP)
drives the loop filter and the 13 MHz VCXO. The VCXO output
is fed back to the RF input of the ADF4001 and also drives the
reference (REFIN) for the LO. A T-circuit configuration provides
50 Ω matching between the VCXO output, the LO REFIN, and
the RFIN terminal of the ADF4001.
CE can be used to power the device up and down to check
for channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it has been programmed at least once after VDD was
initially applied.
REV. B
LOOP
FILTER
–13–
ADF4001
COHERENT CLOCK GENERATION
13MHz SYSTEM
CLOCK FOR GSM
R1
REFIN
When testing A/D converters, it is often advantageous to use a
coherent test system, that is, a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
function. Figure 8 shows how the ADF4001 can be used to handle
all the possible combinations of the input signal frequency and
sampling rate. The first ADF4001 is phase locked to a VCO. The
output of the VCO is also fed into the N divider of the second
ADF4001. This results in both ADF4001s being coherent with
the REFIN. Since the REFIN comes from the signal generator, the
MUXOUT signal of the second ADF4001 is coherent with the fIN
frequency to the ADC. This is used as fS, the sampling clock.
4
CPRF
VCXO
13MHz
LOOP
FILTER
RFIN
1
N1
ADF4001
REFIN
19.44MHz SYSTEM
CLOCK FOR WCDMA
R2
1300
CPRF
52MHz
MASTER
CLOCK
VCXO
19.44MHz
LOOP
FILTER
RFIN
486
N2
ADF4001
fIN
fS = (fIN N1)/(R1 N2)
SINE
OUTPUT
AIN
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
A/D
CONVERTER
UNDER
TEST
65
SAMPLING
CLOCK
REFIN
CPRF
VCXO
19.2MHz
LOOP
FILTER
RFIN
24
N3
fS
ADF4001
R1
ADF4001
19.2MHz SYSTEM
CLOCK FOR CDMA
R3
REFIN
CPRF
N1
N2
LOOP
FILTER
VCO
100MHz
Figure 9. Tri-Band System Clock Generation
RFIN
VP
RFIN
POWER-DOWN CONTROL
NC7S04
MUXOUT
S
ADF4001
VDD
VDD
RFOUT
IN
ADG702
Figure 8. Coherent Clock Generator
D
GND
100pF
TRI-BAND CLOCK GENERATION CIRCUIT
In multiband applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz master clock. The low RF
fMIN specification and the ability to program R and N values as
low as 1 makes the ADF4001 suitable for this. Other fOUT
clock frequencies can be realized using the formula
15
7
16
10
AVDD DVDD VP
CE
CP
FREFIN
RSET
18
VCC
2
LOOP
FILTER
1
10k
100pF 18
VCO
OR
VCXO
18
GND
ADF4001
100pF
RFINA 6
fOUT = REFIN × (N ÷ R)
51
RFINB
5
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic 1 is applied to the IN input.
The low cost switch is available in both SOT-23 and micro
SOIC packages.
CPGND AGND DGND
3
4
9
100pF
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
Figure 10. Local Oscillator Shutdown Circuit
–14–
REV. B
ADF4001
INTERFACING
ADSP-2181 Interface
The ADF4001 family has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control
the data transfer. When LE (latch enable) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of SCLK will be transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
Figure 12 shows the interface between the ADF4001 family and
the ADSP-21xx digital signal processor. The ADF4001 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
autobuffered mode, and then write to the transmit register of
the DSP. This last operation initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 ms. This is certainly more than adequate
for systems with typical lock times in hundreds of microseconds.
ADuC812 Interface
SCLK
DT
TFS
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will
be 166 kHz.
ADF4001
ADuC812
SCLOCK
MOSI
SCLK
SDATA
LE
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
Figure 11. ADuC812 to ADF4001 Family Interface
REV. B
SCLK
SDATA
LE
CE
I/O FLAGS
On first applying power to the ADF4001 family, it needs three
writes (one each to the R counter latch, the N counter latch, and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
ADF4001
ADSP-21xx
Figure 11 shows the interface between the ADF4001 family and
the ADuC812 MicroConverter®. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4001 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
MUXOUT
(LOCK DETECT)
Figure 12. ADSP-21xx to ADF4001 Family Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip package (CP-20) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edge of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
–15–
ADF4001
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 13. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
20
16
15
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
TOP VIEW
0.80
0.75
0.70
0.65
0.60
0.55
5
10
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
08-16-2010-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 14. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4001BRU
ADF4001BRU-REEL
ADF4001BRU-REEL7
ADF4001BRUZ
ADF4001BRUZ-R7
ADF4001BRUZ-RL
ADF4001BCPZ
ADF4001BCPZ-RL
ADF4001BCPZ-RL7
EV-ADF4001SD1Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 16
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
CP-20-6
CP-20-6
CP-20-6
ADF4001
REVISION HISTORY
4/13—Rev. A to Rev. B
Changed RFINA to RFINB from ±320 mV to ±600 mV ................ 3
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
10/03—Rev. 0 to Rev. A
Changes to Specifications ................................................................ 2
Edits to Ordering Guide .................................................................. 3
Changes to Pin Configurations....................................................... 4
Updated Outline Dimensions ....................................................... 16
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02569-0-4/13(B)
Rev. B | Page 17
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