32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3... Simultaneous Read/Write Flash S29JL032H Distinctive Characteristics

32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3... Simultaneous Read/Write Flash S29JL032H Distinctive Characteristics
S29JL032H
32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V
Simultaneous Read/Write Flash
Distinctive Characteristics
Architectural Advantages
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
– 200 nA in standby or automatic sleep mode
 Simultaneous Read/Write Operations
– Data can be continuously read from one bank while executing
erase/program functions in another bank.
– Zero latency between read and write operations
 Multiple Bank Architecture
– Four bank architectures available (refer to Table on page 11).
 Boot Sectors
– Top and bottom boot sectors in the same device
– Any combination of sectors can be erased
 Manufactured on 0.13 µm Process Technology
 Secured Silicon Sector: Extra 256 Byte sector
– Customer lockable: One-time programmable only. Once locked,
data cannot be changed
 Zero Power Operation
– Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
 Compatible with JEDEC standards
– Pinout and software compatible with single-power-supply flash
standard
 Cycling Endurance: 1 million cycles per sector typical
 Data Retention: 20 years typical
Software Features
 Supports Common Flash Memory Interface (CFI)
 Erase Suspend/Erase Resume
– Suspends erase operations to read data from, or program data to,
a sector that is not being erased, then resumes the erase
operation.
 Data# Polling and Toggle Bits
– Provides a software method of detecting the status of program or
erase cycles
 Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple
program command sequences
Hardware Features
 Ready/Busy# Output (RY/BY#)
– Hardware method for detecting program or erase cycle
completion
 Hardware Reset Pin (RESET#)
– Hardware method of resetting the internal state machine to the
read mode
Package options
 48-pin TSOP
Performance Characteristics
 High Performance
– Access time as fast as 60 ns
– Program time: 4 µs/word typical using accelerated programming
function
 Sector Protection
– Hardware method to prevent any program or erase operation
within a sector
– Temporary Sector Unprotect allows changing data in protected
sectors in-system
Th
 Ultra Low Power Consumption (typical values)
– 2 mA active read current at 1 MHz
– 10 mA active read current at 5 MHz
 WP#/ACC Input Pin
– Write protect (WP#) function protects the two outermost boot
sectors regardless of sector protect status
– Acceleration (ACC) function accelerates program timing
General Description
The S29JL032H is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to
be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.
The device is available with an access time of 60, 70, or 90 ns and is offered in a 48-pin TSOP package. Standard control pins—
chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus
contention issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
Cypress Semiconductor Corporation
Document Number: 002-01186 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 08, 2015
S29JL032H
Contents
14.1 CMOS Compatible ........................................................ 38
14.2 Zero-Power Flash ......................................................... 39
1.1
Simultaneous Read/Write Operations with Zero
Latency ......................................................................... 3
S29JL032H Features ..................................................... 3
2.
Product Selector Guide ............................................... 3
16.
Key To Switching Waveforms .................................... 41
3.
3.1
3.2
Block Diagram.............................................................. 4
4 Bank Device................................................................ 4
2 Bank Device................................................................ 5
4.
Connection Diagrams.................................................. 6
5.
Pin Description............................................................. 6
6.
Logic Symbol ............................................................... 7
17.
17.1
17.2
17.3
17.4
17.5
17.6
7.
Ordering Information ................................................... 7
AC Characteristics...................................................... 41
Read-Only Operations .................................................. 41
Hardware Reset (RESET#)........................................... 43
Word/Byte Configuration (BYTE#) ................................ 44
Erase and Program Operations .................................... 45
Temporary Sector Unprotect......................................... 49
Alternate CE# Controlled Erase and Program
Operations ....................................................................50
8.
8.1
8.2
8.3
8.4
18.
Erase and Programming Performance ..................... 51
19.
TSOP Pin Capacitance................................................ 52
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
Device Bus Operations................................................ 8
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................. 10
Simultaneous Read/Write Operations with
Zero Latency ................................................................ 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 11
RESET#: Hardware Reset Pin..................................... 11
Output Disable Mode ................................................... 11
Autoselect Mode .......................................................... 16
Sector/Sector Block Protection and Unprotection........ 17
Write Protect (WP#) ..................................................... 19
Temporary Sector Unprotect........................................ 19
Secured Silicon Sector Flash Memory Region ............ 21
Hardware Data Protection............................................ 22
9.
Common Flash Memory Interface (CFI) ................... 23
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Command Definitions................................................ 26
Reading Array Data ..................................................... 26
Reset Command .......................................................... 26
Autoselect Command Sequence ................................. 26
Enter Secured Silicon Sector/Exit Secured
Silicon Sector Command Sequence ............................ 27
Byte/Word Program Command Sequence................... 27
Chip Erase Command Sequence ................................ 28
Sector Erase Command Sequence ............................. 28
Erase Suspend/Erase Resume Commands ................ 30
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Write Operation Status ..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
DQ3: Sector Erase Timer.............................................
12.
Absolute Maximum Ratings...................................... 37
13.
Operating Ranges ...................................................... 38
14.
DC Characteristics..................................................... 38
Test Conditions ........................................................... 40
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
15.
20. Physical Dimensions .................................................. 53
20.1 TS 048—48-Pin Standard TSOP .................................. 53
21. Revision History.......................................................... 54
21.1 Revision A0 (May 21, 2004).......................................... 54
21.2 Revision A1 (August 5, 2004) ....................................... 54
21.3 Revision A2 (March 10, 2005) ...................................... 54
21.4 Revision B0 (September 21, 2005)............................... 54
21.5 Revision B1 (November 28, 2005)................................ 54
21.6 Revision B2 (March 13, 2006) ...................................... 55
21.7 Revision B3 (May 19, 2006).......................................... 55
21.8 Revision B4 (June 7, 2007)........................................... 55
21.9 Revision B5 (August 10, 2007) ..................................... 55
21.10Revision B6 (March 7, 2008) ........................................ 55
21.11Revision B7 (July 7, 2008)............................................ 55
21.12Revision B8 (August 31, 2009)..................................... 55
Th
1.
Document Number: 002-01186 Rev. *A
32
32
33
34
35
36
36
37
Page 2 of 58
S29JL032H
1.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into separate banks
(see Table on page 11). Sector addresses are fixed, system software can be used to form user-defined bank groups.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
During an Erase/Program operation, any of the non-busy banks may be read from. Note that only two banks can operate
simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations.
The S29JL032H can be organized as both a top and bottom boot sector configuration.
1.1
S29JL032H Features
The Secured Silicon Sector is an extra 256 byte sector capable of being permanently locked by the customer. The Secured Silicon
Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked and is 0 if lockable.
Customers may utilize the Secured Silicon Sector as bonus space, reading and writing like any other flash sector, or may
permanently lock their own code there.
DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous
read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will
perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a
particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be
updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written
software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or
memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead,
the user's software accesses the Flash memory by calling one of only six functions.
The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash command set standard. Commands
are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to
the read mode.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Th
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both modes.
2. Product Selector Guide
Part Number
Speed Option
Standard Voltage Range: VCC = 3.0–3.6 V
S29JL032H
60
Standard Voltage Range: VCC = 2.7–3.6 V
70
90
Max Access Time (ns), tACC
60
70
90
CE# Access (ns), tCE
60
70
90
OE# Access (ns), tOE
25
30
35
Document Number: 002-01186 Rev. *A
Page 3 of 58
S29JL032H
3. Block Diagram
OE#
Mux
BYTE#
Bank 1
Bank 2 Address
Bank 2
X-Decoder
A20–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
Control
Mux
DQ15–DQ0
DQ0–DQ15
Bank 3 Address
Bank 3
X-Decoder
A20–A0
Bank 4 Address
Y-gate
A20–A0
X-Decoder
DQ15–DQ0
RY/BY#
DQ15–DQ0
A20–A0
X-Decoder
DQ15–DQ0
Bank 1 Address
A20–A0
Y-gate
VCC
VSS
4 Bank Device
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
3.1
Bank 4
Th
Mux
Document Number: 002-01186 Rev. *A
Page 4 of 58
S29JL032H
3.2
2 Bank Device
OE# BYTE#
X-Decoder
CE#
BYTE#
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
Control
DQ15–DQ0
Lower Bank Address
Lower Bank
Latches and
Control Logic
A20–A0
Y-Decoder
A20–A0
X-Decoder
DQ15–DQ0
WE#
DQ15–DQ0
A20–A0
RY/BY#
A20–A0
RESET#
Upper Bank
Latches and Control Logic
Upper Bank Address
A20–A0
Y-Decoder
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
VCC
VSS
Th
OE# BYTE#
Document Number: 002-01186 Rev. *A
Page 5 of 58
S29JL032H
4. Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
5. Pin Description
A20–A0
21 Addresses
DQ14–DQ0
15 Data Inputs/Outputs (x16-only devices)
DQ15/A-1
DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode)
CE#
OE#
WE#
Chip Enable
Output Enable
Write Enable
WP#/ACC
Hardware Write Protect/Acceleration Pin
RESET#
Hardware Reset Pin, Active Low
BYTE#
Ready/Busy Output
3.0 volt-only single power supply (see Product Selector Guide on page 3 for
speed options and voltage supply tolerances)
Th
RY/BY#
Selects 8-bit or 16-bit mode
Device Ground
NC
Pin Not Connected Internally
VCC
VSS
Document Number: 002-01186 Rev. *A
Page 6 of 58
S29JL032H
6. Logic Symbol
21
A20–A0
16 or 8
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
RY/BY#
BYTE#
7.
Ordering Information
The order number (Valid Combination) is formed by the following:
S29JL032H
60
T
A
I
00
0
Packing Type
0 = Tray
3 = 13-inch Tape and Reel
Model Number
01 = Top Boot Device, 4 Banks: 4/12/12/4 Mb
02 = Bottom Boot Device, 4 Banks: 4/12/12/4 Mb
21 = Top Boot Device, 2 Banks: 4/28 Mb
22 = Bottom Boot Device, 2 Banks: 4/28 Mb
31 = Top Boot Device, 2 Banks: 8/24 Mb
32 = Bottom Boot Device, 2 Banks: 8/24 Mb
41 = Top Boot Device, 2 Banks: 16/16 Mb
42 = Bottom Boot Device, 2 Banks: 16/16 Mb
Temperature Range
I = Industrial (–40C to +85C)
Th
Package Material Set
A = Standard
F = Pb-free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
Speed Option
60 = 60 ns
70 = 70 ns
90 = 90 ns
Device Family
S29JL032H
3.0 Volt-only, 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) Simultaneous Read/Write Flash Memory
Manufactured on 130 nm process technology
Document Number: 002-01186 Rev. *A
Page 7 of 58
S29JL032H
S29JL032H Valid Combinations
Device Family
Speed Option
Package, Material, Set and
Temperature Range
Model
Number
Packing Type
Package Type
01
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
02
21
60
S29JL032H
70
TAI
22
90
TFI
31
(Note 2)
0
3
TS048
TSOP
(Note 1)
32
41
42
Note
1. Type 0 is standard. Specify others as required; TSOPs can be packed in Types 0 and 3.
2. Operating voltage VCC varies depending on speed option.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local Spansion sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
8.
Device Bus Operations
Th
This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the
commands, along with the address and data information needed to execute the command. The contents of the register serve as
inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus
operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Document Number: 002-01186 Rev. *A
Page 8 of 58
S29JL032H
S29JL032H Device Bus Operations
Operation
Write
OE#
L
L
WE# RESET# WP#/ACC
H
H
L/H
DQ15–DQ8
Addresses
(Note 1)
BYTE# = VIH
BYTE# = VIL
DQ7–DQ0
AIN
DOUT
DQ14–DQ8 = High-Z,
DQ15 = A-1
DOUT
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Read
CE#
L
L
H
(Note 3)
AIN
DIN
X
X
VCC 
0.3 V
L/H
X
High-Z
High-Z
High-Z
L
H
H
H
L/H
X
High-Z
High-Z
High-Z
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
L
H
L
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
X
X
DIN
Sector Unprotect
(Note 2)
L
H
L
VID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
X
X
DIN
Temporary Sector
Unprotect
X
X
X
VID
(Note 3)
AIN
DIN
High-Z
DIN
VCC 
0.3 V
Output Disable
Reset
Standby
Sector Protect
(Note 2)
H
DIN
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 8.5–12.5 V
VHH = 9.0 ± 0.5 V
X = Don’t Care
SA = Sector Address
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector/Sector Block Protection and Unprotection
on page 17.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, protection on the two outermost boot sectors depends on whether they were
last protected or unprotected using the method described in Sector/Sector Block Protection and Unprotection on page 17. If WP#/ACC = VHH, all sectors will be
unprotected.
8.1
Word/Byte Configuration
Th
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic
‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by
CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for read access until the command register contents are altered.
Refer to the Read-Only Operations on page 41 for timing specifications and to Figure 17.1 on page 42 for the timing diagram. ICC1 in
DC Characteristics on page 38 represents the active current specification for reading array data.
Document Number: 002-01186 Rev. *A
Page 9 of 58
S29JL032H
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte
Configuration on page 9 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only
two write cycles are required to program a word or byte, instead of four. Byte/Word Program Command Sequence on page 27 has
details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 12 and Table on page 14 indicate
the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector.
Command Definitions on page 26 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics on page 41
contains timing specification tables and timing diagrams for write operations.
8.3.1
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC
pin. This function is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The
system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than
accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result. See Write Protect (WP#) on page 19 for related information.
8.3.2
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings
apply in this mode. Refer to Autoselect Mode on page 16 and Autoselect Command Sequence on page 26 for more information.
8.4
Simultaneous Read/Write Operations with Zero Latency
Th
This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An
erase operation may also be suspended to read from or program to another location within the same bank (except the sector being
erased). Figure 17.8 on page 47 shows how read and write cycles may be initiated for simultaneous operation with zero latency.
ICC6 and ICC7 in DC Characteristics on page 38 represent the current specifications for read-while-program and read-while-erase,
respectively.
8.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC3 in DC Characteristics on page 38 represents the standby current specification.
Document Number: 002-01186 Rev. *A
Page 10 of 58
S29JL032H
8.6
Automatic Sleep Mode
8.7
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC5 in DC Characteristics on page 38 represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
“1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to AC Characteristics on page 41 for RESET# parameters and to Figure 17.2 on page 43 for the timing diagram.
8.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
S29JL032H Bank Architecture
Device
Model
Number
Bank 2
Bank 3
Bank 4
Megabit
Sector Size
Megabit
Sector Size
Megabit
Sector Size
Megabit
Sector Size
4 Mbit
Eight
8 Kbyte/
4 Kword,
seven
64 Kbyte/
32 Kword
12 Mbit
Twenty-four
64 Kbyte/
32 Kword
12 Mbit
Twenty-four
64 Kbyte/
32 Kword
4 Mbit
Eight 64 Kbyte/
32 Kword
Th
01, 02
Bank 1
Device
Model
Number
Bank 1
Megabits
Sector Size
Megabit
21, 22
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
28 Mbit
31, 32
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Forty-eight
64 Kbyte/32 Kword
41, 42
16 Mbit
Eight 8 Kbyte/4 Kword,
thirty-one 64 Kbyte/32 Kword
16 Mbit
Thirty-two
64 Kbyte/32 Kword
Document Number: 002-01186 Rev. *A
Bank 2
Sector Size
Fifty-six
64 Kbyte/32 Kword
Page 11 of 58
S29JL032H
Th
Bank 3
Bank 2
Bank 2
Bank 2
Bank 4
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
S29JL032H (Model 01)
S29JL032H (Model 21)
S29JL032H (Model 31)
S29JL032H (Model 41)
S29JL032H Sector Addresses - Top Boot Devices (Sheet 1 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
000000xxx
64/32
000000h-00FFFFh
000000h-07FFFh
SA1
000001xxx
64/32
010000h-01FFFFh
008000h-0FFFFh
SA2
000010xxx
64/32
020000h-02FFFFh
010000h-17FFFh
018000h-01FFFFh
SA3
000011xxx
64/32
030000h-03FFFFh
SA4
000100xxx
64/32
040000h-04FFFFh
020000h-027FFFh
SA5
000101xxx
64/32
050000h-05FFFFh
028000h-02FFFFh
SA6
000110xxx
64/32
060000h-06FFFFh
030000h-037FFFh
SA7
000111xxx
64/32
070000h-07FFFFh
038000h-03FFFFh
SA8
001000xxx
64/32
080000h-08FFFFh
040000h-047FFFh
SA9
001001xxx
64/32
090000h-09FFFFh
048000h-04FFFFh
SA10
001010xxx
64/32
0A0000h-0AFFFFh
050000h-057FFFh
058000h-05FFFFh
SA11
001011xxx
64/32
0B0000h-0BFFFFh
SA12
001100xxx
64/32
0C0000h-0CFFFFh
060000h-067FFFh
SA13
001101xxx
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
SA14
001110xxx
64/32
0E0000h-0EFFFFh
070000h-077FFFh
078000h-07FFFFh
SA15
001111xxx
64/32
0F0000h-0FFFFFh
SA16
010000xxx
64/32
100000h-10FFFFh
080000h-087FFFh
SA17
010001xxx
64/32
110000h-11FFFFh
088000h-08FFFFh
SA18
010010xxx
64/32
120000h-12FFFFh
090000h-097FFFh
SA19
010011xxx
64/32
130000h-13FFFFh
098000h-09FFFFh
SA20
010100xxx
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
SA21
010101xxx
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
SA22
010110xxx
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
SA23
010111xxx
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
SA24
011000xxx
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
SA25
011001xxx
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
SA26
011010xxx
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
SA27
011011xxx
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
SA28
011100xxx
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
SA29
011101xxx
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
SA30
011110xxx
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
SA31
011111xxx
64/32
1F0000h-1FFFFFh
0F8000h-0FFFFFh
Document Number: 002-01186 Rev. *A
Page 12 of 58
S29JL032H
Bank 1
Bank 1
Bank 1
Th
Bank 2
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
S29JL032H (Model 01)
S29JL032H (Model 21)
S29JL032H (Model 31)
Bank 1
Bank 2 (cont’d)
Bank 2 (cont’d)
S29JL032H (Model 41)
S29JL032H Sector Addresses - Top Boot Devices (Sheet 2 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA32
100000xxx
64/32
200000h-20FFFFh
100000h-107FFFh
SA33
100001xxx
64/32
210000h-21FFFFh
108000h-10FFFFh
SA34
100010xxx
64/32
220000h-22FFFFh
110000h-117FFFh
SA35
100011xxx
64/32
230000h-23FFFFh
118000h-11FFFFh
SA36
100100xxx
64/32
240000h-24FFFFh
120000h-127FFFh
SA37
100101xxx
64/32
250000h-25FFFFh
128000h-12FFFFh
SA38
100110xxx
64/32
260000h-26FFFFh
130000h-137FFFh
138000h-13FFFFh
SA39
100111xxx
64/32
270000h-27FFFFh
SA40
101000xxx
64/32
280000h-28FFFFh
140000h-147FFFh
SA41
101001xxx
64/32
290000h-29FFFFh
148000h-14FFFFh
SA42
101010xxx
64/32
2A0000h-2AFFFFh
150000h-157FFFh
158000h-15FFFFh
SA43
101011xxx
64/32
2B0000h-2BFFFFh
SA44
101100xxx
64/32
2C0000h-2CFFFFh
160000h-167FFFh
SA45
101101xxx
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
SA46
101110xxx
64/32
2E0000h-2EFFFFh
170000h-177FFFh
SA47
101111xxx
64/32
2F0000h-2FFFFFh
178000h-17FFFFh
SA48
110000xxx
64/32
300000h-30FFFFh
180000h-187FFFh
SA49
110001xxx
64/32
310000h-31FFFFh
188000h-18FFFFh
SA50
110010xxx
64/32
320000h-32FFFFh
190000h-197FFFh
SA51
110011xxx
64/32
330000h-33FFFFh
198000h-19FFFFh
SA52
110100xxx
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
SA53
110101xxx
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
SA54
110110xxx
64/32
360000h-36FFFFh
1B0000h-1BFFFFh
SA55
110111xxx
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
SA56
111000xxx
64/32
380000h-38FFFFh
1C0000h-1C7FFFh
SA57
111001xxx
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
SA58
111010xxx
64/32
3A0000h-3AFFFFh
1D0000h-1DFFFFh
1D8000h-1DFFFFh
SA59
111011xxx
64/32
3B0000h-3BFFFFh
SA60
111100xxx
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
SA61
111101xxx
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
SA62
111110xxx
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
SA63
111111000
8/4
3F0000h-3F1FFFh
1F8000h-1F8FFFh
SA64
111111001
8/4
3F2000h-3F3FFFh
1F9000h-1F9FFFh
SA65
111111010
8/4
3F4000h-3F5FFFh
1FA000h-1FAFFFh
SA66
111111011
8/4
3F6000h-3F7FFFh
1FB000h-1FBFFFh
SA67
111111100
8/4
3F8000h-3F9FFFh
1FC000h-1FCFFFh
SA68
111111101
8/4
3FA000h-3FBFFFh
1FD000h-1FDFFFh
SA69
111111110
8/4
3FC000h-3FDFFFh
1FE000h-1FEFFFh
SA70
111111111
8/4
3FE000h-3FFFFFh
1FF000h-1FFFFFh
Document Number: 002-01186 Rev. *A
Page 13 of 58
S29JL032H
Bank 2
Bank 2
Bank 2
Th
Bank 1
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
S29JL032H (Model 02)
S29JL032H (Model 22)
S29JL032H (Model 32)
Bank 1
Bank 1
Bank 1
S29JL032H (Model 42)
S29JL032H Sector Addresses - Bottom Boot Devices (Sheet 1 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
000000000
8/4
000000h-001FFFh
000000h-000FFFh
SA1
000000001
8/4
002000h-003FFFh
001000h-001FFFh
SA2
000000010
8/4
004000h-005FFFh
002000h-002FFFh
SA3
000000011
8/4
006000h-007FFFh
003000h-003FFFh
SA4
000000100
8/4
008000h-009FFFh
004000h-004FFFh
SA5
000000101
8/4
00A000h-00BFFFh
005000h-005FFFh
SA6
000000110
8/4
00C000h-00DFFFh
006000h-006FFFh
SA7
000000111
8/4
00E000h-00FFFFh
007000h-007FFFh
SA8
000001xxx
64/32
010000h-01FFFFh
008000h-00FFFFh
SA9
000010xxx
64/32
020000h-02FFFFh
010000h-017FFFh
SA10
000011xxx
64/32
030000h-03FFFFh
018000h-01FFFFh
SA11
000100xxx
64/32
040000h-04FFFFh
020000h-027FFFh
SA12
000101xxx
64/32
050000h-05FFFFh
028000h-02FFFFh
SA13
000110xxx
64/32
060000h-06FFFFh
030000h-037FFFh
SA14
000111xxx
64/32
070000h-07FFFFh
038000h-03FFFFh
SA15
001000xxx
64/32
080000h-08FFFFh
040000h-047FFFh
SA16
001001xxx
64/32
090000h-09FFFFh
048000h-04FFFFh
SA17
001010xxx
64/32
0A0000h-0AFFFFh
050000h-057FFFh
SA18
001011xxx
64/32
0B0000h-0BFFFFh
058000h-05FFFFh
SA19
001100xxx
64/32
0C0000h-0CFFFFh
060000h-067FFFh
SA20
001101xxx
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
SA21
001110xxx
64/32
0E0000h-0EFFFFh
070000h-077FFFh
SA22
001111xxx
64/32
0F0000h-0FFFFFh
078000h-07FFFFh
SA23
010000xxx
64/32
100000h-10FFFFh
080000h-087FFFh
SA24
010001xxx
64/32
110000h-11FFFFh
088000h-08FFFFh
SA25
010010xxx
64/32
120000h-12FFFFh
090000h-097FFFh
SA26
010011xxx
64/32
130000h-13FFFFh
098000h-09FFFFh
SA27
010100xxx
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
SA28
010101xxx
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
SA29
010110xxx
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
SA30
010111xxx
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
SA31
011000xxx
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
SA32
011001xxx
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
SA33
011010xxx
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
SA34
011011xxx
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
SA35
011100xxx
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
SA36
011101xxx
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
SA37
011110xxx
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
SA38
011111xxx
64/32
1F0000h-1FFFFFh
0F8000h-0FFFFFh
Document Number: 002-01186 Rev. *A
Page 14 of 58
S29JL032H
Bank 4
Th
Bank 2 (cont’d)
Bank 2 (cont’d)
Bank 2
Bank 3
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
S29JL032H (Model 02)
S29JL032H (Model 22)
S29JL032H (Model 32)
S29JL032H (Model 42)
S29JL032H Sector Addresses - Bottom Boot Devices (Sheet 2 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA39
100000xxx
64/32
200000h-20FFFFh
100000h-107FFFh
SA40
100001xxx
64/32
210000h-21FFFFh
108000h-10FFFFh
SA41
100010xxx
64/32
220000h-22FFFFh
110000h-117FFFh
SA42
100011xxx
64/32
230000h-23FFFFh
118000h-11FFFFh
SA43
100100xxx
64/32
240000h-24FFFFh
120000h-127FFFh
SA44
100101xxx
64/32
250000h-25FFFFh
128000h-12FFFFh
SA45
100110xxx
64/32
260000h-26FFFFh
130000h-137FFFh
138000h-13FFFFh
SA46
100111xxx
64/32
270000h-27FFFFh
SA47
101000xxx
64/32
280000h-28FFFFh
140000h-147FFFh
SA48
101001xxx
64/32
290000h-29FFFFh
148000h-14FFFFh
SA49
101010xxx
64/32
2A0000h-2AFFFFh
150000h-157FFFh
SA50
101011xxx
64/32
2B0000h-2BFFFFh
158000h-15FFFFh
SA51
101100xxx
64/32
2C0000h-2CFFFFh
160000h-167FFFh
SA52
101101xxx
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
SA53
101110xxx
64/32
2E0000h-2EFFFFh
170000h-177FFFh
178000h-17FFFFh
SA54
110111xxx
64/32
2F0000h-2FFFFFh
SA55
111000xxx
64/32
300000h-30FFFFh
180000h-187FFFh
SA56
110001xxx
64/32
310000h-31FFFFh
188000h-18FFFFh
SA57
110010xxx
64/32
320000h-32FFFFh
190000h-197FFFh
SA58
110011xxx
64/32
330000h-33FFFFh
198000h-19FFFFh
SA59
110100xxx
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
SA60
110101xxx
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
SA61
110110xxx
64/32
360000h-36FFFFh
1B0000h-1B7FFFh
SA62
110111xxx
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
SA63
111000xxx
64/32
380000h-38FFFFh
1C0000h-1C7FFFh
SA64
111001xxx
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
SA65
111010xxx
64/32
3A0000h-3AFFFFh
1D0000h-1D7FFFh
SA66
111011xxx
64/32
3B0000h-3BFFFFh
1D8000h-1DFFFFh
SA67
111100xxx
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
SA68
111101xxx
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
SA69
111110xxx
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
SA70
111111xxx
64/32
3F0000h-3F1FFFh
1F8000h-1FFFFFh
Document Number: 002-01186 Rev. *A
Page 15 of 58
S29JL032H
8.9
Autoselect Mode
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in
Table . In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits.
Table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed insystem through the command register, for instances when the S29JL032H is erased or programmed in a system without access to
high voltage on the A9 pin. The command sequence is illustrated in Table on page 31. Note that if a Bank Address (BA) on address
bits A20, A19 and A18 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data
from that bank and then immediately read array data from another bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table on page 31. This method does not require VID. Refer to Autoselect Command Sequence on page 26 for more information.
S29JL032H Autoselect Codes (High Voltage Method)
Description
Device ID
(Models 01, 02)
Manufacturer ID:
Spansion Products
CE#
OE#
WE#
A20
to
A12
L
L
H
BA
A11
to
A10
X
A9
A8
to
A7
VID
X
Read Cycle 1
L
H
BA
X
VID
Device ID
(Models 21, 22)
Device ID
(Models 31, 32)
Device ID
(Models 41, 42)
L
L
L
L
L
H
H
H
BA
BA
BA
X
X
X
VID
VID
VID
X
X
X
L
L
X
X
01h
L
L
H
22h
H
H
L
22h
A1
L
X
L
L
L
H
X
L
L
DQ7
to
DQ0
A2
X
Read Cycle 3
BYTE#
= VIL
A3
L
L
A0
BYTE#
= VIH
A6
L
Read Cycle 2
DQ15 to DQ8
A5
to
A4
L
L
L
X
X
X
7Eh
0Ah
X
H
H
H
H
22h
H
X
X
L
22h
H
H
X
X
X
X
L
L
22h
22h
00h (bottom boot)
01h (top boot)
X
X
X
56h (bottom boot)
55h (top boot)
53h (bottom boot)
50h (top boot)
5Fh (bottom boot)
5Ch (top boot)
L
L
H
SA
X
VID
X
L
X
L
L
H
L
X
X
01h (protected),
00h (unprotected)
Secured Silicon
Indicator Bit (DQ6,
DQ7)
L
L
H
BA
X
VID
X
L
X
L
L
H
H
X
X
42h (customer locked),
82h (not customer
locked) (See Note)
Th
Sector Protection
Verification
Legend
L = Logic Low = VIL
H = Logic High = VIH
BA = Bank Address
SA = Sector Address
X = Don’t care.
Note
Some current and most future Spansion devices (including future revisions of this device) offer an option for programming and permanently locking
the Secured Silicon Sector at the factory. The Secured Silicon Indicator data changes to 82h if factory locked, 42h if customer locked, and 02h (not
82h) if non-factory/customer locked.
Document Number: 002-01186 Rev. *A
Page 16 of 58
S29JL032H
8.10
Sector/Sector Block Protection and Unprotection
Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more
adjacent sectors that are protected or unprotected at the same time (see Table ).
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be
implemented via two methods.
S29JL032H Boot Sector/Sector Block Addresses for
Protection/Unprotection (Top Boot Devices)
Sector
A20-A12
Sector/
Sector Block Size
SA0
000000XXX
64 Kbytes
000001XXX
SA1-SA3
000010XXX
192 (3X64) Kbytes
000011XXX
SA4-SA7
0001XXXXX
256 (4X64) Kbytes
SA8-SA11
0010XXXXX
256 (4X64) Kbytes
SA12-SA15
0011XXXXX
256 (4X64) Kbytes
SA16-SA19
0100XXXXX
256 (4X64) Kbytes
SA20-SA23
0101XXXXX
256 (4X64) Kbytes
SA24-SA27
0110XXXXX
256 (4X64) Kbytes
SA28-SA31
0111XXXXX
256 (4X64) Kbytes
SA32-SA35
1000XXXXX
256 (4X64) Kbytes
SA36-SA39
1001XXXXX
256 (4X64) Kbytes
SA40-SA43
1010XXXXX
256 (4X64) Kbytes
SA44-SA47
1011XXXXX
256 (4X64) Kbytes
SA48-SA51
1100XXXXX
256 (4X64) Kbytes
SA52-SA55
1101XXXXX
256 (4X64) Kbytes
SA56-SA59
1110XXXXX
256 (4X64) Kbytes
111100XXX
SA60-SA62
111101XXX
192 (3X64) Kbytes
111110XXX
111111000
8 Kbytes
SA64
111111001
8 Kbytes
SA65
111111010
8 Kbytes
SA66
111111011
8 Kbytes
Th
SA63
SA67
111111100
8 Kbytes
SA68
111111101
8 Kbytes
SA69
111111110
8 Kbytes
SA70
111111111
8 Kbytes
Document Number: 002-01186 Rev. *A
Page 17 of 58
S29JL032H
S29JL032H Sector/Sector Block Addresses for
Protection/Unprotection (Bottom Boot Devices)
Sector
Sector/
Sector Block Size
111111XXX
64 Kbytes
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
SA70
A20-A12
111110XXX
SA69-SA67
111101XXX
192 (3X64) Kbytes
111100XXX
SA66-SA63
1110XXXXX
256 (4X64) Kbytes
SA62-SA59
1101XXXXX
256 (4X64) Kbytes
SA58-SA55
1100XXXXX
256 (4X64) Kbytes
SA54-SA51
1011XXXXX
256 (4X64) Kbytes
SA50-SA47
1010XXXXX
256 (4X64) Kbytes
SA46-SA43
1001XXXXX
256 (4X64) Kbytes
SA42-SA39
1000XXXXX
256 (4X64) Kbytes
SA38-SA35
0111XXXXX
256 (4X64) Kbytes
SA34-SA31
0110XXXXX
256 (4X64) Kbytes
SA30-SA27
0101XXXXX
256 (4X64) Kbytes
SA26-SA23
0100XXXXX
256 (4X64) Kbytes
SA22-SA19
0011XXXXX
256 (4X64) Kbytes
SA18-SA15
0010XXXXX
256 (4X64) Kbytes
SA14-SA11
0001XXXXX
256 (4X64) Kbytes
SA10-SA8
000010XXX
000011XXX
192 (3X64) Kbytes
000001XXX
SA7
000000111
SA6
000000110
8 Kbytes
8 Kbytes
SA5
000000101
8 Kbytes
SA4
000000100
8 Kbytes
000000011
8 Kbytes
SA2
000000010
8 Kbytes
SA1
000000001
8 Kbytes
SA0
000000000
8 Kbytes
Th
SA3
Sector protect/Sector Unprotect requires VID on the RESET# pin only, and can be implemented either in-system or via programming
equipment. Figure 8.2 on page 20 shows the algorithms and Figure 17.13 on page 50 shows the timing diagram. For sector
unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect
algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in
protected sectors efficiently, the temporary sector unprotect function is available. See Temporary Sector Unprotect on page 49..
The device is shipped with all sectors unprotected. Optional Spansion programming service enable programming and protecting
sectors at the factory prior to shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 16 for details.
Document Number: 002-01186 Rev. *A
Page 18 of 58
S29JL032H
8.11
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of
two provided by the WP#/ACC pin.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 8 Kbyte boot
sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Block
Protection and Unprotection on page 17. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest
addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last
protected or unprotected using the method described in Sector/Sector Block Protection and Unprotection on page 17.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
WP#/ACC Modes
WP# Input Voltage
8.12
Device Mode
VIL
Disables programming and erasing in the two outermost boot sectors
VIH
Enables programming and erasing in the two outermost boot sectors, dependent on whether they were last
protected or unprotected
VHH
Enables accelerated programming (ACC). See Accelerated Program Operation on page 10.
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or
more adjacent sectors that are protected or unprotected at the same time (see Table on page 17 and Table on page 18).)
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Temporary Sector
Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are
protected again. Figure 8.1 shows the algorithm, and Figure 17.12 on page 49 shows the timing diagrams, for this feature. If the
WP#/ACC pin is at VIL, the two outermost boot sectors will remain protected during the Temporary sector Unprotect mode.
Figure 8.1 Temporary Sector Unprotect Operation
Th
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected (If WP#/ACC = VIL, the outermost two boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Document Number: 002-01186 Rev. *A
Page 19 of 58
S29JL032H
Figure 8.2 In-System Sector Protect/Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
RESET# = VID
PLSCNT = 1
Wait 1 ms
Temporary Sector
Unprotect Mode
No
Wait 1 ms
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6=0, A3=0, A2=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
Wait 150 µs
Increment
PLSCNT
Temporary Sector
Unprotect Mode
A6=1, A3=0, A2=0,
A1=1, A0=0
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A3=0,
Reset
PLSCNT = 1
Wait 15 ms
A2=0, A1=1, A0=0
Verify Sector
Unprotect: Write
40h to sector
address with
Read from
sector address with
A6=0, A3=0, A2=0,
A1=1, A0=0
Increment
PLSCNT
No
A6=1, A3=0, A2=0,
A1=1, A0=0
No
PLSCNT
= 25?
Th
Yes
Device failed
Read from
sector address with
Data = 01h?
Yes
No
Yes
Protect another
sector?
No
PLSCNT
= 1000?
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
A6=1, A3=0, A2=0,
A1=1, A0=0
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Document Number: 002-01186 Rev. *A
Page 20 of 58
S29JL032H
8.13
Secured Silicon Sector Flash Memory Region
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic
Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and is shipped unprotected, allowing customers to utilize
that sector in any manner they choose. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has
been customer locked and is 0 if customer lockable. DQ7, alternatively, is set to 0 if the part has been customer locked, and is 1 if
customer-lockable.
Some current and most future Spansion devices (including future revisions of this device) will offer an option for programming and
permanently locking the Secured Silicon Sector at the factory. DQ7 will become the Secured Silicon Factory Indicator bit, and as
such the Secured Silicon Indicator Bit data will change to 82h for factory locked, 42h for customer locked, and 02h (no longer 82h)
for not factory/customer locked.
The system accesses the Secured Silicon through a command sequence (see Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence on page 27). After the system has written the Enter Secured Silicon Sector command sequence, it may
read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues
until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On powerup, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note that the ACC
function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
8.13.1
Factory Locked: Secured Silicon Sector Programmed and Protected At the
Factory
In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon
Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word
random number is at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN is
programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The device is available
preprogrammed with one of the following:
 A random, secure ESN only
 Customer code through Spansion programming services
 Both a random, secure ESN and customer code through Spansion programming services
Contact an your local sales office for details on using Spansion programming services.
8.13.2
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At
the Factory
Th
If the security feature is not required, the Secured Silicon Sector can be treated as an additional Flash memory space. The Secured
Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated
programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector.
The Secured Silicon Sector area can be protected using one of the following procedures:
 Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect
algorithm as shown in Figure 8.2 on page 20, except that RESET# may be at either VIH or VID. This allows in-system protection of
the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
 To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 8.3 on page 22.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command
sequence to return to reading and writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.
Document Number: 002-01186 Rev. *A
Page 21 of 58
S29JL032H
Figure 8.3 Secured Silicon Sector Protect Verify
START
Wait 1 ms
Write 60h to
any address
Write 40h to Secure
Silicon Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from Secure
Silicon Sector address
with A6 = 0,
A1 = 1, A0 = 0
8.14
If data = 00h,
Secure Silicon Sector
is unprotected.
If data = 01h,
Secure Silicon Sector
is protected.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
RESET# =
VIH or VID
Remove VIH or VID
from RESET#
Write reset
command
Secure Silicon Sector
Protect Verify
complete
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table on page 31 for command definitions). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
8.14.1
Low VCC Write Inhibit
Th
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
8.14.2
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.14.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
8.14.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
Document Number: 002-01186 Rev. *A
Page 22 of 58
S29JL032H
9. Common Flash Memory Interface (CFI)
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or
address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table . To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible
when the device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query
mode, and the system can read CFI data at the addresses given in Table . The system must write the reset command to reading
array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of
these documents.
CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Description
System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Th
1Bh
1Ch
Data
Description
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0003h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
0009h
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Document Number: 002-01186 Rev. *A
Page 23 of 58
S29JL032H
Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Th
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Description
Document Number: 002-01186 Rev. *A
Page 24 of 58
S29JL032H
Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
88h
0033h
Minor version number, ASCII (reflects modifications to the CFI table)
45h
8Ah
000Ch
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Description
Silicon Revision Number (Bits 7-2)
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode
Number of sectors (excluding Bank 1)
4Ah
94h
00XXh
XX = 38 (models 01, 02, 21, 22)
XX = 30 (models 31, 32)
XX = 20 (models 41, 42)
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
0085h
4Eh
9Ch
0095h
4Fh
9Eh
000Xh
50h
A0h
0001h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
Program Suspend
0 = Not supported, 1 = Supported
Th
Bank Organization
57h
AEh
000Xh
00 = Data at 4Ah is zero
X = 4 (4 banks, models 01, 02)
X = 2 (2 banks, all other models)
Bank 1 Region Information - Number of sectors on Bank 1
58h
B0h
00XXh
XX = 0F (models 01, 02, 21, 22)
XX = 17 (models 31, 32)
XX = 27 (models 41, 42)
Bank 2 Region Information - Number of sectors in Bank 2
XX = 18 (models 01, 02)
59h
B2h
00XXh
XX = 38 (models 21, 22)
XX = 30 (models 31, 32)
XX = 20 (models 41, 42)
Bank 3 Region Information - Number of sectors in Bank 3
5Ah
B4h
00XXh
XX = 18 (models 01, 02)
XX = 00 (all other models)
Bank 4 Region Information - Number of sectors in Bank 4
5Bh
B6h
00XXh
XX = 08 (models 01, 02)
XX = 00 (all other models)
Document Number: 002-01186 Rev. *A
Page 25 of 58
S29JL032H
10. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 31
defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence
may place the device in an unknown state. A hardware reset may be required to return the device to reading array data.
10.1
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to AC Characteristics on page 41 for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank
is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which
the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the
standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After
completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 30 for more information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an
active program or erase operation, or if the bank is in the autoselect mode. See Reset Command on page 26, for more information.
See also Requirements for Reading Array Data on page 9 for more information. Read-Only Operations on page 41 provides the
read parameters, and Figure 17.1 on page 42 shows the timing diagram.
10.2
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming
begins, however, the device ignores reset commands until the operation is complete.
Th
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erasesuspend-read mode if that bank was in Erase Suspend).
10.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or
not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in
another bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains
the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of
autoselect codes without reinitiating the command sequence.
Table on page 31 shows the address and data requirements. To determine sector protection information, the system must write to
the appropriate bank address (BA) and sector address (SA). Table on page 12 and Table on page 14 show the address range and
bank number associated with each sector.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in
Erase Suspend).
Document Number: 002-01186 Rev. *A
Page 26 of 58
S29JL032H
10.4
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
10.5
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.
Table on page 31 shows the address and data requirements for both command sequences. See also Secured Silicon Sector
Flash Memory Region on page 21 for further information. Note that the ACC function and unlock bypass modes are not available
when the Secured Silicon Sector is enabled.
Byte/Word Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The device automatically provides internally generated program pulses and
verifies the programmed cell margin. Table on page 31 shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched.
The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to Write Operation Status
on page 32 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read
mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program
operation is in progress.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.”
Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was
successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
10.5.1
Unlock Bypass Command Sequence
Th
The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command
sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program
command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same
manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Table on page 31 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (Table on page 31).
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin,
the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC
pin must not be at VHH for any operation other than accelerated programming, or device damage may result. In addition, the WP#/
ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Figure 10.1 illustrates the algorithm for the program operation. Refer to Erase and Program Operations on page 45 for parameters,
and Figure 17.5 on page 46 for timing diagrams.
Document Number: 002-01186 Rev. *A
Page 27 of 58
S29JL032H
Figure 10.1 Program Operation
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note
See Table on page 31 for program command sequence.
10.6
Chip Erase Command Sequence
Th
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table on page 31 shows the address and data requirements for
the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The
system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status
on page 32 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an
erase operation is in progress.
Figure 10.2 on page 29 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for
parameters, and Figure 17.7 on page 47 for timing diagrams.
Document Number: 002-01186 Rev. *A
Page 28 of 58
S29JL032H
10.7
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table on page 31 shows the address and data requirements for the sector erase command sequence.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and
verifies the entire sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs,
otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase
Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.).
The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge) in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note
that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can
determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation
Status on page 32 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured Silicon Sector,
autoselect, and CFI functions are unavailable when an erase operation is in progress.
Th
Figure 10.2 on page 29 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 45 for
parameters, and Figure 17.7 on page 47 for timing diagrams.
Document Number: 002-01186 Rev. *A
Page 29 of 58
S29JL032H
Figure 10.2 Erase Operation
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table on page 31 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
10.8
Erase Suspend/Erase Resume Commands
Th
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only
during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The bank address must
contain one of the sectors currently selected for erase.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to
suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or
program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any
address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status on page 32 for
information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation.
Refer to Write Operation Status on page 32 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading
autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device
exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to
Autoselect Mode on page 16 and Autoselect Command Sequence on page 26 for details.
Document Number: 002-01186 Rev. *A
Page 30 of 58
S29JL032H
To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erasesuspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
Cycles
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
S29JL032H Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First
Second
Addr
Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Word
Manufacturer ID
555
4
Autoselect (Note 8)
Byte
Word
Secured Silicon Sector
Factory Protect (Note 10) Byte
Sector/Sector Block
Protect Verify (Note 11)
Word
Enter Secured Silicon Sector
Region
Word
Exit Secured Silicon Sector
Region
Word
Word
Program
Word
Unlock Bypass
2AA
2
XXX
A0
PA
PD
XXX
90
XXX
00
555
6
Word
Th
Sector Erase
2AA
AA
AAA
Erase Suspend (Note 14)
1
BA
B0
Erase Resume (Note 15)
1
BA
30
Word
CFI Query (Note 16)
PD
555
80
555
10
AAA
2AA
AA
AAA
555
55
555
555
80
AAA
2AA
AA
AAA
55
SA
30
555
55
1
Byte
PA
555
55
555
A0
AAA
2AA
AA
AAA
00
20
55
555
555
6
Byte
XXX
AAA
2
Word
90
555
55
555
Unlock Bypass Reset (Note 13)
Byte
00/01
AAA
Unlock Bypass Program (Note 12)
Chip Erase
(SA)X02
(SA)X04
555
55
AA
See
Table
555
555
AAA
(BA)X0F
(BA)X1E
AAA
2AA
555
3
Byte
(BA)X1C
88
55
AA
See
Table
555
555
555
See
Table
Data
AAA
2AA
AAA
(BA)X0E
Addr
82/02
90
55
AA
4
Byte
(BA)555
555
AAA
Data
(BA)X06
(BA)AAA
2AA
555
4
Byte
Sixth
Addr
(BA)X03
90
55
AA
AAA
(BA)X01
(BA)X02
(BA)555
555
555
3
Byte
01
(BA)AAA
2AA
AA
(BA)X00
90
55
555
AAA
90
(BA)AAA
2AA
555
4
Byte
Data
(BA)555
55
AA
AAA
Fifth
Addr
(BA)555
555
555
4
Fourth
Data
(BA)AAA
2AA
AA
AAA
Addr
55
555
555
6
Byte
Data
2AA
AA
AAA
Word
Device ID (Note 9)
Addr
Third
98
AA
Legend
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector.
Refer to Table on page 12 and Table on page 14 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A20–A18 uniquely select a bank.
Document Number: 002-01186 Rev. *A
Page 31 of 58
S29JL032H
Notes
1. See Table on page 9 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
5. Unless otherwise noted, address bits A20–A11 are don’t cares for unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect
mode, or if DQ5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or Secured
Silicon Sector factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the same until a
reset command is given. See Autoselect Command Sequence on page 26 for more information.
9. For models 01, 02, the device ID must be read across the fourth, fifth, and sixth cycles.
10. The data is 42h for customer locked, and 82h for not customer locked. Some current and most future Spansion devices (including future revisions of this device) will
offer an option for programming and permanently locking the Secured Silicon Sector at the factory. The Secured Silicon Indicator data will change to 82h for factory
locked, 42h for customer locked, and 02h (no longer 82h) for not factory/customer locked.
11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid
only during a sector erase operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table
on page 37 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining
whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/
BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.
11.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or
completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command
sequence.
Th
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or
if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at
an address within a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 (or DQ7–DQ0
for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-only device) while Output Enable (OE#) is asserted low. That is, the
device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
Document Number: 002-01186 Rev. *A
Page 32 of 58
S29JL032H
data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on
successive read cycles.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Table on page 37 shows the outputs for Data# Polling on DQ7. Figure 11.1 on page 33 shows the Data# Polling algorithm.
Figure 17.9 on page 48 shows the Data# Polling timing diagram.
Figure 11.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
Th
No
FAIL
PASS
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
11.2
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read
mode.
Table on page 37 shows the outputs for RY/BY#.
Document Number: 002-01186 Rev. *A
Page 33 of 58
S29JL032H
11.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The
system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 32).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to reading array data.
Th
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Document Number: 002-01186 Rev. *A
Page 34 of 58
S29JL032H
Figure 11.2 Toggle Bit Algorithm
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
No
Th
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note
The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
11.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use
either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table
on page 37 to compare outputs for DQ2 and DQ6.
Figure 11.2 on page 35 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 35 explains the algorithm.
See also DQ6: Toggle Bit I on page 34. Figure 17.10 on page 48 shows the toggle bit timing diagram. Figure 17.11 on page 49
shows the differences between DQ2 and DQ6 in graphical form.
Document Number: 002-01186 Rev. *A
Page 35 of 58
S29JL032H
11.5
Reading Toggle Bits DQ6/DQ2
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Refer to Figure 11.2 on page 35 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully,
and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 11.2 on page 35).
11.6
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only
an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Th
Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suspend-program mode).
Document Number: 002-01186 Rev. *A
Page 36 of 58
S29JL032H
11.7
DQ3: Sector Erase Timer
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than 80 µs, the system need not
monitor DQ3. See also Sector Erase Command Sequence on page 28.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure
that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun;
all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept
additional sector erase commands. To ensure the command has been accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command
might not have been accepted.
Table shows the status of DQ3 relative to the other status bits.
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Status
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-SuspendRead
Erase-Suspend-Program
Notes
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more
information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array
data if the system addresses a non-busy bank.
12. Absolute Maximum Ratings
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
Voltage with Respect to Ground, VCC (Note 1)
–0.5 V to +4.0 V
Th
Storage Temperature, Plastic Packages
–0.5 V to +12.5 V
A9, OE#, and RESET# (Note 2)
WP#/ACC
–0.5 V to +9.5 V
All other pins (Note 1)
–0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3)
200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC
voltage on input or I/O pins is VCC +0.5 V. See Figure 12.1 on page 37. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20
ns. See Figure 12.2 on page 38.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to –
2.0 V for periods of up to 20 ns. See Figure 12.1 on page 37. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns.
Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Figure 12.1 Maximum Negative Overshoot Waveform
Document Number: 002-01186 Rev. *A
Page 37 of 58
S29JL032H
20 ns
20 ns
+0.8 V
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
–0.5 V
–2.0 V
20 ns
Figure 12.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
13. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
–40°C to +85°C
VCC Supply Voltages
VCC for standard voltage range 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Th
14. DC Characteristics
14.1
Parameter
Symbol
CMOS Compatible
Parameter Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, OE# and RESET# Input Load Current
VCC = VCC max, OE# = VIH; A9 or
OE# or RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max, OE# = VIH
ILR
Reset Leakage Current
VCC = VCC max; RESET# = 12.5 V
ICC1
ICC2
VCC Active Read Current
(Notes 1, 2)
VCC Active Write Current (Notes 2, 3)
Document Number: 002-01186 Rev. *A
Typ
10
Max
Unit
1.0
µA
35
µA
1.0
µA
35
µA
CE# = VIL, OE# = VIH,
Byte Mode
5 MHz
16
1 MHz
2
4
CE# = VIL, OE# = VIH,
Word Mode
5 MHz
10
16
mA
1 MHz
2
4
CE# = VIL, OE# = VIH, WE# = VIL
15
30
mA
Page 38 of 58
S29JL032H
Parameter
Symbol
Parameter Description
Typ
Max
Unit
CE#, RESET# = VCC 0.3 V
0.2
10
µA
VCC Reset Current (Note 2)
RESET# = VSS 0.3 V
0.2
10
µA
Automatic Sleep Mode (Notes 2, 4)
VIH = VCC  0.3 V;
VIL = VSS 0.3 V
0.2
10
µA
VCC Active Read-While-Program Current
(Notes 1, 2)
Byte
21
45
CE# = VIL, OE# = VIH
Word
21
45
VCC Active Read-While-Erase Current
(Notes 1, 2)
Byte
21
45
CE# = VIL, OE# = VIH
Word
21
45
VCC Active Program-While-EraseSuspended Current (Notes 2, 5)
CE# = VIL, OE# = VIH
17
35
VCC Standby Current (Note 2)
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
VIH
VHH
VID
VOL
VOH1
VOH2
VLKO
Test Conditions
Min
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
ICC3
mA
mA
mA
Input Low Voltage
–0.5
0.8
V
Input High Voltage
0.7 x VCC
VCC + 0.3
V
Voltage for WP#/ACC Sector Protect/
Unprotect and Program Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
Voltage for Autoselect and Temporary Sector
Unprotect
VCC = 3.0 V  10%
8.5
12.5
V
Output Low Voltage
IOL = 2.0 mA, VCC = VCC min
Output High Voltage
0.45
IOH = –2.0 mA, VCC = VCC min
0.85 x VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage (Note 5)
1.8
V
V
2.0
2.3
V
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.
5. Not 100% tested.
14.2
Zero-Power Flash
Figure 14.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
Supply Current in mA
Th
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz
Document Number: 002-01186 Rev. *A
Page 39 of 58
S29JL032H
Figure 14.2 Typical ICC1 vs. Frequency
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
12
3.6 V
10
2.7 V
Supply Current in mA
8
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note
T = 25 °C
15. Test Conditions
Th
Figure 15.1 Test Setup
3.3 V
2.7 k
Device
Under
Test
CL
6.2 k
Note
Diodes are IN3064 or equivalent.
Document Number: 002-01186 Rev. *A
Page 40 of 58
S29JL032H
Test Specifications
Test Condition
60
70, 90
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
30
Input Rise and Fall Times
Input Pulse Levels
5
ns
0.0 or Vcc
V
Input timing measurement reference levels
0.5 Vcc
V
Output timing measurement reference levels
0.5 Vcc
V
16. Key To Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 16.1 Input Waveforms and Measurement Levels
Vcc
Input
0.5 Vcc
0.5 Vcc
Measurement Level
Output
0.0 V
Th
17. AC Characteristics
17.1
Read-Only Operations
Parameter
JEDEC
tAVAV
tAVQV
Std.
tRC
Speed Options
Description
Test Setup
Read Cycle Time (Note 1)
tACC
Address to Output Delay
CE#,
OE# = VIL
OE# = VIL
60
70
90
Unit
Min
60
70
90
ns
Max
60
70
90
ns
tELQV
tCE
Chip Enable to Output Delay
Max
60
70
90
ns
tGLQV
tOE
Output Enable to Output Delay
Max
25
30
35
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold Time
(Note 1)
Toggle and
Data# Polling
Min
tAXQX
Document Number: 002-01186 Rev. *A
5
10
ns
Page 41 of 58
S29JL032H
Notes
1. Not 100% tested.
2. See Figure 15.1 on page 40 and Table on page 41 for test specifications
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF.
Figure 17.1 Read Operation Timings
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
0V
Th
RY/BY#
Document Number: 002-01186 Rev. *A
Page 42 of 58
S29JL032H
17.2
Hardware Reset (RESET#)
Parameter
Std
Description
tReady
RESET# Pin Low (During Embedded Algorithms) to Read Mode
(See Note)
tReady
RESET# Pin Low (NOT During Embedded Algorithms) to Read
Mode (See Note)
All Speed Options
Unit
Max
20
µs
Max
500
ns
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
JEDEC
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note
Not 100% tested.
Figure 17.2 Reset Timings
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
Th
CE#, OE#
RESET#
Document Number: 002-01186 Rev. *A
tRP
Page 43 of 58
S29JL032H
17.3
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Std.
Description
60
CE# to BYTE# Switching Low or High
Max
70
90
5
Unit
ns
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
tELFL/tELFH
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
tFHQV
BYTE# Switching High to Output Active
Max
16
60
70
ns
90
ns
Figure 17.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
BYTE#
Switching
from word
to byte
mode
Data Output
(DQ7–DQ0)
Data Output
(DQ14–DQ0)
DQ14–DQ0
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
Th
BYTE#
Switching
from byte to
word mode
DQ14–DQ0
DQ15/A-1
Data Output
(DQ7–DQ0)
Address
Input
Data Output
(DQ14–DQ0)
DQ15
Output
tFHQV
Document Number: 002-01186 Rev. *A
Page 44 of 58
S29JL032H
Figure 17.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note
Refer to the Erase/Program Operations table for tAS and tAH specifications.
17.4
Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAS
Address Setup Time
Min
tASO
Address Setup Time to OE# low during toggle bit polling
Min
tAH
Address Hold Time
Min
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
tDS
Data Setup Time
Min
tDH
tAVWL
tWLAX
tDVWH
tWHDX
tGHWL
tELWL
tWHEH
tWLWH
tWHDL
Description
60
70
90
60
70
90
0
40
ns
45
0
35
40
ns
ns
12
35
Unit
ns
ns
45
ns
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
ns
tCS
CE# Setup Time
Min
0
tCH
CE# Hold Time
Min
0
tWP
Write Pulse Width
Min
25
30
35
ns
tWPH
Write Pulse Width High
Min
25
30
30
ns
tSR/W
Latency Between Read and Write Operations
Min
0
Byte
Typ
4
Word
Typ
6
ns
ns
tWHWH1
Programming Operation (Note 2)
tWHWH1
tWHWH1
Accelerated Programming Operation,
Byte or Word (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Th
tWHWH1
µs
Sector Erase Operation (Note 2)
Typ
0.4
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
90
ns
tBUSY
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 51 for more information.
Document Number: 002-01186 Rev. *A
Page 45 of 58
S29JL032H
Figure 17.5 Program Operation Timings
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.6 Accelerated Program Timing Diagram
VHH
Th
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
Document Number: 002-01186 Rev. *A
tVHH
Page 46 of 58
S29JL032H
Figure 17.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
VA
SA
VA
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Addresses
Read Status Data
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 32.
2. These waveforms are for the word mode.
Figure 17.8 Back-to-back Read/Write Cycle Timings
Addresses
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
Th
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tWPH
tDF
tDS
tOH
tDH
Data
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Document Number: 002-01186 Rev. *A
Read Cycle
CE# or CE2# Controlled Write Cycles
Page 47 of 58
S29JL032H
Figure 17.9 Data# Polling Timings (During Embedded Algorithms)
Addresses
VA
VA
VA
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
tACC
tCE
CE#
tCH
tOE
OE
tOEH
WE#
tOH
DQ7
DQ0–DQ6
Complement
Compleme
Status
Status
Valid Data
Tru
Valid Data
Tru
High Z
High Z
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 17.10 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
Th
tOEPH
OE#
tDH
DQ6/DQ2
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Document Number: 002-01186 Rev. *A
Page 48 of 58
S29JL032H
Figure 17.11 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
WE#
Enter Erase
Suspend Program
DQ6
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
17.5
Temporary Sector Unprotect
Parameter
JEDEC
All Speed Options
Unit
tVIDR
Std
VID Rise and Fall Time (See Note)
Description
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRSP
RESET# Setup Time for Temporary Sector Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for Temporary
Sector Unprotect
Min
4
µs
Note
Not 100% tested.
Figure 17.12 Temporary Sector Unprotect Timing Diagram
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Th
Program or Erase Command Sequence
CE#
WE#
tRSP
tRRB
RY/BY#
Document Number: 002-01186 Rev. *A
Page 49 of 58
S29JL032H
Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram
VID
VIH
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Group Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE#
WE#
OE#
Note
*For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0
17.6
Alternate CE# Controlled Erase and Program Operations
Parameter
JEDEC
tAVAV
tAVWL
tELAX
tDVEH
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
Description
60
70
90
Unit
60
70
90
ns
tWC
Write Cycle Time (Note 1)
Min
tAS
Address Setup Time
Min
tAH
Address Hold Time
Min
35
40
45
tDS
Data Setup Time
Min
35
40
45
tDH
Data Hold Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
ns
Th
tEHDX
Speed Options
Std.
tGHEL
0
ns
ns
ns
tWS
WE# Setup Time
Min
0
tWH
WE# Hold Time
Min
0
tCP
CE# Pulse Width
Min
25
30
35
ns
tCPH
CE# Pulse Width High
Min
25
30
30
ns
Byte
Typ
4
Word
Typ
6
ns
tWHWH1
tWHWH1
Programming Operation
(Note 2)
tWHWH1
tWHWH1
Accelerated Programming Operation,
Byte or Word (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
µs
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 51 for more information.
Document Number: 002-01186 Rev. *A
Page 50 of 58
S29JL032H
Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data# Polling
Addresses
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Chip Erase Time
28
Excludes 00h programming
prior to erasure (Note 4)
Byte Program Time
4
80
µs
Th
18. Erase and Programming Performance
Parameter
Word Program Time
6
100
µs
Accelerated Byte/Word Program Time
4
70
µs
Byte Mode
12.6
50
Word Mode
12.0
35
10
30
Chip Program Time
(Note 3)
Accelerated Mode
sec
Excludes system level
overhead (Note 5)
sec
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 31 for further information on
command definitions.
6. The device has a minimum cycling endurance of 100,000 cycles per sector.
Document Number: 002-01186 Rev. *A
Page 51 of 58
S29JL032H
19. TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
Input Capacitance
VIN = 0
TSOP
6
7.5
pF
Output Capacitance
VOUT = 0
TSOP
8.5
12
pF
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
CIN
COUT
CIN2
Control Pin Capacitance
VIN = 0
TSOP
7.5
9
pF
Notes
1. Sampled, not 100% tested.
Th
2. Test conditions TA = 25°C, f = 1.0 MHz.
Document Number: 002-01186 Rev. *A
Page 52 of 58
S29JL032H
20. Physical Dimensions
20.1
TS 048—48-Pin Standard TSOP
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
2
0.10
0.10
1
A2
N
SEE DETAIL B
A
REVERSE PIN OUT (TOP VIEW)
3
B
1
N
E 5
N
+1
2
N
2
D1
0.25
9
A1
4
D
2X (N/2 TIPS)
e
5
C
SEATING
PLANE
B
A
B
N
+1
2
N
2
SEE DETAIL A
0.08MM
(0.0031")
b
M
C A-B S
6
7
WITH PLATING
7
(c)
c1
b1
SECTION B-B
BASE METAL
R
(c)
e/2
GAUGE PLANE
θ°
PARALLEL TO
SEATING PLANE
Th
TS/TSR 048
Jedec
MO-142 (D) DD
MIN
NOM
MAX
1.20
0.15
0.05
0.95
1.00
1.05
0.20
0.23
0.17
0.22
0.17
0.27
0.10
0.16
0.10
0.21
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
0.50 BASIC
0.50
0.70
0.60
0˚
8˚
0.08
0.20
48
X
L
DETAIL A
Package
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
0.25MM (0.0098") BSC
C
X = A OR B
DETAIL B
NOTES:
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16-038.10c
Document Number: 002-01186 Rev. *A
Page 53 of 58
S29JL032H
21. Revision History
Spansion Publication Number: S29JL032H_00
Revision A0 (May 21, 2004)
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
21.1
Initial release.
21.2
Revision A1 (August 5, 2004)
Secured Silicon Sector Flash Memory Region
Reworded how the Secured Silicon Sector area can be protected.
Removed Secured Silicon Sector Protect Verify flowchart.
CMOS Compatible
Updated Output Low Voltage.
Erase and Programming Performance
Updated Word and Byte Mode for the Chip Program Time.
21.3
Revision A2 (March 10, 2005)
Deleted 55 ns speed option
Changed operating voltage (VCC) range for 60ns option
Changed standby current (ICC3, ICC4, ICC5)
Deleted Secured Silicon sector protection functionality with RESET#=VIH method
21.4
Revision B0 (September 21, 2005)
Changed data sheet status from Advance to Preliminary.
21.5
Revision B1 (November 28, 2005)
Th
Removed text or changed text in the following sections.
Distinctive Characteristics
Eliminated sub-bullet under the Secured Silicon Sector information bullet.
General Description
Eliminated text in the S29JL032H Features section.
Device Bus Operations
Added Note and made changes to the S29JL032H Autoselect Codes table.
Eliminated text from the Secured Silicon Sector Flash Memory Region section.
Command Definitions
Modified a note in the S29JL032H Command Definitions table.
DC Characteristics
Modified VOL Parameters.
Document Number: 002-01186 Rev. *A
Page 54 of 58
S29JL032H
21.6
Revision B2 (March 13, 2006)
Erase and Programming Performance
21.7
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Changed chip program time for byte and word modes.
Revision B3 (May 19, 2006)
Changed document status from Preliminary to Full Production.
21.8
Revision B4 (June 7, 2007)
Removed the 7 inch Tape and Reel Packing Type option.
21.9
Revision B5 (August 10, 2007)
DC Characteristics
Changed VLKO minimum, typical, and maximum values.
21.10 Revision B6 (March 7, 2008)
Erase and Programming Performance
Changed the maximum sector erase time from 2 seconds to 5 seconds.
Global
Corrected minor typos
21.11 Revision B7 (July 7, 2008)
Word/Byte Configuration (BYTE#)
Changed tFHQV condition from Min. to Max.
21.12 Revision B8 (August 31, 2009)
Th
Secured Silicon Sector Flash Memory Region
Modified Section
Section Added
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected
At the Factory
In-System Sector Protect/Unprotect Algorithms
Updated table
Document Number: 002-01186 Rev. *A
Page 55 of 58
S29JL032H
Document History Page
Document Title:S29JL032H 32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V, Simultaneous Read/Write Flash
Document Number: 002-01186
Orig. of
Change
Submission
Date
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Rev.
ECN No.
Description of Change
05/21/2004 A0:Initial release
08/05/2004 A1:Secured Silicon Sector Flash Memory Region
Reworded how the Secured Silicon Sector area can be protected.
Removed Secured Silicon Sector Protect Verify flowchart.
CMOS Compatible
Updated Output Low Voltage.
Erase and Programming Performance
Updated Word and Byte Mode for the Chip Program Time.
03/10/2005 A2:Deleted 55 ns speed option
Changed operating voltage (VCC) range for 60ns option
Changed standby current (ICC3, ICC4, ICC5)
Deleted Secured Silicon sector protection functionality with RESET#=VIH
method
**
-
RYSU
09/21/2005 B0:Changed data sheet status from Advance to Preliminary.
11/28/2005
Th
**
-
RYSU
B1:Removed text or changed text in the following sections.
Distinctive Characteristics
Eliminated sub-bullet under the Secured Silicon Sector information bullet.
General Description
Eliminated text in the S29JL032H Features section.
Device Bus Operations
Added Note and made changes to the S29JL032H Autoselect Codes table.
Eliminated text from the Secured Silicon Sector Flash Memory Region
section.
Command Definitions
Modified a note in the S29JL032H Command Definitions table.
DC Characteristics
Modified VOL Parameters.
03/13/2006 B2:Erase and Programming Performance
Changed chip program time for byte and word modes.
05/19/2006 B3:Changed document status from Preliminary to Full Production.
06/07/2007 B4:Removed the 7 inch Tape and Reel Packing Type option.
08/10/2007 B5:DC Characteristics
Changed VLKO minimum, typical, and maximum values.
03/07/2008 B6:Erase and Programming Performance
Changed the maximum sector erase time from 2 seconds to 5 seconds.
Global
Corrected minor typos
07/07/2008 B7:Word/Byte Configuration (BYTE#)
Changed tFHQV condition from Min. to Max.
Document Number: 002-01186 Rev. *A
Page 56 of 58
S29JL032H
Document History Page (Continued)
Document Title:S29JL032H 32 Mbit (4 M x 8-Bit/2 M x 16-Bit), 3 V, Simultaneous Read/Write Flash
Document Number: 002-01186
**
Orig. of
Change
Submission
Date
Description of Change
-
RYSU
5038884
RYSU
08/31/2009 B8:Secured Silicon Sector Flash Memory Region
Modified Section
Section Added
Factory Locked: Secured Silicon Sector Programmed and Protected At the
Factory
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected
At the Factory
In-System Sector Protect/Unprotect Algorithms
Updated table
12/08/2015 Updated to cypress template.
Th
*A
ECN No.
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Rev.
Document Number: 002-01186 Rev. *A
Page 57 of 58
S29JL032H
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers ................................ cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface......................................... cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control............ cypress.com/go/powerpsoc
Community | Forums | Blogs | Video | Training
da es
ta e
sh pa
ee rts
ti a
s re
av o
ai bs
la o
bl le
e te
fo d
r r an
ef d
er th
en e
ce
.
Products
Memory........................................... cypress.com/go/memory
PSoC ....................................................cypress.com/go/psoc
Touch Sensing .................................... cypress.com/go/touch
Technical Support
cypress.com/go/support
USB Controllers....................................cypress.com/go/USB
Th
Wireless/RF .................................... cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01186 Rev. *A
®
®
®
®
Revised December 08, 2015
Page 58 of 58
Cypress , Spansion , MirrorBit , MirrorBit Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement