1 TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor

1  TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor

TMS320C6671

SPRS756E—November 2010—Revised March 2014

Fixed and Floating-Point Digital Signal Processor

Check for Evaluation Modules (EVM): TMS320C6678

1 TMS320C6671 Features and Description

1.1 Features

• One TMS320C66x™ DSP Core Subsystem (C66x

CorePac), with

– 1.0 GHz or 1.25 GHz C66x Fixed/Floating-Point CPU

Core

› 40 GMAC/Core for Fixed Point @ 1.25 GHz

› 20 GFLOP/Core for Floating Point @ 1.25 GHz

– Memory

› 32K Byte L1P

› 32K Byte L1D

› 512K Byte Local L2

• Multicore Shared Memory Controller (MSMC)

– 4096KB MSM SRAM

– Memory Protection Unit for Both MSM SRAM and

DDR3_EMIF

• Multicore Navigator

– 8192 Multipurpose Hardware Queues with Queue

Manager

– Packet-Based DMA for Zero-Overhead Transfers

• Network Coprocessor

– Packet Accelerator Enables Support for

› Transport Plane IPsec, GTP-U, SCTP, PDCP

› L2 User Plane PDCP (RoHC, Air Ciphering)

› 1-Gbps Wire-Speed Throughput at 1.5 MPackets

Per Second

– Security Accelerator Engine Enables Support for

› IPSec, SRTP, 3GPP, WiMAX Air Interface, and

SSL/TLS Security

› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,

GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,

SHA-2 (256-bit Hash), MD5

› Up to 2.8 Gbps Encryption Speed

• Peripherals

– Four Lanes of SRIO 2.1

› 1.24/2.5/3.125/5 GBaud Operation Supported Per

Lane

› Supports Direct I/O, Message Passing

› Supports Four 1×, Two 2×, One 4×, and Two 1× +

One 2× Link Configurations

– PCIe Gen2

› Single Port Supporting 1 or 2 Lanes

› Supports Up To 5 GBaud Per Lane

– HyperLink

› Supports Connections to Other KeyStone

Architecture Devices Providing Resource

Scalability

› Supports up to 50 Gbaud

– Gigabit Ethernet (GbE) Switch Subsystem

› Two SGMII Ports

› Supports 10/100/1000 Mbps Operation

– 64-Bit DDR3 Interface (DDR3-1600)

› 8G Byte Addressable Memory Space

– 16-Bit EMIF

– Two Telecom Serial Ports (TSIP)

› Supports 1024 DS0s Per TSIP

› Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps

Per Lane

– UART Interface

– I

2

C Interface

– 16 GPIO Pins

– SPI Interface

– Semaphore Module

– Nine 64-Bit Timers

– Three On-Chip PLLs

• Commercial Temperature:

– 0°C to 85°C

• Extended Temperature:

– -40°C to 100°C

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

1.2 Applications

• Mission-Critical Systems

• High-Performance Computing Systems

• Communications

• Audio

• Video Infrastructure

• Imaging

• Analytics

• Networking

• Media Processing

• Industrial Automation

• Automation and Process Control

1.3 KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and

HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with

Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

1.4 Device Description

The TMS320C6671 DSP is a highest-performance fixed/floating-point single-core DSP that is based on TI's

KeyStone multicore architecture. It is pin-for-pin compatible with the TMS320C6678 / 6674 / 6672 multicore high-performance DSPs. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission-critical systems, medical imaging, test and automation, and other applications requiring high performance, TI's TMS320C6671 DSP offers a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family fixed and floating point DSPs.

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

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TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per-core raw computational performance in an industry-leading 40 GMACS/core and 20 GFLOPS/core (@1.25 GHz operating frequency). It can execute 8 single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations, and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions.

The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6671 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 512KB of dedicated memory that can be configured as mapped RAM or cache. The device also integrates

4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.

This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and

Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I

2

C, UART, Telecom Serial Interface Port

(TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding to the network awareness of this device is a network co-processor that includes both packet and optional security acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for the entire C6671 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities.

The C6671 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

1.5 Functional Block Diagram

Figure 1-1

shows the functional block diagram of the TMS320C6671 device.

Figure 1-1 Functional Block Diagram

Memory Subsystem

64-Bit

DDR3 EMIF

4MB

MSM

SRAM

MSMC

Debug & Trace

Boot ROM

Semaphore

Power

Management

PLL

´

3

EDMA

´

3

HyperLink

C66x

CorePac

32KB L1

P-Cache

32KB L1

D-Cache

512KB L2 Cache

@ up to 1.25 GHz

6671

Multicore Navigator

Queue

Manager

Packet

DMA

Security

Accelerator

Packet

Accelerator

Network Coprocessor

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

1.6 Release History

Revision Date

SPRS756E March 2014

SPRS756D April 2013

SPRS756C February 2012

SPRS756B August 2011

SPRS756A July 2011

SPRS756 November 2010

Description/Comments

• Added DSP_SUSP_CTL register section

• Updated Core Before IO Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N

• Updated the Trace timing diagram

• Updated Parameter Table Index bit field in I

2

C boot configuration

• Updated PKTDMA_PRI_ALLOC register to be CHIP_MSIC_CTL register with new bit field added.

• Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section

• Updated Chip Select field description in SPI boot device configuration table

• Corrections applied to EMIF16 Boot Device Configuration Bit Fields

• Restored Parameter Information section

• Added Initial Startup row for CVDD in Recommended Operating Conditions table

• Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table

• Added CVDD and SmartReflex voltage parameter in SmartReflex switching table

• Added HOUT timing diagram in Host Interrupt Output section

• Added MPU Registers Reset Values section

• Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns

• Corrected Reserved to be Assert local reset to all CorePacs in LRESET and NMI decoding table

• Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet.

• Updated the Timer numbering across the whole document

• Updated DDR3 PLL initialization sequence

• Added TeraNet connection figures and added bridge numbers to the connection tables

• Changed TPCC to EDMA3CC and TPTC to EDMA3TC

• Changed chip level interrupt controller name from INTC to CIC

• Added the DDR3 PLL and PASS PLL Initialization Sequence

• Added DEVSPEED Register section

• Updated device frequency in the feature section

• Corrected the SPI, DDR3, and Hyperbridge config/data memory map addresses

• Restricted Output Divide of SECCTL Register to max value of divide by 2

• Updated the timing and electrical sections of several peripherals

• Updated the core-specific and general-purpose timer numbers

• Updated the connection matrix tables in chapter 4 “System Interconnection”

• Updated device boot configuration tables and figures

• Updated DDR3 and PASS PLL timing figures

• Removed section 7.1 “Parameter Information”

• Added sections: NMI and LRSET

• Added Pin Map diagrams

• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers

• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL

• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns

• Corrected items in the Memory Map Summary table

• Changed all occurrences of PA_SS to Network Coprocessor

• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR

Initial release

For detailed revision information, see ‘‘Revision History’’ on page 236.

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

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TMS320C6671

SPRS756E—November 2010—Revised March 2014

Contents

1 TMS320C6671 Features and Description . . . . . . . . . . . . .1

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.3

KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.4

Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.5

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.6

Release History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2

DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3

Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4

Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5

Boot Modes Supported and PLL Settings . . . . . . . . . . . . 24

2.5.1

Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.5.2

Device Configuration Field . . . . . . . . . . . . . . . . . . . . 26

2.5.3

Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.4

PLL Boot Configuration Settings . . . . . . . . . . . . . . . 38

2.6

Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.7

Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.7.1

Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.7.2

Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.8

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.9

Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.9.1

Development Support . . . . . . . . . . . . . . . . . . . . . . . . 70

2.9.2

Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.10

Related Documentation from Texas Instruments . . . 72

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.1

Device Configuration at Device Reset . . . . . . . . . . . . . . . 73

3.2

Peripheral Selection After Device Reset. . . . . . . . . . . . . . 74

3.3

Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . 74

3.3.1

Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . 78

3.3.2

Device Configuration Register (DEVCFG) . . . . . . . 79

3.3.3

JTAG ID Register (JTAGID) Description . . . . . . . . . 79

3.3.4

Kicker Mechanism Register (KICK0 and KICK1). . 80

3.3.5

DSP Boot Address Register

(DSP_BOOT_ADDRn) . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.3.6

LRESETNMI PIN Status Register

(LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.3.7

LRESETNMI PIN Status Clear Register

(LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . 81

3.3.8

Reset Status Register (RESET_STAT) . . . . . . . . . . . . 82

3.3.9

Reset Status Clear Register

(RESET_STAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.3.10

Boot Complete Register (BOOTCOMPLETE) . . . 83

3.3.11

Power State Control Register

(PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.3.12

NMI Event Generation to CorePac Register

(NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.3.13

IPC Generation Registers (IPCGRx) . . . . . . . . . . . . 84

3.3.14

IPC Acknowledgement Registers (IPCARx) . . . . 86

3.3.15

IPC Generation Host Register (IPCGRH) . . . . . . . 86

3.3.16

IPC Acknowledgement Host Register

(IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.3.17

Timer Input Selection Register (TINPSEL) . . . . . 88

3.3.18

Timer Output Selection Register

(TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.3.19

Reset Mux Register (RSTMUXx) . . . . . . . . . . . . . . . 90

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3.3.20

DSP Suspension Control Register

(DSP_SUSP_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

3.3.21

Device Speed Register (DEVSPEED) . . . . . . . . . . . 93

3.3.22

Chip Miscellaneous Control Register

(CHIP_MISC_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

3.4

Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4 System Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.1

Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . 95

4.2

Switch Fabric Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.3

Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5 C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

5.1

Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.1.1

L1P Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.1.2

L1D Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

5.1.3

L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

5.1.4

MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

5.1.5

L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

5.2

Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

5.3

Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . .111

5.4

Power-Down Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

5.5

C66x CorePac Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

5.6

C66x CorePac Register Descriptions. . . . . . . . . . . . . . . . .112

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . .113

6.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .113

6.2

Recommended Operating Conditions . . . . . . . . . . . . . .114

6.3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

6.4

Power Supply to Peripheral I/O Mapping. . . . . . . . . . . .116

7 Peripheral Information and

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.1

Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.1.1

Timing Parameters and Board Routing

Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.1.2

1.8-V LVCMOS Signal Transition Levels . . . . . . . .117

7.2

Recommended Clock and Control Signal

Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.3

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

7.3.1

Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . .119

7.3.2

Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . .124

7.3.3

Power Supply Decoupling and

Bulk Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.3.4

SmartReflex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

7.4

Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . .126

7.4.1

Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7.4.2

Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

7.4.3

PSC Register Memory Map . . . . . . . . . . . . . . . . . . . .128

7.5

Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

7.5.1

Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

7.5.2

Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

7.5.3

Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

7.5.4

Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

7.5.5

Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

7.5.6

Reset Controller Register. . . . . . . . . . . . . . . . . . . . . .134

7.5.7

Reset Electrical Data / Timing . . . . . . . . . . . . . . . . .135

7.6

Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . .137

7.6.1

Main PLL Controller Device-Specific

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

7.6.2

PLL Controller Memory Map . . . . . . . . . . . . . . . . . .140

Contents 7

TMS320C6671

SPRS756E—November 2010—Revised March 2014

7.6.3

Main PLL Control Register . . . . . . . . . . . . . . . . . . . . 147

7.6.4

Main PLL and PLL Controller Initialization

Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

7.6.5

Main PLL Controller/SRIO/HyperLink/PCIe

Clock Input Electrical Data/Timing . . . . . . . . . . . 148

7.7

DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.7.1

DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . 150

7.7.2

DDR3 PLL Device-Specific Information . . . . . . . . 151

7.7.3

DDR3 PLL Initialization Sequence. . . . . . . . . . . . . 151

7.7.4

DDR3 PLL Input Clock Electrical Data/Timing. . 152

7.8

PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.8.1

PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . 153

7.8.2

PASS PLL Device-Specific Information . . . . . . . . 154

7.8.3

PASS PLL Initialization Sequence . . . . . . . . . . . . . 154

7.8.4

PASS PLL Input Clock Electrical Data/Timing . . 155

7.9

Enhanced Direct Memory Access (EDMA3)

Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.9.1

EDMA3 Device-Specific Information . . . . . . . . . . 157

7.9.2

EDMA3 Channel Controller Configuration . . . . 157

7.9.3

EDMA3 Transfer Controller Configuration. . . . . 157

7.9.4

EDMA3 Channel Synchronization Events. . . . . . 158

7.10

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.10.1

Interrupt Sources and Interrupt Controller . . . 162

7.10.2

CIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.10.3

Inter-Processor Register Map. . . . . . . . . . . . . . . . 181

7.10.4

NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.10.5

External Interrupts Electrical Data/Timing . . . 183

7.10.6

Host Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . 183

7.11

Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . 184

7.11.1

MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.11.2

MPU Programmable Range Registers . . . . . . . . 192

7.12

DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.12.1

DDR3 Memory Controller Device-Specific

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.12.2

DDR3 Memory Controller Race Condition

Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.12.3

DDR3 Memory Controller Electrical

Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

7.13

I

2

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

7.13.1

I

2

C Device-Specific Information . . . . . . . . . . . . . .199

7.13.2

I

2

C Peripheral Register Description(s) . . . . . . . .200

7.13.3

I

2

C Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .201

7.14

SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

7.14.1

SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .204

7.15

HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

7.15.1

HyperLink Device-Specific Interrupt Event. . . .207

7.15.2

HyperLink Electrical Data/Timing . . . . . . . . . . . .209

7.16

UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

7.17

PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

7.18

TSIP Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

7.18.1

TSIP Electrical Data/Timing . . . . . . . . . . . . . . . . . .213

7.19

EMIF16 Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

7.19.1

EMIF16 Electrical Data/Timing . . . . . . . . . . . . . . .215

7.20

Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

7.21

Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

7.22

Gigabit Ethernet (GbE) Switch Subsystem. . . . . . . . . .218

7.23

Management Data Input/Output (MDIO) . . . . . . . . . .220

7.24

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

7.24.1

Timers Device-Specific Information . . . . . . . . . .221

7.24.2

Timers Electrical Data/Timing . . . . . . . . . . . . . . . .222

7.25

Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . .222

7.26

General-Purpose Input/Output (GPIO) . . . . . . . . . . . . .223

7.26.1

GPIO Device-Specific Information . . . . . . . . . . . .223

7.26.2

GPIO Electrical Data/Timing. . . . . . . . . . . . . . . . . .223

7.27

Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

7.28

Emulation Features and Capability . . . . . . . . . . . . . . . .224

7.28.1

Advanced Event Triggering (AET) . . . . . . . . . . . .224

7.28.2

Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

7.28.3

IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

9.1

Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

9.2

Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

8 Contents Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

TMS320C6671

SPRS756E—November 2010—Revised March 2014

List of Figures

Figure 1-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . .4

Figure 2-1 DSP Core Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2-2 Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2-3 No Boot/ EMIF16 Configuration Fields. . . . . . . . . . 26

Figure 2-4 Serial Rapid I/O Device Configuration Fields . . . . 26

Figure 2-5 Ethernet (SGMII) Device Configuration Fields . . . 27

Figure 2-6 PCI Device Configuration Fields. . . . . . . . . . . . . . . . 27

Figure 2-7 I

2

C Master Mode Device Configuration

Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 2-8 I

2

C Passive Mode Device Configuration

Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 2-9 SPI Device Configuration Bit Fields . . . . . . . . . . . . . 29

Figure 2-10 HyperLink Boot Device Configuration Fields. . . . 30

Figure 2-11 CYP 841-Pin BGA Package (Bottom View). . . . . . . 39

Figure 2-12 Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . 39

Figure 2-13 Upper Left Quadrant—A (Bottom View) . . . . . . . . 40

Figure 2-14 Upper Right Quadrant—B (Bottom View) . . . . . . 41

Figure 2-15 Lower Right Quadrant—C (Bottom View) . . . . . . 42

Figure 2-16 Lower Left Quadrant—D (Bottom View). . . . . . . . 43

Figure 2-17 C66x DSP Device Nomenclature (including the TMS320C6671) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 3-1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 3-2 Device Configuration Register (DEVCFG) . . . . . . . 79

Figure 3-3 JTAG ID Register (JTAGID) . . . . . . . . . . . . . . . . . . . . . 79

Figure 3-4 DSP BOOT Address Register

(DSP_BOOT_ADDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 3-5 LRESETNMI PIN Status Register

(LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 3-6 LRESETNMI PIN Status Clear Register

(LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 3-7 Reset Status Register (RESET_STAT) . . . . . . . . . . . . 82

Figure 3-8 Reset Status Clear Register (RESET_STAT_CLR). . 82

Figure 3-9 Boot Complete Register (BOOTCOMPLETE) . . . . . 83

Figure 3-10 Power State Control Register (PWRSTATECTL) . . 83

Figure 3-11 NMI Generation Register (NMIGRx). . . . . . . . . . . . . 84

Figure 3-12 IPC Generation (IPCGRx) Registers . . . . . . . . . . . . . 85

Figure 3-13 IPC Acknowledgement (IPCARx) Registers. . . . . . 86

Figure 3-14 IPC Generation (IPCGRH) Registers . . . . . . . . . . . . . 86

Figure 3-15 IPC Acknowledgement Register (IPCARH) . . . . . . 87

Figure 3-16 Timer Input Selection Register (TINPSEL) . . . . . . . 88

Figure 3-17 Timer Output Selection Register (TOUTPSEL) . . . 90

Figure 3-18 Reset Mux Register (RSTMUXx). . . . . . . . . . . . . . . . . 90

Figure 3-19 DSP Suspension Control Register

(DSP_SUSP_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 3-20 Device Speed Register (DEVSPEED) . . . . . . . . . . . . 93

Figure 3-21 Chip Miscellaneous Control Register

(CHIP_MISC_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 4-1 TeraNet 2A for C6671. . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 4-2 TeraNet 3A for C6671. . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 4-3 TeraNet 3P_A & B for C6671 . . . . . . . . . . . . . . . . . . . 99

Figure 4-4 TeraNet 6P_B and 3P_Tracer for C6671. . . . . . . . 100

Figure 5-1 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . 105

Figure 5-2 L1P Memory Configurations . . . . . . . . . . . . . . . . . . 106

Copyright 2014 Texas Instruments Incorporated

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Figure 5-3

Figure 5-4

L1D Memory Configurations . . . . . . . . . . . . . . . . . .107

L2 Memory Configurations . . . . . . . . . . . . . . . . . . . .108

Figure 5-5

Figure 7-1

CorePac Revision ID Register (MM_REVID)

Address - 0181 2000h . . . . . . . . . . . . . . . . . . . . . . . . .112

Input and Output Voltage Reference Levels for AC Timing Measurements. . . . . . . . . . . . . . . . . .117

Figure 7-2 Rise and Fall Transition Time Voltage

Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Figure 7-3 Core Before IO Power Sequencing . . . . . . . . . . . .120

Figure 7-4 IO Before Core Power Sequencing . . . . . . . . . . . .122

Figure 7-5 SmartReflex 4-Pin VID Interface Timing . . . . . . . .125

Figure 7-6 RESETFULL Reset Timing . . . . . . . . . . . . . . . . . . . . . .135

Figure 7-7

Figure 7-8

Soft/Hard-Reset Timing . . . . . . . . . . . . . . . . . . . . . . .135

Boot Configuration Timing . . . . . . . . . . . . . . . . . . . .136

Figure 7-9 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . .137

Figure 7-10 PLL Secondary Control Register (SECCTL)) . . . . .141

Figure 7-11 PLL Controller Divider Register (PLLDIVn) . . . . . .142

Figure 7-12 PLL Controller Clock Align Control

Register (ALNCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-13 PLLDIV Divider Ratio Change Status

Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 7-14 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . .143

Figure 7-15 Reset Type Status Register (RSTYPE) . . . . . . . . . . .144

Figure 7-16 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . .145

Figure 7-17 Reset Configuration Register (RSTCFG). . . . . . . . .145

Figure 7-18 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . .146

Figure 7-19 Main PLL Control Register 0 (MAINPLLCTL0) . . .147

Figure 7-20 Main PLL Control Register 1 (MAINPLLCTL1) . . .147

Figure 7-21 Main PLL Controller/SRIO/HyperLink/PCIe

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Figure 7-22 Main PLL Clock Input Transition Time . . . . . . . . .149

Figure 7-23 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . .150

Figure 7-24 DDR3 PLL Control Register 0 (DDR3PLLCTL0). . .150

Figure 7-25 DDR3 PLL Control Register 1 (DDR3PLLCTL1). . .151

Figure 7-26 DDR3 PLL DDRCLK Timing. . . . . . . . . . . . . . . . . . . . .152

Figure 7-27 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . .153

Figure 7-28 PASS PLL Control Register 0 (PASSPLLCTL0) . . . .153

Figure 7-29 PASS PLL Control Register 1 (PASSPLLCTL1) . . . .154

Figure 7-30 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Figure 7-31 TMS320C6671 Interrupt Topology . . . . . . . . . . . . .163

Figure 7-32 TMS320C6671 System Event Inputs —

C66x CorePac Primary Interrupts . . . . . . . . . . . . . .163

Figure 7-33 NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . .183

Figure 7-34 HOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Figure 7-35 Configuration Register (CONFIG) . . . . . . . . . . . . . .191

Figure 7-36 Programmable Range n Start Address

Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . .192

Figure 7-37 Programmable Range n End Address

Register (PROGn_MPEAR) . . . . . . . . . . . . . . . . . . . . .192

Figure 7-38 Programmable Range n Memory Protection

Page Attribute Register (PROGn_MPPA) . . . . . . .193

Figure 7-39 I

2

C Module Block Diagram. . . . . . . . . . . . . . . . . . . . .200

Figure 7-40 I

2

C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 7-41 I

2

C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . .203

List of Figures 9

TMS320C6671

SPRS756E—November 2010—Revised March 2014

Figure 7-42 SPI Master Mode Timing Diagrams —

Base Timings for 3 Pin Mode . . . . . . . . . . . . . . . . . . 206

Figure 7-43 SPI Additional Timings for 4 Pin Master

Mode with Chip Select Option . . . . . . . . . . . . . . . . 206

Figure 7-44 HyperLink Station Management Clock

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 7-45 HyperLink Station Management Transmit

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 7-46 HyperLink Station Management Receive

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 7-47 UART Receive Timing Waveform . . . . . . . . . . . . . . 211

Figure 7-48 UART CTS (Clear-to-Send Input) —

Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . 211

Figure 7-49 UART Transmit Timing Waveform . . . . . . . . . . . . . 212

Figure 7-50 UART RTS (Request-to-Send Output) —

Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . 212

Figure 7-51 TSIP 2x Timing Diagram

(1)

. . . . . . . . . . . . . . . . . . . . 213

Figure 7-52 TSIP 1x Timing Diagram

(1)

. . . . . . . . . . . . . . . . . . . . .214

Figure 7-53 EMIF16 Asynchronous Memory Read

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Figure 7-54 EMIF16 Asynchronous Memory Write

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Figure 7-55 EMIF16 EM_WAIT Read Timing Diagram . . . . . . .217

Figure 7-56 EMIF16 EM_WAIT Write Timing Diagram . . . . . . .217

Figure 7-57 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Figure 7-58 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Figure 7-59 CPTS_RFTCLK_SEL Register. . . . . . . . . . . . . . . . . . . .219

Figure 7-60 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Figure 7-61 MDIO Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . .220

Figure 7-62 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Figure 7-63 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Figure 7-64 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Figure 7-65 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . .227

10 List of Figures Copyright 2014 Texas Instruments Incorporated

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TMS320C6671

SPRS756E—November 2010—Revised March 2014

List of Tables

Table 2-1

Table 2-2

Table 2-3

Table 2-4

Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . 17

Bootloader section in L2 SRAM . . . . . . . . . . . . . . . . 23

Boot Mode Pins: Boot Device Values . . . . . . . . . . . 25

Table 2-5

Table 2-6

Table 2-7

Table 2-8

Extended Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . 25

No Boot / EMIF16 Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Rapid I/O Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Ethernet (SGMII) Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2-9 PCI Device Configuration Field Descriptions . . . . 27

Table 2-10 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . 28

Table 2-11 I

2

C Master Mode Device Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 2-12 I

2

C Passive Mode Device Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 2-13 SPI Device Configuration Field Descriptions . . . . 29

Table 2-14 HyperLink Boot Device Configuration

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 2-15 Boot Parameter Table Common Parameters . . . . 31

Table 2-16 EMIF16 Boot Mode Parameter Table . . . . . . . . . . . 31

Table 2-17 SRIO Boot Mode Parameter Table . . . . . . . . . . . . . . 32

Table 2-18 Ethernet Boot Mode Parameter Table . . . . . . . . . . 32

Table 2-19 PCIe Boot Mode Parameter Table . . . . . . . . . . . . . . 34

Table 2-20 I

2

C Boot Mode Parameter Table. . . . . . . . . . . . . . . . 34

Table 2-21 SPI Boot Mode Parameter Table. . . . . . . . . . . . . . . . 35

Table 2-22 HyperLink Boot Mode Parameter Table . . . . . . . . 36

Table 2-23 DDR3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . 37

Table 2-24 C66x DSP System PLL Configuration . . . . . . . . . . . 38

Table 2-25 I/O Functional Symbol Definitions . . . . . . . . . . . . . 44

Table 2-26 Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 2-27 Terminal Functions — Power and Ground. . . . . . 57

Table 2-28 Terminal Functions — By Signal Name . . . . . . . . . 58

Table 2-29 Terminal Functions — By Ball Number . . . . . . . . . 63

Table 3-1 TMS320C6671 Device Configuration Pins . . . . . . 73

Table 3-2

Table 3-3

Table 3-4

Table 3-5

Table 3-6

Device State Control Registers . . . . . . . . . . . . . . . . . 74

Device Status Register Field Descriptions. . . . . . . 78

Device Configuration Register (DEVCFG) Field

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

JTAG ID Register (JTAGID) Field Descriptions . . . 79

Table 3-7

DSP BOOT Address Register (DSP_BOOT_ADDRn)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 3-8 LRESETNMI PIN Status Clear Register

(LRSTNMIPINSTAT_CLR) Field Descriptions . . . . . 81

Table 3-9 Reset Status Register (RESET_STAT) Field

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 3-10 Reset Status Clear Register (RESET_STAT_CLR) Field

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 3-11 Boot Complete Register (BOOTCOMPLETE) Field

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Table 3-12 Power State Control Register (PWRSTATECTL)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 3-13 NMI Generation Register (NMIGRx)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 3-14 IPC Generation Registers (IPCGRx)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 3-15 IPC Acknowledgement Registers (IPCARx)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 3-16 IPC Generation Registers (IPCGRH)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 3-17 IPC Acknowledgement Register (IPCARH)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 3-18 Timer Input Selection Field Description

(TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 3-19 Timer Output Selection Register (TOUTPSEL)

Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 3-20 Reset Mux Register (RSTMUXx)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 3-21 DSP Suspension Control Register

(DSP_SUSP_CTL) Field Descriptions. . . . . . . . . . . . .92

Table 3-22 Device Speed Register (DEVSPEED)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table 3-23 Chip Miscellaneous Control Register

(CHIP_MISC_CTL) Field Descriptions . . . . . . . . . . . . 93

Table 4-1

Table 4-2

Data Switch Fabric Connection Matrix . . . . . . . . . . 98

Configuration Switch Fabric Connection

Matrix Section1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Table 4-3

Table 5-1

Table 5-2

Configuration Switch Fabric Connection

Matrix Section2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Available Memory Page Protection Schemes . . .110

CorePac Revision ID Register (MM_REVID)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 6-1

Table 6-2

Table 6-3

Table 6-4

Table 7-1

Table 7-2

Table 7-3

Table 7-4

Table 7-5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . .113

Recommended Operating Conditions . . . . . . . . .114

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .115

Power Supply to Peripheral I/O Mapping . . . . . .116

Power Supply Rails on the TMS320C6671 . . . . . .118

Core Before IO Power Sequencing . . . . . . . . . . . . .121

IO Before Core Power Sequencing . . . . . . . . . . . . .123

Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

SmartReflex 4-Pin VID Interface Switching

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Table 7-6

Table 7-7

Table 7-8

Table 7-9

Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

PSC Register Memory Map . . . . . . . . . . . . . . . . . . . .128

Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Table 7-10 Reset Timing Requirements . . . . . . . . . . . . . . . . . . .135

Table 7-11 Reset Switching Characteristics Over

Recommended Operating Conditions . . . . . . . . .135

Table 7-12 Boot Configuration Timing Requirements. . . . . .136

Table 7-13 Main PLL Stabilization, Lock, and Reset Times . .139

Table 7-14 PLL Controller Registers (Including Reset

Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

List of Tables 11

TMS320C6671

SPRS756E—November 2010—Revised March 2014

Table 7-15 PLL Secondary Control Register (SECCTL)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 7-16 PLL Controller Divider Register (PLLDIVn)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 7-17 PLL Controller Clock Align Control Register

(ALNCTL) Field Descriptions . . . . . . . . . . . . . . . . . . 143

Table 7-18 PLLDIV Divider Ratio Change Status Register

(DCHANGE) Field Descriptions . . . . . . . . . . . . . . . . 143

Table 7-19 SYSCLK Status Register (SYSTAT)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 7-20 Reset Type Status Register (RSTYPE)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 7-21 Reset Control Register (RSTCTRL)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 7-22 Reset Configuration Register (RSTCFG)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 7-23 Reset Isolation Register (RSISO)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 7-24 Main PLL Control Register 0 (MAINPLLCTL0)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 7-25 Main PLL Control Register 1 (MAINPLLCTL1)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe

Clock Input Timing Requirements. . . . . . . . . . . . . 148

Table 7-27 DDR3 PLL Control Register 0

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 7-28 DDR3 PLL Control Register 1

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 7-29 DDR3 PLL DDRSYSCLK1(N|P)

Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 7-30 PASS PLL Control Register 0

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 7-31 PASS PLL Control Register 1

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 7-32 PASS PLL Timing Requirements . . . . . . . . . . . . . . . 155

Table 7-33 EDMA3 Channel Controller Configuration . . . . . 157

Table 7-34 EDMA3 Transfer Controller Configuration . . . . . 158

Table 7-35 EDMA3CC0 Events for C6671 . . . . . . . . . . . . . . . . . 158

Table 7-36 EDMA3CC1 Events for C6671 . . . . . . . . . . . . . . . . . 158

Table 7-37 EDMA3CC2 Events for C6671 . . . . . . . . . . . . . . . . . 160

Table 7-38 CIC0 Event Inputs (Secondary Interrupts for

C66x CorePacs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 7-39 CIC2 Event Inputs (Secondary Events for

EDMA3CC1 and EDMA3CC2). . . . . . . . . . . . . . . . . . 170

Table 7-40 CIC3 Event Inputs (Secondary Events for

EDMA3CC0 and HyperLink) . . . . . . . . . . . . . . . . . . . 174

Table 7-41 CIC0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 7-42 CIC2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 7-43 CIC3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 7-44 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . 181

Table 7-45 LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . 182

Table 7-46 NMI and Local Reset Timing Requirements . . . . 183

Table 7-47 HOUT Switching Characteristics . . . . . . . . . . . . . . 183

Table 7-48 MPU Default Configuration . . . . . . . . . . . . . . . . . . . 184

Table 7-49 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 7-50 Privilege ID Settings. . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-51 Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Table 7-52 MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-53 MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Table 7-54 MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-55 MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-56 Configuration Register (CONFIG)

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-57 Programmable Range n Start Address Register

(PROGn_MPSAR) Field Descriptions. . . . . . . . . . . .192

Table 7-58 Programmable Range n End Address Register

(PROGn_MPEAR) Field Descriptions. . . . . . . . . . . .192

Table 7-59 Programmable Range n Memory Protection

Page Attribute Register (PROGn_MPPA) Field

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Table 7-60 Programmable Range n Registers Reset

Values for MPU0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-61 Programmable Range n Registers Reset

Values for MPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 7-62 Programmable Range n Registers Reset

Values for MPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Table 7-63 Programmable Range n Registers Reset

Values for MPU3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Table 7-64 I

2

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Table 7-65 I

2

C Timing Requirements. . . . . . . . . . . . . . . . . . . . . .201

Table 7-66 I

2

C Switching Characteristics . . . . . . . . . . . . . . . . . .202

Table 7-67 SPI Timing Requirements. . . . . . . . . . . . . . . . . . . . . .204

Table 7-68 SPI Switching Characteristics . . . . . . . . . . . . . . . . . .204

Table 7-69 HyperLink Events for C6671 . . . . . . . . . . . . . . . . . . .207

Table 7-70 HyperLink Peripheral Timing Requirements . . . .209

Table 7-71 HyperLink Peripheral Switching

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Table 7-72 UART Timing Requirements . . . . . . . . . . . . . . . . . . .211

Table 7-73 UART Switching Characteristics. . . . . . . . . . . . . . . .212

Table 7-74 Timing Requirements for TSIP 2x Mode . . . . . . . .213

Table 7-75 Timing Requirements for TSIP 1x Mode . . . . . . . .214

Table 7-76 EMIF16 Asynchronous Memory Timing

Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Table 7-77 MACID1 Register Field Descriptions. . . . . . . . . . . .218

Table 7-78 MACID2 Register Field Descriptions. . . . . . . . . . . .218

Table 7-79 CPTS_RFTCLK_SEL Register

Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

Table 7-80 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . .220

Table 7-81 MDIO Switching Characteristics . . . . . . . . . . . . . . .220

Table 7-82 Timer Input Timing Requirements . . . . . . . . . . . . .222

Table 7-83 Timer Output Switching Characteristics. . . . . . . .222

Table 7-84 GPIO Input Timing Requirements . . . . . . . . . . . . . .223

Table 7-85 GPIO Output Switching Characteristics . . . . . . . .223

Table 7-86 DSP Trace Switching Characteristics . . . . . . . . . . .225

Table 7-87 STM Trace Switching Characteristics . . . . . . . . . .225

Table 7-88 JTAG Test Port Timing Requirements . . . . . . . . . .226

Table 7-89 JTAG Test Port Switching Characteristics . . . . . . .226

Table 9-1 Thermal Resistance Characteristics for

CYP (PBGA 841-Pin Package) . . . . . . . . . . . . . . . . . .233

12 List of Tables Copyright 2014 Texas Instruments Incorporated

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Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2 Device Overview

2.1 Device Characteristics

Table 2-1

shows the significant features of the device.

Table 2-1 Device Characteristics

Peripherals

Accelerators

On-Chip Memory

C66x CorePac Rev ID

JTAG BSDL_ID

Features

DDR3 Memory Controller (64-bit bus width) [1.5 V I/O]

(clock source = DDRREFCLKN|P)

EDMA3 (16 independent channels) [DSP/2 clock rate]

EDMA3 (64 independent channels) [DSP/3 clock rate]

High-speed 1× / 2× / 4× Serial RapidIO Port (4 lanes)

PCIe (2 lanes)

10/100/1000 Ethernet

Management Data Input/Output (MDIO)

HyperLink

EMIF16

TSIP

SPI

UART

I

2

C

64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency)

General-Purpose Input/Output Port (GPIO)

Packet Accelerator

Security Accelerator

(1)

Size (Bytes)

Organization

CorePac Revision ID Register (address location: 0181 2000h)

JTAGID register (address location: 0262 0018h)

1

TMS320C6671

1

1

2

1

1

1

1

2

1

1

2

1

Nine 64-bit (each configurable as two 32-bit timers)

16

1

1

4800KB

32KB L1 Program Memory [SRAM/Cache]

32KB L1 Data Memory [SRAM/Cache]

512KB L2 Unified Memory/Cache

4096KB MSM SRAM

128KB L3 ROM

See Section

5.5 ‘‘C66x CorePac Revision’’.

See Section 3.3.3

‘‘JTAG ID Register (JTAGID)

Description’’

Frequency MHz

Cycle Time ns

1250 (1.25 GHz)

1000 (1.0 GHz)

0.8 ns (1.25 GHz)

1 ns (1.0 GHz)

Core (V) SmartReflex variable supply

Voltage

I/O (V) 1.0 V, 1.5 V, and 1.8 V

Process Technology

m 0.040

BGA Package

Product Status

(2)

24 mm × 24 mm lead-free die bump and solder ball package

Product Preview (PP), Advance Information (AI), or Production Data (PD)

CYP 841-Pin (lead-free)

PD

1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.

2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2014 Texas Instruments Incorporated

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Device Overview 13

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2.2 DSP Core Description

The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through enhancements and new features. Many of the new features target increased performance for vector processing. The

C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.

On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions.

C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.

The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain thirty-two 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.

40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3 upper registers.

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions that multiply a complex number with a complex conjugate of another number with rounding capability.

Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.

A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.

Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The

C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one the following floating-point operations each clock cycle: one, two, or four single-precision multiplies or a complex single-precision multiply.

The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and

14 Device Overview Copyright 2014 Texas Instruments Incorporated

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Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number.

The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall until the completion of all the DSP-triggered memory transactions, including:

• Cache line fills

• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints

• Victim write backs

• Block or global coherence operations

• Cache mode changes

• Outstanding XMC prefetch requests

This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations.

For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following documents:

C66x DSP CPU and Instruction Set Reference Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

C66x DSP CorePac User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

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Device Overview 15

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Figure 2-1

shows the DSP core functional units and data paths.

Figure 2-1 DSP Core Data Paths

Note:

Default bus width is 64 bits

(i.e. a register pair)

.L1

src1 src2 dst

ST1

.S1

src1 src2 dst

Data Path A

.M1

src1 src1_hi src2 src2_hi dst2 dst1

LD1

DA1

32

.D1

src1 dst src2

32

32

DA2

32

.D2

Register

File A

(A0, A1, A2,

...A31)

32

32 src2 dst src1

32

32

32

32

32

2

´

1

´

Register

File B

(B0, B1, B2,

...B31)

LD2

.M2

dst1 dst2 src2_hi src2 src1_hi src1

Data Path B

.S2

dst src2 src1

ST2

.L2

dst src2 src1

32

32

Control

Register

16 Device Overview Copyright 2014 Texas Instruments Incorporated

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2.3 Memory Map Summary

Table 2-2

shows the memory map address ranges of the TMS320C6671 device.

Table 2-2 Memory Map Summary (Part 1 of 7)

Logical 32-bit Address

Start End

00000000

00800000

007FFFFF

0087FFFF

00880000

00E00000

00E08000

00F00000

00DFFFFF

00E07FFF

00EFFFFF

00F07FFF

017FFFFF 00F08000

01800000

01C00000

01D00000

01D00080

01D08000

01D08080

01D10000

01D10080

01D18000

01D18080

01D20000

01D20080

01D28000

01D28080

01D30000

01D30080

01D38000

01D38080

01D40000

01D40080

01D48000

01D48080

01D50000

01D50080

01D58000

01D58080

01D60000

01D60080

01D68000

01D68080

01D70000

01D70080

01D78000

01CFFFFF

01D0007F

01D07FFF

01D0807F

01D0FFFF

01D1007F

01D17FFF

01D1807F

01D1FFFF

01D2007F

01D27FFF

01D2807F

01D2FFFF

01D3007F

01D37FFF

01D3807F

01D3FFFF

01D4007F

01D47FFF

01D4807F

01D4FFFF

01D5007F

01D57FFF

01D5807F

01D5FFFF

01D6007F

01D67FFF

01D6807F

01D6FFFF

01D7007F

01D77FFF

01D7807F

Physical 36-bit Address

Start End

0 00000000

0 00800000

0 007FFFFF

0 0087FFFF

0 00880000

0 00E00000

0 00E08000

0 00F00000

0 00F08000

0 00DFFFFF

0 00E07FFF

0 00EFFFFF

0 00F07FFF

0 01C00000

0 01D00000

0 01D00080

0 01D08000

0 01D08080

0 01D10000

0 01D10080

0 01D18000

0 01D18080

0 01D20000

0 01D20080

0 01D28000

0 01D28080

0 01D30000

0 01D30080

0 01D38000

0 01D38080

0 01D40000

0 01D40080

0 01D48000

0 01D48080

0 01D50000

0 01D50080

0 01D58000

0 01D58080

0 01D60000

0 01D60080

0 01D68000

0 01D68080

0 01D70000

0 01D70080

0 01D78000

0 017FFFFF

0 01BFFFFF

0 01CFFFFF

0 01D0007F

0 01D07FFF

0 01D0807F

0 01D0FFFF

0 01D1007F

0 01D17FFF

0 01D1807F

0 01D1FFFF

0 01D2007F

0 01D27FFF

0 01D2807F

0 01D2FFFF

0 01D3007F

0 01D37FFF

0 01D3807F

0 01D3FFFF

0 01D4007F

0 01D47FFF

0 01D4807F

0 01D4FFFF

0 01D5007F

0 01D57FFF

0 01D5807F

0 01D5FFFF

0 01D6007F

0 01D67FFF

0 01D6807F

0 01D6FFFF

0 01D7007F

0 01D77FFF

0 01D7807F

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

32K-128

128

4M

1M

128

32K-128

128

32K-128

128

32K-128

Bytes

8M

512K

5M+512K

32K

1M-32K

32K

9M-32K

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Tracer_MSMC_3

Reserved

Tracer_QM_DMA

Reserved

Tracer_DDR

Reserved

Tracer_SM

Reserved

Tracer_QM_CFG

Reserved

Tracer_CFG

Reserved

Tracer_L2_0

Reserved

Reserved

Reserved

Description

Reserved

Local L2 SRAM

Reserved

Local L1P SRAM

Reserved

Local L1D SRAM

Reserved

C66x CorePac Registers

Reserved

Tracer_MSMC_0

Reserved

Tracer_MSMC_1

Reserved

Tracer_MSMC_2

Reserved

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Device Overview 17

02100000

02200000

02200080

02210000

02210080

02220000

02220080

02230000

02230080

02240000

02240080

02250000

02250080

02260000

02260080

02270000

02270080

02280000

02280080

02290000

02290080

022A0000

022A0080

022B0000

022B0080

022C0000

022C0080

022D0000

022D0080

022E0000

022E0080

022F0000

022F0080

02300000

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 2 of 7)

Logical 32-bit Address

Start End

01D78080

01D80000

01D80080

01E00000

01D7FFFF

01D8007F

01DFFFFF

01E3FFFF

01E40000

01E80000

01EC0000

02000000

01E7FFFF

01EBFFFF

01FFFFFF

020FFFFF

Physical 36-bit Address

Start End

0 01D78080

0 01D80000

0 01D80080

0 01E00000

0 01D7FFFF

0 01D8007F

0 01DFFFFF

0 01E3FFFF

0 01E40000

0 01E80000

0 01EC0000

0 02000000

0 01E7FFFF

0 01EBFFFF

0 01FFFFFF

0 020FFFFF

Bytes

32K-128

128

512K-128

256K

256K

256K

1M +256K

1M

021FFFFF

0220007F

0220FFFF

0221007F

0221FFFF

0222007F

0222FFFF

0223007F

0223FFFF

0224007F

0224FFFF

0225007F

0225FFFF

0226007F

0226FFFF

0227007F

0227FFFF

0228007F

0228FFFF

0229007F

0229FFFF

022A007F

022AFFFF

022B007F

022BFFFF

022C007F

022CFFFF

022D007F

022DFFFF

022E007F

022EFFFF

022F007F

022FFFFF

0230FFFF

0 02100000

0 02200000

0 02200080

0 02210000

0 02210080

0 02220000

0 02220080

0 02230000

0 02230080

0 02240000

0 02240080

0 02250000

0 02250080

0 02260000

0 02260080

0 02270000

0 02270080

0 02280000

0 02280080

0 02290000

0 02290080

0 022A0000

0 022A0080

0 022B0000

0 022B0080

0 022C0000

0 022C0080

0 022D0000

0 022D0080

0 022E0000

0 022E0080

0 022F0000

0 022F0080

0 02300000

0 021FFFFF

0 0220007F

0 0220FFFF

0 0221007F

0 0221FFFF

0 0222007F

0 0222FFFF

0 0223007F

0 0223FFFF

0 0224007F

0 0224FFFF

0 0225007F

0 0225FFFF

0 0226007F

0 0226FFFF

0 0227007F

0 0227FFFF

0 0228007F

0 0228FFFF

0 0229007F

0 0229FFFF

0 022A007F

0 022AFFFF

0 022B007F

0 022BFFFF

0 022C007F

0 022CFFFF

0 022D007F

0 022DFFFF

0 022E007F

0 022EFFFF

0 022F007F

0 022FFFFF

0 0230FFFF

64K-128

128

64K-128

128

64K-128

128

64K-128

128

1M

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

128

64K-128

64K

18 Device Overview

Reserved

Timer8

Reserved

Timer9

Reserved

Timer10

Reserved

Timer11

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Timer0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Description

Reserved

Reserved

Reserved

Telecom Serial Interface Port (TSIP) 0

Reserved

Telecom Serial Interface Port (TSIP) 1

Reserved

Network Coprocessor (Packet Accelerator, Gigabit Ethernet

Switch Subsystem and Security Accelerator)

Reserved

Timer12

Reserved

Timer13

Reserved

Timer14

Reserved

Timer15

Reserved

Reserved

Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 3 of 7)

02494000

024A0000

024A4000

024B0000

024B4000

024C0000

02530000

02530080

02540000

02540400

02550000

02600000

02602000

02604000

02606000

02370000

02370400

02378000

02378400

02400000

02440000

02444000

02450000

02454000

02460000

02464000

02470000

02474000

02480000

02484000

02490000

Logical 32-bit Address

Start End

02310000

02310200

02320000

02320100

023101FF

0231FFFF

023200FF

0232FFFF

02330000

02330400

02350000

02351000

02360000

02360400

02368000

02368400

023303FF

0234FFFF

02350FFF

0235FFFF

023603FF

02367FFF

023683FF

0236FFFF

023703FF

02377FFF

023783FF

023FFFFF

0243FFFF

02443FFF

0244FFFF

02453FFF

0245FFFF

02463FFF

0246FFFF

02473FFF

0247FFFF

02483FFF

0248FFFF

02493FFF

0249FFFF

024A3FFF

024AFFFF

024B3FFF

024BFFFF

0252FFFF

0253007F

0253FFFF

0254003F

0254FFFF

025FFFFF

02601FFF

02603FFF

02605FFF

02607FFF

0 02494000

0 024A0000

0 024A4000

0 024B0000

0 024B4000

0 024C0000

0 02530000

0 02530080

0 02540000

0 02540400

0 02550000

0 02600000

0 02602000

0 02604000

0 02606000

0 02370000

0 02370400

0 02378000

0 02378400

0 02400000

0 02440000

0 02444000

0 02450000

0 02454000

0 02460000

0 02464000

0 02470000

0 02474000

0 02480000

0 02484000

0 02490000

Physical 36-bit Address

Start End

0 02310000

0 02310200

0 02320000

0 02320100

0 023101FF

0 0231FFFF

0 023200FF

0 0232FFFF

0 02330000

0 02330400

0 02350000

0 02351000

0 02360000

0 02360400

0 02368000

0 02368400

0 023303FF

0 0234FFFF

0 02350FFF

0 0235FFFF

0 023603FF

0 02367FFF

0 023683FF

0 0236FFFF

0 023703FF

0 02377FFF

0 023783FF

0 023FFFFF

0 0243FFFF

0 02443FFF

0 0244FFFF

0 02453FFF

0 0245FFFF

0 02463FFF

0 0246FFFF

0 02473FFF

0 0247FFFF

0 02483FFF

0 0248FFFF

0 02493FFF

0 0249FFFF

0 024A3FFF

0 024AFFFF

0 024B3FFF

0 024BFFFF

0 0252FFFF

0 0253007F

0 0253FFFF

0 0254003F

0 0254FFFF

0 025FFFFF

0 02601FFF

0 02603FFF

0 02605FFF

0 02607FFF

Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

48K

16K

48K

16K

48K

16K

48K

16K

48K

16K

48K

16K

1K

543K

256K

16K

1K

31K

1K

31K

4K

64K-4K

1K

31K

Bytes

512

64K-512

256

64K-256

1K

127K

704K

8K

8K

8K

8K

48K

16K

48K

448K

128

64K-128

64

64K-64

Description

PLL Controller

Reserved

GPIO

Reserved

SmartReflex

Reserved

Power Sleep Controller (PSC)

Reserved

Memory Protection Unit (MPU) 0

Reserved

Memory Protection Unit (MPU) 1

Reserved

Memory Protection Unit (MPU) 2

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Memory Protection Unit (MPU) 3

Reserved

Debug Subsystem Configuration

DSP trace formatter 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

I

2

C data & control

Reserved

UART

Reserved

Reserved

Chip Interrupt Controller (CIC) 0

Reserved

Reserved

Reserved

Device Overview 19

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 4 of 7)

02790400

02798000

02798400

027A0000

027A0400

027A8000

027A8400

027B0000

027D0000

027D1000

027E0000

027E1000

027F0000

027F1000

02800000

02728000

02740000

02748000

02760000

02760400

02768000

02768400

02770000

02770400

02778000

02778400

02780000

02780400

02788000

02788400

02790000

Logical 32-bit Address

Start End

02608000

0260A000

0260C000

0260E000

02609FFF

0260BFFF

0260DFFF

0261FFFF

02620000

02620800

02640000

02640800

02650000

02700000

02708000

02720000

026207FF

0263FFFF

026407FF

0264FFFF

026FFFFF

02707FFF

0271FFFF

02727FFF

0273FFFF

02747FFF

0275FFFF

027603FF

02767FFF

027683FF

0276FFFF

027703FF

02777FFF

027783FF

0277FFFF

027803FF

02787FFF

027883FF

0278FFFF

027903FF

02797FFF

027983FF

0279FFFF

027A03FF

027A7FFF

027A83FF

027AFFFF

027CFFFF

027D0FFF

027DFFFF

027E0FFF

027EFFFF

027F0FFF

027FFFFF

02800FFF

0 02790400

0 02798000

0 02798400

0 027A0000

0 027A0400

0 027A8000

0 027A8400

0 027B0000

0 027D0000

0 027D1000

0 027E0000

0 027E1000

0 027F0000

0 027F1000

0 02800000

0 02728000

0 02740000

0 02748000

0 02760000

0 02760400

0 02768000

0 02768400

0 02770000

0 02770400

0 02778000

0 02778400

0 02780000

0 02780400

0 02788000

0 02788400

0 02790000

Physical 36-bit Address

Start End

0 02608000

0 0260A000

0 0260C000

0 0260E000

0 02609FFF

0 0260BFFF

0 0260DFFF

0 0261FFFF

0 02620000

0 02620800

0 02640000

0 02640800

0 02650000

0 02700000

0 02708000

0 02720000

0 026207FF

0 0263FFFF

0 026407FF

0 0264FFFF

0 026FFFFF

0 02707FFF

0 0271FFFF

0 02727FFF

0 0273FFFF

0 02747FFF

0 0275FFFF

0 027603FF

0 02767FFF

0 027683FF

0 0276FFFF

0 027703FF

0 02777FFF

0 027783FF

0 0277FFFF

0 027803FF

0 02787FFF

0 027883FF

0 0278FFFF

0 027903FF

0 02797FFF

0 027983FF

0 0279FFFF

0 027A03FF

0 027A7FFF

0 027A83FF

0 027AFFFF

0 027CFFFF

0 027D0FFF

0 027DFFFF

0 027E0FFF

0 027EFFFF

0 027F0FFF

0 027FFFFF

0 02800FFF

31K

1K

31K

1K

31K

1K

31K

1K

31K

1K

31K

1K

96K

1K

31K

1K

96K

32K

96K

32K

2K

64K-2K

704K

32K

Bytes

8K

8K

8K

72K

2K

126K

31K

1K

31K

1K

31K

128K

4K

60K

4K

60K

4K

60K

4K

20 Device Overview

Description

Chip Interrupt Controller (CIC) 2

Reserved

Chip Interrupt Controller (CIC) 3

Reserved

Chip-Level Registers

Reserved

Semaphore

Reserved

Reserved

EDMA3 Channel Controller (EDMA3CC) 0

Reserved

EDMA3 Channel Controller (EDMA3CC) 1

Reserved

EDMA3 Channel Controller (EDMA3CC) 2

Reserved

EDMA3CC0 Transfer Controller (EDMA3TC) 0

Reserved

EDMA3CC0 Transfer Controller (EDMA3TC) 1

Reserved

EDMA3CC1 Transfer Controller (EDMA3TC) 0

Reserved

EDMA3CC1 Transfer Controller (EDMA3TC) 1

Reserved

EDMA3CC1 Transfer Controller (EDMA3TC) 2

Reserved

EDMA3CC1 Transfer Controller (EDMA3TC) 3

Reserved

EDMA3PCC2 Transfer Controller (EDMA3TC) 0

Reserved

EDMA3CC2 Transfer Controller (EDMA3TC) 1

Reserved

EDMA3CC2 Transfer Controller (EDMA3TC) 2

Reserved

EDMA3CC2 Transfer Controller (EDMA3TC) 3

Reserved

Reserved

TI embedded trace buffer (TETB) - CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 5 of 7)

10F08000

11800000

11880000

11900000

11E00000

11E08000

11F00000

11F08000

12800000

12880000

12900000

12E00000

12E08000

12F00000

12F08000

02900000

02921000

02A00000

02C00000

08000000

08010000

0BC00000

0BD00000

0C000000

0C400000

10800000

10880000

10900000

10E00000

10E08000

10F00000

Logical 32-bit Address

Start End

02801000

02810000

02811000

02820000

0280FFFF

02810FFF

0281FFFF

02820FFF

02821000

02830000

02831000

02840000

02841000

02850000

02858000

02860000

0282FFFF

02830FFF

0283FFFF

02840FFF

0284FFFF

02857FFF

0285FFFF

028FFFFF

02920FFF

029FFFFF

02BFFFFF

07FFFFFF

0800FFFF

0BBFFFFF

0BCFFFFF

0BFFFFFF

0C3FFFFF

107FFFFF

1087FFFF

108FFFFF

10DFFFFF

10E07FFF

10EFFFFF

10F07FFF

117FFFFF

1187FFFF

118FFFFF

11DFFFFF

11E07FFF

11EFFFFF

11F07FFF

127FFFFF

1287FFFF

128FFFFF

12DFFFFF

12E07FFF

12EFFFFF

12F07FFF

137FFFFF

0 10F08000

0 11800000

0 11880000

0 11900000

0 11E00000

0 11E08000

0 11F00000

0 11F08000

0 12800000

0 12880000

0 12900000

0 12E00000

0 12E08000

0 12F00000

0 12F08000

0 02900000

0 02921000

0 02A00000

0 02C00000

0 08000000

0 08010000

0 0BC00000

0 0BD00000

0 0C000000

0 0C400000

0 10800000

0 10880000

0 10900000

0 10E00000

0 10E08000

0 10F00000

Physical 36-bit Address

Start End

0 02801000

0 02810000

0 02811000

0 02820000

0 0280FFFF

0 02810FFF

0 0281FFFF

0 02820FFF

0 02821000

0 02830000

0 02831000

0 02840000

0 02841000

0 02850000

0 02858000

0 02860000

0 0282FFFF

0 02830FFF

0 0283FFFF

0 02840FFF

0 0284FFFF

0 02857FFF

0 0285FFFF

0 028FFFFF

0 02920FFF

0 029FFFFF

0 02BFFFFF

0 07FFFFFF

0 0800FFFF

0 0BBFFFFF

0 0BCFFFFF

0 0BFFFFFF

0 0C3FFFFF

0 107FFFFF

0 1087FFFF

0 108FFFFF

0 10DFFFFF

0 10E07FFF

0 10EFFFFF

0 10F07FFF

0 117FFFFF

0 1187FFFF

0 118FFFFF

0 11DFFFFF

0 11E07FFF

0 11EFFFFF

0 11F07FFF

0 127FFFFF

0 1287FFFF

0 128FFFFF

0 12DFFFFF

0 12E07FFF

0 12EFFFFF

0 12F07FFF

0 137FFFFF

Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

512K

512K

5M

32K

1M-32K

32K

9M-32K

512K

2M

84M

64K

60M-64K

1M

3M

4M

68 M

Bytes

60K

4K

60K

4K

60K

4K

60K

4K

60K

32K

32K

640K

132K

1M-132K

512K

5M

32K

1M-32K

32K

9M-32K

512K

512K

5M

32K

1M-32K

32K

9M-32K

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Description

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TI embedded trace buffer (TETB) — system

Reserved

Reserved

Serial RapidIO (SRIO) configuration

Reserved

Queue manager subsystem configuration

Reserved

Extended memory controller (XMC) configuration

Reserved

Multicore shared memory controller (MSMC) config

Reserved

Multicore shared memory (MSM)

Reserved

CorePac0 L2 SRAM

Reserved

Reserved

CorePac0 L1P SRAM

Reserved

CorePac0 L1D SRAM

Reserved

Reserved

Device Overview 21

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 6 of 7)

17800000

17880000

17900000

17E00000

17E08000

17F00000

17F08000

20000000

20100000

20B00000

20B20000

20BF0000

20BF0200

20C00000

20C00100

14F00000

14F08000

15800000

15880000

15900000

15E00000

15E08000

15F00000

15F08000

16800000

16880000

16900000

16E00000

16E08000

16F00000

16F08000

Logical 32-bit Address

Start End

13800000

13880000

13900000

13E00000

1387FFFF

138FFFFF

13DFFFFF

13E07FFF

13E08000

13F00000

13F08000

14800000

14880000

14900000

14E00000

14E08000

13EFFFFF

13F07FFF

147FFFFF

1487FFFF

148FFFFF

14DFFFFF

14E07FFF

14EFFFFF

14F07FFF

157FFFFF

1587FFFF

158FFFFF

15DFFFFF

15E07FFF

15EFFFFF

15F07FFF

167FFFFF

1687FFFF

168FFFFF

16DFFFFF

16E07FFF

16EFFFFF

16F07FFF

177FFFFF

1787FFFF

178FFFFF

17DFFFFF

17E07FFF

17EFFFFF

17F07FFF

1FFFFFFF

200FFFFF

20AFFFFF

20B1FFFF

20BEFFFF

20BF01FF

20BFFFFF

20C000FF

20FFFFFF

0 17800000

0 17880000

0 17900000

0 17E00000

0 17E08000

0 17F00000

0 17F08000

0 20000000

0 20100000

0 20B00000

0 20B20000

0 20BF0000

0 20BF0200

0 20C00000

0 20C00100

0 14F00000

0 14F08000

0 15800000

0 15880000

0 15900000

0 15E00000

0 15E08000

0 15F00000

0 15F08000

0 16800000

0 16880000

0 16900000

0 16E00000

0 16E08000

0 16F00000

0 16F08000

Physical 36-bit Address

Start End

0 13800000

0 13880000

0 13900000

0 13E00000

0 1387FFFF

0 138FFFFF

0 13DFFFFF

0 13E07FFF

0 13E08000

0 13F00000

0 13F08000

0 14800000

0 14880000

0 14900000

0 14E00000

0 14E08000

0 13EFFFFF

0 13F07FFF

0 147FFFFF

0 1487FFFF

0 148FFFFF

0 14DFFFFF

0 14E07FFF

0 14EFFFFF

0 14F07FFF

0 157FFFFF

0 1587FFFF

0 158FFFFF

0 15DFFFFF

0 15E07FFF

0 15EFFFFF

0 15F07FFF

0 167FFFFF

0 1687FFFF

0 168FFFFF

0 16DFFFFF

0 16E07FFF

0 16EFFFFF

0 16F07FFF

0 177FFFFF

0 1787FFFF

0 178FFFFF

0 17DFFFFF

0 17E07FFF

0 17EFFFFF

0 17F07FFF

0 1FFFFFFF

0 200FFFFF

0 20AFFFFF

0 20B1FFFF

0 20BEFFFF

0 20BF01FF

0 20BFFFFF

0 20C000FF

0 20FFFFFF

512K

5M

32K

1M-32K

32K

9M-32K

512K

512K

512K

512K

5M

32K

1M-32K

32K

9M-32K

512K

9M-32K

512K

512K

5M

32K

1M-32K

32K

9M-32K

Bytes

512K

512K

5M

32K

1M-32K

32K

5M

32K

1M-32K

32K

129M-32K

1M

10M

128K

832K

512

64K-512

256

12M - 256

22 Device Overview

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Description

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

System trace manager (STM) configuration

Reserved

Boot ROM

Reserved

SPI

Reserved

EMIF16 config

Reserved

Copyright 2014 Texas Instruments Incorporated

Submit Documentation Feedback

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-2 Memory Map Summary (Part 7 of 7)

Logical 32-bit Address

Start End

21000000

21000200

21400000

21400100

210001FF

213FFFFF

214000FF

21800000

21808000

34000000

34200000

40000000

50000000

60000000

70000000

74000000

78000000

7C000000

33FFFFFF

341FFFFF

3FFFFFFF

4FFFFFFF

5FFFFFFF

6FFFFFFF

73FFFFFF

77FFFFFF

7BFFFFFF

7FFFFFFF

80000000

End of Table 2-2

FFFFFFFF

Physical 36-bit Address

Start

1 00000000

0 21000200

0 21400000

0 21808000

0 34000000

0 34200000

0 40000000

0 50000000

0 60000000

0 70000000

0 74000000

0 78000000

0 7C000000

8 00000000

End

1 000001FF

0 213FFFFF

0 214000FF

0 217FFFFF

0 341FFFFF

0 3FFFFFFF

0 4FFFFFFF

0 5FFFFFFF

0 6FFFFFFF

0 73FFFFFF

0 77FFFFFF

0 7BFFFFFF

0 7FFFFFFF

8 7FFFFFFF

Bytes

512

4M-512

256

4M-256

0 21807FFF 32K

0 33FFFFFF 296M-32K

2M

190M

256M

256M

256M

64M

64M

64M

64M

2G

Description

DDR3 EMIF configuration

Reserved

HyperLink config

Reserved

Reserved

Queue manager subsystem data

Reserved

HyperLink data

Reserved

PCIe data

EMIF16 CE0 data space, supports NAND, NOR or SRAM memory

(1)

EMIF16 CE1 data space, supports NAND, NOR or SRAM memory

(1)

EMIF16 CE2 data space, supports NAND, NOR or SRAM memory

(1)

EMIF16 CE3 data space, supports NAND, NOR or SRAM memory

(1)

DDR3 EMIF data

(2)

1 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. The 32MB and 16MB size restrictions do not apply to NAND.

2 The memory map shows only the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access (up to 8GB), see the MPAX configuration

details in C66x CorePac User Guide and Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The

DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to the C66x CorePac should not affect the state

of the hardware boot controller on the device. For more details on the initiators of the resets, see section 7.5

‘‘Reset

Controller’’ on page 130. The bootloader uses a section of the L2 SRAM (start address 0x0087 2DC0 and end address

0x0087 FFFF) during initial booting of the device. For more details on the type of configurations stored in this

reserved L2 section see Table 2-3 .

Table 2-3 Bootloader section in L2 SRAM (Part 1 of 2)

Start Address (Hex)

0x00872DC0

0x00872E00

0x00873200

0x008732E0

0x00873300

0x00873400

0x00873420

0x00873500

0x00873600

0x00873680

0x00873700

0x00878000

Size (Hex Bytes)

0x40

0x400

0xE0

0x20

0x100

0x20

0xE0

0x100

0x80

0x80

0x4900

0x7F80

Description

ROM boot version string (Unreserved)

Boot code stack

Boot log

Boot progress register stack (copies of boot program on mode change)

Boot Internal Stats

Boot table arguments

ROM boot FAR data

DDR configuration table

RAM table

Boot parameter table

Clear text packet scratch

Ethernet/SRIO packet/message/descriptor memory

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Table 2-3 Bootloader section in L2 SRAM (Part 2 of 2)

Start Address (Hex)

0x0087FF80

0x0087FFC0

0x0087FFFC

End of Table 2-3

Size (Hex Bytes)

0x40

0x3C

0x4

Description

Small stack

Not used

Boot magic address

The C6671 supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on Boot Sequence see the DSP Bootloader for KeyStone Devices User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

2.5 Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

Public ROM Boot

- C66x CorePac0 is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I

2

C ROM, Ethernet, or RapidIO), C66x CorePac0 then begins execution from the provided boot entry point. See the DSP Bootloader for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72 for more details.

Secure ROM Boot

- On secure devices, the C66x CorePac0 is released from reset and begin executing from secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C66x CorePac0 initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the bootloaded image prior to beginning execution.

The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the

associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].

Figure 2-2 Boot Mode Pin Decoding

12 11 10

PLL Mult I

2

C /SPI Ext Dev Cfg

9 8 7

Boot Mode Pins

6

Device Configuration

5 4 3 2 1

Boot Device

0

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2.5.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-4 shows the supported boot

modes.

Table 2-4

Bit

2-0

Boot Mode Pins: Boot Device Values

Field

Boot Device

Description

Device boot mode

0 = EMIF16 / No Boot

1 = Serial Rapid I/O

2 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as CORECLK(P|N); BOOTMODE[12:10] values drive the PASS PLL configuration during boot)

3 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as SRIOSGMIICLK(P|N); BOOTMODE[9:8] values drive the PASS PLL configuration during boot)

4 = PCIe

5 = I

2

C

6 = SPI

7 = HyperLink

End of Table 2-4

Internally, these boot modes are translated by RBL into the extended boot mode value that is used in the boot parameter table.

Table 2-5

shows the details of extended boot mode values.

Table 2-5 Extended Boot Modes

Boot Type

Ethernet Boot Mode

SRIO Boot Mode

PCIe Boot Mode

I

2

C Master Boot Mode

I

2

C Passive Boot Mode

SPI Boot Mode

HyperLink Boot Mode

EMIF 16 Boot Mode

Sleep Boot Mode

40

41

50

60

Extended Boot Mode Value (Decimal)

10

20

30

70

100

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2.5.2 Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode

2.5.2.1 No Boot/ EMIF16 Boot Device Configuration

Figure 2-3

9

No Boot/ EMIF16 Configuration Fields

Reserved

8 7

Wait Enable

6

Reserved

5

Sub-Mode

4 3

Reserved

Table 2-6

Bit

9-8

7

6

5-4

No Boot / EMIF16 Configuration Field Descriptions

Field

Reserved

Wait Enable

Reserved

Sub-Mode

3 Reserved

End of Table 2-6

Description

Reserved

Extended Wait mode for EMIF16.

0 = Wait enable disabled (EMIF16 sub mode)

1 = Wait enable enabled (EMIF16 sub mode)

Reserved

Sub mode selection.

0 = No boot

1 = EMIF16 boot

2 -3 = Reserved

Reserved

2.5.2.2 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-4 Serial Rapid I/O Device Configuration Fields

9

Lane Setup

8

Data Rate

7 6

Ref Clock

5 4

Reserved

3

Table 2-7

Bit

9

8-7

6-5

Serial Rapid I/O Configuration Field Descriptions

Field

Lane Setup

Data Rate

Ref Clock

4-3 Reserved

End of Table 2-7

Description

SRIO port and lane configuration

0 = Port Configured as 4 ports each 1 lane wide (4 -1× ports)

1 = Port Configured as 2 ports 2 lanes wide (2 – 2× ports)

SRIO data rate configuration

0 = 1.25 GBaud

1 = 2.5 GBaud

2 = 3.125 GBaud

3 = 5.0 GBaud

SRIO reference clock configuration

0 = 156.25 MHz

1 = 250 MHz

2 = 312.5 MHz

3 = Reserved

Reserved

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In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.

2.5.2.3 Ethernet (SGMII) Boot Device Configuration

Figure 2-5

9

Ethernet (SGMII) Device Configuration Fields

8 7

SerDes Clock Mult Ext connection

6 5 4

Device ID

3

Table 2-8

Bit

9-8

7-6

Ethernet (SGMII) Configuration Field Descriptions

Field

SerDes Clock Mult

Ext connection

5-3 Device ID

End of Table 2-8

Description

SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.

0 = ×8 for input clock of 156.25 MHz

1 = ×5 for input clock of 250 MHz

2 = ×4 for input clock of 312.5 MHz

3 = Reserved

External connection mode

0 = MAC to MAC connection, master with auto negotiation

1 = MAC to MAC connection, slave, and MAC to PHY

2 = MAC to MAC, forced link

3 = MAC to fiber connection

This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.

Note—

Both of the SGMII ports have been initialized for boot. The device can boot through either of the ports. If only one SGMII port is used, then the other port will time out before the boot process completes.

2.5.2.4 PCI Boot Device Configuration

Extra device configuration is provided by the PCI bits in the DEVSTAT register.

Figure 2-6 PCI Device Configuration Fields

9

Reserved

8 7

BAR Config

6 5

Table 2-9

Bit

9

8-5

PCI Device Configuration Field Descriptions

Field

Reserved

BAR Config

4-3 Reserved

End of Table 2-9

Description

Reserved

PCIe BAR registers configuration

This value can range from 0 to 0xf. See Table 2-10 .

Reserved

4

Reserved

3

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Table 2-10

BAR cfg

0b0000

0b0001

0b0010

0b0011

0b0100

0b0101

0b0110

0b0111

0b1000

0b1001

0b1010

0b1011

BAR0

PCIe MMRs

0b1100

0b1101

0b1110

0b1111

End of Table 2-10

BAR Config / PCIe Window Sizes

4

4

32

64

4

32

16

16

32

BAR1

32

16

16

32

64

128

128

128

32

16

32

32

BAR2

32

16

32

32-Bit Address Translation

BAR3 BAR4

32

32

32

64

32

32

64

64

64

64

64

64

64

64

128

128

128

256

64

128

256

128

256

256

BAR5

Clone of BAR4

64-Bit Address Translation

BAR2/3 BAR4/5

256

512

1024

2048

256

512

1024

2048

2.5.2.5 I

2

C Boot Device Configuration

2.5.2.5.1 I

2

C Master Mode

In master mode, the I

2

C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device will make the initial read of the I

2

C EEPROM while the PLL is in bypass mode.

The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

Figure 2-7 I

2

C Master Mode Device Configuration Bit Fields

12

Reserved

11

Speed

10

Address

9

Mode

8 7 6 5

Parameter Index

4 3

Table 2-11

Bit

12

11

10

Field

Reserved

Speed

Address

I

2

C Master Mode Device Configuration Field Descriptions (Part 1 of 2)

Description

Reserved

I

2

C data rate configuration

0 = I

2

C slow mode. Initial data rate is CORECLK/5000 until PLLs and clocks are programmed

1 = I

2

C fast mode. Initial data rate is CORECLK/250 until PLLs and clocks are programmed

I

2

C bus address configuration

0 = Boot from I

2

C EEPROM at I

2

C bus address 0x50

1 = Boot from I

2

C EEPROM at I

2

C bus address 0x51

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Table 2-11 I

2

C Master Mode Device Configuration Field Descriptions (Part 2 of 2)

Bit

9-8

7-3

Field

Mode

Description

I

2

C operation mode

0 = Master mode

3 = Passive mode (see section 2.5.2.5.2

‘‘I2C Passive Mode’’ )

Others = Reserved

Parameter Table Index Specifies which parameter table is loaded from I

2

C EEPROM. The boot ROM reads the parameter table (each table is

0x80 bytes) from the I

2

C EEPROM starting at I

2

C address (0x80 * parameter index).

This value can range from 0 to 31.

End of Table 2-11

2.5.2.5.2 I

2

C Passive Mode

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

Figure 2-8 I

2

C Passive Mode Device Configuration Bit Fields

9

Mode

8 7 6

Receive I

2

C Address

5 4

Reserved

3

Table 2-12

Bit

9-8

7-5

Field

Mode

I

2

C Passive Mode Device Configuration Field Descriptions

Receive I

2

C Address

4-3 Reserved

End of Table 2-12

Description

I

2

C operation mode

0 = Master mode (see section 2.5.2.5.1

‘‘I2C Master Mode’’

)

3 = Passive mode

Others = Reserved

I

2

C bus address configuration

0 - 7h= The I

2

C Bus address the device will listen to for data

The actual value on the bus is 0x19 plus the value in bits [7:5]. For Ex. if bits[7:5] = 0 then the device will listen to I

2

C bus address 0x19.

Reserved

2.5.2.6 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.

Figure 2-9 SPI Device Configuration Bit Fields

12

Mode

11 10

4, 5 Pin

9

Addr Width

8

Chip Select

7 6 5 4

Parameter Table Index

3

Table 2-13

Bit

12-11

Field

Mode

SPI Device Configuration Field Descriptions (Part 1 of 2)

Description

Clk Pol / Phase

0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.

1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.

2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.

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Table 2-13 SPI Device Configuration Field Descriptions (Part 2 of 2)

Bit

10

9

Field

4, 5 Pin

Addr Width

Description

SPI operation mode configuration

0 = 4-pin mode used

1 = 5-pin mode used

SPI address width configuration

0 = 16-bit address values are used

1 = 24-bit address values are used

8-7 Chip Select The chip select field value

00b = CS0 and CS1 are both active (not used)

01b = CS1 is active

10b = CS0 is active

11b = None is active

6-3 Parameter Table Index Specifies which parameter table is loaded from SPI. The boot ROM reads the parameter table (each table is 0x80 bytes) from the SPI starting at SPI address (0x80 * parameter index).

The value can range from 0 to 15.

End of Table 2-13

2.5.2.7 HyperLink Boot Device Configuration

Figure 2-10

9

Reserved

HyperLink Boot Device Configuration Fields

8 7

Data Rate

6

Ref Clock

Table 2-14

Bit

9

8-7

Field

Reserved

Data Rate

6-5

HyperLink Boot Device Configuration Field Descriptions

Ref Clocks

4-3 Reserved

End of Table 2-14

Description

Reserved

HyperLink data rate configuration

0 = 1.25 GBaud

1 = 3.125 GBaud

2 = 6.25 GBaud

3 = Reserved

HyperLink reference clock configuration

0 = 156.25 MHz

1 = 250 MHz

2 = 312.5 MHz

3 = Reserved

Reserved

5 4

Reserved

3

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2.5.3 Boot Parameter Table

The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the most common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common entries in the boot parameter table are shown in the table below:

Table 2-15 Boot Parameter Table Common Parameters

0

2

Byte

Offset Name

Length

Checksum

4

6

Boot Mode

Port Num

8 SW PLL, MSW

10 SW PLL, LSW

End of Table 2-15

Description

The length of the table, including the length field, in bytes.

The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification of the table by the boot ROM.

Internal values used by RBL for different boot modes.

Identifies the device port number to boot from, if applicable

PLL configuration, MSW

PLL configuration, LSW

2.5.3.1 EMIF16 Boot Parameter Table

Table 2-16 EMIF16 Boot Mode Parameter Table

16

18

20

22

24

Byte

Offset

12

14

Name

Options

Description

Option for EMIF16 boot (currently none)

Type Boot only from NOR flash is supported for C6671

Branch Address MSW Most significant bit for Branch address (depends on chip select)

Branch Address LSW

Chip Select

Memory Width

Wait Enable

Least significant bit for Branch address (depends on chip select)

Chip Select for the NOR flash

Memory width of the Emif16 bus (16 bits)

Extended wait mode enabled

0 = Wait enable is disabled

1 = Wait enable is enabled

End of Table 2-16

-

-

-

-

YES

-

-

Configured Through Boot

Configuration Pins

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2.5.3.2 SRIO Boot Parameter Table

Table 2-17

Byte

Offset

12

14

16

SRIO Boot Mode Parameter Table

Name

Options

Lane Setup

Config Index

18

20

22

24

Node ID

SerDes ref clk

Link Rate

PF Low

26 PF High

End of Table 2-17

Description

Bit 0 TX enable

0 = SRIO transmit disable

1 = SRIO transmit enable

Bit 1 Mailbox enable

0 = Mailbox mode disabled. SRIO boot is in directIO mode).

1 = Mailbox mode enabled. SRIO boot is in messaging mode).

Bit 2 Bypass configuration

0 = Configure the SRIO

1 = Bypass SRIO configuration

Bit 15-3 = Reserved

SRIO lane setup

0 = SRIO configured as 4 1x ports

1 = SRIO configured as 3 ports (2x, 1x, 1x)

2 = SRIO configured as 3 ports (1x, 1x, 2x)

3 = SRIO configured as 2 ports (2x, 2x)

4 = SRIO configured as 1 4x port

Others = Reserved

Specifies the template used for RapidIO configuration.

Must be 0 for KeyStone architecture

The node ID value to set for this device

The SerDes reference clock frequency, in 1/100 MHz

Link rate, MHz

Packet forward address range, low value

Packet forward address range, high value

2.5.3.3 Ethernet Boot Parameter Table

Table 2-18

Byte

Offset

12

14

16

Ethernet Boot Mode Parameter Table (Part 1 of 2)

Name

Options

MAC High

MAC Med

Description

Bits 2-0 Interface

101b = SGMII

Others = Reserved

Bit 3 Half or Full duplex

0 = Half Duplex

1 = Full Duplex

Bit 4 Skip TX

0 = Send Ethernet ready frame every 3 seconds

1 = Don't send Ethernet ready frame

Bits 6-5 Initialize config

00b = Switch, SerDes, SGMII and PASS are configured

01b = Only SGMII and PASS are configured

10b= Reserved

11b = None of the Ethernet system is configured.

Bits 15-7 = Reserved

The 16 MSBs of the MAC address to receive during boot

The 16 middle bits of the MAC address to receive during boot

32 Device Overview

Configured Through Boot

Configuration Pins

-

YES

(but not all lane setup are possible through the boot configuration pins)

-

-

YES

YES

-

-

Configured Through Boot

Configuration Pins

-

-

-

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Table 2-18

22

24

26

Byte

Offset

18

20

28

30

32

34

36

38

40

Ethernet Boot Mode Parameter Table (Part 2 of 2)

Name

MAC Low

Multi MAC High

Multi MAC Med

Multi MAC Low

Source Port

Dest Port

Device ID 12

Device ID 34

Dest MAC High

Dest MAC Med

Dest MAC Low

SGMII Config

50

52

54

56

42

44

46

48

SGMII Control

SGMII Adv Ability

SGMII TX Cfg High

SGMII TX Cfg Low

SGMII RX Cfg High

SGMII RX Cfg Low

SGMII Aux Cfg High

SGMII Aux Cfg Low

58 PKT PLL Cfg MSW

60 PKT PLL CFG LSW

End of Table 2-18

Description

The 16 LSBs of the MAC address to receive during boot

The 16 MSBs of the multi-cast MAC address to receive during boot

The 16 middle bits of the multi-cast MAC address to receive during boot

The 16 LSBs of the multi-cast MAC address to receive during boot

The source UDP port to accept boot packets from.

A value of 0 will accept packets from any UDP port

The destination port to accept boot packets on.

The first two bytes of the device ID.

This is typically a string value, and is sent in the Ethernet ready frame

The 2nd two bytes of the device ID.

The 16 MSBs of the MAC destination address used for the Ethernet ready frame. Default is broadcast.

The 16 middle bits of the MAC destination address

The 16 LSBs of the MAC destination address

Bits 3-0 are the config index

Bit 4 set if direct config used

Bit 5 set if no configuration done

Bits 15-6 Reserved

The SGMII control register value

The SGMII ADV Ability register value

The 16 MSBs of the SGMII TX config register

The 16 LSBs of the SGMII TX config register

The 16 MSBs of the SGMII RX config register

The 16 LSBs of the SGMII RX config register

The 16 MSBs of the SGMII Aux config register

The 16 LSBs of the SGMII Aux config register

The packet subsystem PLL configuration, MSW

The packet subsystem PLL configuration, LSW

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Configured Through Boot

Configuration Pins

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2.5.3.4 PCIe Boot Parameter Table

Table 2-19

Byte

Offset

12

14

16

18

PCIe Boot Mode Parameter Table

Name

Options

Address Width

Link Rate

Reference clock

28

30

32

34

20

22

24

26

Window 1 Size

Window 2 Size

Window 3 Size

Window 4 Size

Vendor ID

Device ID

Class code Rev ID MSW

Class code Rev ID LSW

36

38

40

42

SerDes Cfg MSW

SerDes Cfg LSW

SerDes lane 0 Cfg MSW

SerDes lane 0 Cfg LSW

44 SerDes lane 1 Cfg MSW

46 SerDes lane 1 Cfg LSW

End of Table 2-19

Description

Bit 0 Mode

0 = Host mode (direct boot mode)

1 = Boot table boot mode

Bit 1 Configuration of PCIe

0 = PCIe is configured by RBL

1 = PCIe is not configured by RBL

Bits 3-2 Reserved

Bit 4 Multiplier

0 = SerDes PLL configuration is done based on SerDes register values

1 = SerDes PLL configuration based on the reference clock values

Bits 15-5 Reserved

PCI address width, can be 32 or 64

SerDes frequency, in Mbps. Can be 2500 or 5000

Reference clock frequency, in units of 10 kHz. Value values are 10000

(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz), and 31250

(312.5 MHz). A value of 0 means that value is already in the SerDes configuration parameters and will not be computed by the boot ROM.

-

-

-

Configured Through Boot

Configuration Pins

-

Window 1 size.

Window 2 size.

Window 3 size. Valid only if address width is 32.

Window 4 Size. Valid only if the address width is 32.

Vendor ID

Device ID

Class code revision ID MSW

Class code revision ID LSW

YES

YES

YES

YES

-

-

-

-

PCIe SerDes config word, MSW

PCIe SerDes config word, LSW

SerDes lane config word, MSW, lane 0

SerDes lane config word, LSW, lane 0

SerDes lane config word, MSW, lane 1

SerDes lane config word, LSW, lane 1

-

-

-

-

-

-

2.5.3.5 I

2

C Boot Parameter Table

Table 2-20 I

2

C Boot Mode Parameter Table (Part 1 of 2)

Configured Through Boot

Configuration Pins

YES

Byte Offset Name

12

14

16

Option

Boot Dev Addr

Description

Bits 1-0 Mode

00b = Boot Parameter Table Mode

01b = Boot Table Mode

10b = Boot Config Mode

11b = Slave Receive Boot Config

Bits 15-2 Reserved

The I

2

C device address to boot from

Boot Dev Addr Ext Extended boot device address

YES

YES

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Table 2-20 I

2

C Boot Mode Parameter Table (Part 2 of 2)

Byte Offset Name

18

20

Broadcast Addr

Local Address

Description

I

2

C address used to send data in the I

2

C master broadcast mode.

The I

2

C address of this device

22

24

Device Freq

Bus Frequency

The operating frequency of the device (MHz)

The desired I

2

C data rate (kHz)

The next device address to boot (Used only if boot config option is selected) 26 Next Dev Addr -

28

30

Next Dev Addr Ext The extended next device address to boot (Used only if boot config option is selected) -

Address Delay The number of CPU cycles to delay between writing the address to an I

2

C EEPROM and reading data.

-

End of Table 2-20

-

YES

-

-

Configured Through Boot

Configuration Pins

2.5.3.6 SPI Boot Parameter Table

Table 2-21 SPI Boot Mode Parameter Table

Byte Offset Name

12 Options

22

24

26

28

14

16

18

20

Address Width

NPin

Chipsel

Mode

C2Delay

CPU Freq MHz

Bus Freq, MHz

Bus Freq, kHz

30

32

28

30

Read Addr MSW

Read Addr LSW

Next Chip Select

Next Read Addr MSW

32 Next Read Addr LSW

End of Table 2-21

Description

Bits 1-0 Modes

00b = Load a boot parameter table from the SPI (Default mode)

01b = Load boot records from the SPI (boot tables)

10b = Load boot config records from the SPI (boot config tables)

11b = Reserved

Bits 15-2 Reserved

The number of bytes in the SPI device address. Can be 16 or 24 bit.

The operational mode, 4 or 5 pin

The chip select used (valid in 4-pin mode only). Can be 0-3.

Standard SPI mode (0-3)

Setup time between chip assert and transaction

The speed of the CPU, in MHz

The MHz portion of the SPI bus frequency. Default = 5 MHz

The kHz portion of the SPI buf frequency. Default = 0

The first address to read from, MSW (valid for 24-bit address width only)

The first address to read from, LSW

Next Chip Select to be used (Used only in boot config mode)

The Next read address (used in boot config mode only)

The Next read address (used in boot config mode only)

Configured Through Boot

Configuration Pins

-

-

-

-

-

YES

YES

YES

YES

-

-

-

YES

YES

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2.5.3.7 HyperLink Boot Parameter Table

Table 2-22 HyperLink Boot Mode Parameter Table

30

32

34

36

22

24

26

28

14

16

18

20

Byte Offset

12

Name

Options

Description

Bit 0 Mode

0 = Host Mode (Direct boot mode)

1 = Boot Table Boot Mode

Bit 1 Configuration of PCIe

0 = HyperLink is configured by RBL

1 = HyperLink is not configured by RBL

Bits 15-2 Reserved

Number of Lanes

SerDes cfg msw

Number of lanes to be configured

HyperLink SerDes config word, MSW

SerDes cfg lsw HyperLink SerDes config word, LSW

SerDes CFG RX lane 0 cfg msw SerDes RX lane config word, MSW lane 0

SerDes CFG RXlane 0 cfg lsw

SerDes CFG TX lane 0 cfg msw

SerDes CFG TXlane 0 cfg lsw

SerDes CFG RX lane 1 cfg msw

SerDes CFG RXlane 1 cfg lsw

SerDes CFG TX lane 1 cfg msw

SerDes CFG TXlane 1 cfg lsw

SerDes CFG RX lane 2 cfg msw

SerDes RX lane config word, LSW, lane 0

SerDes TX lane config word, MSW lane 0

SerDes TX lane config word, LSW, lane 0

SerDes RX lane config word, MSW lane 1

SerDes RX lane config word, LSW, lane 1

SerDes TX lane config word, MSW lane 1

SerDes TX lane config word, LSW, lane 1

SerDes RX lane config word, MSW lane 2

38

40

42

44

SerDes CFG RXlane 2 cfg lsw SerDes RX lane config word, LSW, lane 2

SerDes CFG TX lane 2 cfg msw SerDes TX lane config word, MSW lane 2

SerDes CFG TXlane 2 cfg lsw SerDes TX lane config word, LSW, lane 2

SerDes CFG RX lane 3 cfg msw SerDes RX lane config word, MSW lane 3

46

48

SerDes CFG RXlane 3 cfg lsw

50 SerDes CFG TXlane 3 cfg lsw

End of Table 2-22

SerDes RX lane config word, LSW, lane 3

SerDes CFG TX lane 3 cfg msw SerDes TX lane config word, MSW lane 3

SerDes TX lane config word, LSW, lane 3

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Configured Through Boot

Configuration Pins

-

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Fixed and Floating-Point Digital Signal Processor

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2.5.3.8 DDR3 Configuration Table

The ROM Bootloader (RBL) also provides an option to configure the DDR table before loading the image into the external memory. More information on how to configure the DDR3, see the DSP Bootloader for KeyStone Devices

User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72 for more details. The configuration

table for DDR3 is shown below:

Table 2-23 DDR3 Boot Parameter Table

Byte Offset Name

0 configselect

52

56

60

64

36

40

44

48

20

24

28

32

4

8

12

16 pllprediv pllMult pllPostDiv sdRamConfig sdRamConfig2 sdRamRefreshctl sdRamTiming1 sdRamTiming2 sdRamTiming3

IpDfrNvmTiming powerMngCtl iODFTTestLogic performCountCfg performCountMstRegSel readIdleCtl sysVbusmIntEnSet

84

88

92

96

68

72

76

80 sdRamOutImpdedCalcfg tempAlertCfg ddrPhyCtl1 ddrPhyCtl2 proClassSvceMap mstId2ClsSvce1Map mstId2ClsSvce2Map eccCtl

100

104 eccRange1 eccRange2

108 rdWrtExcThresh

End of Table 2-23

Description

Selecting the configuration register below that to be set. Each field below is represented by one bit, each.

-

Configured Through Boot

Configuration Pins

PLL pre divider value (Should be the exact value not value -1)

PLL Multiplier value (Should be the exact value not value -1)

PLL post divider value (Should be the exact value not value -1)

SDRAM config register

-

-

-

-

SDRAM Config register

SDRAM Refresh Control Register

SDRAM Timing 1 Register

SDRAM Timing 2 Register

SDRAM Timing 3 Register

LP DDR2 NVM Timing Register

Power management Control Register

IODFT Test Logic Global Control Register

-

-

-

-

-

-

-

-

Performance Counter Config Register

Performance Counter Master Region Select Register

Read IDLE counter Register

System Interrupt Enable Set Register

SDRAM Output Impedance Calibration Config Register

Temperature Alert Configuration Register

DDR PHY Control Register 1

DDR PHY Control Register 1

Priority to Class of Service mapping Register

Master ID to Class of Service Mapping 1 Register

Master ID to Class of Service Mapping 2Register

ECC Control Register

ECC Address Range1 Register

ECC Address Range2 Register

Read Write Execution Threshold Register

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2.5.4 PLL Boot Configuration Settings

The PLL default settings are determined by the BOOTMODE[12:10] bits. The table below shows settings for various input clock frequencies.

Table 2-24 C66x DSP System PLL Configuration

(1)

800 MHz Device 1000 MHz Device 1200 MHz Device 1250 MHz Device PASS PLL = 350 MHz

(2)

BOOTMODE

[12:10]

0b000

0b001

0b010

0b011

0b100

0b101

Input Clock

Freq (MHz)

50.00

66.67

80.00

100.00

156.25

250.00

0b110 312.50

0b111 122.88

End of Table 2-24

0 31 800 0 39 1000 0 47 1200 0 49 1250 0 41 1050

0 23 800.04

0 29 1000.05

0 35 1200.06

1 74 1250.06 1 62 1050.053

0 19 800

0 15 800

24 255 800

4 31 800

24 127 800

47 624 800

0 24 1000

0 19 1000

4 63 1000

0 7 1000

4 31 1000

28 471 999.989

0 29 1200

0 23 1200

24 383 1200

4 47 1200

24 191 1200

31 624 1200

3

0 24

0

124 1250

0 9

0

2

1250

15 1250

7

1250

1250

3 104 1050

0 20 1050

24 335 1050

4 41 1050

24 167 1050

60 1249.28 11 204 1049.6

1 The PLL boot configuration of initial silicon 1.0 may support only 800 MHz, 1000 MHz, and 1200 MHz frequencies by default.

2 The PASS PLL generates 1050 MHz and is internally divided by 3 to supply 350 MHz to the packet accelerator.

OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=1, by default).

CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))

The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the PASS clock). See

Table 2-4

for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip divider (=3), feeds 350 MHz to the NETCP.

The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are

controlled by chip level MMRs. For details on how to set up the PLL see section 7.6

‘‘Main PLL and PLL Controller’’ on page 137. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) for KeyStone

Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

2.6 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

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Fixed and Floating-Point Digital Signal Processor

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2.7 Terminals

2.7.1 Package Terminals

Figure 2-11

shows the TMS320C6671CYP ball grid area (BGA) package (bottom view).

Figure 2-11 CYP 841-Pin BGA Package (Bottom View)

AH

AG

AF

AJ

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4

6 8 10 12 14 16 18 20 22 24 26 28

2.7.2 Pin Map

Figure 2-13

through Figure 2-16

show the TMS320C6671 pin assignments in four quadrants (A, B, C, and D).

Figure 2-12 Pin Map Quadrants (Bottom View)

A B

D C

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Device Overview 39

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Figure 2-13

1

Upper Left Quadrant—A (Bottom View)

2 3 4 5 6 7 8 9 10 11 12 13 14 15

AJ

VSS DVDD18 RSV05 PASSCLKN PASSCLKP

SRIOSGMII

CLKN

VSS PCIERXP1 PCIERXN1 VSS RIORXN0 RIORXP0 VSS RIORXP3 RIORXN3

AH

DVDD18 RSV04 RSV25 RSV24 PCIECLKN VSS PCIERXN0 PCIERXP0 VSS RIORXN1 RIORXP1 VSS RIORXP2 RIORXN2 VSS

AG

SPISCS0 SPISCS1 CORECLKP CORECLKN PCIECLKP

SRIOSGMII

CLKP

VSS PCIETXP1 PCIETXN1 VSS RIOTXN1 RIOTXP1 VSS RIOTXP2 RIOTXN2

AF

RSV22 CORESEL0 RSV20 VSS DVDD18 VSS PCIETXP0 PCIETXN0 VSS RIOTXN0 RIOTXP0 VSS RIOTXP3 RIOTXN3 VSS

AE

SPICLK

BOOT

COMPLETE

SYSCLKOUT PACLKSEL CORESEL3 CORESEL2 VSS VSS VSS VDDR2 VSS RSV15 VSS VDDR4 VSS

AD

UARTRXD SPIDIN SCL CORESEL1 AVDDA3 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2

AC

UARTTXD VSS DVDD18 SDA VSS AVDDA2 VSS VDDT2 RSV16 VDDT2 VSS VDDT2 VSS VDDT2 VSS

AB

SPIDOUT UARTRTS UARTCTS VSS DVDD18 VSS DVDD18 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2

AA

MCMTX

FLCLK

MCMTX

PMCLK

MCMTX

FLDAT

MCMTX

PMDAT

VSS DVDD18 VSS CVDD

Y

MCMREF

CLKOUTP

MCMCLKN

MCMRX

PMCLK

MCMRX

PMDAT

RSV12 VSS DVDD18 VSS

VSS CVDD VSS CVDD VSS CVDD VSS

CVDD VSS CVDD VSS CVDD VSS CVDD

W

MCMREF

CLKOUTN

MCMCLKP

MCMRX

FLCLK

MCMRX

FLDAT

RSV13 RSV14 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS

V

VSS VSS VSS VSS VDDR1 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1

U

VSS MCMRXN0 VSS MCMTXP1 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS

T

MCMRXN1 MCMRXP0 VSS MCMTXN1 MCMTXP2 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD

A

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Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Figure 2-14

16 17

Upper Right Quadrant—B (Bottom View)

18 19 20 21 22

VSS SGMII0RXP SGMII0RXN VSS

23 24 25 26 27 28 29

TR15 TR13 FSB1 CLKA1 TX02 TR01 FSA0 EMU16 DVDD18 VSS

AJ

SGMII1RXP SGMII1RXN VSS RSV08 TX16 TR16 TR14 CLKB1 TX04 TR05 TR00 EMU18 RSV01 DVDD18

AH

VSS SGMII0TXP SGMII0TXN VSS TX14 TR17 DVDD18 FSA1 TX03 CLKB0 FSB0 EMU15 EMU14 EMU12

AG

SGMII1TXP SGMII1TXN VSS RSV09 TX17 TX10 VSS TX07 TX05 CLKA0 DVDD18 EMU17 EMU11 EMU09

AF

VDDR3 VSS VDDT2 VSS TX15 TX13 TR10 TX06 TX00 TR07 VSS EMU10 EMU08 EMU07

AE

VSS VDDT2 VSS RSV17 HOUT TR11 TX11 TR02 TR03 TX01 EMU13 EMU06 EMU05 EMU04

AD

VDDT2 VSS VDDT2 VSS POR TR12 TX12 TR04 TR06 EMIFD15 EMU03 EMU02 EMU01 EMU00

AC

VSS VDDT2 VSS DVDD18 VSS DVDD18 VSS EMIFD12 EMIFD13 EMIFD09 EMIFD14 EMIFD05 DVDD18 EMIFD01

AB

CVDD VSS CVDD VSS RSV0B RSV0A CVDD VSS EMIFD10 EMIFD07 EMIFD06 EMIFD04 VSS EMIFD02

AA

VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFD11 EMIFD08 EMIFD03 EMIFD00 EMIFA22 EMIFA21

Y

CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFA20 EMIFA19 EMIFA18 EMIFA17 EMIFA15 EMIFA14 EMIFA16

W

VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFA13 EMIFA12 EMIFA11 EMIFA10 EMIFA08 EMIFA09

V

CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFA23 EMIFA07 EMIFA06 DVDD18 EMIFA04 EMIFA05 EMIFA02

U

VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFA01 EMIFA03 VSS EMIFA00 EMIFWAIT1 EMIFWAIT0

T

B

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Figure 2-15 Lower Right Quadrant—C (Bottom View)

C

CVDD1 VSS CVDD VSS CVDD VSS CVDD EMIFBE1 EMIFBE0 EMIFCE3 EMIFOE EMIFCE1 EMIFCE2 TDO

VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 EMIFWE EMIFCE0 EMIFRW TDI TRST TMS

R

P

CVDD VSS CVDD VSS CVDD1 VSS CVDD1 RSV03 RSV02 RESETFULL LRESET RESETSTAT DVDD18 TCK

N

VSS CVDD VSS CVDD VSS CVDD1 VSS RSV26 RSV27 NMI TIMO1

LRESET

NMIEN

VSS RESET

M

CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VCNTL0 TIMI0 TIMO0 TIMI1 GPIO15 GPIO11 GPIO12

L

VSS CVDD VSS CVDD VSS CVDD RSV10 VCNTL1 GPIO14 GPIO13 GPIO09 GPIO07 GPIO08 GPIO10

K

CVDD VSS CVDD VSS CVDD VSS RSV11 VCNTL2 GPIO06 GPIO04 GPIO03 GPIO05 GPIO01 GPIO02

J

VSS CVDD VSS CVDD VSS CVDD AVDDA1 VCNTL3 DVDD18 GPIO00 MDCLK

DDRSL

RATE1

RSV06 DDRCLKN

H

DVDD15 VSS DVDD15 VSS DVDD15 VSS PTV15 DVDD15 VSS RSV21 MDIO

DDRSL

RATE0

RSV07 DDRCLKP

G

VSS DVDD15 VSS DVDD15 DDRD25 DDRD27 DDRD17 DDRD16 DDRD08 DDRD07 DVDD15 VSS DVDD15 VSS

F

DDRA10 DDRA12 DDRCKE1 DDRCB00 VSS DDRD26 DDRD23 DDRD19 DDRD09 DDRD10 DDRD06 DDRD02 DDRD00 DDRDQM0

E

DDRA11 DDRA14 VSS DDRCB02 DVDD15 DDRD24 DDRD28 DVDD15 DDRD18 DDRD11 DDRD12 DDRD04 DDRD03 DDRD01

D

DDRA13 DDRA15 DDRCB05 DDRCB04 DDRCB01 DDRD29 DDRD31 VSS DDRD22 DVDD15 DDRD13 DDRDQM1 DDRDQS0P DDRDQS0N

C

DDRCLK

OUTN1

VSS DDRCB06 DDRDQS8N DDRCB03 DDRDQS3N DDRD30 DDRD21 DDRDQS2N VSS DDRD14 DDRDQS1N DDRD05 DVDD15

B

DDRCLK

OUTP1

DVDD15 DDRCB07 DDRDQS8P DDRDQM8 DDRDQS3P DDRDQM3 DDRD20 DDRDQS2P DDRDQM2 DDRD15 DDRDQS1P DVDD15 VSS

A

16 17 18 19 20 21 22 23 24 25 26 27 28 29

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Figure 2-16 Lower Left Quadrant—D (Bottom View)

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

D

R

MCMRXP1 VSS VSS VSS MCMTXN2 VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS

P

VSS MCMRXN3 VSS MCMTXP3 VSS VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD

N

MCMRXP2 MCMRXP3 VSS MCMTXN3 MCMTXP0 VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

VSS VSS MCMTXN0 VSS VDDT1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD

M

MCMRXN2 VSS

L

VSS VSS VSS VSS VSS VSS VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS

K

VSS

J

VSS

VSS

VSS

VSS VSS

VSS VSS

VSS VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDD1

VSS VSS VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD1 VSS

H

VSS VSS VSS VSS VSS VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD

G

VSS DVDD15 VSS DVDD15 VSS VSS VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS

F

DDRD63 DDRD60 DDRD61 DDRD56 DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DDRA03 DDRA02 DDRA08

E

DDRD62 DDRD58 DVDD15 DDRD53 VSS DDRD45 DDRD42 DDRD39 DDRD36 DDRD32 DDRRESET DDRWE DDRODT1 VREFSSTL DDRA09

D

DDRDQS7P DDRD57 VSS DDRD52 DVDD15 DDRD46 DDRD41 DVDD15 DDRD35 DDRD33 DDRCKE0 DDRCAS DDRODT0 VSS DDRA07

C

DDRDQS7N DDRD59 DDRD55 DDRD54 DDRD48 DDRD47 DDRD43 VSS DDRD37 DDRRAS DDRCE0 DDRCE1 DDRBA2 DVDD15 DDRA05

B

DVDD15 DDRDQM7 DDRDQS6P DDRD50 DDRDQM6 DDRDQS5P DDRD44 DDRD38 DDRDQS4N DDRD34 VSS

DDRCLK

OUTN0

DDRBA1 DDRA01 DDRA06

A

VSS DVDD15 DDRDQS6N DDRD51 DDRD49 DDRDQS5N DDRD40 DDRDQM5 DDRDQS4P DDRDQM4 DVDD15

DDRCLK

OUTP0

DDRBA0 DDRA00 DDRA04

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

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2.8 Terminal Functions

The terminal functions table (

Table 2-26 ) identifies the external signal names, the associated pin (ball) numbers, the

pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin

descriptions. This table is arranged by function. The power terminal functions table ( Table 2-27 ) lists the various

power supply pins and ground pins and gives functional pin descriptions.

Table 2-28 shows all pins arranged by

signal name.

Table 2-29 shows all pins arranged by ball number.

There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and

pullup/pulldown resistors, see section 3.4

‘‘Pullup/Pulldown Resistors’’ on page 94.

Use the symbol definitions in

Table 2-25 when reading Table 2-26 .

Table 2-25 I/O Functional Symbol Definitions

Functional

Symbol

IPD or IPU

Definition

Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k

 resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see the Hardware Design Guide for

KeyStone I Devices in

‘‘Related Documentation from Texas Instruments’’ on page 72.

Analog signal

Ground

A

GND

I

O

Input terminal

Output terminal

S Supply voltage

Z

End of Table 2-25

Three-state terminal or high impedance

Table 2-26

Column Heading

IPD/IPU

Type

Type

Type

Type

Type

Type

Table 2-26

Signal Name

LENDIAN †

BOOTMODE00 †

BOOTMODE01†

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

BOOTMODE09 †

BOOTMODE10 †

BOOTMODE11 †

BOOTMODE12 †

Terminal Functions — Signals and Control by Function (Part 1 of 13)

K29

L28

L29

K25

J29

J26

J25

J27

J24

Ball No. Type IPD/IPU Description

Boot Configuration Pins

H25

J28

IOZ

IOZ

UP

Down

Endian configuration pin (Pin shared with GPIO[0])

K27

K28

K26

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

Down

Down

Down

Down

Down

Down

Down

Down

See Section 2.5

‘‘Boot Modes Supported and PLL Settings’’ on page 24 for more details

(Pins shared with GPIO[1:13])

IOZ

IOZ

IOZ

IOZ

Down

Down

Down

Down

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PACLKSEL

HOUT

NMI

LRESET

LRESETNMIEN

CORESEL0

CORESEL1

CORESEL2

CORESEL3

RESETFULL

RESET

POR

RESETSTAT

BOOTCOMPLETE

CORECLKP

CORECLKN

SRIOSGMIICLKP

SRIOSGMIICLKN

DDRCLKP

DDRCLKN

PCIECLKP

PCIECLKN

MCMCLKP

MCMCLKN

PASSCLKP

PASSCLKN

AVDDA1

AVDDA2

AVDDA3

SYSCLKOUT

PTV15

Table 2-26

Signal Name

PCIESSMODE0 †

PCIESSMODE1 †

PCIESSEN †

Terminal Functions — Signals and Control by Function (Part 2 of 13)

M27

AF2

AD4

AE6

AE5

N25

M29

AC20

N27

AE2

H22

AC6

AD5

AE3

AE4

AD20

M25

N26

I

I

I

I

I

I

I

I

O

OZ

I

I

I

OZ

P

P

P

OZ

W2

Y2

AJ5

AJ4

G29

H29

AG5

AH5

AG3

AG4

AG6

AJ6

Ball No. Type IPD/IPU Description

K24

L27

L24 I

IOZ

IOZ

Down

Down

Down

PCIe Mode selection pins (Pins shared with GPIO[14:15])

PCIe module enable (Pin shared with TIMI0)

Clock / Reset

I

I

I

I

Core Clock Input to main PLL.

RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes

I

I

I

I

I

I

I

I

DDR Reference Clock Input to DDR PLL (

PCIe Clock Input to drive PCIe SerDes

HyperLink Reference Clock to drive the HyperLink SerDes

Network Coprocessor (PASS PLL) Reference Clock

Down

Down

UP

UP

UP

UP

Down

Down

Down

Down

UP

UP

UP

Down

SYS_CLK PLL Power Supply Pin

DDR_CLK PLL Power Supply Pin

PASS_CLK PLL Power Supply Pin

System Clock Output to be used as a general purpose output clock for debug purposes

PA clock select to choose between core clock and PASSCLK pins

Interrupt output pulse created by IPCGRH

Non-maskable Interrupt

Warm Reset

Enable for core selects

Select for the target core for LRESET and NMI. For more details see Table 7-46

Timing Requirements’’

Full Reset

on page 183

Warm Reset of non isolated portion on the IC

Power-on Reset

Reset Status Output

Boot progress indication output

‘‘NMI and Local Reset

G22 A PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50

.

Presently the recommended value for this 1% resistor is 45.3

.

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

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DDRDQS3N

DDRDQS4P

DDRDQS4N

DDRDQS5P

DDRDQS5N

DDRDQS6P

DDRDQS6N

DDRDQS7P

DDRDQS7N

DDRDQS8P

DDRDQS8N

DDRCB00

DDRCB01

DDRCB02

DDRCB03

DDRCB04

DDRCB05

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM4

DDRDQM5

DDRDQM6

DDRDQM7

DDRDQM8

DDRDQS0P

DDRDQS0N

DDRDQS1P

DDRDQS1N

DDRDQS2P

DDRDQS2N

DDRDQS3P

DDRCB06

DDRCB07

Table 2-26

Signal Name

Terminal Functions — Signals and Control by Function (Part 3 of 13)

Ball No. Type IPD/IPU Description

DDR

C20

D19

B20

C19

C18

C1

A19

B19

E19

A6

B3

A3

D1

B21

A9

B9

B6

B27

A24

B24

A21

A20

C28

C29

A27

A10

A8

B5

B2

E29

C27

A25

A22

B18

A18

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

OZ

IOZ

IOZ

IOZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

IOZ

IOZ

DDR EMIF Data Masks

DDR EMIF Data Strobe

DDR EMIF Check Bits

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Table 2-26

DDRD34

DDRD35

DDRD36

DDRD37

DDRD38

DDRD39

DDRD40

DDRD41

DDRD22

DDRD23

DDRD24

DDRD25

DDRD26

DDRD27

DDRD28

DDRD29

DDRD14

DDRD15

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

DDRD21

DDRD30

DDRD31

DDRD32

DDRD33

Signal Name

DDRD00

DDRD01

DDRD02

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

Terminal Functions — Signals and Control by Function (Part 4 of 13)

C9

B8

E8

B10

D9

E9

A7

D7

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

E21

F21

D22

C21

C24

E22

D21

F20

B22

C22

E10

D10

D24

E23

A23

B23

B26

A26

F23

F22

E25

D25

D26

C26

E26

F25

F24

E24

Ball No. Type IPD/IPU Description

E28

D29

IOZ

IOZ

E27

D28

D27

B28

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

DDR EMIF Data Bus

DDR EMIF Data Bus

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

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Device Overview 47

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

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Table 2-26

DDRCE0

DDRCE1

DDRBA0

DDRBA1

DDRBA2

DDRA00

DDRA01

DDRA02

DDRD56

DDRD57

DDRD58

DDRD59

DDRD60

DDRD61

DDRD62

DDRD63

DDRA03

DDRA04

DDRA05

DDRA06

Signal Name

DDRD42

DDRD43

DDRD44

DDRD45

DDRD46

DDRD47

DDRD48

DDRD49

DDRD50

DDRD51

DDRD52

DDRD53

DDRD54

DDRD55

DDRA07

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

Terminal Functions — Signals and Control by Function (Part 5 of 13)

D15

F15

E15

E16

D16

E17

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

C13

A14

B14

F14

C11

C12

A13

B13

F13

A15

C15

B15

F2

F3

E1

F1

F4

D2

E2

C2

D4

E4

C4

C3

C5

A5

B4

A4

B7

E6

D6

C6

Ball No. Type IPD/IPU Description

E7

C7

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

DDR EMIF Data Bus

DDR EMIF Chip Enables

DDR EMIF Bank Address

C16

D17

C17

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

DDR EMIF Address Bus

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EMIFRW

EMIFCE0

EMIFCE1

EMIFCE2

EMIFCE3

EMIFOE

EMIFWE

EMIFBE0

EMIFBE1

EMIFWAIT0

EMIFWAIT1

Table 2-26

Signal Name

DDRCAS

DDRRAS

DDRWE

DDRCKE0

DDRCKE1

DDRCLKOUTP0

DDRCLKOUTN0

DDRCLKOUTP1

DDRCLKOUTN1

DDRODT0

DDRODT1

DDRRESET

DDRSLRATE0

DDRSLRATE1

VREFSSTL

Terminal Functions — Signals and Control by Function (Part 6 of 13)

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

I

I

OZ

R25

R26

P24

R24

P26

P25

R27

R28

R23

T29

T28

E13

E11

G27

H27

E14

B12

A16

B16

D13

Ball No. Type IPD/IPU Description

D12

C10

OZ

OZ

DDR EMIF Column Address Strobe

DDR EMIF Row Address Strobe

E12

D11

E18

A12

OZ

OZ

OZ

OZ

DDR EMIF Write Enable

DDR EMIF Clock Enable

DDR EMIF Clock Enable

I

I

OZ

OZ

OZ

OZ

OZ

OZ

P

Down

Down

DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR Reset signal

DDR Slew rate control

Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)

EMIF16

UP

UP

UP

UP

UP

UP

UP

UP

UP

Down

Down

EMIF16 Control Signals

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Device Overview 49

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-26

EMIFA22

EMIFA23

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

EMIFD05

EMIFA14

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFD06

EMIFD07

EMIFD08

EMIFD09

Signal Name

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

EMIFA06

EMIFA07

EMIFA08

EMIFA09

EMIFA10

EMIFA11

EMIFA12

EMIFA13

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFD15

Terminal Functions — Signals and Control by Function (Part 7 of 13)

AA24

Y24

AB23

AB24

AB26

AC25

IOZ

IOZ

IOZ

IOZ

OZ

OZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Y28

U23

Y27

AB29

AA29

Y26

AA27

AB27

W25

W24

W23

Y29

W28

W27

W29

W26

AA26

AA25

Y25

AB25

V27

V26

V25

V24

U25

U24

V28

V29

Ball No. Type IPD/IPU Description

T27

T24

OZ

OZ

Down

Down

U29

T25

U27

U28

OZ

OZ

OZ

OZ

Down

Down

Down

Down

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

Down

Down

Down

Down

Down

Down

Down

Down

EMIF16 Address

EMIF16 Data

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

Down

Down

Down

Down

Down

Down

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EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU00

EMU01

EMU02

EMU03

EMU04

EMU05

EMU06

EMU07

EMU16

EMU17

EMU18

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

Table 2-26

Signal Name

J25

J27

J24

K27

H25

J28

J29

J26

K28

K26

K29

L28

L29

K25

K24

L27

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

Terminal Functions — Signals and Control by Function (Part 8 of 13)

Ball No. Type IPD/IPU Description

EMU

AE28

AF29

AE27

AF28

AG29

AD26

AG28

AG27

AC29

AC28

AC27

AC26

AD29

AD28

AD27

AE29

AJ27

AF27

AH27

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

UP

Emulation and Trace Port

General Purpose Input/Output (GPIO)

UP

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

General Purpose Input/Output

These GPIO pins have secondary functions assigned to them as mentioned in the ‘‘Boot

Configuration Pins’’ on page 44.

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Device Overview 51

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-26

Signal Name

MCMRXN0

MCMRXP0

MCMRXN1

MCMRXP1

MCMRXN2

MCMRXP2

MCMRXN3

MCMRXP3

MCMTXN0

MCMTXP0

MCMTXN1

MCMTXP1

MCMTXN2

MCMTXP2

MCMTXN3

MCMTXP3

MCMRXFLCLK

MCMRXFLDAT

MCMTXFLCLK

MCMTXFLDAT

MCMRXPMCLK

MCMRXPMDAT

MCMTXPMCLK

MCMTXPMDAT

MCMREFCLKOUTP

MCMREFCLKOUTN

Terminal Functions — Signals and Control by Function (Part 9 of 13)

Ball No. Type IPD/IPU Description

HyperLink

R5

T5

N4

P4

M5

N5

T4

U4

M1

N1

P2

N2

U2

T2

T1

R1

Y3

Y4

AA2

AA4

W3

W4

AA1

AA3

Y1

W1

O

O

O

O

O

O

O

O

I

I

I

I

I

I

I

I

O

O

I

I

O

O

I

I

O

O

Down

Down

Down

Down

Down

Down

Down

Down

Serial HyperLink Receive Data

Serial HyperLink Transmit Data

Serial HyperLink Sideband Signals

HyperLink Reference clock output for daisy chain connection

SCL

SDA

TCK

TDI

TDO

TMS

TRST

MDIO

MDCLK

AD3

AC4

N29

P27

R29

P29

P28

G26

H26

IOZ

IOZ

I

I

I

I

OZ

IOZ

O

UP

UP

UP

UP

Down

UP

Down

I

2

C

I

2

C Clock

I

2

C Data

JTAG

JTAG Clock Input

JTAG Data Input

JTAG Data Output

JTAG Test Mode Input

JTAG Reset

MDIO

MDIO Data

MDIO Clock

52 Device Overview Copyright 2014 Texas Instruments Incorporated

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Table 2-26

Signal Name

RIOTXN0

RIOTXP0

RIOTXN1

RIOTXP1

RIOTXN2

RIOTXP2

RIOTXN3

RIOTXP3

RIORXN0

RIORXP0

RIORXN1

RIORXP1

RIORXN2

RIORXP2

RIORXN3

RIORXP3

PCIERXN0

PCIERXP0

PCIERXN1

PCIERXP1

PCIETXN0

PCIETXP0

PCIETXN1

PCIETXP1

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SGMII1RXN

SGMII1RXP

SGMII1TXN

SGMII1TXP

VCNTL0

VCNTL1

VCNTL2

VCNTL3

AF10

AF11

AG11

AG12

AG15

AG14

AF14

AF13

AJ11

AJ12

AH10

AH11

AH14

AH13

AJ15

AJ14

Terminal Functions — Signals and Control by Function (Part 10 of 13)

Ball No. Type IPD/IPU Description

PCIe

AF8

AF7

AG9

AG8

AH7

AH8

AJ9

AJ8

O

O

O

O

I

I

I

I

PCIexpress Receive Data (2 links)

PCIexpress Transmit Data (2 links)

Serial RapidIO

O

O

O

O

O

O

O

O

I

I

I

I

I

I

I

I

Serial RapidIO Receive Data (2 links)

Serial RapidIO Receive Data (2 links)

Serial RapidIO Transmit Data (2 links)

Serial RapidIO Transmit Data (2 links)

SGMII

AJ18

AJ17

AG18

AG17

AH17

AH16

AF17

AF16

I

I

O

O

O

I

I

O

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

SmartReflex

L23

K23

J23

H23

OZ

OZ

OZ

OZ

Voltage Control Outputs to variable core power supply. These are open-drain output buffers.

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Device Overview 53

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

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TR04

TR05

TR06

TR07

TX00

TX01

TX02

TX03

CLKA0

CLKB0

FSA0

FSB0

TR00

TR01

TR02

TR03

TX04

TX05

TX06

TX07

CLKA1

CLKB1

FSA1

FSB1

Table 2-26

Signal Name

SPISCS0

SPISCS1

SPICLK

SPIDIN

SPIDOUT

TIMI0

TIMI1

TIMO0

TIMO1

Terminal Functions — Signals and Control by Function (Part 11 of 13)

AH24

AF24

AE23

AF23

AJ23

AH23

AC23

AH25

AC24

AE25

AE24

AD25

AJ24

AG24

AF25

AG25

AJ26

AG26

AH26

AJ25

AD23

AD24

OZ

OZ

OZ

OZ

I

I

I

I

I

I

I

I

I

I

I

I

L24

L26

L25

M26

Ball No. Type IPD/IPU Description

AG1

AG2

AE1

AD2

AB1

I

OZ

OZ

OZ

OZ

UP

UP

Down

Down

Down

SPI

SPI Interface Enable 0

SPI Interface Enable 1

SPI Clock

SPI Data In

SPI Data Out

Timer

I

I

OZ

OZ

Down

Down

Down

Down

Timer Inputs

Timer Outputs

TSIP

TSIP0 external clock A

TSIP0 external clock B

TSIP0 frame sync A

TSIP0 frame sync B

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

TSIP0 receive data

TSIP0 transmit data

I

I

OZ

OZ

OZ

OZ

Down

Down

Down

Down

Down

Down

TSIP1 external clock A

TSIP1 external clock B

AG23

AJ22 I

I Down

Down

TSIP1 frame sync A

TSIP1 frame sync B

54 Device Overview Copyright 2014 Texas Instruments Incorporated

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Fixed and Floating-Point Digital Signal Processor

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RSV13

RSV14

RSV15

RSV16

RSV17

RSV20

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RSV08

RSV09

RSV10

RSV11

RSV12

RSV21

RSV22

RSV24

Table 2-26

TR16

TR17

TX10

TX11

TX12

TX13

TX14

TX15

TX16

TX17

Signal Name

TR10

TR11

TR12

TR13

TR14

TR15

UARTRXD

UARTTXD

UARTCTS

UARTRTS

Terminal Functions — Signals and Control by Function (Part 12 of 13)

W5

W6

AE12

AC9

AD19

AF3

AH28

N24

N23

AH2

AJ3

H28

G28

AH19

AF19

K22

J22

Y5

O

A

O

O

IOZ

OZ

OZ

O

A

A

A

A

AD1

AC1

AB3

AB2

AH21

AG21

AF21

AD22

AC22

AE21

AG20

AE20

AH20

AF20

Ball No. Type IPD/IPU Description

AE22

AD21

I

I

Down

Down

AC21

AJ21

AH22

AJ20

I

I

I

I

Down

Down

Down

Down

TSIP1 receive data

I

I

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

TSIP1 transmit data

I

I

OZ

OZ

Down

Down

Down

Down

Down

Down

Down

UART

UART Serial Data In

UART Serial Data Out

UART Clear To Send

UART Request To Send

Reserved

Reserved - Pullup to DVDD18

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - Connect to GND

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

G25

AF1

AH4

A

A

A

A

A

OZ

OZ

OZ

O

Down

Down

Down

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

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Device Overview 55

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-26 Terminal Functions — Signals and Control by Function (Part 13 of 13)

Signal Name

RSV25

RSV26

RSV27

RSV0A

RSV0B

End of Table 2-26

Ball No. Type IPD/IPU Description

AH3

M23

O

IOZ

Reserved - leave unconnected

Reserved - leave unconnected

M24

AA21

AA20

IOZ

A

A

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

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Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-27 Terminal Functions — Power and Ground

Supply

AVDDA1

AVDDA2

AVDDA3

CVDD

CVDD1

DVDD15

DVDD18

Ball No.

H22

AC6

AD5

Volts Description

1.8

1.8

1.8

H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16,

L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19,

P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11,

V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12,

AA14, AA16, AA18, AA22

0.9 to

1.1

PLL Supply - CORE_PLL

PLL Supply - DDR3_PLL

PLL Supply - PASS_PLL

SmartReflex core supply voltage

J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16,

V13, V15, W12, W14, W16

1.0

A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28,

G2, G4, G8, G10, G12, G14, G16, G18, G20, G23

1.5

H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26,

AG22, AH1, AH29, AJ2, AJ28

1.8

Fixed core supply voltage for memory array

DDR IO supply

IO supply

VDDR1

VDDR2

VDDR3

VDDR4

VDDT1

V5

AE10

AE16

AE14

M7, N6, P7, R6, T7, U6, V7

1.5

1.5

1.5

1.5

1.0

HyperLink SerDes regulator supply

PCIe SerDes regulator supply

SGMII SerDes regulator supply

SRIO SerDes regulator supply

HyperLink SerDes termination supply

VDDT2 AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13,

AD15, AD17, AE18

E14

1.0

SGMII/SRIO/PCIe SerDes termination supply

0.75

DDR3 reference voltage VREFSSTL

VSS A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1,

G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24, H1, H2, H3, H4, H5, H6, H8, H10, H12,

H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6,

K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2,

M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17,

N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13,

R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11,

U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9,

W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9,

AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18,

AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14,

AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15,

AF18, AF22, AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10,

AJ13, AJ16, AJ19, AJ29

End of Table 2-27

GND Ground

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Device Overview 57

Table 2-28

Signal Name

AVDDA1

AVDDA2

AVDDA3

BOOTCOMPLETE

BOOTMODE00 †

BOOTMODE01†

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

BOOTMODE09 †

BOOTMODE10 †

BOOTMODE11 †

BOOTMODE12 †

CLKA0

CLKA1

CLKB0

CLKB1

CORECLKN

CORECLKP

CORESEL0

CORESEL1

CORESEL2

CORESEL3

CVDD

CVDD

Terminal Functions

— By Signal Name

(Part 1 of 13)

K28

K26

K29

L28

J25

J27

J24

K27

AE2

J28

J29

J26

Ball Number

H22

AC6

AD5

L29

K25

AF25

AJ23

AG25

AH23

AG4

AG3

AF2

AD4

AE6

AE5

H7, H9, H11, H13,

H15, H17, H19, H21,

J10, J12, J16, J18,

J20, K11, K17, K19,

K21, L10, L12, L16,

L18, M11, M13,

M15, M17, M19, N8,

N10, N12, N14,

N16, N18, P9, P11,

P13, P15, P17, P19,

P21, R8, R10, R18,

R20, R22, T9, T11,

T13, T15, T17, T19,

T21, U8, U10, U18,

U20, U22, V9, V11,

V17, V19, V21, W8,

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DDRBA0

DDRBA1

DDRBA2

DDRCAS

DDRCB00

DDRCB01

DDRCB02

DDRCB03

DDRCB04

DDRCB05

DDRCB06

DDRCB07

DDRCE0

DDRCE1

DDRCKE0

DDRCKE1

DDRCLKN

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

DDRA00

DDRA01

DDRA02

DDRA03

DDRA04

DDRA05

DDRA06

DDRA07

Table 2-28

Signal Name

CVDD

CVDD1

Terminal Functions

— By Signal Name

(Part 2 of 13)

D19

B20

C19

C18

C13

D12

E19

C20

D17

C17

A13

B13

E16

D16

E17

C16

B18

A18

C11

C12

D11

E18

H29

B15

D15

F15

E15

F14

F13

A15

C15

Ball Number

W10, W18, W20,

W22, Y9, Y11, Y13,

Y15, Y17, Y19, Y21,

AA8, AA10, AA12,

AA14, AA16, AA18,

AA22

J8, J14, K7, K9, K13,

K15, L8, L14, L20,

L22, M9, M21, N20,

N22, R12, R14, R16,

U12, U14, U16, V13,

V15, W12, W14,

W16

A14

B14

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-28 Terminal Functions

— By Signal Name

(Part 3 of 13)

C21

B22

C22

E10

D10

B10

D9

E9

B23

C24

E22

D21

F22

D24

E23

A23

F20

E21

F21

D22

C26

B26

A26

F23

E24

E25

D25

D26

B28

E26

F25

F24

D29

E27

D28

D27

Ball Number

B12

B16

A12

A16

G29

E28

DDRD29

DDRD30

DDRD31

DDRD32

DDRD33

DDRD34

DDRD35

DDRD36

DDRD17

DDRD18

DDRD19

DDRD20

DDRD21

DDRD22

DDRD23

DDRD24

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

DDRD14

DDRD15

DDRD16

DDRD25

DDRD26

DDRD27

DDRD28

Signal Name

DDRCLKOUTN0

DDRCLKOUTN1

DDRCLKOUTP0

DDRCLKOUTP1

DDRCLKP

DDRD00

DDRD01

DDRD02

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

Device Overview 58

Table 2-28 Terminal Functions

— By Signal Name

(Part 4 of 13)

B27

A27

B24

A24

A8

B5

B2

A20

C29

C28

F1

E29

C27

A25

C2

F2

F3

E1

A22

A10

C3

F4

D2

E2

A4

D4

E4

C4

C6

C5

A5

B4

C7

B7

E6

D6

E8

A7

D7

E7

Ball Number

C9

B8

DDRD51

DDRD52

DDRD53

DDRD54

DDRD55

DDRD56

DDRD57

DDRD58

DDRD59

DDRD60

DDRD61

DDRD62

DDRD63

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM4

Signal Name

DDRD37

DDRD38

DDRD39

DDRD40

DDRD41

DDRD42

DDRD43

DDRD44

DDRD45

DDRD46

DDRD47

DDRD48

DDRD49

DDRD50

DDRDQM5

DDRDQM6

DDRDQM7

DDRDQM8

DDRDQS0N

DDRDQS0P

DDRDQS1N

DDRDQS1P

DDRDQS2N

DDRDQS2P

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

EMIFA06

EMIFA07

EMIFA08

EMIFA09

EMIFA10

EMIFA11

EMIFA12

Table 2-28

Signal Name

DDRDQS3N

DDRDQS3P

DDRDQS4N

DDRDQS4P

DDRDQS5N

DDRDQS5P

DDRDQS6N

DDRDQS6P

DDRDQS7N

DDRDQS7P

DDRDQS8N

DDRDQS8P

DDRODT0

DDRODT1

DDRRAS

DDRRESET

DDRSLRATE0

DDRSLRATE1

DDRWE

DVDD15

DVDD18

Terminal Functions

— By Signal Name

(Part 5 of 13)

U25

U24

V28

V29

V27

V26

V25

B19

A19

D13

E13

A3

B3

C1

D1

B9

A9

A6

B6

Ball Number

B21

A21

C10

E11

G27

H27

E12

A2, A11, A17, A28,

B1, B29, C14, C25,

D5, D8, D20, D23,

E3, F5, F7, F9, F11,

F17, F19, F26, F28,

G2, G4, G8, G10,

G12, G14, G16, G18,

G20, G23

U29

T25

U27

U28

H24, N28, P23, T23,

U26, V23, Y7, Y23,

AA6, AB5, AB7,

AB19, AB21, AB28,

AC3, AF5, AF26,

AG22, AH1, AH29,

AJ2, AJ28

T27

T24

59 Device Overview Copyright 2014 Texas Instruments Incorporated

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Table 2-28 Terminal Functions

— By Signal Name

(Part 6 of 13)

AC25

R26

P26

T29

T28

P24

AB27

AA26

AA25

Y25

AB25

AA24

Y24

AB23

AB24

AB26

R27

R28

R25

Y27

AB29

AA29

Y26

AA27

U23

R24

R23

P25

W24

W23

Y29

Y28

Ball Number

V24

W28

W27

W29

W26

W25

AC29

AC28

AC27

AC26

EMIFD05

EMIFD06

EMIFD07

EMIFD08

EMIFD09

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFCE1

EMIFCE2

EMIFCE3

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

Signal Name

EMIFA13

EMIFA14

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23

EMIFBE0

EMIFBE1

EMIFCE0

EMIFD15

EMIFOE

EMIFRW

EMIFWAIT0

EMIFWAIT1

EMIFWE

EMU00

EMU01

EMU02

EMU03

Table 2-28

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

EMU18

FSA0

FSA1

FSB0

FSB1

GPIO00

GPIO01

GPIO02

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

Signal Name

EMU04

EMU05

EMU06

EMU07

EMU08

EMU09

GPIO13

GPIO14

GPIO15

HOUT

LENDIAN †

LRESETNMIEN

LRESET

MCMCLKN

MCMCLKP

MCMREFCLKOUTN

Terminal Functions

— By Signal Name

(Part 7 of 13)

N26

Y2

W2

W1

K25

K24

L27

AD20

H25

M27

K27

K28

K26

K29

J26

J25

J27

J24

L28

L29

AH27

AJ26

AG23

AG26

AJ22

H25

J28

J29

AE27

AF28

AG29

AD26

AG28

AG27

AJ27

AF27

Ball Number

AD29

AD28

AD27

AE29

AE28

AF29

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-28

MCMTXFLDAT

MCMTXN0

MCMTXN1

MCMTXN2

MCMTXN3

MCMTXP0

MCMTXP1

MCMTXP2

MCMTXP3

MCMTXPMCLK

MCMTXPMDAT

MDCLK

MDIO

NMI

PACLKSEL

PASSCLKN

PASSCLKP

PCIECLKN

Signal Name

MCMREFCLKOUTP

MCMRXFLCLK

MCMRXFLDAT

MCMRXN0

MCMRXN1

MCMRXN2

MCMRXN3

MCMRXP0

MCMRXP1

MCMRXP2

MCMRXP3

MCMRXPMCLK

MCMRXPMDAT

MCMTXFLCLK

PCIECLKP

PCIERXN0

PCIERXN1

PCIERXP0

PCIERXP1

PCIESSMODE0 †

PCIESSMODE1 †

PCIESSEN †

PCIETXN0

PCIETXN1

Terminal Functions

— By Signal Name

(Part 8 of 13)

L27

L24

AF8

AG9

AG5

AH7

AJ9

AH8

AJ8

K24

G26

M25

AE4

AJ4

P4

AA2

AA4

H26

AJ5

AH5

N4

N5

U4

T5

AA3

M5

T4

R5

N2

Y3

Y4

AA1

P2

T2

R1

N1

Ball Number

Y1

W3

W4

U2

T1

M1

Table 2-28 Terminal Functions

— By Signal Name

(Part 9 of 13)

AA21

AA20

K22

J22

Y5

W5

AH2

AJ3

H28

G28

AF13

AH28

N24

N23

AH19

AF19

AJ14

AF10

AG11

AG15

AF14

AF11

AG12

AG14

M29

AJ11

AH10

AH14

AJ15

AJ12

AH11

AH13

Ball Number

AF7

AG8

AC20

G22

N25

N27

W6

AE12

AC9

AD19

RSV0A

RSV0B

RSV10

RSV11

RSV12

RSV13

RIOTXP3

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RSV08

RSV09

RIORXP3

RIOTXN0

RIOTXN1

RIOTXN2

RIOTXN3

RIOTXP0

RIOTXP1

RIOTXP2

Signal Name

PCIETXP0

PCIETXP1

POR

PTV15

RESETFULL

RESETSTAT

RESET

RIORXN0

RIORXN1

RIORXN2

RIORXN3

RIORXP0

RIORXP1

RIORXP2

RSV14

RSV15

RSV16

RSV17

Device Overview 60

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-28 Terminal Functions

— By Signal Name

(Part 10 of 13)

AJ25

AD23

AD24

AC23

AH25

AC24

L24

L26

L25

M26

AE3

N29

P27

R29

P29

AH26

AG1

AG2

AJ6

AG6

AF16

AE1

AD2

AB1

AC4

AJ18

AJ17

AG18

AG17

AH17

AH16

AF17

Ball Number

AF3

G25

AF1

AH4

AH3

AD3

AE25

AE22

AD21

AC21

TR01

TR02

TR03

TR04

TR05

TR06

SGMII1TXP

SPICLK

SPIDIN

SPIDOUT

SPISCS0

SPISCS1

SRIOSGMIICLKN

SRIOSGMIICLKP

SYSCLKOUT

TCK

TDI

TDO

TIMI0

TIMI1

TIMO0

TIMO1

TMS

TR00

Signal Name

RSV20

RSV21

RSV22

RSV24

RSV25

SCL

SDA

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SGMII1RXN

SGMII1RXP

SGMII1TXN

TR07

TR10

TR11

TR12

Table 2-28

VDDT2

VREFSSTL

Terminal Functions

— By Signal Name

(Part 11 of 13)

L23

K23

J23

H23

AB3

AB2

AD1

AC1

V5

AE10

AF21

AD22

AC22

AE21

AG20

AE20

AH20

AF20

AE24

AD25

AJ24

AG24

AH24

AF24

AE23

AF23

Ball Number

AJ21

AH22

AJ20

AH21

AG21

P28

AE16

AE14

M7, N6, P7, R6, T7,

U6, V7

AB9, AB11, AB13,

AB15, AB17, AC8,

AC10, AC12, AC14,

AC16, AC18, AD7,

AD9, AD11, AD13,

AD15, AD17, AE18

E14

TX10

TX11

TX12

TX13

TX14

TX15

TX16

TX17

UARTCTS

UARTRTS

UARTRXD

UARTTXD

VCNTL0

VCNTL1

VCNTL2

VCNTL3

VDDR1

VDDR2

TX00

TX01

TX02

TX03

TX04

TX05

TX06

TX07

Signal Name

TR13

TR14

TR15

TR16

TR17

TRST

VDDR3

VDDR4

VDDT1

61 Device Overview Copyright 2014 Texas Instruments Incorporated

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Table 2-28

Signal Name

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Terminal Functions

— By Signal Name

(Part 12 of 13)

N11, N13, N15, N17,

N19, N21, P1, P3,

P5, P6, P8, P10, P12,

P14, P16, P18, P20,

P22, R2, R3, R4, R7,

R9, R11, R13, R15,

R17, R19, R21, T3,

T6, T8, T10, T12,

T14, T16, T18, T20,

T22, T26, U1, U3,

U5, U7, U9, U11,

U13, U15, U17, U19,

U21, V1, V2, V3, V4,

V6, V8, V10, V12,

V14, V16, V18, V20,

V22, W7, W9, W11,

W13, W15, W17,

W19, W21, Y6, Y8,

Y10, Y12, Y14, Y16,

Y18, Y20, Y22, AA5,

AA7, AA9, AA11,

AA13, AA15, AA17,

AA19, AA23, AA28,

AB4, AB6, AB8,

AB10, AB12, AB14,

AB16, AB18, AB20,

AB22, AC2, AC5,

AC7, AC11, AC13,

AC15, AC17, AC19,

AD6, AD8, AD10,

AD12, AD14, AD16,

AD18, AE7, AE8,

Ball Number

A1, A29, B11, B17,

B25, C8, C23, D3,

D14, D18, E5, E20,

F6, F8, F10, F12,

F16, F18, F27, F29,

G1, G3, G5, G6, G7,

G9, G11, G13, G15,

G17, G19, G21, G24,

H1, H2, H3, H4, H5,

H6, H8, H10, H12,

H14, H16, H18, H20,

J1, J2, J3, J4, J5, J6,

J7, J9, J11, J13, J15,

J17, J19, J21, K1, K2,

K3, K4, K5, K6, K8,

K10, K12, K14, K16,

K18, K20, L1, L2, L3,

L4, L5, L6, L7, L9,

L11, L13, L15, L17,

L19, L21, M2, M3,

M4, M6, M8, M10,

M12, M14, M16,

M18, M20, M22,

M28, N3, N7, N9,

Table 2-28

Signal Name

VSS

VSS

Terminal Functions

— By Signal Name

(Part 13 of 13)

Ball Number

AE9, AE11, AE13,

AE15, AE17, AE19,

AE26, AF4, AF6,

AF9, AF12, AF15,

AF18, AF22AG7,

AG10, AG13, AG16,

AG19, AH6, AH9,

AH12, AH15, AH18,

AJ1, AJ7, AJ10,

AJ13, AJ16, AJ19,

AJ29

End of Table 2-28

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Copyright 2014 Texas Instruments Incorporated

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Device Overview 62

Table 2-29 Terminal Functions

— By Ball Number

(Part 1 of 21)

DDRCLKOUTP1

DVDD15

DDRCB07

DDRDQS8P

DDRDQM8

DDRDQS3P

DDRDQM3

DDRD20

DDRDQS2P

DDRDQM2

DDRD15

DDRDQS1P

DVDD15

VSS

DVDD15

DDRDQM7

DDRDQS6P

DDRD50

Signal Name

VSS

DVDD15

DDRDQS6N

DDRD51

DDRD49

DDRDQS5N

DDRD40

DDRDQM5

DDRDQS4P

DDRDQM4

DVDD15

DDRCLKOUTP0

DDRBA0

DDRA00

DDRA04

DDRDQM6

DDRDQS5P

DDRD44

DDRD38

DDRDQS4N

DDRD34

VSS

DDRCLKOUTN0

DDRBA1

B5

B6

B7

B8

B9

B10

A28

A29

B1

B2

A24

A25

A26

A27

B3

B4

A20

A21

A22

A23

A16

A17

A18

A19

A12

A13

A14

A15

A8

A9

A10

A11

A4

A5

A6

A7

Ball Number

A1

A2

A3

B11

B12

B13

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 2 of 21)

DDRD43

VSS

DDRD37

DDRRAS

DDRCE0

DDRCE1

DDRBA2

DVDD15

DDRD05

DVDD15

DDRDQS7N

DDRD59

DDRD55

DDRD54

DDRD48

DDRD47

DDRA05

DDRA13

DDRA15

DDRCB05

Signal Name

DDRA01

DDRA06

DDRCLKOUTN1

VSS

DDRCB06

DDRDQS8N

DDRCB03

DDRDQS3N

DDRD30

DDRD21

DDRDQS2N

VSS

DDRD14

DDRDQS1N

DDRCB04

DDRCB01

DDRD29

DDRD31

VSS

DDRD22

DVDD15

DDRD13

C19

C20

C21

C22

C23

C24

C25

C26

C11

C12

C13

C14

C7

C8

C9

C10

C15

C16

C17

C18

C3

C4

C5

C6

B28

B29

C1

C2

B24

B25

B26

B27

B20

B21

B22

B23

Ball Number

B14

B15

B16

B17

B18

B19

63 Device Overview

Table 2-29 Terminal Functions

— By Ball Number

(Part 3 of 21)

DVDD15

DDRD53

VSS

DDRD45

DDRD42

DDRD39

DDRD36

DDRD32

DVDD15

DDRD24

DDRD28

DVDD15

DDRD18

DDRD11

DDRD12

DDRD04

DDRCAS

DDRODT0

VSS

DDRA07

DDRA11

DDRA14

VSS

DDRCB02

DDRD03

DDRD01

DDRD62

DDRD58

Signal Name

DDRDQM1

DDRDQS0P

DDRDQS0N

DDRDQS7P

DDRD57

VSS

DDRD52

DVDD15

DDRD46

DDRD41

DVDD15

DDRD35

DDRD33

DDRCKE0

E6

E7

E8

E3

E4

E5

E9

E10

D24

D25

D26

D27

D20

D21

D22

D23

D28

D29

E1

E2

D16

D17

D18

D19

D12

D13

D14

D15

D8

D9

D10

D11

D4

D5

D6

D7

Ball Number

C27

C28

C29

D1

D2

D3

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Table 2-29 Terminal Functions

— By Ball Number

(Part 4 of 21)

DDRD56

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DDRA03

DDRD10

DDRD06

DDRD02

DDRD00

DDRDQM0

DDRD63

DDRD60

DDRD61

Signal Name

DDRRESET

DDRWE

DDRODT1

VREFSSTL

DDRA09

DDRA10

DDRA12

DDRCKE1

DDRCB00

VSS

DDRD26

DDRD23

DDRD19

DDRD09

DDRA02

DDRA08

VSS

DVDD15

VSS

DVDD15

DDRD25

DDRD27

DDRD17

DDRD16

F20

F21

F22

F23

F14

F15

F16

F17

F18

F19

F8

F9

F10

F11

F4

F5

F6

F7

F12

F13

E29

F1

F2

F3

E25

E26

E27

E28

E21

E22

E23

E24

E17

E18

E19

E20

Ball Number

E11

E12

E13

E14

E15

E16

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Table 2-29 Terminal Functions

— By Ball Number

(Part 5 of 21)

VSS

DVDD15

VSS

DVDD15

VSS

PTV15

DVDD15

VSS

RSV21

MDIO

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

Signal Name

DDRD08

DDRD07

DVDD15

VSS

DVDD15

VSS

VSS

DVDD15

VSS

DVDD15

VSS

VSS

VSS

DVDD15

DDRSLRATE0

RSV07

DDRCLKP

VSS

VSS

VSS

VSS

VSS

VSS

CVDD

H4

H5

H6

H7

H1

H2

H3

G27

G28

G29

G21

G22

G23

G24

G17

G18

G19

G20

G25

G26

G13

G14

G15

G16

G9

G10

G11

G12

G5

G6

G7

G8

G1

G2

G3

G4

Ball Number

F24

F25

F26

F27

F28

F29

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 6 of 21)

AVDDA1

VCNTL3

DVDD18

GPIO00

LENDIAN †

MDCLK

DDRSLRATE1

RSV06

VSS

VSS

VSS

VSS

DDRCLKN

VSS

VSS

VSS

CVDD1

VSS

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

Signal Name

VSS

CVDD

VSS

CVDD

VSS

CVDD

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

J16

J17

J18

J19

J10

J11

J12

J13

J14

J15

J4

J5

J6

J7

H29

J1

J2

J3

J8

J9

H25

H26

H27

H28

H22

H23

H24

H25

H18

H19

H20

H21

H14

H15

H16

H17

Ball Number

H8

H9

H10

H11

H12

H13

Device Overview 64

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 7 of 21)

CVDD

VSS

CVDD

VSS

CVDD

RSV10

CVDD1

VSS

CVDD1

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

VSS

VSS

VSS

VSS

GPIO02

BOOTMODE01†

VSS

VSS

Signal Name

CVDD

VSS

RSV11

VCNTL2

GPIO06

BOOTMODE05 †

GPIO04

BOOTMODE03 †

GPIO03

BOOTMODE02 †

GPIO05

BOOTMODE04 †

GPIO01

BOOTMODE00 †

VCNTL1

GPIO14

PCIESSMODE0 †

GPIO13

K23

K24

K24

K25

K17

K18

K19

K20

K21

K22

K11

K12

K13

K14

K7

K8

K9

K10

K15

K16

K3

K4

K5

K6

J29

J29

K1

K2

J27

J27

J28

J28

J25

J25

J26

J26

Ball Number

J20

J21

J22

J23

J24

J24

Table 2-29 Terminal Functions

— By Ball Number

(Part 8 of 21)

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VCNTL0

VSS

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

Signal Name

BOOTMODE12 †

GPIO09

BOOTMODE08 †

GPIO07

BOOTMODE06 †

GPIO08

VSS

VSS

VSS

VSS

BOOTMODE07 †

GPIO10

BOOTMODE09 †

VSS

TIMI0

PCIESSEN †

TIMO0

TIMI1

GPIO15

PCIESSMODE1 †

GPIO11

BOOTMODE10 †

GPIO12

BOOTMODE11 †

L28

L28

L29

L29

L24

L24

L25

L26

L27

L27

L18

L19

L20

L21

L14

L15

L16

L17

L22

L23

L10

L11

L12

L13

L6

L7

L8

L9

L2

L3

L4

L5

K28

K29

K29

L1

Ball Number

K25

K26

K26

K27

K27

K28

65 Device Overview

Table 2-29 Terminal Functions

— By Ball Number

(Part 9 of 21)

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

NMI

TIMO1

LRESETNMIEN

VSS

RESET

MCMRXP2

MCMRXP3

VSS

MCMTXN3

MCMTXP0

VDDT1

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

Signal Name

MCMRXN2

VSS

VSS

VSS

MCMTXN0

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

N12

N13

N14

N15

N6

N7

N8

N9

N10

N11

M29

N1

N2

N3

M25

M26

M27

M28

N4

N5

M19

M20

M21

M22

M15

M16

M17

M18

M11

M12

M13

M14

M7

M8

M9

M10

Ball Number

M1

M2

M3

M4

M5

M6

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Table 2-29 Terminal Functions

— By Ball Number

(Part 10 of 21)

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

VSS

MCMRXN3

VSS

MCMTXP3

VSS

VSS

VDDT1

VSS

Signal Name

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

RSV03

RSV02

RESETFULL

LRESET

RESETSTAT

DVDD18

TCK

CVDD

VSS

CVDD

VSS

DVDD18

EMIFWE

EMIFCE0

EMIFRW

TDI

TRST

P25

P26

P27

P28

P19

P20

P21

P22

P23

P24

P13

P14

P15

P16

P9

P10

P11

P12

P17

P18

P5

P6

P7

P8

P1

P2

P3

P4

N26

N27

N28

N29

N22

N23

N24

N25

Ball Number

N16

N17

N18

N19

N20

N21

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Table 2-29 Terminal Functions

— By Ball Number

(Part 11 of 21)

CVDD1

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFBE1

EMIFBE0

EMIFCE3

EMIFOE

EMIFCE1

EMIFCE2

TDO

MCMRXN1

MCMRXP0

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

Signal Name

TMS

MCMRXP1

VSS

VSS

VSS

MCMTXN2

VSS

MCMTXN1

MCMTXP2

VSS

VDDT1

VSS

CVDD

VSS

CVDD

VSS

T9

T10

T11

T12

T6

T7

T8

T3

T4

T5

R26

R27

R28

R29

R22

R23

R24

R25

T1

T2

R18

R19

R20

R21

R14

R15

R16

R17

R10

R11

R12

R13

R6

R7

R8

R9

R2

R3

R4

R5

Ball Number

P29

R1

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 12 of 21)

VDDT1

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

EMIFA00

EMIFWAIT1

EMIFWAIT0

VSS

MCMRXN0

VSS

MCMTXP1

VSS

Signal Name

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

EMIFA01

EMIFA03

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFA23

EMIFA07

EMIFA06

U22

U23

U24

U25

U16

U17

U18

U19

U20

U21

U10

U11

U12

U13

U6

U7

U8

U9

U14

U15

U2

U3

U4

U5

T27

T28

T29

U1

T23

T24

T25

T26

T19

T20

T21

T22

Ball Number

T13

T14

T15

T16

T17

T18

Device Overview 66

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 13 of 21)

CVDD

VSS

CVDD

VSS

DVDD18

EMIFA13

EMIFA12

EMIFA11

EMIFA10

EMIFA08

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

CVDD

VSS

VSS

VSS

VDDR1

VSS

VDDT1

VSS

CVDD

VSS

Signal Name

DVDD18

EMIFA04

EMIFA05

EMIFA02

VSS

VSS

EMIFA09

MCMREFCLKOUTN

MCMCLKP

MCMRXFLCLK

MCMRXFLDAT

RSV13

RSV14

VSS

CVDD

VSS

W6

W7

W8

W9

V29

W1

W2

W3

W4

W5

V23

V24

V25

V26

V19

V20

V21

V22

V27

V28

V15

V16

V17

V18

V11

V12

V13

V14

V7

V8

V9

V10

V3

V4

V5

V6

Ball Number

U26

U27

U28

U29

V1

V2

Table 2-29 Terminal Functions

— By Ball Number

(Part 14 of 21)

CVDD

VSS

CVDD

VSS

CVDD

VSS

Signal Name

CVDD

VSS

CVDD1

VSS

CVDD1

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

EMIFA20

EMIFA19

EMIFA18

EMIFA17

EMIFA15

EMIFA14

EMIFA16

MCMREFCLKOUTP

MCMCLKN

MCMRXPMCLK

MCMRXPMDAT

RSV12

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

Y19

Y20

Y21

Y22

Y13

Y14

Y15

Y16

Y17

Y18

Y7

Y8

Y9

Y10

Y3

Y4

Y5

Y6

Y11

Y12

W28

W29

Y1

Y2

W24

W25

W26

W27

W20

W21

W22

W23

W16

W17

W18

W19

Ball Number

W10

W11

W12

W13

W14

W15

67 Device Overview

Table 2-29 Terminal Functions

— By Ball Number

(Part 15 of 21)

CVDD

VSS

CVDD

VSS

RSV0B

RSV0A

CVDD

VSS

EMIFD10

EMIFD07

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

Signal Name

DVDD18

EMIFD11

EMIFD08

EMIFD03

EMIFD00

EMIFA22

EMIFA21

MCMTXFLCLK

MCMTXPMCLK

MCMTXFLDAT

MCMTXPMDAT

VSS

DVDD18

VSS

EMIFD06

EMIFD04

VSS

EMIFD02

SPIDOUT

UARTRTS

UARTCTS

VSS

DVDD18

VSS

AB3

AB4

AB5

AB6

AA26

AA27

AA28

AA29

AB1

AB2

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA4

AA5

AA6

AA7

Y29

AA1

AA2

AA3

Ball Number

Y23

Y24

Y25

Y26

Y27

Y28

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Table 2-29 Terminal Functions

— By Ball Number

(Part 16 of 21)

DVDD18

VSS

EMIFD12

EMIFD13

EMIFD09

EMIFD14

EMIFD05

DVDD18

EMIFD01

UARTTXD

VSS

DVDD18

SDA

VSS

AVDDA2

VSS

VDDT2

RSV16

Signal Name

DVDD18

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

DVDD18

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

AC10

AC11

AC12

AC13

AC14

AC15

AC4

AC5

AC6

AC7

AB29

AC1

AC2

AC3

AC8

AC9

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

Ball Number

AB7

AB8

AB9

AB10

AB11

AB12

AC16

AC17

AC18

AC19

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Table 2-29 Terminal Functions

— By Ball Number

(Part 17 of 21)

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

RSV17

HOUT

TR11

TX11

AVDDA3

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

Signal Name

POR

TR12

TX12

TR04

TR06

EMIFD15

EMU03

EMU02

EMU01

EMU00

UARTRXD

SPIDIN

SCL

CORESEL1

TR02

TR03

TX01

EMU13

EMU06

EMU05

EMU04

SPICLK

BOOTCOMPLETE

SYSCLKOUT

AD23

AD24

AD25

AD26

AD27

AD28

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD1

AD2

AD3

AD4

AC26

AC27

AC28

AC29

Ball Number

AC20

AC21

AC22

AC23

AC24

AC25

AD29

AE1

AE2

AE3

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 18 of 21)

VDDT2

VSS

TX15

TX13

TR10

TX06

TX00

TR07

VSS

EMU10

EMU08

EMU07

RSV22

CORESEL0

RSV20

VSS

DVDD18

VSS

VDDR2

VSS

RSV15

VSS

VDDR4

VSS

VDDR3

VSS

Signal Name

PACLKSEL

CORESEL3

CORESEL2

VSS

VSS

VSS

PCIETXP0

PCIETXN0

VSS

RIOTXN0

RIOTXP0

VSS

RIOTXP3

RIOTXN3

VSS

SGMII1TXP

AF7

AF8

AF9

AF10

AF11

AF12

AF1

AF2

AF3

AF4

AE26

AE27

AE28

AE29

AF5

AF6

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

Ball Number

AE4

AE5

AE6

AE7

AE8

AE9

AF13

AF14

AF15

AF16

Device Overview 68

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 2-29 Terminal Functions

— By Ball Number

(Part 19 of 21)

SPISCS1

CORECLKP

CORECLKN

PCIECLKP

SRIOSGMIICLKP

VSS

PCIETXP1

PCIETXN1

VSS

RIOTXN1

RIOTXP1

VSS

RIOTXP2

RIOTXN2

VSS

SGMII0TXP

SGMII0TXN

VSS

Signal Name

SGMII1TXN

VSS

RSV09

TX17

TX10

VSS

TX07

TX05

CLKA0

DVDD18

EMU17

EMU11

EMU09

SPISCS0

TX14

TR17

DVDD18

FSA1

TX03

CLKB0

FSB0

EMU15

EMU14

EMU12

AG20

AG21

AG22

AG23

AG24

AG25

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG6

AG7

AG8

AG9

AG2

AG3

AG4

AG5

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AG1

Ball Number

AF17

AF18

AF19

AF20

AF21

AF22

AG26

AG27

AG28

AG29

Table 2-29 Terminal Functions

— By Ball Number

(Part 20 of 21)

CLKB1

TX04

TR05

TR00

EMU18

RSV01

DVDD18

VSS

DVDD18

RSV05

VSS

SGMII1RXP

SGMII1RXN

VSS

RSV08

TX16

TR16

TR14

Signal Name

DVDD18

RSV04

RSV25

RSV24

PCIECLKN

VSS

PCIERXN0

PCIERXP0

VSS

RIORXN1

RIORXP1

VSS

RIORXP2

RIORXN2

PASSCLKN

PASSCLKP

SRIOSGMIICLKN

VSS

PCIERXP1

PCIERXN1

VSS

RIORXN0

RIORXP0

VSS

AJ4

AJ5

AJ6

AJ7

AJ8

AJ9

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AJ1

AJ2

AJ3

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH7

AH8

AH9

AH10

AH11

AH12

AH13

AH14

Ball Number

AH1

AH2

AH3

AH4

AH5

AH6

AJ10

AJ11

AJ12

AJ13

69 Device Overview

Table 2-29 Terminal Functions

— By Ball Number

(Part 21 of 21)

Ball Number

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

Signal Name

RIORXP3

RIORXN3

VSS

SGMII0RXP

SGMII0RXN

VSS

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

TR15

TR13

FSB1

CLKA1

TX02

TR01

FSA0

EMU16

AJ28 DVDD18

AJ29

End of Table 2-29

VSS

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

2.9 Development and Support

2.9.1 Development Support

In case the customer would like to develop their own features and software on the C6671 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools.

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)

EVM (Evaluation Module)

2.9.2 Device Support

2.9.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,

TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:

TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX:

Experimental device that is not necessarily representative of the final device's electrical specifications

TMP:

Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification

TMS:

Fully qualified production device

Support tool development evolutionary flow:

TMDX:

Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS:

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

70 Device Overview Copyright 2014 Texas Instruments Incorporated

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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CYP), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for TMS320C6671 in the CYP package type, see the TI website www.ti.com

or contact your TI sales representative.

Figure 2-17

provides a legend for reading the complete device name for any C66x KeyStone device.

Figure 2-17 C66x DSP Device Nomenclature (including the TMS320C6671)

PREFIX

TMX = Experimental device

TMS = Qualified device

TMS 320 C6671 ( ) ( ) CYP ( ) ( )

DEVICE SPEED RANGE

Blank = 1 GHz

25 = 1.25 GHz

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C66x DSP: C6671

SILICON REVISION

Blank = Initial Silicon 1.0

A = Silicon Revision 2.0

TEMPERATURE RANGE

Blank = 0°C to +85°C (default case temperature)

A = Extended temperature range

(-40°C to +100°C)

PACKAGE TYPE

CYP = 841-pin plastic ball grid array, with

Pb-free die bumps and Pb-free solder balls

ENCRYPTION

Blank = Encryption NOT enabled

X = Encryption enabled

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TMS320C6671

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2.10 Related Documentation from Texas Instruments

These documents describe the TMS320C6671 Fixed and Floating-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com

C66x DSP CorePac User Guide

C66x DSP CPU and Instruction Set Reference Guide

C66x DSP Cache User Guide

Chip Interrupt Controller (CIC) for KeyStone Devices User Guide

DDR3 Design Requirements for KeyStone Devices

DDR3 Memory Controller for KeyStone Devices User Guide

Debug and Trace for KeyStone I Devices User Guide

DSP Bootloader for KeyStone Devices User Guide

Emulation and Trace Headers Technical Reference

Enhanced Direct Memory Access 3 (EDMA3) Controller for KeyStone Devices User Guide

External Memory Interface (EMIF16) for KeyStone Devices User Guide

General Purpose Input/Output (GPIO) for KeyStone Devices User Guide

Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide

Hardware Design Guide for KeyStone I Devices

HyperLink for KeyStone Devices User Guide

Inter -IC Control Bus (I

2

C) for KeyStone Devices User Guide

Memory Protection Unit (MPU) for KeyStone Devices User Guide

Multicore Navigator for KeyStone Devices User Guide

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide

Network Coprocessor (NETCP) for KeyStone Devices User Guide

Packet Accelerator (PA) for KeyStone Devices User Guide

Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide

Phase Locked Loop (PLL) for KeyStone Devices User Guide

Power Consumption Summary for KeyStone C66x Devices

Power Sleep Controller (PSC) for KeyStone Devices User Guide

Security Accelerator (SA) for KeyStone Devices User Guide

Semaphore2 Hardware Module for KeyStone Devices User Guide

Serial Peripheral Interface (SPI) for KeyStone Devices User Guide

Serial RapidIO (SRIO) for KeyStone Devices User Guide

Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide

Timer64P for KeyStone Devices User Guide

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs

Using IBIS Models for Timing Analysis

SPRUGW5

SPRUGR9

SPRUGW7

SPRUGZ6

SPRUGS4

SPRUGS6

SPRUGV2

SPRABL5

SPRUGV4

SPRUGY6

SPRUGS3

SPRUGP2

SPRUGW1

SPRUGY4

SPRUGV5

SPRUGP1

SPRUGW0

SPRUGH7

SPRUGY8

SPRUGW4

SPRABI1

SPRUGV8

SPRUGZ2

SPRUGY5

SPRU655

SPRUGS5

SPRUGZ3

SPRUGV1

SPRUGV9

SPRABI2

SPRUGW8

SPRUGV3

SPRA387

SPRA753

SPRA839

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3 Device Configuration

On the TMS320C6671 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.

3.1 Device Configuration at Device Reset

Table 3-1

describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP can be taken out of reset.

Also, note that most of the device configuration pins are shared with other function pins (LENDIAN/GPIO[0],

BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0), some time must be given following the rising edge of reset in order to drive these device configuration input pins before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that must be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.

Note—

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in

which external pullup/pulldown resistors are required, see Section 3.4

‘‘Pullup/Pulldown Resistors’’ on page 94.

Table 3-1 TMS320C6671 Device Configuration Pins

Configuration Pin

LENDIAN

(1) (2)

Pin No.

H25

IPD/IPU

IPU

(1)

Functional Description

Device endian mode (LENDIAN).

0 = Device operates in big endian mode

1 = Device operates in little endian mode

BOOTMODE[12:0]

(1) (2)

J28, J29, J26, J25,

J27, J24, K27, K28,

K26, K29, L28, L29,

K25

IPD Method of boot.

Some pins may not be used by bootloader and can be used as general purpose config

pins. See the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from

Texas Instruments’’ on page 72 for how to determine the device enumeration ID value.

PCIESSMODE[1:0]

(1) (2)

L27, K24 IPD PCIe Subsystem mode selection.

00 = PCIe in end point mode

01 = PCIe legacy end point (support for legacy INTx)

10 = PCIe in root complex mode

11 = Reserved

PCIESSEN

(1) (2)

L24

0 = PCIE Subsystem is disabled

1 = PCIE Subsystem is enabled

PACLKSEL

(1)

AE4 IPD Network Coprocessor (PASS PLL) input clock select.

0 = CORECLK is used as the input to PASS PLL

1 = PASSCLK is used as the input to PASS PLL

End of Table 3-1

1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k

 resistor can be used to oppose the IPD/IPU. For more detailed information on

pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4

‘‘Pullup/Pulldown Resistors’’ on page 94.

2 These signal names are the secondary functions of these pins.

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TMS320C6671

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3.2 Peripheral Selection After Device Reset

Several of the peripherals on the TMS320C6671 are controlled by the Power Sleep Controller (PSC). By default, the

PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. The software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

3.3 Device State Control Registers

The TMS320C6671 device has a set of registers that are used to provide the status or configure certain parts of its

peripherals. These registers are shown in Table 3-2 .

Table 3-2 Device State Control Registers (Part 1 of 4)

Address Start

0x02620000

0x02620008

0x02620018

0x0262001C

0x02620020

0x02620024

0x02620038

0x0262003C

0x02620040

0x02620044

0x02620048

0x0262004C

0x02620050

0x02620054

0x02620058

0x0262005C

0x02620060

0x026200E0

0x02620110

Address End

0x02620007

0x02620017

0x0262001B

0x0262001F

0x02620023

0x02620037

0x0262003B

0x0262003F

0x02620043

0x02620047

0x0262004B

0x0262004F

0x02620053

0x02620057

0x0262005B

0x0262005F

0x026200DF

0x0262010F

0x02620117

4B

4B

4B

4B

4B

4B

4B

4B

20B

4B

Size

8B

16B

4B

4B

Field

Reserved

Reserved

JTAGID

Reserved

DEVSTAT

Reserved

KICK0

KICK1

DSP_BOOT_ADDR0

Reserved

Reserved

Reserved

Reserved

Reserved

4B

4B

Reserved

Reserved

128B Reserved

48B Reserved

8B MACID

Description

See section

3.3.3

See section

3.3.1

See section

3.3.4

The boot address for C66x DSP CorePac0, see section

3.3.5

See section 7.22

‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on page 218

0x02620118

0x02620130

0x02620134

0x02620138

0x0262013C

0x02620140

0x02620144

0x02620148

0x0262012F

0x02620133

0x02620137

0x0262013B

0x0262013F

0x02620143

0x02620147

0x0262014B

4B

4B

4B

4B

24B

4B

4B

4B

Reserved

LRSTNMIPINSTAT_CLR

RESET_STAT_CLR

Reserved

BOOTCOMPLETE

Reserved

RESET_STAT

LRSTNMIPINSTAT

See section

3.3.7

See section

3.3.9

See section

3.3.10

See section

3.3.8

See section

3.3.6

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Table 3-2

0x0262019C

0x026201A0

0x026201A4

0x026201A8

0x026201AC

0x026201B0

0x026201B4

0x026201B8

0x026201BC

0x026201C0

0x026201C4

0x026201C8

0x026201CC

0x026201D0

0x02620200

0x02620204

Address Start

0x0262014C

0x02620150

0x02620154

0x02620158

0x0262015C

0x02620160

0x02620164

0x02620168

0x0262016C

0x02620180

0x02620184

0x02620190

0x02620194

0x02620198

0x02620208

0x0262020C

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620240

0x02620244

0x02620248

0x0262024C

0x02620250

0x02620254

Device State Control Registers (Part 2 of 4)

0x0262019F

0x026201A3

0x026201A7

0x026201AB

0x026201AF

0x026201B3

0x026201B7

0x026201BB

0x026201BF

0x026201C3

0x026201C7

0x026201CB

0x026201CF

0x026201FF

0x02620203

0x02620207

Address End

0x0262014F

0x02620153

0x02620157

0x0262015B

0x0262015F

0x02620163

0x02620167

0x0262016B

0x0262017F

0x02620183

0x0262018F

0x02620193

0x02620197

0x0262019B

0x0262020B

0x0262020F

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620243

0x02620247

0x0262024B

0x0262024F

0x02620253

0x02620257

4B

4B

4B

4B

32B

4B

4B

4B

48B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

12B

4B

4B

4B

4B

4B

20B

4B

4B

4B

4B

4B

Size

4B

4B

4B

4B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

NMIGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Field

DEVCFG

PWRSTATECTL

SRIO_SERDES_STS

SMGII_SERDES_STS

PCIE_SERDES_STS

HYPERLINK_SERDES_STS

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCGR0

Reserved

Reserved

Reserved

Reserved

Reserved

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Description

See section

3.3.2

See section

3.3.11

See ‘‘Related Documentation from Texas Instruments’’ on page 72

See section

3.3.12

See section

3.3.13

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TMS320C6671

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Table 3-2

0x02620298

0x0262029C

0x026202A0

0x026202BC

0x026202C0

0x02620300

0x02620304

0x02620308

0x0262030C

0x02620310

0x02620314

0x02620318

0x0262031C

0x02620320

0x02620324

0x02620328

0x0262032C

0x02620330

0x02620334

0x02620338

0x0262033C

Address Start

0x02620258

0x0262025C

0x02620260

0x0262027C

0x02620280

0x02620284

0x02620288

0x0262028C

0x02620290

0x02620294

Device State Control Registers (Part 3 of 4)

0x02620317

0x0262031B

0x0262031F

0x02620323

0x02620327

0x0262032B

0x0262032F

0x02620333

0x02620337

0x0262033B

0x0262033F

0x0262029B

0x0262029F

0x026202BB

0x026202BF

0x026202FF

0x02620303

0x02620307

0x0262030B

0x0262030F

0x02620313

Address End

0x0262025B

0x0262025F

0x0262027B

0x0262027F

0x02620283

0x02620287

0x0262028B

0x0262028F

0x02620293

0x02620297

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

28B

4B

64B

4B

4B

Size

4B

4B

28B

4B

4B

4B

4B

4B

4B

4B

Field

Reserved

Reserved

Reserved

IPCGRH

IPCAR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCARH

Reserved

TINPSEL

TOUTPSEL

RSTMUX0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

MAINPLLCTL0

MAINPLLCTL1

DDR3PLLCTL0

DDR3PLLCTL1

PASSPLLCTL0

PASSPLLCTL1

Description

See section

3.3.15

See section

3.3.14

See section

3.3.16

See section

3.3.17

See section

3.3.18

See section

3.3.19

See section 7.6

‘‘Main PLL and PLL Controller’’ on page 137

See section 7.7

‘‘DD3 PLL’’ on page 150

See section 7.8

‘‘PASS PLL’’ on page 153

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0x0262037B

0x0262037F

0x02620383

0x0262038B

0x0262038F

0x026203B3

0x026203B7

0x026203BB

0x026203BF

0x026203C3

0x026203C7

0x026203CB

0x026203CF

0x026203D3

0x026203D7

0x026203DB

0x026203F7

0x026203FB

0x026203FF

0x02620403

Address End

0x02620343

0x02620347

0x0262034B

0x0262034F

0x02620353

0x02620357

0x0262035B

0x0262035F

0x02620363

0x02620367

0x0262036B

0x0262036F

0x02620373

0x02620377

0x02620467

Table 3-2

0x02620378

0x0262037C

0x02620380

0x02620384

0x0262038C

0x02620390

0x026203B4

0x026203B8

0x026203BC

0x026203C0

0x026203C4

0x026203C8

0x026203CC

0x026203D0

0x026203D4

0x026203D8

0x026203DC

0x026203F8

0x026203FC

0x02620400

Address Start

0x02620340

0x02620344

0x02620348

0x0262034C

0x02620350

0x02620354

0x02620358

0x0262035C

0x02620360

0x02620364

0x02620368

0x0262036C

0x02620370

0x02620374

0x02620404

End of Table 3-2

Device State Control Registers (Part 4 of 4)

4B

4B

4B

4B

4B

4B

4B

4B

28B

4B

4B

4B

4B

36B

4B

4B

4B

4B

4B

8B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

Size

4B

4B

100B Reserved

Field

SGMII_SERDES_CFGPLL

SGMII_SERDES_CFGRX0

SGMII_SERDES_CFGTX0

SGMII_SERDES_CFGRX1

SGMII_SERDES_CFGTX1

Reserved

PCIE_SERDES_CFGPLL

Reserved

SRIO_SERDES_CFGPLL

SRIO_SERDES_CFGRX0

SRIO_SERDES_CFGTX0

SRIO_SERDES_CFGRX1

SRIO_SERDES_CFGTX1

SRIO_SERDES_CFGRX2

SRIO_SERDES_CFGTX2

SRIO_SERDES_CFGRX3

SRIO_SERDES_CFGTX3

Reserved

DSP_SUSP_CTL

Reserved

HYPERLINK_SERDES_CFGPLL

HYPERLINK_SERDES_CFGRX0

HYPERLINK_SERDES_CFGTX0

HYPERLINK_SERDES_CFGRX1

HYPERLINK_SERDES_CFGTX1

HYPERLINK_SERDES_CFGRX2

HYPERLINK_SERDES_CFGTX2

HYPERLINK_SERDES_CFGRX3

HYPERLINK_SERDES_CFGTX3

Reserved

Reserved

DEVSPEED

Reserved

CHIP_MISC_CTL

Description

See ‘‘Related Documentation from Texas Instruments’’ on page 72

See section

3.3.20

See ‘‘Related Documentation from Texas Instruments’’ on page 72

See section

3.3.21

See section

3.3.22

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3.3.1 Device Status Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or

RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is

shown in Figure 3-1 and described in Table 3-3 .

Figure 3-1 Device Status Register

31

Reserved

R-0

18 17

PACLKSEL

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 x indicates the bootstrap value latched via the external pin

16

PCIESSEN

R-x

15 14

PCIESSMODE[1:0

R/W -xx

13

BOOTMODE[12:0]

R/W-xxxxxxxxxxxx

1 0

LENDIAN

R-x

(1)

Table 3-3 Device Status Register Field Descriptions

Bit

31-18

17

16

Field

Reserved

PACLKSEL

PCIESSEN

Description

Reserved. Read only, writes have no effect.

PA Clock select to select the reference clock for PA Sub-System PLL

0 = Selects CORECLK(P/N)

1 = Selects PASSCLK(P/N)

PCIe module enable

0 = PCIe module disabled

1 = PCIe module enabled

15-14 PCIESSMODE[1:0] PCIe Mode selection pins

00b = PCIe in end-point mode

01b = PCIe in legacy end-point mode (support for legacy INTx)

10b = PCIe in root complex mode

11b = Reserved

13-1

0

BOOTMODE[12:0]

Determines the bootmode configured for the device. For more information on bootmode, see Section 2.5

‘‘Boot Modes

Supported and PLL Settings’’

on page 24 and see the DSP Bootloader for KeyStone Devices User Guide in 2.10 ‘‘Related

Documentation from Texas Instruments’’ on page 72

LENDIAN Device endian mode (LENDIAN) — Shows the status of whether the system is operating in big endian mode or little endian mode.

0 = System is operating in big endian mode

1 = System is operating in little endian mode

End of Table 3-3

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3.3.2 Device Configuration Register (DEVCFG)

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in

Figure 3-2

and described in

Table 3-4

.

Figure 3-2 Device Configuration Register (DEVCFG)

31

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

SYSCLKOUTEN

R/W-1

Table 3-4 Device Configuration Register (DEVCFG) Field Descriptions

Bit

31-1

Field

Reserved

0 SYSCLKOUTEN

Description

Reserved. Read only, writes have no effect.

0 = No clock output

1 = Clock output enabled (default)

End of Table 3-4

3.3.3 JTAG ID Register (JTAGID) Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the

JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3

and

described in Table 3-5 .

Figure 3-3 JTAG ID Register (JTAGID)

31 28 27

VARIANT

R-xxxxb

PART NUMBER

R-0000 0000 1001 1110b

Legend: RW = Read/Write; R = Read only; -n = value after reset

12 11

MANUFACTURER

0000 0010 111b

1 0

LSB

R-1

Table 3-5 JTAG ID Register (JTAGID) Field Descriptions

Bit Field

31-28 VARIANT

27-12 PART NUMBER

11-1 MANUFACTURER

0 LSB

End of Table 3-5

Value

xxxxb

Description

Variant (4-bit) value.

0000 0000 1001 1110b Part number for boundary scan

0000 0010 111b Manufacturer

1b This bit is read as a 1 for TMS320C6671

Note—

The value of the VARIANT and PART NUMBER fields depend on the silicon revision being used.

See the Silicon Errata for details.

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3.3.4 Kicker Mechanism Register (KICK0 and KICK1)

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg

MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with

exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on page 74 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable

(the read-only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.

Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to

Bootcfg MMRs.

The kicker mechanism is unlocked by the ROM code. Do not write any other different values afterward to these registers because that will lock the kicker mechanism and block any writes to Bootcfg registers.

3.3.5 DSP Boot Address Register (DSP_BOOT_ADDRn)

The DSP_BOOT_ADDRn register stores the initial boot fetch address of CorePac_n (n = core number). The fetch address is the public ROM base address (for any boot mode) by default. DSP_BOOT_ADDRn register access should be permitted to any master or emulator when the device is non-secure. CorePac will boot from that address when a

reset is performed. The DSP_BOOT_ADDRn register is shown in Figure 3-4 and described in Table 3-6 .

Figure 3-4 DSP BOOT Address Register (DSP_BOOT_ADDRn)

31

DSP_BOOT_ADDR

RW-0010000010110000000000

Legend: R = Read only; RW = Read/Write; -n = value after reset

10 9

Reserved

R-0

0

Table 3-6 DSP BOOT Address Register (DSP_BOOT_ADDRn) Field Descriptions

Bit Field

9-0 Reserved

End of Table 3-6

Description

31-10 DSP_BOOT_ADDR Boot address of CorePac. CorePac will boot from that address when a reset is performed.

The reset value is 22 MSBs of ROM base address = 0x20B00000.

Reserved

3.3.6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on

CORESEL. The LRESETNMI PIN Status Register is shownin Figure 3-5

and described in

Table 3-7

.

Figure 3-5 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

9 7 1 31

Reserved

R, +0000 0000 0000 0000 0000 000

Legend: R = Read only; -n = value after reset;

8

NMI0

R-0

Reserved

R, +000 0000

0

LR0

R-0

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Table 3-7

Bit Field

31-17 Reserved

16

15-1

NMI0

Reserved

0 LR0

End of Table 3-7

LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions

Description

Reserved

CorePac0 in NMI

Reserved

CorePac0 in Local Reset

3.3.7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The

LRESETNMI PIN Status Clear Register is shownin Figure 3-6

and described in

Table 3-8

Figure 3-6 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

31 9

Reserved

R, +0000 0000 0000 0000 0000 000

Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

8

NMI0

WC,+0

7

Reserved

R, +0000 000

1 0

LR0

WC,+0

Table 3-8

Bit

31-9

8

7-1

Field

Reserved

NMI0

Reserved

0 LR0

End of Table 3-8

LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions

Description

Reserved

CorePac0 in NMI clear

Reserved

CorePac0 in local reset clear

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3.3.8 Reset Status Register (RESET_STAT)

The reset status register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

In case of local reset:

The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives a local reset without receiving a global reset.

In case of global reset:

The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

The Reset Status Register is shown in Figure 3-7 and described in Table 3-9 .

Figure 3-7 Reset Status Register (RESET_STAT)

31

GR

30

R, +1

Legend: R = Read only; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

1 0

LR0

R,+0

Table 3-9

Bit

31

30-1

0

Field

GR

Reserved

LR0

Reset Status Register (RESET_STAT) Field Descriptions

Description

Global reset status

0 = Device has not received a global reset.

1 = Device received a global reset.

Reserved.

CorePac0 reset status

0 = CorePac0 has not received a local reset.

1 = CorePac0 received a local reset.

End of Table 3-9

3.3.9 Reset Status Clear Register (RESET_STAT_CLR)

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The

Reset Status Clear Register is shown in

Figure 3-8

and described in

Table 3-10

.

Figure 3-8 Reset Status Clear Register (RESET_STAT_CLR)

31

GR

30

RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

1 0

LR0

RW,+0

Table 3-10

Bit

31

Field

GR

Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 1 of 2)

Description

Global reset clear bit

0 = Writing a 0 has no effect.

1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

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Table 3-10

Bit

30-1

0

Field

Reserved

LR0

Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 2 of 2)

Description

Reserved.

CorePac0 reset clear bit

0 = Writing a 0 has no effect.

1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

End of Table 3-10

3.3.10 Boot Complete Register (BOOTCOMPLETE)

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the

completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-9

and described in

Table 3-11

.

Figure 3-9 Boot Complete Register (BOOTCOMPLETE)

31

Reserved

R, + 0000 0000 0000 0000 0000 0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

BC0

RW,+0

Table 3-11

Bit

31-1

0

Field

Reserved

BC0

Boot Complete Register (BOOTCOMPLETE) Field Descriptions

Description

Reserved.

CorePac0 boot status

0 = CorePac0 boot NOT complete

1 = CorePac0 boot complete

End of Table 3-11

The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before branching to the predefined location in memory.

3.3.11 Power State Control Register (PWRSTATECTL)

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will

survive all other device resets. See the Hardware Design Guide for KeyStone I Devices in ‘‘Related Documentation from Texas Instruments’’ on page 72 for more information. The Power State Control Register is shown in

Figure 3-10

and described in

Table 3-12 .

Figure 3-10 Power State Control Register (PWRSTATECTL)

31

GENERAL_PURPOSE

RW-0000 0000 0000 0000 0000 0000 0000 0

Legend: RW = Read/Write; -n = value after reset

3 2

HIBERNATION_MODE

RW-0

1

HIBERNATION

RW-0

0

STANDBY

RW-0

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Table 3-12 Power State Control Register (PWRSTATECTL) Field Descriptions

Bit

31-3

2

1

0

Field

GENERAL_PURPOSE

Description

Used to provide a start address for execution out of the hibernation modes. See the DSP Bootloader for KeyStone

Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.

0 = Hibernation mode 1

1 = Hibernation mode 2

HIBERNATION Indicates whether the device is in hibernation mode or not.

0 = Not in hibernation mode

1 = Hibernation mode

STANDBY Indicates whether the device is in standby mode or not.

0 = Not in standby mode

1 = Standby mode

End of Table 3-12

3.3.12 NMI Event Generation to CorePac Register (NMIGRx)

NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6671 has one NMIGRx register (NMIGR0). The NMIGR0 register generates an NMI event to CorePac0. Writing a 1 to the

NMIG field generates a NMI pulse. Writing a 0 has no effect and reads return 0 and have no other effect. The NMI

Even Generation to CorePac Register is shown in Figure 3-11 and described in Table 3-13

.

Figure 3-11 NMI Generation Register (NMIGRx)

31

Legend: RW = Read/Write; -n = value after reset

Reserved

R-0000 0000 0000 0000 0000 0000 0000 000

1 0

NMIG

RW-0

Table 3-13

Bit

31-1

0

Field

Reserved

NMIG

NMI Generation Register (NMIGRx) Field Descriptions

Description

Reserved

NMI pulse generation.

Reads return 0

Writes:

0 = No effect

1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.

End of Table 3-13

3.3.13 IPC Generation Registers (IPCGRx)

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6671 has one IPCGRx register (IPCGR0). This register can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an interrupt pulse to

CorePac0.

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These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.

Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these

registers. The IPC Generation Register is shown in Figure 3-12

and described in

Table 3-14

.

Figure 3-12 IPC Generation (IPCGRx) Registers

31

SRCS27

RW-0

30

SRCS26

RW-0

29

SRCS25

RW-0

28

SRCS24

RW-0

27

SRCS23 – SRCS4

RW-0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW-0 RW-0 RW-0 RW-0

3

Reserved

1

R-000

0

IPCG

RW-0

Table 3-14

Bit

31-4

Field

SRCSx

3-1

0

Reserved

IPCG

IPC Generation Registers (IPCGRx) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Inter-DSP interrupt generation.

Reads return 0.

Writes:

0 = No effect

1 = Creates an Inter-DSP interrupt.

End of Table 3-14

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3.3.14 IPC Acknowledgement Registers (IPCARx)

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

The C6671 has one IPCARx register (IPCAR0). This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to

BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in Figure 3-13

and described in

Table 3-15

.

Figure 3-13 IPC Acknowledgement (IPCARx) Registers

31

SRCC27

RW-0

30

SRCC26

RW-0

29

SRCC25

RW-0

28

SRCC24

RW-0

27

SRCC23 – SRCC4

RW-0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW-0 RW-0 RW-0 RW-0

3

Reserved

R-0000

0

Table 3-15

Bit

31-4

Field

SRCCx

IPC Acknowledgement Registers (IPCARx) Field Descriptions

3-0 Reserved

End of Table 3-15

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Clears both SRCCx and the corresponding SRCSx

Reserved

3.3.15 IPC Generation Host Register (IPCGRH)

The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin

HOUT.

The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock (CPU/6) cycles followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight

CPU/6-cycles long. Back to back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight CPU/6 cycle window -- the pulse blocking window. In order to generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be greater than eight

CPU/6 cycle window. The IPC Generation Host Register is shown in Figure 3-14

and described in Table 3-16

.

Figure 3-14 IPC Generation (IPCGRH) Registers

31

SRCS27

RW-0

30

SRCS26

RW-0

29

SRCS25

RW-0

28

SRCS24

RW-0

27

SRCS23 – SRCS4

RW-0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW-0 RW-0 RW-0 RW-0

3

Reserved

1

R-000

0

IPCG

RW-0

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Table 3-16

Bit

31-4

Field

SRCSx

3-1

0

Reserved

IPCG

IPC Generation Registers (IPCGRH) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Host interrupt generation.

Reads return 0.

Writes:

0 = No effect

1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

End of Table 3-16

3.3.16 IPC Acknowledgement Host Register (IPCARH)

IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in

Figure 3-15 and described in

Table 3-17

.

Figure 3-15 IPC Acknowledgement Register (IPCARH)

31

SRCC27

RW-0

30

SRCC26

RW-0

29

SRCC25

RW-0

28

SRCC24

RW-0

27

SRCC23 – SRCC4

RW-0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW-0 RW-0 RW-0 RW-0

3

Reserved

R-0000

0

Table 3-17

Bit

31-4

Field

SRCCx

IPC Acknowledgement Register (IPCARH) Field Descriptions

3-0 Reserved

End of Table 3-17

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

0 = No effect

1 = Clears both SRCCx and the corresponding SRCSx

Reserved

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3.3.17 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown

in Figure 3-16

and described in

Table 3-18

. Timer 1~7 are reserved.

Figure 3-16 Timer Input Selection Register (TINPSEL)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TINPHS

EL15

TINPLS

EL15

TINPHS

EL14

TINPLS

EL14

TINPHS

EL13

TINPLS

EL13

TINPHS

EL12

TINPLS

EL12

TINPHS

EL11

TINPLS

EL11

TINPHS

EL10

TINPLS

EL10

TINPHS

EL9

TINPLS

EL9

TINPHS

EL8

TINPLS

EL8

RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 spacer

15 2 1 0

Reserved

R, +0

TINPHS

EL0

TINPLS

EL0

RW, +1 RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-18

Bit

31

30

29

28

27

26

25

24

23

22

21

Timer Input Selection Field Description (TINPSEL) (Part 1 of 2)

Field

TINPHSEL15

TINPLSEL15

TINPHSEL14

TINPLSEL14

TINPHSEL13

TINPLSEL13

TINPHSEL12

TINPLSEL12

TINPHSEL11

TINPLSEL11

TINPHSEL10

Description

Input select for TIMER15 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER15 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER14 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER14 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER13 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER13 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER12 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER12 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER11 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER11 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER10 high.

0 = TIMI0

1 = TIMI1

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Table 3-18

Bit

20

19

18

17

16

15-2 Reserved

1 TINPHSEL0

0

Field

TINPLSEL10

TINPHSEL9

TINPLSEL9

TINPLSEL8

TINPLSEL0

Timer Input Selection Field Description (TINPSEL) (Part 2 of 2)

TINPHSEL8

Description

Input select for TIMER10 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER9 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER9 low.

0 = TIMI0

1 = TIMI1

Input select for TIMER8 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER8 low.

0 = TIMI0

1 = TIMI1

Reserved

Input select for TIMER0 high.

0 = TIMI0

1 = TIMI1

Input select for TIMER0 low.

0 = TIMI0

1 = TIMI1

End of Table 3-18

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3.3.18 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in

Figure 3-17 and described in Table 3-19 .

Figure 3-17 Timer Output Selection Register (TOUTPSEL)

31

Reserved

R-000000000000000000000000

Legend: R = Read only; RW = Read/Write; -n = value after reset

10 9

TOUTPSEL1

RW-00001

5 4

TOUTPSEL0

RW-00000

0

Table 3-19

Bit

31-10

9-5

4-0

Timer Output Selection Register (TOUTPSEL) Field Description

Field

Reserved

TOUTPSEL1

TOUTPSEL0

Description

Reserved

Output select for TIMO1

00000: TOUTL0

00001: TOUTH0

00010 to 01111: Reserved

10000: TOUTL8

10001: TOUTH8

10010: TOUTL9

10011: TOUTH9

10100: TOUTL10

10101: TOUTH10

Output select for TIMO0

00000: TOUTL0

00001: TOUTH0

00010 to 01111: Reserved

10000: TOUTL8

10001: TOUTH8

10010: TOUTL9

10011: TOUTH9

10100: TOUTL10

10101: TOUTH10

10110: TOUTL11

10111: TOUTH11

11000: TOUTL12

11001: TOUTH12

11010: TOUTL13

11011: TOUTH13

11100: TOUTL14

11101: TOUTH14

11110: TOUTL15

11111: TOUTH15

10110: TOUTL11

10111: TOUTH11

11000: TOUTL12

11001: TOUTH12

11010: TOUTL13

11011: TOUTH13

11100: TOUTL14

11101: TOUTH14

11110: TOUTL15

11111: TOUTH15

End of Table 3-19

3.3.19 Reset Mux Register (RSTMUXx)

The software controls the Reset Mux block through the reset multiplex register (RSTMUX0). This register is located

in Bootcfg memory space. The Reset Mux Register is shown in Figure 3-18 and described in

Table 3-20 .

Figure 3-18 Reset Mux Register (RSTMUXx)

31 10

Reserved

R-0000 0000 0000 0000 0000 00

9

EVTSTATCLR

RC-0

8

Reserved

R-0

7

DELAY

RW-100

5

Legend: R = Read only; RW = Read/Write; -n = value after reset; RC

= Read only and write 1 to clear

4

EVTSTAT

R-0

3

OMODE

1

RW-000

0

LOCK

RW-0

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Table 3-20 Reset Mux Register (RSTMUXx) Field Descriptions

Bit Field

31-10 Reserved

9

8

7-5

Description

Reserved

EVTSTATCLR Clear event status

0 = Writing 0 has no effect

1 = Writing 1 to this bit clears the EVTSTAT bit

Reserved

DELAY

Reserved

Delay cycles between NMI & local reset

000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b

001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)

101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

4

3-1

0

EVTSTAT

OMODE

LOCK

Event status.

0 = No event received (Default)

1 = WD timer event received by Reset Mux block

Timer event operation mode

000b = WD timer event input to the reset mux block does not cause any output event (default)

001b = Reserved

010b = WD timer event input to the reset mux block causes local reset input to CorePac

011b = WD timer event input to the reset mux block causes NMI input to CorePac

100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay between NMI and local reset is set in DELAY bit field.

101b = WD timer event input to the reset mux block causes device reset to C6671

110b = Reserved

111b = Reserved

Lock register fields

0 = Register fields are not locked (default)

1 = Register fields are locked until the next timer reset

End of Table 3-20

3.3.20 DSP Suspension Control Register (DSP_SUSP_CTL)

The DSP Suspension Control Register controls the emulation suspension signals from DSP cores. The DSP

Suspension Control Register is shown in

Figure 3-19

and described in Table 3-21 .

Figure 3-19 DSP Suspension Control Register (DSP_SUSP_CTL)

31

DSP_SUSP_CTL

30

R/W-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R-0

0

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Table 3-21

Bit

31

DSP Suspension Control Register (DSP_SUSP_CTL) Field Descriptions

Field

DSP_SUSP_CTL

30-0 Reserved

End of Table 3-21

Description

Control the combination of emulation suspension signals from DSP cores

0 = AND suspension signals from all DSP cores

1 = OR suspension signals from all DSP cores

Reserved. Read only

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3.3.21 Device Speed Register (DEVSPEED)

The Device Speed Register depicts the device speed grade. The Device Speed Register is shown below.

Figure 3-20 Device Speed Register (DEVSPEED)

31 23 22

DEVSPEED

R-n

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R-n

0

Table 3-22 Device Speed Register (DEVSPEED) Field Descriptions

Bit Field

31-23 DEVSPEED

22-0 Reserved

End of Table 3-22

Description

Indicates the speed of the device (read only)

0000 0000 0b = 800 MHz

0000 0000 1b = 1000 MHz

0000 0001 xb = 1200 MHz

0000 001x xb = 1250 MHz

0000 01xx xb = Reserved

0000 1xxx xb = Reserved

0001 xxxx xb = 1250 MHz

001x xxxx xb = 1200 MHz

01xx xxxx xb = 1000 MHz

1xxx xxxx xb = 800 MHz

Reserved. Read only

3.3.22 Chip Miscellaneous Control Register (CHIP_MISC_CTL)

The Chip Miscellaneous Control Register is shown below.

Figure 3-21 Chip Miscellaneous Control Register (CHIP_MISC_CTL)

31 13

Reserved

R/W-0000000000000000000

Legend: R = Read only; R/W = Read/Write; -n = value after reset

12

MSMC_BLOCK_PARITY_RST

RW-0

11

Reserved

R/W-001000011

3 2 0

QM_PRIORITY

RW-000

Table 3-23 Chip Miscellaneous Control Register (CHIP_MISC_CTL) Field Descriptions

Bit Field Description

31-13 Reserved

12 MSMC_BLOCK_PARITY_RST

Reserved.

Controls MSMC parity RAM reset. When set to 1, it means the MSMC parity RAM will not be reset.

11-3 Reserved Reserved.

2-0 QM_PRIORITY Control the priority level for the transactions from QM Packet DMA master port, which access the external linking RAM.

End of Table 3-23

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3.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown

(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor must be used in the following situations:

Device Configuration Pins:

If the pin is both routed out and are not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

Other Input Pins:

If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in

Table 3-1 ), if they are both routed out and are not driven (in Hi-Z state),

it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V

IL connected to the net. For a pullup resistor, this should be above the highest V

IH

A reasonable choice would be to target the V

OL by definition, have margin to the V

IL

and V

IH

or V

OH

levels.

level of all inputs

level of all inputs on the net.

levels for the logic family of the limiting device; which,

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DV

DD

rail.

For most systems:

• A 1-k resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

• A 20-k resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

I

), and the low-level/high-level input voltages (V

IL

and V

IH

) for

the TMS320C6671 device, see Section 6.3

‘‘Electrical Characteristics’’ on page 115.

To determine which pins on the device include internal pullup/pulldown resistors, see

Table 2-26 ‘‘Terminal

Functions — Signals and Control by Function’’ on page 44.

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4 System Interconnect

On the TMS320C6671 device, the C66x CorePac, the EDMA3 transfer controllers, and the system peripherals are interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free internal data movement. The TeraNet allows for low-latency, concurrent data transfers between master peripherals and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing system slaves.

4.1 Internal Buses and Switch Fabrics

Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus and a configuration bus interface, while others have only one type of interface. Further, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers.

The C66x CorePac, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the masters to perform transfers to and from them. Examples of masters include the EDMA3 traffic controllers, SRIO, and Network Coprocessor packet

DMA. Examples of slaves include the SPI, UART, and I

2

C.

The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric (configuration

TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The data TeraNet connects masters to slaves via data buses. Some peripherals require a bridge to connect to the data

TeraNet. The configuration TeraNet, is mainly used to access peripheral registers. The configuration TeraNet connects masters to slaves via configuration buses. As with the data TeraNet, some peripherals require the use of a bridge to interface to the configuration TeraNet. Note that the data TeraNet also connects to the configuration

TeraNet. For more details see 4.2

‘‘Switch Fabric Connections’’ .

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4.2 Switch Fabric Connections

The following figures show the connections between masters and slaves on TeraNet 2A and TeraNet 3A.

Figure 4-1

XMC

´

n

*

TeraNet 2A for C6671

Bridge_5

Bridge_6

Bridge_7

Bridge_8

Bridge_9

Bridge_10

From TeraNet_3_A

EDMA

CC0

HyperLink

TC_0

TC_1

M

M

M

S

S

SES

SMS

M S

MSMC

M

DDR3

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

Tracer_DDR

S

HyperLink

To TeraNet_3_A

Bridge_1

Bridge_2

Bridge_3

Bridge_4

*

n varies with the number of CorePacs present in the specific device.

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Figure 4-2 TeraNet 3A for C6671

Bridge_1

Bridge_2

Bridge_3

Bridge_4

From TeraNet_2_A

PCIe

SRIO_M

M

M

SRIO

Packet DMA

M

NETCP

M

QM_SS

Packet DMA

M

QM_SS

Second

M

EDMA

CC1

EDMA

CC2

Debug_SS

TSIP0

TSIP1

TC_0

TC_1

TC_2

TC_3

TC_0

TC_1

TC_2

TC_3

M

M

M

M

M

M

M

M

M

M

M

TNet_3_D

CPU/3

TNet_3_C

CPU/3

*

n varies with the number of CorePacs present in the specific device.

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Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Tracer_QM_M

MPU_1

TNet_6P_A

CPU/3

S

S

S

S

S

S

S

QM_SS

PCIe

SRIO

SPI

Boot_ROM

EMIF16

To TeraNet_2_A

Bridge_5

Bridge_6

Bridge_7

Bridge_8

Bridge_9

Bridge_10

To TeraNet_3P_A

Bridge_12

Bridge_13

Bridge_14

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Allowed connections on TeraNet 2A and TeraNet 3A are summarized in the table below.

Intersecting cells may contain one of the following:

Y

— There is a direct connection between this master and that slave.

-

— There is NO connection between this master and that slave.

n

— A numeric value indicates that the path between this master and that slave goes through bridge n.

Table 4-1 Data Switch Fabric Connection Matrix

Slaves

Masters

HyperLink_Master

EDMA3CC0_TC0_RD

EDMA3CC0_TC0_WR

EDMA3CC0_TC1_RD

EDMA3CC0_TC1_WR

EDMA3CC1_TC0_RD

EDMA3CC1_TC0_WR

EDMA3CC1_TC1_RD

EDMA3CC1_TC1_WR

EDMA3CC1_TC2_RD

EDMA3CC1_TC2_WR

EDMA3CC1_TC3_RD

EDMA3CC1_TC3_WR

EDMA3CC2_TC0_RD

EDMA3CC2_TC0_WR

EDMA3CC2_TC1_RD

EDMA3CC2_TC1_WR

EDMA3CC2_TC2_RD

EDMA3CC2_TC2_WR

EDMA3CC2_TC3_RD

EDMA3CC2_TC3_WR

SRIO packet DMA

SRIO_Master

PCIe_Master

NETCP packet DMA

MSMC_Data_Master

QM packet DMA

QM_Second

DebugSS_Master

TSIP0_Master

TSIP1_Master

End of Table 4-1

98 System Interconnect

10

5

5

8

8

10

-

9

7

6

9

5

6

10

5

9

10

8

9

7

8

6

7

5

6

Y

5

Y

Y

Y

Y

10

-

-

8

8

-

Y

9

7

6

-

5

6

10

5

9

10

8

9

7

8

6

7

5

6

Y

5

Y

Y

-

Y

10

5

5

8

8

10

-

9

7

6

9

5

6

10

5

9

10

8

9

7

8

6

7

5

6

Y

5

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

4

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

3

Y

2

3

1

2

Y

-

-

-

-

-

4

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

3

Y

2

3

1

2

Y

-

-

-

-

-

4

Y

Y

Y

-

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

3

Y

2

3

1

2

Y

-

-

-

-

-

4

-

-

-

-

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

3

1

2

Y

-

-

-

-

-

4

-

-

Y

-

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

3

Y

2

3

1

2

Y

-

-

Y

-

Y

4

Y

Y

-

Y

-

-

Y

-

-

Y

-

-

-

-

Y

-

-

Y

-

-

-

-

1

-

Y

-

-

-

-

-

4

-

-

Y

-

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

3

Y

2

3

1

2

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Fixed and Floating-Point Digital Signal Processor

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The following figure shows the connection between masters and slaves on TeraNet 3P and TeraNet 6P.

Figure 4-3 TeraNet 3P_A & B for C6671

Bridge_12

Bridge_13

Bridge_14

From TeraNet_3_A

M

TNet_3P_C

CPU/3

TNet_3P_D

CPU/3

Tracer_QM_CFG

Tracer_SM

TNet_2P

CPU/2

MPU_2

MPU_3

S

S

S

S

S

S

S

CC0

CC1

CC2

S

QM_SS

S

Semaphore

TETB (Debug_SS)

TETB (for core)

To TeraNet_3P_Tracer

MPU_0

Tracer_CFG

S

S

S

S

S

To TeraNet_6P_B

SRIO

Tracer

NETCP

TSIP0

TSIP1

Bridge_20

*

n varies with the number of CorePacs present in the specific device.

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System Interconnect 99

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SPRS756E—March 2014

Figure 4-4 TeraNet 6P_B and 3P_Tracer for C6671

From TeraNet_3P_A

Tracer_

MSMC_0

Tracer_

MSMC_1

Tracer_

MSMC_2

M

M

M

Tracer_

MSMC_3

M

Tracer_CFG

M

Tracer_DDR

M

Tracer_SM

M

Tracer_

QM_M

M

Tracer_

QM_P

M

M

Bridge_20

From TeraNet_3P_B

S

S

Debug_SS

STM

Debug_SS

TETB

S

S

S

S

S

S

S

S

S

S

SmartReflex

GPIO

2

I C

UART

BOOTCFG

PSC

PLL_CTL

Debug_SS

CIC

Timer

*

n varies with the number of CorePacs present in the specific device.

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Allowed connections on TeraNet 3P and TeraNet 6P are summarized in the tables below.

Intersecting cells may contain one of the following:

Y

— There is a direct connection between this master and that slave.

-

— There is NO connection between this master and that slave.

n

— A numeric value indicates that the path between this master and that slave goes through bridge n.

Table 4-2 Configuration Switch Fabric Connection Matrix Section1 (Part 1 of 2)

Slave

Masters

HyperLink_Master

EDMA3CC0_TC0_RD

EDMA3CC0_TC0_WR

EDMA3CC0_TC1_RD

EDMA3CC0_TC1_WR

EDMA3CC1_TC0_RD

EDMA3CC1_TC0_WR

EDMA3CC1_TC1_RD

EDMA3CC1_TC1_WR

EDMA3CC1_TC2_RD

EDMA3CC1_TC2_WR

EDMA3CC1_TC3_RD

EDMA3CC1_TC3_WR

EDMA3CC2_TC0_RD

EDMA3CC2_TC0_WR

EDMA3CC2_TC1_RD

EDMA3CC2_TC1_WR

EDMA3CC2_TC2_RD

EDMA3CC2_TC2_WR

EDMA3CC2_TC3_RD

EDMA3CC2_TC3_WR

SRIO packet DMA

SRIO_Master

PCIe_Master

NETCP packet DMA

MSMC_Data_Master

QM packet DMA

QM_Second

DebugSS_Master

TSIP0_Master

TSIP1_Master

EDMA3CC0

-

-

12

-

-

-

-

-

14

-

12

12

13

12

12

14

12

12

12

13

13

14

14

12

1,12 1,12 1,12

2,12 2,12 2,12

2,12 2,12

3,12 3,12

2,12

3,12

3,12 3,12

12 12

12

13

12

13

3,12

12

12

13

13

14

14

12

12

12

12

13

12

12

12

13

13

14

14

12

-

-

12

-

-

-

-

-

14

-

12

12

13

12

12

14

-

Y

12

-

-

-

-

-

14

-

12

12

13

12

12

14

-

-

12

-

-

-

-

-

14

-

12

12

13

12

12

14

12

12

12

13

13

14

14

12

3,12

12

12

13

1,12

2,12

2,12

3,12

-

-

12

-

-

-

-

-

14

-

12

12

13

12

12

14

-

-

12

-

-

-

-

-

12

12

-

-

-

12

12

-

-

-

12

-

-

-

-

-

14

-

12

12

13

12

12

14

12

12

12

13

13

14

14

12

1,12 1,12 1,12 1,12 1,12 1,12 1,12 1,12 1,12 1,12 1,12 1,12

2,12 2,12 -

2,12 2,12

3,12 3,12

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

3,12 3,12

12 12

12

13

12

13

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

-

12

12

-

13

14

14

12

12

12

12

13

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

-

-

-

12

12

12

12

-

12

12

12

-

-

12

-

-

-

12

12

-

-

-

12

12

-

-

-

-

-

-

-

12

-

12

12

-

-

-

12

12

-

-

-

-

12

-

-

-

-

12

12

-

-

-

12

12

-

-

-

-

12

-

-

-

-

12

12

-

-

-

12

12

-

-

-

-

12

-

-

-

-

12

12

-

-

-

12

12

-

-

-

-

12

-

-

-

-

12

12

-

-

-

12

12

-

-

-

-

12

-

-

-

-

-

12

-

-

-

-

-

12

12

-

-

-

12

12

-

-

-

12

-

-

-

-

-

12

12

-

-

-

12

12

-

-

-

12

-

-

-

-

-

12

12

-

-

-

12

12

-

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TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 4-2 Configuration Switch Fabric Connection Matrix Section1 (Part 2 of 2)

Slave

Masters

EDMA3CC1

EDMA3CC2

CorePac0_CFG

End of Table 4-2

-

-

Y

-

-

Y

-

-

Y

-

-

Y

Y

-

Y

-

Y

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

-

-

Y

Table 4-3 Configuration Switch Fabric Connection Matrix Section2 (Part 1 of 2)

Slave

Masters

HyperLink_Master

EDMA3CC0_TC0_RD

EDMA3CC0_TC0_WR

EDMA3CC0_TC1_RD

EDMA3CC0_TC1_WR

EDMA3CC1_TC0_RD

EDMA3CC1_TC0_WR

EDMA3CC1_TC1_RD

EDMA3CC1_TC1_WR

EDMA3CC1_TC2_RD

EDMA3CC1_TC2_WR

EDMA3CC1_TC3_RD

EDMA3CC1_TC3_WR

EDMA3CC2_TC0_RD

EDMA3CC2_TC0_WR

EDMA3CC2_TC1_RD

EDMA3CC2_TC1_WR

EDMA3CC2_TC2_RD

EDMA3CC2_TC2_WR

EDMA3CC2_TC3_RD

EDMA3CC2_TC3_WR

SRIO packet DMA

SRIO_Master

PCIe_Master

NETCP packet DMA

MSMC_Data_Master

102 System Interconnect

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

-

-

12

12

12

-

12

12

12

-

-

-

12

-

-

-

12

12

-

1,12

-

-

-

12

-

-

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-

-

12

12

-

-

-

-

-

12

-

-

12

-

-

-

-

-

12

-

2,12

-

3,12

12

-

-

-

-

12

-

-

-

12

-

-

-

13

-

-

-

-

-

-

-

-

13

-

-

-

-

-

-

Table 4-3

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Configuration Switch Fabric Connection Matrix Section2 (Part 2 of 2)

Slave

Masters

QM packet DMA

QM_Second

DebugSS_Master

TSIP0_Master

TSIP1_Master

EDMA3CC0

EDMA3CC1

EDMA3CC2

CorePac0_CFG

End of Table 4-3

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

-

-

-

-

Y

12

-

-

-

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4.3 Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority - PRI = 000b = urgent, PRI = 111b = low.

All other masters provide their priority directly and do not need a default priority setting. Examples include the

CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based peripherals also have internal registers to define the priority level of their initiated transactions.

The QM Packet DMA master port is one master port that does not have priority allocation register inside the IP. The priority level for transaction from this master port is described by QM_PRIORITY bit field in CHIP_MISC_CTL register in section

3.3.22

.

For all other modules, see the respective User Guides in “Related Documentation from Texas Instruments” on page 72

for programmable priority registers.

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5 C66x CorePac

The C66x CorePac consists of several components:

• The C66x DSP and associated C66x CorePac core

• Level-one and level-two memories (L1P, L1D, L2)

• Data Trace Formatter (DTF)

• Embedded Trace Buffer (ETB)

• Interrupt Controller

• Power-down controller

• External Memory Controller

• Extended Memory Controller

• A dedicated power/sleep controller (LPSC)

The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the

C66x CorePac) and address extension.

Figure 5-1

shows a block diagram of the C66x CorePac.

Figure 5-1 C66x CorePac Block Diagram

32KB L1P

PLLC

Boot

Controller

LPSC

GPSC

Program Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

C66x DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A Data Path B

A Register File

A31-A16

A15-A0

B Register File

B31-B16

B15-B0

.L1

.S1

.M1

xx xx

.D1

.D2

.M2

xx xx

.S2

.L2

L2 Cache/

SRAM

512KB

MSM

SRAM

4096KB

DDR3

SRAM

DMA Switch

Fabric

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

CFG Switch

Fabric

32KB L1D

For more detailed information on the TMS320C66x CorePac on the C6671 device, see the C66x DSP CorePac User

Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

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5.1 Memory Architecture

The C66x CorePac of the TMS320C6671 device contains a 512KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory

(MSM). All memory on the C6671 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map

Summary’’ on page 17.

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the

L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the DSP

Bootloader for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

5.1.1 L1P Memory

The L1P memory configuration for the C6671 device is as follows:

• 32K bytes with no wait states

Figure 5-2

shows the available SRAM/cache configurations for L1P.

Figure 5-2 L1P Memory Configurations

L1P mode bits

000 001 010 011 100 L1P memory

Block base address

00E0 0000h

All

SRAM

7/8

SRAM

3/4

SRAM

1/2

SRAM direct mapped cache dm cache direct mapped cache direct mapped cache

16K bytes

00E0 4000h

8K bytes

4K bytes

4K bytes

00E0 6000h

00E0 7000h

00E0 8000h

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5.1.2 L1D Memory

The L1D memory configuration for the C6671 device is as follows:

• 32K bytes with no wait states

Figure 5-3

shows the available SRAM/cache configurations for L1D.

Figure 5-3 L1D Memory Configurations

L1D mode bits

000 001 010 011 100 L1D memory

Block base address

00F0 0000h

All

SRAM

7/8

SRAM

3/4

SRAM

1/2

SRAM

2-way cache

2-way cache

2-way cache

2-way cache

16K bytes

00F0 4000h

8K bytes

4K bytes

4K bytes

00F0 6000h

00F0 7000h

00F0 8000h

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5.1.3 L2 Memory

The L2 memory configuration for the C6671 device is as follows:

• Total memory size is 4096KB

• Each core contains 512KB of memory

• Local starting address for each core is 0080 0000h

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register

(L2CFG) of the C66x CorePac.

Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is

configured as all SRAM after device reset.

Figure 5-4 L2 Memory Configurations

L2 Mode Bits

000 001 010 011 100 101

L2 Memory

Block Base

Address

0080 0000h

ALL

SRAM

15/16

SRAM

7/8

SRAM

3/4

SRAM

1/2

SRAM

ALL

Cache

256Kbytes

4-Way

Cache

0084 0000h

128Kbytes

4-Way

Cache

0086 0000h

4-Way

Cache

4-Way

Cache

4-Way

Cache

64Kbytes

32Kbytes

32Kbytes

0087 0000h

0087 8000h

0087 FFFFh

Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.

For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

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5.1.4 MSM SRAM

The MSM SRAM configuration for the C6671 device is as follows:

• Memory size is 4096KB

• The MSM SRAM can be configured as shared L2 and/or shared L3 memory

• Allows extension of external addresses from 2GB to up to 8GB

• Has built in memory protection features

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in

L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller

(MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

5.1.5 L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

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5.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct

DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see

Table 5-1

.

Table 5-1

AIDx Bit

0

0

1

Available Memory Page Protection Schemes

Local Bit Description

0 No access to memory page is permitted.

1

0

Only direct access by DSP is permitted.

Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).

End of Table 5-1

Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

• Block the access — reads return 0, writes are ignored

• Capture the initiator in a status register — ID, address, and access type are stored

• Signal event to DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x DSP CorePac

User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

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5.3 Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware:

• Level 1 Program (L1P) SRAM/Cache

• Level 1 Data (L1D) SRAM/Cache

• Level 2 (L2) SRAM/Cache

• Memory-mapped registers configuration bus

The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x

CorePac. These operations are:

• DSP-initiated transfers

• User-programmed cache coherency operations

• IDMA-initiated transfers

The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the

Priority Allocation Register (PRI_ALLOC), see section 4.3

‘‘Bus Priorities’’ on page 104 for more details. System

peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C66x CorePac can be found in the C66x DSP

CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

5.4 Power-Down Control

The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power requirements.

Note—

The C6671 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the C66x DSP CorePac User

Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

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5.5 C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in

Figure 5-5

and described in

Table 5-2

. The

C66x CorePac revision is dependant on the silicon revision being used.

Figure 5-5 CorePac Revision ID Register (MM_REVID)

Address - 0181 2000h

31

VERSION

R-n

Legend: R = Read; -n = value after reset

16 15

REVISION

R-n

0

Table 5-2

Bit Field

31-16 VERSION

15-0 REVISION

End of Table 5-2

CorePac Revision ID Register (MM_REVID) Field Descriptions

Description

Version of the C66x CorePac implemented on the device.

Revision of the C66x CorePac version implemented on the device.

5.6 C66x CorePac Register Descriptions

See the C66x DSP CorePac User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72 for register

offsets and definitions.

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6 Device Operating Conditions

6.1 Absolute Maximum Ratings

Table 6-1 Absolute Maximum Ratings

(1)

Over Operating Case Temperature Range (Unless Otherwise Noted)

Supply voltage range

Input voltage (V

I

(2)

:

) range:

Output voltage (V

O

) range:

Operating case temperature range, T

ESD stress voltage, V

ESD

(3)

:

C

:

CVDD

CVDD1

DVDD15

DVDD18

VREFSSTL

VDDT1, VDDT2

VDDR1, VDDR2, VDDR3, VDDR4

AVDDA1, AVDDA2, AVDDA3

VSS Ground

LVCMOS (1.8V)

DDR3

I

2

I

2

C

LVDS

LJCB

SerDes

LVCMOS (1.8V)

DDR3

C

SerDes

Commercial

Extended

HBM (human body model)

(4)

CDM (charged device model)

(5)

-0.3 V to 1.3 V

-0.3 V to 1.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

0.49 × DVDD15 to 0.51 × DVDD15

-0.3 V to 1.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

0 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 1.3 V

-0.3 V to CVDD1+0.3 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

-0.3 V to CVDD1+0.3 V

0°C to 85°C

-40°C to 100°C

±1000 V

±250 V

Overshoot/undershoot

(6)

LVCMOS (1.8V)

DDR3

I

2

C

20% Overshoot/Undershoot for 20% of

Signal Duty Cycle

Storage temperature range, T stg

:

End of Table 6-1

-65°C to 150°C

1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2 All voltage values are with respect to V

SS

.

3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.

5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be V

SS

- 0.20 × DVDD18

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6.2 Recommended Operating Conditions

Table 6-2 Recommended Operating Conditions

(1) (2)

CVDD SR Core Supply Initial Startup

1000MHz - Device

1250MHz - Device

Min

VINITnom × 0.95

SRVnom

(4)

× 0.95

SRVnom × 0.95

Nom

1.1

(3)

0.85-1.1

0.9-1.1

Max Unit

VINITnom × 1.05

SRVnom × 1.05

SRVnom × 1.05

V

CVDD1

DVDD18

Core supply voltage for memory array

1.8-V supply I/O voltage

DVDD15 1.5-V supply I/O voltage

VREFSSTL

V

DDRx

(5)

V

DDAx

V

DDTx

DDR3 reference voltage

SerDes regulator supply

PLL analog supply

SerDes termination supply

V

SS

Ground

V

V

T

IH

IL

C

High-level input voltage

Low-level input voltage

Operating case temperature

LVCMOS (1.8 V)

I

2

C

DDR3 EMIF

LVCMOS (1.8 V)

DDR3 EMIF

I

2

C

Commercial

Extended

0.95

1.71

1.425

0.49 × DVDD15

1.425

1.71

0.95

0

0.65 × DVDD18

0.7 × DVDD18

VREFSSTL + 0.1

-0.3

0

-40

1

1.8

1.5

0.5 × DVDD15

1.5

1.8

1

0

1.05

1.89

1.575

0.51 × DVDD15

1.575

1.89

1.05

0

0.35 × DVDD18

VREFSSTL - 0.1

0.3 × DVDD18

85

100

End of Table 6-2

1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE

802.3ae-2002.

2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

3 The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed by TI.

4 SRVnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.

5 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.

°C

°C

V

V

V

V

V

V

V

V

V

V

V

V

V

V

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6.3 Electrical Characteristics

Table 6-3 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

I

V

V

I

OH

OL

(3)

Parameter

LVCMOS (1.8 V)

Low-level output voltage

Input current [DC]

I

DDR3

I

2

C

(2)

LVCMOS (1.8 V)

DDR3

I

2

C

LVCMOS (1.8 V)

2

C

I

O

Test Conditions

= I

OH

(1)

Min

DVDD18 - 0.45

DVDD15 - 0.4

I

I

O

= I

OL

0.45

0.4

O

= 3 mA, pulled up to 1.8 V

No IPD/IPU

Internal pullup

Internal pulldown

-5

50

-170

100

-100

0.4

5

170

(4)

-50

0.1 × DVDD18 V < V

I

< 0.9 ×

DVDD18 V

-10 10

-6

-8

I

I

OH

High-level output current [DC]

LVCMOS (1.8 V)

DDR3

I

2

C

(5)

LVCMOS (1.8 V)

I

OL

Low-level output current [DC]

OZ

(6)

Off-state output current [DC]

DDR3

I

2

C

LVCMOS (1.8 V) -2

DDR3 -2

I

2

C -2

End of Table 6-3

Typ Max

6

8

3

2

2

2

Unit

V

V

A mA mA

A

1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

2

I

2

C uses open collector IOs and does not have a V

OH

Minimum.

3 I

I

applies to input-only pins and bidirectional pins. For input-only pins, I

I off-state (Hi-Z) output leakage current.

indicates the input leakage current. For bidirectional pins, I

I includes input leakage current and

4 For RESETSTAT, max DC input current is 300

A.

5 I

2

C uses open collector IOs and does not have an I

OH

Maximum.

6 I

OZ

applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

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6.4 Power Supply to Peripheral I/O Mapping

Table 6-4 Power Supply to Peripheral I/O Mapping

(1) (2)

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

CVDD

DVDD15

DVDD18

Power Supply

Supply Core Voltage

1.5-V supply I/O voltage

1.8-V supply I/O voltage

I/O Buffer Type

LJCB

DDR3 (1.5 V)

LVCMOS (1.8 V)

Open-drain (1.8V)

Associated Peripheral

CORECLK(P|N) PLL input buffers

SRIOSGMIICLK(P|N) SerDes PLL input buffers

DDRCLK(P|N) PLL input buffers

PCIECLK(P|N) SerDes PLL input buffers

MCMCLK(P|N) SerDes PLL input buffers

PASSCLK(P|N) PLL input buffers

All DDR3 memory controller peripheral I/O buffers

All GPIO peripheral I/O buffers

All JTAG and EMU peripheral I/O buffers

All Timer peripheral I/O buffers

All SPI peripheral I/O buffers

All RESETs, NMI, Control peripheral I/O buffers

All Hyperlink sideband peripheral I/O buffers

All MDIO peripheral I/O buffers

All UART peripheral I/O buffers

All TSIP0 and TSIP1 peripheral I/O buffers

All EMIF16 peripheral I/O buffers

All I

2

C peripheral I/O buffers

All SmartReflex peripheral I/O buffers

Hyperlink SerDes CML IO buffers VDDT1

VDDT2

Hyperlink SerDes termination and analog front-end supply

SRIO/SGMII/PCIE SerDes termination and analog front-end supply

SerDes/CML

SerDes/CML SRIO/SGMII/PCIE SerDes CML IO buffers

End of Table 6-4

1 Note that this table does not attempt to describe all functions of all power supply terminals, but only those whose purpose it is to power peripheral I/O buffers and clock input buffers.

2 See the Hardware Design Guide for KeyStone I Devices in

‘‘Related Documentation from Texas Instruments’’ on page 72 for more information about individual peripheral I/O.

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7 Peripheral Information and Electrical Specifications

This chapter covers the various peripherals on the TMS320C6671 DSP. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

7.1 Parameter Information

This section describes the conditions used to capture the electrical data seen in this chapter.

7.1.1 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays caused by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report in

‘‘Related Documentation from Texas Instruments’’ on page 72. If needed, external logic hardware such as buffers may be used to compensate

any timing differences.

7.1.2 1.8-V LVCMOS Signal Transition Levels

All input and output timing parameters are referenced to VDD/2 for both 0 and 1 logic levels.

Figure 7-1 Input and Output Voltage Reference Levels for AC Timing Measurements

V ref

= VDD / 2

All rise and fall transition timing parameters are referenced to V

IL

V

OL

MAX and V

OH

MIN for output clocks.

MAX and V

IH

MIN for input clocks,

Figure 7-2 Rise and Fall Transition Time Voltage Reference Levels

V ref

= V

IH

MIN (or V

OH

MIN)

V ref

= V

IL

MAX (or V

OL

MAX)

7.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V

IH manner.

and V

IL

(or between V

IL

and V

IH

) in a monotonic

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7.3 Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the

C6671. The various power supply rails and their primary function is listed in Table 7-1 .

Table 7-1 Power Supply Rails on the TMS320C6671

Name

CVDD

CVDD1

VDDT1

VDDT2

DVDD15

VDDR1

VDDR2

VDDR3

VDDR4

Primary Function

SmartReflex core supply voltage

Core supply voltage for memory array

HyperLink SerDes termination supply

SGMII/SRIO/PCIE SerDes termination supply

Voltage

0.9 V to 1.1 V

1.0 V

1.0 V

1.0 V

1.5-V DDR3 IO supply 1.5 V

HyperLink SerDes regulator supply 1.5 V

PCIE SerDes regulator supply

SGMII SerDes regulator supply

SRIO SerDes regulator supply

DVDD18

AVDDA1

AVDDA2

AVDDA3

1.8-V IO supply

Main PLL supply

DDR3 PLL supply

PASS PLL supply

VREFSSTL 0.75-V DDR3 reference voltage

VSS Ground

End of Table 7-1

1.5 V

1.5 V

1.5 V

1.8V

1.8 V

1.8 V

1.8 V

0.75 V

GND

Notes

Includes core voltage for DDR3 module

Fixed supply at 1.0 V

Filtered version of CVDD1. Special considerations for noise. Filter is not needed if HyperLink is not in use.

Filtered version of CVDD1. Special considerations for noise. Filter is not needed if SGMII/SRIO/PCIE is not in use.

Fixed supply at 1.5V

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if HyperLink is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIe is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SGMII is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO is not in use.

Fixed supply at 1.8V

Filtered version of DVDD18. Special considerations for noise.

Filtered version of DVDD18. Special considerations for noise.

Filtered version of DVDD18. Special considerations for noise.

Should track the 1.5-V supply. Use 1.5 V as source.

Ground

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7.3.1 Power-Supply Sequencing

This section defines the requirements for a power up sequencing from a power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.

1.

CVDD

2.

CVDD1, VDDT1-2

3.

DVDD18, AVDD1, AVDD2

4.

DVDD15, VDDR1-4

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

1.

DVDD18, AVDD1, AVDD2

2.

CVDD

3.

CVDD1, VDDT1-2

4.

DVDD15, VDDR1-4

The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until

CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the clock inputs should be removed from the high impedance state shortly after CVDD is present.

If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until

CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.

The device initialization is broken into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase.

This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. REFCLK in the following section refers to the clock input that has been selected as the source for the main PLL and SYSCLK1 refers to the main PLL output that is used by the CorePac, see

Figure 7-9 for more details.

7.3.1.1 Core-Before-IO Power Sequencing

Figure 7-3

shows the power sequencing and reset control of TMS320C6671 for device initialization. POR may be removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the

GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.

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REFCLK must always be active before POR can be removed. Core-before-IO power sequencing is defined in

Table 7-2

.

Note—

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level within 20ms.

Figure 7-3 Core Before IO Power Sequencing

Power Stabilization Phase Device Initialization Phase

POR

7

RESETFULL

8

GPIO Config

Bits

4b 9 10

RESET

1 2c

CVDD

6

2a

CVDD1

3

DVDD18

4a

DVDD15

5

REFCLKP&N

2b

DDRCLKP&N

RESETSTAT

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Table 7-2 Core Before IO Power Sequencing

Time

1

2a

2b

2c

3

System State

Begin Power Stabilization Phase

• CVDD (core AVS) ramps up.

• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from

POR) is put into the reset state.

• Once enabled, the power supply should ramp to its valid voltage level within 20 ms.

• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.

• The maximum duration is 100 ms.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.

• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t6.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.

7

8

4a

4b

5

6

• DVDD15 (1.5 V) supply is ramped up after DVDD18 is valid. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18.

• RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven high.

• POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.

• RESETFULL must be held low for at least 24 transitions of the REFCLK after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.

End Device Initialization Phase

9 • GPIO configuration bits must be valid for at least 12 transitions of the REFCLK before the rising edge of RESETFULL

10 • GPIO configuration bits must be held valid for at least 12 transitions of the REFCLK after the rising edge of RESETFULL

End of Table 7-2

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7.3.1.2 IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in

Figure 7-4

and defined in Table 7-3 .

Note—

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level within 20 ms.

Figure 7-4 IO Before Core Power Sequencing

Power Stabilization Phase Device Initialization Phase

POR

5 7

RESETFULL

8

GPIO Config

Bits

2a

9 10

RESET

3c

2b

CVDD

6

3a

CVDD1

DVDD18

1

4

DVDD15

3b

REFCLKP&N

DDRCLKP&N

RESETSTAT

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Table 7-3 IO Before Core Power Sequencing

4

5

Time

1

2a

2b

3a

3b

3c

System State

Begin Power Stabilization Phase

• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must remain low through Power Stabilization Phase.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before

DVDD18 could cause damage to the device.

• Once enabled, the power supply should ramp to its valid voltage level within 20 ms.

• RESET may be driven high anytime after DVDD18 is at a valid level.

• CVDD (core AVS) ramps up.

• The maximum duration is 100 ms.

• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state with one leg high and one leg low.

• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t6.

• DVDD15 (1.5 V) supply is ramped up after CVDD1 is valid.

• POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

6

7

Begin Device Initialization

• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.

• POR must remain low.

• RESETFULL is held low for at least 24 transitions of the REFCLK after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

8 • Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles.

End Device Initialization Phase

• GPIO configuration bits must be valid for at least 12 transitions of the REFCLK before the rising edge of RESETFULL 9

10 • GPIO configuration bits must be held valid for at least 12 transitions of the REFCLK after the rising edge of RESETFULL

End of Table 7-3

7.3.1.3 Prolonged Resets

Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.

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7.3.1.4 Clocking During Power Sequencing

Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the

clocks is contingent on the state of the boot configuration pins. Table 7-4 describes the clock sequencing and the

conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until

CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the other connected to CVDD.

Table 7-4 Clock Sequencing

Clock

DDRCLK

CORECLK

Condition

None

None

PASSCLKSEL = 0

Sequencing

Must be present 16 μsec before POR transitions high.

CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.

PASSCLK is not used and should be tied to a static state.

PASSCLK

PASSCLKSEL = 1 PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from reset and programmed.

An SGMII port will be used.

SRIOSGMIICLK must be present 16 μsec before POR transitions high.

SGMII will not be used. SRIO will be used as a boot device.

SRIOSGMIICLK must be present 16 μsec before POR transitions high.

SRIOSGMIICLK

SGMII will not be used. SRIO will be used after boot.

SRIOSGMIICLK is used as a source to the SRIO SerDes PLL. It must be present before the SRIO is removed from reset and programmed.

SRIOSGMIICLK is not used and should be tied to a static state.

SGMII will not be used. SRIO will not be used.

PCIE will be used as a boot device.

PCIECLK must be present 16 μsec before POR transitions high.

PCIECLK PCIE will be used after boot.

PCIECLK is used as a source to the PCIE SerDes PLL. It must be present before the PCIE is removed from reset and programmed.

PCIE will not be used.

HyperLink will be used as a boot device.

PCIECLK is not used and should be tied to a static state.

MCMCLK must be present 16usec before POR transitions high.

MCMCLK HyperLink will be used after boot.

MCMCLK is used as a source to the MCM SerDes PLL. It must be present before the HyperLink is removed from reset and programmed.

HyperLink will not be used.

MCMCLK is not used and should be tied to a static state.

End of Table 7-4

7.3.2 Power-Down Sequence

The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,

POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can also affect long term reliability.

7.3.3 Power Supply Decoupling and Bulk Capacitors

In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply

Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone I Devices in ‘‘Related Documentation from Texas Instruments’’ on page 72.

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7.3.4 SmartReflex

Increasing the device complexity increases its power consumption and with the smaller transistor structures responsible for higher achievable clock rates and increased performance, comes an inevitable penalty: increasing the leakage currents. Leakage currents are present in any active circuit, independent of clock rates and usage scenarios.

This static power consumption is mainly determined by the transistor type and process technology used in the manufacture of the device. Higher clock rates also increase dynamic power — the power used when transistors switch. The dynamic power depends mostly on a specific usage scenario, clock rates, and I/O activity.

Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining device performance.

SmartReflex in the TMS320C6671 is a feature that allows the core supply voltage to be optimized based on the process corner of the device. Voltage selection is done using four VCNTL pins that control the output voltage of the core voltage regulator supplying the device. Each TMS320C6671 device in an application requires a separate core voltage regulator. For information on the implementation of SmartReflex, see the Power Consumption Summary for

KeyStone C66x Devices application report and the Hardware Design Guide for KeyStone I Devices in ‘‘Related

Documentation from Texas Instruments’’ on page 72.

Table 7-5

(see Figure 7-5

)

SmartReflex 4-Pin VID Interface Switching Characteristics

2

3

No.

1 td(VCNTL[2:0]-VCNTL[3]) toh(VCNTL[3] -VCNTL[2:0]) td(VCNTL[2:0]-VCNTL[3])

Parameter

Delay Time - VCNTL[2:0] valid after VCNTL[3] low

Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low

Delay Time - VCNTL[2:0] valid after VCNTL[3] high

4

5 toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high

VCNTL being valid to CVDD being switched to SmartReflex Voltage

End of Table 7-5

(2)

1 C = 1/SYSCLK1 frequency in ms

2 SmartReflex voltage must be set before execution of application code

Figure 7-5 SmartReflex 4-Pin VID Interface Timing

Min Max

300.00

0.07

172020C

(1)

0.07

300.00

172020C

10

Unit

ns ms ns ms ms

IV*

SRV

* IV = Initial Voltage

SRV = Smart Reflex Voltage

CVDD

4 5

VCNTL[3]

1 3

VCNTL[2:0]

LSB VID[2:0] MSB VID[5:3]

2

Note—

The initial CVDD voltage (IV) at power on will be 1.1 V nominal and it must transition to the VID set value immediately after being presented on the VCNTL pins. This is required to maintain full power functionality and reliability targets specified by TI.

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7.4 Power Sleep Controller (PSC)

The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations.

For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User

Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

7.4.1 Power Domains

The device has several power domains that can be turned on for operation or off to minimize power dissipation. The global power/sleep controller (GPSC) is used to control the power gating of various power domains.

Table 7-6

shows the TMS320C6671 power domains.

Table 7-6 Power Domains

5

6

3

4

7

8

1

2

Domain

0

Block(s)

Most peripheral logic

Per-core TETB and System TETB

Packet Coprocessor

PCIe

SRIO

HyperLink

Reserved

MSMC RAM

C66x CorePac 0, L1/L2 RAMs

Note

Cannot be disabled

RAMs can be powered down

Logic can be powered down

Logic can be powered down

Logic can be powered down

Logic can be powered down

Reserved

MSMC RAM can be powered down

L2 RAMs can sleep

9

10

11

12

Reserved

Reserved

Reserved

Reserved

13

14

Reserved

Reserved

15 Reserved

End of Table 7-6

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Power Connection

Always on

Software control

Software control

Software control

Software control

Software control

Reserved

Software control

Software control via C66x core. For details, see the

C66x CorePac User Guide.

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

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7.4.2 Clock Domains

Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls the clock gating.

Table 7-7

shows the TMS320C6671 clock domains.

Table 7-7

11

12

13

14

7

8

9

10

5

6

3

4

1

2

LPSC Number

0

15

16

17

18

19

20

21

22

No LPSC

End of Table 7-7

Clock Domains

Module(s)

Shared LPSC for all peripherals other than those listed in this table

SmartReflex

DDR3 EMIF

EMIF16 and SPI

TSIP

Debug Subsystem and Tracers

Per-core TETB and System TETB

Packet Accelerator

Ethernet SGMIIs

Security Accelerator

PCIe

SRIO

HyperLink

Reserved

MSMC RAM

C66x CorePac 0 and Timer 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Bootcfg, PSC, and PLL controller

Notes

Always on

Always on

Always on

Software control

Software control

Software control

Software control

Software control

Software control

Software control

Software control

Software control

Software control

Reserved

Software control

Always on

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

These modules do not use LPSC

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7.4.3 PSC Register Memory Map

Table 7-8

shows the PSC Register memory map.

Table 7-8 PSC Register Memory Map (Part 1 of 3)

0x318

0x31C

0x320

0x324

0x328

0x32C

0x330

0x334

0x338

0x33C

0x21C

0x220

0x224

0x228

0x22C

0x230

0x234

0x238

0x23C

0x240 - 0x2FC

0x300

0x304

0x308

0x30C

0x310

0x314

Offset

0x000

0x004 - 0x010

0x014

0x018 - 0x11C

0x120

0x124

0x128

0x12C - 0x1FC

0x200

0x204

0x208

0x20C

0x210

0x214

0x218

Reserved

Reserved

PDCTL0

PDCTL1

PDCTL2

PDCTL3

PDCTL4

PDCTL5

PDSTAT7

PDSTAT8

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

PDCTL6

PDCTL7

PDCTL8

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

PDSTAT0

PDSTAT1

PDSTAT2

PDSTAT3

PDSTAT4

PDSTAT5

PDSTAT6

Register

PID

Reserved

VCNTLID

Reserved

PTCMD

Reserved

PTSTAT

Description

Peripheral Identification Register

Reserved

Voltage Control Identification Register

(1)

Reserved

Power Domain Transition Command Register

Reserved

Power Domain Transition Status Register

Reserved

Power Domain Status Register 0 (AlwaysOn)

Power Domain Status Register 1 (Per-core TETB and System TETB)

Power Domain Status Register 2 (Packet Coprocessor)

Power Domain Status Register 3 (PCIe)

Power Domain Status Register 4 (SRIO)

Power Domain Status Register 5 (HyperLink)

Power Domain Status Register 6 (Reserved)

Power Domain Status Register 7 (MSMC RAM)

Power Domain Status Register 8 (C66x CorePac 0)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Power Domain Control Register 0 (AlwaysOn)

Power Domain Control Register 1 (Per-core TETB and System TETB)

Power Domain Control Register 2 (Packet Coprocessor)

Power Domain Control Register 3 (PCIe)

Power Domain Control Register 4 (SRIO)

Power Domain Control Register 5 (HyperLink)

Power Domain Control Register 6 (Reserved)

Power Domain Control Register 7 (MSMC RAM)

Power Domain Control Register 8 (C66x CorePac 0)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

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Table 7-8

Offset

0x340 - 0x7FC

0x800

0x804

0x808

0x80C

0x810

0x814

PSC Register Memory Map (Part 2 of 3)

Register

Reserved

MDSTAT0

MDSTAT1

MDSTAT2

MDSTAT3

MDSTAT4

MDSTAT5

Description

Reserved

Module Status Register 0 (Never Gated)

Module Status Register 1 (SmartReflex)

Module Status Register 2 (DDR3 EMIF)

Module Status Register 3 (EMIF16 and SPI)

Module Status Register 4 (TSIP)

Module Status Register 5 (Debug Subsystem and Tracers)

MDCTL0

MDCTL1

MDCTL2

MDCTL3

MDCTL4

MDCTL5

MDCTL6

MDCTL7

MDCTL8

MDSTAT8

MDSTAT9

MDSTAT10

MDSTAT11

MDSTAT12

MDSTAT13

MDSTAT14

MDSTAT15

MDSTAT16

MDSTAT17

MDSTAT18

MDSTAT19

MDSTAT20

MDSTAT21

MDSTAT22

Reserved

MDCTL9

MDCTL10

MDCTL11

MDCTL12

MDCTL13

MDCTL14

MDCTL15

MDCTL16

MDCTL17

0xA24

0xA28

0xA2C

0xA30

0xA34

0xA38

0xA00

0xA04

0xA08

0xA0C

0xA10

0xA14

0xA18

0xA1C

0xA20

0x820

0x824

0x828

0x82C

0x830

0x834

0x838

0x83C

0x840

0x844

0x848

0x84C

0x850

0x854

0x858

0x85C - 0x9FC

0xA3C

0xA40

0xA44

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Module Status Register 8 (Ethernet SGMIIs)

Module Status Register 9 (Security Accelerator)

Module Status Register 10 (PCIe)

Module Status Register 11 (SRIO)

Module Status Register 12 (HyperLink)

Module Status Register 13 (Reserved)

Module Status Register 14 (MSMC RAM)

Module Status Register 15 (C66x CorePac 0 and Timer 0)

Module Control Register 0 (Never Gated)

Module Control Register 1 (SmartReflex)

Module Control Register 2 (DDR3 EMIF)

Module Control Register 3 (EMIF16 and SPI)

Module Control Register 4 (TSIP)

Module Control Register 5 (Debug Subsystem and Tracers)

Module Control Register 6 (Per-core TETB and System TETB)

Module Control Register 7 (Packet Accelerator)

Module Control Register 8 (Ethernet SGMIIs)

Module Control Register 9 (Security Accelerator)

Module Control Register 10 (PCIe)

Module Control Register 11 (SRIO)

Module Control Register 12 (HyperLink)

Module Control Register 13 (Reserved)

Module Control Register 14 (MSMC RAM)

Module Control Register 15 (C66x CorePac 0 and Timer 0)

Reserved

Reserved

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Table 7-8 PSC Register Memory Map (Part 3 of 3)

Offset

0xA48

0xA4C

0xA50

0xA54

0xA58

0xA5C - 0xFFC

End of Table 7-8

Register

MDCTL18

MDCTL19

MDCTL20

MDCTL21

MDCTL22

Reserved

1 VCNTLID register is available for debug purposes only.

Description

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

7.5 Reset Controller

The reset controller detects the different type of resets supported on the TMS320C6671 device and manages the distribution of those resets throughout the device.

The device has several types of resets:

• Power-on reset

• Hard reset

• Soft reset

• CPU local reset

Table 7-9

explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more

information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /

Timing’’ on page 135

Table 7-9 Reset Types

Reset Type Initiator

POR (Power On Reset) POR pin active low

RESETFULL pin active low

Hard Reset

Soft Reset

C66x CorePac local reset

RESET pin active low

Emulation

PLLCTL register (RSCTRL)

Watchdog timers

RESET pin active low

PLLCTL register (RSCTRL)

Watchdog timers

Software (through

LPSC MMR)

Watchdog timers

LRESET pin

Effect on Device When Reset Occurs

Resets everything except for test/emu logic and reset isolation modules. Emulator and reset Isolation modules stay alive during this reset. This reset is also different from POR in that the PLLCTL assumes power and clocks are stable when device reset is asserted. Boot configurations are not latched. ROM boot process is initiated.

RESETSTAT Pin Status

Total reset of the chip. Everything on the device is reset to its default state in response to this. Activates the POR signal on chip, which is used to reset test/emu logic. Boot configurations are latched. ROM boot process is initiated.

Toggles RESETSTAT pin

Toggles RESETSTAT pin

Software can program these initiators to be hard or soft. Hard reset is the default, but can be programmed to be soft reset. Soft reset will behave like hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs, the sticky bits in PCIe MMRs, and external memory contents are retained.

Boot configurations are not latched. ROM boot process is initiated.

Toggles RESETSTAT pin

MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog timers (in the event of a timeout) to reset C66x CorePac. Can also be initiated by LRESET device pin. C66x CorePac memory system and slave

DMA port are still alive when C66x CorePac is in local reset. Provides a local reset of the C66x CorePac, without destroying clock alignment or memory contents. Does not initiate ROM boot process.

Does not toggle

RESETSTAT pin

End of Table 7-9

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7.5.1 Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following

1.

POR pin

2.

RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,

RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on reset, the Main PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.

The following sequence must be followed during a power-on reset:

1.

Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control

registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 74).

2.

Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.

3.

POR must be held active until all supplies on the board are stable then for at least an additional time for the

Chip level PLLs to lock.

4.

The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.

5.

After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3

PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.

6.

The device is now out of reset and device execution begins as dictated by the selected boot mode.

Note—

To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted

(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the

POR pin.

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7.5.2 Hard Reset

A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.

POR should also remain de-asserted during this time.

Hard reset is initiated by the following

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

• Emulation

All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can be configured as soft resets in the RSCFG register in PLLCTL.

The following sequence must be followed during a hard reset:

1.

The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.

2.

Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3.

The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.

4.

After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

Note—

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.

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7.5.3 Soft Reset

A soft reset will behave like a hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs and the PCIe MMRs sticky bits, and external memory contents are retained. POR should also remain de-asserted during this time.

Soft reset is initiated by the following

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can be configured as soft resets in the RSCFG register in PLLCTL.

In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.

During a soft reset, the following happens:

1.

The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

2.

After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL controllers pause their system clocks for about 8 cycles.

At this point:

The state of the peripherals before the soft reset is not changed.

The I/O pins are controlled as dictated by the DEVSTAT register.

The DDR3 MMRs and the PCIe MMRs sticky bits retain their previous values. Only the DDR3

Memory Controller and PCIe state machines are reset by the soft reset.

The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Because the configuration pins are not latched with a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.

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7.5.4 Local Reset

The local reset can be used to reset a particular CorePac without resetting any other chip components.

Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) for KeyStone Devices User

Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72:

• LRESET pin

• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG register in the PLL controller. See

‘‘Reset Configuration Register (RSTCFG)’’

on page 145 and ‘‘CIC Registers’’ on page 175:

Local reset

NMI

NMI followed by a time delay and then a local reset for the CorePac selected

Hard Reset by requesting reset via PLLCTL

• LPSC MMRs (memory-mapped registers)

7.5.5 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.

The reset request priorities are as follows (high to low):

• Power-on reset

• Hard/soft reset

7.5.6 Reset Controller Register

The reset controller register are part of the PLLCTL MMRs. All C6671 device-specific MMRs are covered in Section

7.6.3

‘‘Main PLL Control Register’’ on page 147. For more details on these registers and how to program them, see

the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

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7.5.7 Reset Electrical Data / Timing

Table 7-10 Reset Timing Requirements

(see Figure 7-6

and

Figure 7-7 )

(1)

No.

1 tw(RESETFULL)

RESETFULL Pin Reset

Pulse width - Pulse width RESETFULL low

Soft/Hard-Reset

Pulse width - Pulse width RESET low 2 tw(RESET)

End of Table 7-10

1 C = 1/SYSCLK1 frequency in ns.

500C

500C

Min Max Unit

ns ns

Table 7-11 Reset Switching Characteristics Over Recommended Operating Conditions

(see Figure 7-6

and

Figure 7-7 )

(1)

No.

3 td(RESETFULLH-RESETSTATH)

Parameter

RESETFULL Pin Reset

Delay time - RESETSTAT high after RESETFULL high

Soft/Hard Reset

Delay time - RESETSTAT high after RESET high 4 td(RESETH-RESETSTATH)

End of Table 7-11

1 C = 1/SYSCLK1 frequency in ns.

Min Max Unit

50000C ns

50000C ns

Figure 7-6 RESETFULL Reset Timing

POR

1

RESETFULL

RESET

Figure 7-7

RESETSTAT

Soft/Hard-Reset Timing

POR

RESETFULL

RESET

RESETSTAT

2

3

4

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Table 7-12

(See Figure 7-8

)

Boot Configuration Timing Requirements

(1)

No.

1 tsu(GPIOn-RESETFULL)

2 th(RESETFULL-GPIOn)

End of Table 7-12

1 C = 1/SYSCLK1 frequency in ns.

Figure 7-8

Setup time - GPIO valid before RESETFULL asserted

Hold time - GPIO valid after RESETFULL asserted

Boot Configuration Timing

POR

1

RESETFULL

GPIO[15:0]

2

Min

12C

12C

Max Unit

ns ns

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7.6 Main PLL and PLL Controller

This section provides a description of the Main PLL and the PLL Controller. For details on the operation of the PLL

Controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

The Main PLL is controlled by the standard PLL Controller. The PLL controller manages the clock ratios, alignment, and gating for the system clocks to the device.

Figure 7-9 shows a block diagram of the main PLL and the PLL

Controller.

Figure 7-9 Main PLL and PLL Controller

PLLD

PLL xPLLM

CORECLK(N|P)

0

PLLOUT

1

BYPASS

PLL Controller

1

0

1

PLLEN

PLLENSRC

0

0

/1

PLLDIV1

/x

PLLDIV2

/2

PLLDIV3

/3

PLLDIV4

/y

PLLDIV5

/64

PLLDIV6

/6

PLLDIV7

/z

PLLDIV8

PLLDIV9

PLLDIV10

/3

/6

PLLDIV11

/12

SYSCLK1

C66x

CorePac

SYSCLK2

SYSCLK3

SYSCLK4

SYSCLK5

SYSCLK6

SYSCLK7

SYSCLK8

SYSCLK9

To Switch Fabric,

Peripherals,

Accelerators

SYSCLK10

SYSCLK11

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Note—

The Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the chip-level MAINPLLCTL0 register. The Output Divide and Bypass logic of the PLL are controlled by fields in the SECCTL register in the PLL controller. Only PLLDIV2, PLLDIV5, and

PLLDIV8 are programmable on the C6671 device. See the Phase Locked Loop (PLL) for KeyStone Devices

User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72 for more details on how to

program the PLL controller.

The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the PLL Controller. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone I Devices in

‘‘Related

Documentation from Texas Instruments’’ on page 72 for detailed recommendations. For the best performance, TI

recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see

Section 7.6.5

‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’ .

Note—

The PLL controller module as described in the see the Phase Locked Loop (PLL) for KeyStone Devices

User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72 includes a superset of features,

some of which are not supported on the TMS320C6671 device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

7.6.1 Main PLL Controller Device-Specific Information

7.6.1.1 Internal Clocks and Maximum Operating Frequencies

The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the

DDR3 and the network coprocessor (PASS)) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The Main PLL Controller has several SYSCLK outputs that are listed below, along with the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

SYSCLK1:

Full-rate clock for the CorePac.

SYSCLK2:

1/x-rate clock for CorePac (emulation). Default rate for this is 1/3. This is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.

SYSCLK3:

1/2-rate clock used to clock the MSMC, HyperLink, CPU/2 TeraNet, DDR EMIF and CPU/2

EDMA.

SYSCLK4:

1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs use this as well.

SYSCLK5:

1/y-rate clock for system trace module, only. Default rate for this is 1/5. It is configurable and the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned off by software.

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SYSCLK6:

1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3

EMIF.

SYSCLK7:

1/6-rate clock for slow peripherals (GPIO, UART, Timer, I

2

C, SPI, EMIF16, etc.) and sources the

SYSCLKOUT output pin.

SYSCLK8:

1/z-rate clock. This clock is used as slow_sysclk in the system. Default for this will be 1/64. This is programmable from /24 to /80.

SYSCLK9:

1/12-rate clock for SmartReflex.

SYSCLK10:

1/3-rate clock for SRIO only.

SYSCLK11:

1/6-rate clock for PSC only.

Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on the TMS320C6671 device.

Note—

In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8

(SLOW_SYSCLK) must be programmed to either match, or be slower than, the slowest SYSCLK in the system.

7.6.1.2 Main PLL Controller Operating Modes

The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by BYPASS bit of the PLL Secondary control register (SECCTL). In PLL mode, SYSCLK1 is generated from the PLL output using the values set in PLLM and PLLD bit fields in the MAINPLLCTL0 register. In bypass mode, PLL input is fed directly out as SYSCLK1.

All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

7.6.1.3 Main PLL Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has elapsed.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the

PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see

Table 7-13

.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1) to when to when the PLL Controller can be switched to PLL mode. The Main PLL lock time is given in

Table 7-13

.

Table 7-13 Main PLL Stabilization, Lock, and Reset Times

Min

100

Typ Max Unit

μs PLL stabilization time

PLL lock time

PLL reset time

End of Table 7-13

1 PLLD is the value in PLLD bit fields of MAINPLLCTL0 register

2 C = SYSCLK1 cycle time in ns.

1000

500×(PLLD

(1)

+1)×C

(2) ns

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7.6.2 PLL Controller Memory Map

The memory map of the PLL Controller is shown in

Table 7-14

. TMS320C6671-specific PLL Controller register

definitions can be found in the sections following Table 7-14 . For other registers in the table, see the Phase Locked

Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

Note—

Only registers documented here are accessible on the TMS320C6671. Other addresses in the PLL

Controller memory map including the reserved registers should not be modified. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to make any changes to the valid bits in the register.

Table 7-14 PLL Controller Registers (Including Reset Controller) (Part 1 of 2)

Hex Address Range

0231 0000 - 0231 00E3

0231 00E4

0231 00E8

0231 00EC

0231 00F0

0231 00F0 - 0231 00FF

0231 0100

0231 0104

0231 0108

0231 010C

0231 0110

0231 0114

0231 0118

0231 011C

0231 0120

0231 0124

0231 0128

0231 012C - 0231 0134

0231 0138

0231 013C

0231 0140

0231 0144

0231 0148

0231 014C

0231 0150

0231 0154 - 0231 015C

0231 0160

0231 0164

0231 0168

0231 016C

0231 0170

CKSTAT

SYSTAT

-

PLLDIV4

PLLDIV5

PLLDIV6

PLLDIV7

PLLDIV8

-

-

-

PLLCMD

PLLSTAT

ALNCTL

DCHANGE

CKEN

-

SECCTL

-

PLLM

-

PLLDIV1

PLLDIV2

PLLDIV3

Field

-

RSTYPE

RSTCTRL

RSTCFG

RSISO

-

PLLCTL

Register Name

Reserved

Reset Type Status Register (Reset Controller)

Software Reset Control Register (Reset Controller)

Reset Configuration Register (Reset Controller)

Reset Isolation Register (Reset Controller)

Reserved

PLL Control Register

Reserved

PLL Secondary Control Register

Reserved

PLL Multiplier Control Register

Reserved

Reserved

PLL Controller Divider 2 Register

Reserved

Reserved

Reserved

Reserved

PLL Controller Command Register

PLL Controller Status Register

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

Reserved

Reserved

SYSCLK Status Register

Reserved

Reserved

PLL Controller Divider 5 Register

Reserved

Reserved

PLL Controller Divider 8 Register

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Table 7-14 PLL Controller Registers (Including Reset Controller) (Part 2 of 2)

Hex Address Range

0231 0174 - 0231 0193

0231 0194 - 0231 01FF

End of Table 7-14

Field

PLLDIV9 - PLLDIV16

-

Register Name

Reserved

Reserved

7.6.2.1 PLL Secondary Control Register (SECCTL)

The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-10

and

described in Table 7-15 .

Figure 7-10 PLL Secondary Control Register (SECCTL))

31

Reserved

R-0000 0000

Legend: R/W = Read/Write; R = Read only; -n = value after reset

24 23

BYPASS

RW-0

22

OUTPUT DIVIDE

RW-0001

19 18

Reserved

RW-001 0000 0000 0000 0000

0

Table 7-15 PLL Secondary Control Register (SECCTL) Field Descriptions

Bit Field

31-24 Reserved

Description

Reserved

23 BYPASS

18-0 Reserved

End of Table 7-15

Main PLL Bypass Enable

0 = Main PLL Bypass disabled

1 = Main PLL Bypass enabled

22-19 OUTPUT Output Divider ratio bits.

0h = ÷1. Divide frequency by 1.

1h = ÷2. Divide frequency by 2.

2h - Fh = Reserved.

Reserved

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7.6.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)

The PLL controller divider registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in

Figure 7-11 and described in Table 7-16

. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different

and mentioned in the footnote of Figure 7-11

.

Figure 7-11 PLL Controller Divider Register (PLLDIVn)

31 16

Reserved

R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset

1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8

2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8

15

Dn

(1)

EN

R/W-1

14

Reserved

R-0

8 7

RATIO

R/W-n

(2)

0

Table 7-16 PLL Controller Divider Register (PLLDIVn) Field Descriptions

Bit Field Description

31-16 Reserved Reserved.

15 DnEN Divider

Figure 7-11

)

0 = Divider n is disabled.

1 = No clock output. Divider n is enabled.

7-0 RATIO Divider ratio bits. (see footnote of

Figure 7-11

)

0h = ÷1. Divide frequency by 1.

1h = ÷2. Divide frequency by 2.

2h = ÷3. Divide frequency by 3.

3h = ÷4. Divide frequency by 4.

4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.

End of Table 7-16

7.6.2.3 PLL Controller Clock Align Control Register (ALNCTL)

The PLL Controller clock align control register (ALNCTL) is shown in

Figure 7-12

and described in Table 7-17 .

Figure 7-12 PLL Controller Clock Align Control Register (ALNCTL)

31

Reserved

R-0

8 7

ALN8

R/W-1

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

6

Reserved

5

R-0

4

ALN5

R/W-1

3

Reserved

2

R-0

1

ALN2

R/W-1

0

Reserved

R-0

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Table 7-17

Field

7

4

1

Bit

31-8

6-5

3-2

0

ALN8

ALN5

ALN2

PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Reserved

Description

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYSCLKn alignment. Do not change the default values of these fields.

0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.

The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

End of Table 7-17

7.6.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE status register. During the GO operation, the PLL Controller will change only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks. The PLLDIV divider ratio change status register is shown in

Figure 7-13 and described in Table 7-18 .

Figure 7-13 PLLDIV Divider Ratio Change Status Register (DCHANGE)

31

Reserved

R-0

8 7

SYS8

R/W-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

6

Reserved

5

R-0

4

SYS5

R/W-0

3

Reserved

2

R-0

1

SYS2

R/W-0

0

Reserved

R-0

Table 7-18 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit

31-8

6-5

3-2

0

Field

Reserved

7

4

SYS8

SYS5

1 SYS2

End of Table 7-18

Description

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Identifies when the SYSCLKn divide ratio has been modified.

0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.

1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.

7.6.2.5 SYSCLK Status Register (SYSTAT)

The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in

Figure 7-14 and

described in Table 7-19 .

Figure 7-14

SYSCLK

Status Register (SYSTAT)

31

Reserved

R-n

11 10 9 8 7 6 5 4 3 2 1 0

SYS11ON SYS10ON SYS9ON SYS8ON SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON

R-1 R-1 R-1 R-1

Legend: R/W = Read/Write; R = Read only; -n = value after reset

R-1 R-1 R-1 R-1 R-1 R-1 R-1

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Table 7-19 SYSCLK Status Register (SYSTAT) Field Descriptions

Bit Field Description

31-11 Reserved Reserved. reserved bit location is always read as 0. A value written to this field has no effect.

10-0 SYS[N

(1)

]ON SYSCLK[N] on status.

0 = SYSCLK[N] is gated.

1 = SYSCLK[N] is on.

End of Table 7-19

1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)

7.6.2.6 Reset Type Status Register (RSTYPE)

The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in

Figure 7-15

and described in

Table 7-20 .

Figure 7-15 Reset Type Status Register (RSTYPE)

31

Reserved

29 28

EMU-RST

27

Reserved

R-0 R-0

Legend: R = Read only; -n = value after reset

R-0

12 11

WDRST[N]

R-0

8 7

Reserved

3

R-0

2

PLLCTRLRST

R-0

1

RESET

R-0

0

POR

R-0

Table 7-20

Bit Field

31-29 Reserved

28 EMU-RST

Reset Type Status Register (RSTYPE) Field Descriptions

27-12 Reserved

9

8

11

10

WDRST3

WDRST2

WDRST1

WDRST0

7-3

2

Reserved

PLLCTLRST

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by emulation.

0 = Not the last reset to occur.

1 = The last reset to occur.

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by watchdog timer[N].

0 = Not the last reset to occur.

1 = The last reset to occur.

1

0

RESET

POR

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by PLLCTL.

0 = Not the last reset to occur.

1 = The last reset to occur.

RESET reset.

0 = RESET was not the last reset to occur.

1 = RESET was the last reset to occur.

Power-on reset.

0 = Power-on reset was not the last reset to occur.

1 = Power-on reset was the last reset to occur.

End of Table 7-20

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7.6.2.7 Reset Control Register (RSTCTRL)

This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register

(RSTCTRL) is shown in Figure 7-16

and described in

Table 7-21

.

Figure 7-16 Reset Control Register (RSTCTRL)

31

Reserved

R-0x0000

Legend: R = Read only; -n = value after reset;

1 Writes are conditional based on valid key.

17 16

SWRST

R/W-0x

(1)

15

KEY

R/W-0x0003

0

Table 7-21

Bit Field

31-17 Reserved

16 SWRST

Reset Control Register (RSTCTRL) Field Descriptions

15-0 KEY

End of Table 7-21

Description

Reserved.

Software reset

0 = Reset

1 = Not reset

Key used to enable writes to RSTCTRL and RSTCFG.

7.6.2.8 Reset Configuration Register (RSTCFG)

This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL Controller’s

RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard resets. The Reset

Configuration Register (RSTCFG) is shown in

Figure 7-17 and described in Table 7-22 .

Figure 7-17 Reset Configuration Register (RSTCFG)

31

Reserved

R-0

14 13

PLLCTLRSTTYPE

R/W-0

(2)

12

RESETTYPE

R/W-0

2

11

Reserved

R-0

4

Legend: R = Read only; R/W = Read/Write; -n = value after reset

1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)

2 Writes are conditional based on valid key. For details, see Section 7.6.2.7

‘‘Reset Control Register (RSTCTRL)’’

.

3

WDTYPE[N

(1)

]

R/W-0

2

0

Table 7-22 Reset Configuration Register (RSTCFG) Field Descriptions (Part 1 of 2)

Bit Field

31-14 Reserved

13

12

Description

Reserved.

PLLCTLRSTTYPE PLL Controller initiates a software-driven reset of type:

0 = Hard reset (default)

1 = Soft reset

RESETTYPE RESET initiates a reset of type:

0 = Hard reset (default)

1 = Soft reset

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Table 7-22 Reset Configuration Register (RSTCFG) Field Descriptions (Part 2 of 2)

Bit

11-4

Field

Reserved

3

2

1

WDTYPE3

WDTYPE2

WDTYPE1

0 WDTYPE0

End of Table 7-22

Description

Reserved.

Watchdog timer [N] initiates a reset of type:

0 = Hard reset (default)

1 = Soft reset

7.6.2.9 Reset Isolation Register (RSISO)

This register is used to select the module clocks that must maintain their clocking without pausing through non power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current values of PLL multiplier, divide ratios and other settings. Along with setting module specific bit in RSISO, the corresponding MDCTLx[12] bit also must be set in PSC to reset isolate a particular module. For more information

on MDCTLx register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 72. The Reset Isolation Register (RSTCTRL) is shown in

Figure 7-18

and described in

Table 7-23 .

Figure 7-18 Reset Isolation Register (RSISO)

31

Reserved

R-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

10 9

SRIOISO

R/W-0

8

SRISO

R/W-0

7

Reserved

R-0

0

Table 7-23

Bit Field

31-10 Reserved

9 SRIOISO

8 SRISO

Reset Isolation Register (RSISO) Field Descriptions

7-0 Reserved

End of Table 7-23

Description

Reserved.

Isolate SRIO module

0 = Not reset isolated

1 = Reset Isolated

Isolate SmartReflex

0 = Not reset isolated

1 = Reset Isolated

Reserved.

Note—

The boot ROM code will enable the reset isolation for both SRIO and SmartReflex modules during boot with the Reset Isolation Register. It is up to the user application to disable.

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7.6.3 Main PLL Control Register

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL Controller for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using KICK0/KICK1 registers. For valid configurable values into the

MAINPLLCTL0 and MAINPLLCTL1 registers see Section 2.5.4

‘‘PLL Boot Configuration Settings’’ on page 38. See

section 3.3.4

‘‘Kicker Mechanism Register (KICK0 and KICK1)’’ on page 80 for the address location of the registers

and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.

Figure 7-19 Main PLL Control Register 0 (MAINPLLCTL0)

31 24 23

BWADJ[7:0]

RW-0000 0101

Legend: RW = Read/Write; -n = value after reset

Reserved

RW-0000 0

19 18

PLLM[12:6]

RW-0000000

12 11

Reserved

6

RW-000000

5 0

PLLD

RW-000000

Table 7-24 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions

Bit Field

31-24 BWADJ[7:0]

23-19 Reserved

18-12 PLLM[12:6]

11-6 Reserved

5-0 PLLD

End of Table 7-24

Description

BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

Reserved

A 13-bit bus that selects the values for the multiplication factor (see

Note—

below)

Reserved

A 6-bit bus that selects the values for the reference divider

Figure 7-20 Main PLL Control Register 1 (MAINPLLCTL1)

31

Reserved

RW-0000000000000000000000000

Legend: RW = Read/Write; -n = value after reset

7 6

ENSAT

RW-0

5

Reserved

4

RW-00

3

BWADJ[11:8]

RW-0000

0

Table 7-25

Bit

31-7

6

5-4

3-0

Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions

Field

Reserved

ENSAT

Reserved

BWADJ[11:8]

Description

Reserved

Must be set to 1 for proper operation of PLL

Reserved

BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

End of Table 7-25

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Note—

PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL Controller and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The MAINPLLCTL0 register

PLLM[12:6] bits should be written just before writing to the PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the

Phase Locked Loop (PLL) for KeyStone Devices User Guide in

‘‘Related Documentation from Texas

Instruments’’ on page 72 for the recommended programming sequence. Output divide ratio and Bypass

enable/disable of the Main PLL is controlled by the SECCTL register in the PLL Controller. See the

7.6.2.1

‘‘PLL Secondary Control Register (SECCTL)’’

for more details.

7.6.4 Main PLL and PLL Controller Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 72 for details on the initialization sequence for Main PLL and PLL Controller.

7.6.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing

2

3

4

3

2

1

1

2

3

4

3

2

1

1

4

5

5

Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements

(see Figure 7-21 and Figure 7-22 )

(1)

(Part 1 of 2)

No.

4

5

5

5

5 tc(CORCLKN) tc(CORECLKP) tw(CORECLKN) tw(CORECLKN) tw(CORECLKP) tw(CORECLKP) tr(CORECLK_250mv) tf(CORECLK_250mv) tj(CORECLKN) tj(CORECLKP) tc(SRIOSGMIICLKN) tc(SRIOSGMIICLKP) tw(SRIOSGMIICLKN) tw(SRIOSGMIICLKN) tw(SRIOSGMIICLKP) tw(SRIOSGMIICLKP) tr(SRIOSGMIICLK_

250mv) tf(SRIOSGMIICLK_

250mv) tj(SRIOSGMIICLKN) tj(SRIOSGMIICLKP) tj(SRIOSGMIICLKN) tj(SRIOSGMIICLKP)

Min Max Unit

CORECLK[P:N]

Cycle time _ CORECLKN cycle time

Cycle time _ CORECLKP cycle time

Pulse width _ CORECLKN high

Pulse width _ CORECLKN low

Pulse width _ CORECLKP high

Pulse width _ CORECLKP low

Transition time _ CORECLK differential rise time

(250mV)

Transition time _ CORECLK differential fall time (250mV)

Jitter, peak_to_peak _ periodic CORECLKN

Jitter, peak_to_peak _ periodic CORECLKP

SRIOSGMIICLK[P:N]

Cycle time _ SRIOSGMIICLKN cycle time

Cycle time _ SRIOSGMIICLKP cycle time

Pulse width _ SRIOSGMIICLKN high

Pulse width _ SRIOSGMIICLKN low

Pulse width _ SRIOSGMIICLKP high

Pulse width _ SRIOSGMIICLKP low

Transition time _ SRIOSGMIICLK differential rise time

(250 mV)

Transition time _ SRIOSGMIICLK differential fall time

(250 mV)

Jitter, peak_to_peak _ periodic SRIOSGMIICLKN

Jitter, peak_to_peak _ periodic SRIOSGMIICLKP

Jitter, peak_to_peak _ periodic SRIOSGMIICLKN (SRIO not used)

Jitter, peak_to_peak _ periodic SRIOSGMIICLKP (SRIO not used)

3.2

3.2

0.45*tc(CORECLKN)

0.45*tc(CORECLKN)

0.45*tc(CORECLKP)

0.45*tc(CORECLKP)

50

50

25

25

0.55*tc(CORECLKN)

0.55*tc(CORECLKN)

0.55*tc(CORECLKP)

0.55*tc(CORECLKP)

3.2 or 4 or 6.4

3.2 or 4 or 6.4

0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)

0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)

0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)

0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)

50

50

350

350

0.02*tc(CORECLKN)

0.02*tc(CORECLKP)

350

350

4

4

(2)

(2)

ps ps ps ps ps ps ps,RMS ps,RMS ns ns ns ns ns ns ns ns ns ns ns ns

8

(2)

ps,RMS

8

(2)

ps,RMS

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Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements

(see Figure 7-21 and Figure 7-22 )

(1)

(Part 2 of 2)

No.

Min Max Unit

4

4

2

3

5

5

3

2

1

1 tc(MCMCLKN) tc(MCMCLKP) tw(MCMCLKN) tw(MCMCLKN) tw(MCMCLKP) tw(MCMCLKP) tr(MCMCLK_250mv) tf(MCMCLK_250mv) tj(MCMCLKN) tj(MCMCLKP)

4

4

2

3

3

2

1

1 tc(PCIECLKN) tc(PCIECLKP) tw(PCIECLKN) tw(PCIECLKN) tw(PCIECLKP) tw(PCIECLKP) tr(PCIECLK_250mv) tf(PCIECLK_250mv)

5 tj(PCIECLKN)

5 tj(PCIECLKP)

End of Table 7-26

HyperLinkCLK[P:N]

Cycle time _ MCMCLKN cycle time

Cycle time _ MCMCLKP cycle time

Pulse width _ MCMCLKN high

Pulse width _ MCMCLKN low

Pulse width _ MCMCLKP high

Pulse width _ MCMCLKP low

Transition time _ MCMCLK differential rise time (250mV)

Transition time _ MCMCLK differential fall time (250mV)

Jitter, peak_to_peak _ periodic MCMCLKN

Jitter, peak_to_peak _ periodic MCMCLKP

PCIECLK[P:N]

Cycle time _ PCIECLKN cycle time

Cycle time _ PCIECLKP cycle time

Pulse width _ PCIECLKN high

Pulse width _ PCIECLKN low

Pulse width _ PCIECLKP high

Pulse width _ PCIECLKP low

Transition time _ PCIECLK differential rise time (250 mV)

Transition time _ PCIECLK differential fall time (250 mV)

Jitter, peak_to_peak _ periodic PCIECLKN

Jitter, peak_to_peak _ periodic PCIECLKP

3.2 or 4 or 6.4

3.2 or 4 or 6.4

0.45*tc(MCMCLKN)

0.45*tc(MCMCLKN)

0.45*tc(MCMCLKP)

0.45*tc(MCMCLKP)

50

50

0.45*tc(PCIECLKN)

0.45*tc(PCIECLKN)

0.45*tc(PCIECLKP)

0.45*tc(PCIECLKP)

50

50

0.55*tc(MCMCLKN)

0.55*tc(MCMCLKN)

0.55*tc(MCMCLKP)

0.55*tc(MCMCLKP)

3.2 or 4 or 6.4 or 10

3.2 or 4 or 6.4 or 10

350

350

4

(2)

4

(2)

0.55*tc(PCIECLKN)

0.55*tc(PCIECLKN)

0.55*tc(PCIECLKP)

0.55*tc(PCIECLKP)

350

350

4

(2)

4

(2)

ns ns ps ps ns ns ns ns ps,RMS ps,RMS ns ns ps ps ns ns ns ns ps,RMS ps,RMS

1 See the Hardware Design Guide for KeyStone I Devices in

‘‘Related Documentation from Texas Instruments’’ on page 72 for detailed recommendations.

2 The jitter frequency mask shown in the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 72 must also be met for

the specific operating mode chosen.

Figure 7-21 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing

1

2

<CLK_NAME>CLKN

<CLK_NAME>CLKP

4

Figure 7-22 Main PLL Clock Input Transition Time

3

5 peak-to-peak Differential Input

Voltage (250 mV to 2 V)

0

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7.7 DD3 PLL

The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

DDR3 PLL power is supplied externally via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone I Devices in

‘‘Related

Documentation from Texas Instruments’’ on page 72. For the best performance, TI recommends that all the PLL

external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI filter).

Figure 7-23

shows the DDR3 PLL.

Figure 7-23 DDR3 PLL Block Diagram

PLLD

DDR3 PLL xPLLM

DDRCLK(N|P)

0

PLLOUT

DDR3

PHY

1

BYPASS

7.7.1 DDR3 PLL Control Register

The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs

(memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through

an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.4

‘‘PLL Boot

Configuration Settings’’

on page 38. See section 3.3.4

‘‘Kicker Mechanism Register (KICK0 and KICK1)’’ on page 80 for the address location of the registers and locking and unlocking sequences for accessing the registers. This

register is reset on POR only.

.

Figure 7-24 DDR3 PLL Control Register 0 (DDR3PLLCTL0)

(1)

31

BWADJ[7:0]

RW-0000 1001

24 23

BYPASS

RW-0

22 19

Reserved

RW-0001

18

PLLM

RW-0000000010011

6 5

PLLD

0

RW-000000

Legend: RW = Read/Write; -n = value after reset

1 This register is reset on POR only. The regreset, reset, and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

Table 7-27

Bit Field

31-24 BWADJ[7:0]

23 BYPASS

DDR3 PLL Control Register 0 Field Descriptions (Part 1 of 2)

22-19 Reserved

Description

BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

Enable bypass mode

0 = Bypass disabled

1 = Bypass enabled

Reserved

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Table 7-27

Bit

18-6

Field

PLLM

5-0 PLLD

End of Table 7-27

DDR3 PLL Control Register 0 Field Descriptions (Part 2 of 2)

Description

A 13-bit bus that selects the values for the multiplication factor

A 6-bit bus that selects the values for the reference divider

Figure 7-25 DDR3 PLL Control Register 1 (DDR3PLLCTL1)

12 31 14

Reserved

RW-000000000000000000

Legend: RW = Read/Write; -n = value after reset

13

PLLRST

RW-0

Reserved

RW-000000

7 6

ENSAT

RW-0

5

Reserved

4

R-0

3

BWADJ[11:8]

RW-0000

0

Table 7-28

Bit Field

31-14 Reserved

13 PLLRST

12-7

6

5-4

3-0

DDR3 PLL Control Register 1 Field Descriptions

Reserved

ENSAT

Reserved

BWADJ[11:8]

Description

Reserved

PLL reset bit.

0 = PLL reset is released.

1 = PLL reset is asserted.

Reserved

Must be set to 1 for proper operation of PLL

Reserved

BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

End of Table 7-28

7.7.2 DDR3 PLL Device-Specific Information

As shown in Figure 7-23

, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3

PLL are affected as described in Section 7.5

‘‘Reset Controller’’ on page 130. DDR3 PLL is unlocked only during the

power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

7.7.3 DDR3 PLL Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 72 for details on the initialization sequence for DDR3 PLL.

Note—

The DDR3 interface must reset every time the DDR3 PLL is re-programmed.

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7.7.4 DDR3 PLL Input Clock Electrical Data/Timing

Table 7-29 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements

(see Figure 7-26

and Figure 7-22 )

No.

DDRCLK[P:N]

4

4

2

3

3

2

1

1 tc(DDRCLKN) tc(DDRCLKP) tw(DDRCLKN) tw(DDRCLKN) tw(DDRCLKP) tw(DDRCLKP)

5 tj(DDRCLKN)

5 tj(DDRCLKP)

End of Table 7-29

Cycle time _ DDRCLKN cycle time

Cycle time _ DDRCLKP cycle time

Pulse width _ DDRCLKN high

Pulse width _ DDRCLKN low

Pulse width _ DDRCLKP high

Pulse width _ DDRCLKP low tr(DDRCLK_250mv) Transition time _ DDRCLK differential rise time (250 mV) tf(DDRCLK_250mv) Transition time _ DDRCLK differential fall time (250 mV)

Jitter, peak_to_peak _ periodic DDRCLKN

Jitter, peak_to_peak _ periodic DDRCLKP

Figure 7-26 DDR3 PLL DDRCLK Timing

1

2

DDRCLKN

DDRCLKP

4

Min Max Unit

3.2

3.2

0.45*tc(DDRCLKN)

0.45*tc(DDRCLKN)

0.45*tc(DDRCLKP)

0.45*tc(DDRCLKP)

50

50

25

25

0.55*tc(DDRCLKN)

0.55*tc(DDRCLKN)

0.55*tc(DDRCLKP)

0.55*tc(DDRCLKP)

350

350

0.02*tc(DDRCLKN)

0.02*tc(DDRCLKP) ns ns ps ps ns ns ns ns ps ps

3

5

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7.8 PASS PLL

The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select the input source of PASS PLL as either the output of CORECLK clock reference sources or the PASSCLK clock reference sources. When coming out of power-on reset, PASS PLL comes out in a bypass mode and must be programmed to a valid frequency before being enabled and used.

PASS PLL power is supplied via the PASS PLL power-supply pin (AVDDA3). An external EMI filter circuit must be

added to all PLL supplies. See the Hardware Design Guide for KeyStone I Devices in ‘‘Related Documentation from

Texas Instruments’’ on page 72. for detailed recommendations. For the best performance, TI recommends that all

the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

Figure 7-27

shows the PASS PLL.

Figure 7-27 PASS PLL Block Diagram

PLL

PLLOUT

PLL

Controller

SYSCLK

n

SYSCLK1

C66x

CorePac

CORECLK(P|N)

PASSCLK(P|N)

PACLKSEL

PLLD

PASS PLL xPLLM / /2

0

/3

Network

Coprocessor

1

PLLOUT

BYPASS

PLLSELECT

7.8.1 PASS PLL Control Register

The PASS PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. The PASS PLL can be controlled using the PASSPLLCTL0 and PASSPLLCTL1 registers located in Bootcfg module. These MMRs

(memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through

an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.4

‘‘PLL Boot

Configuration Settings’’

on page 38. See section 3.3.4

‘‘Kicker Mechanism Register (KICK0 and KICK1)’’ on page 80

for the address location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on POR only.

.

Figure 7-28 PASS PLL Control Register 0 (PASSPLLCTL0)

(1)

31

BWADJ[7:0]

RW-0000 1001

24 23

BYPASS

RW-0

22 19

Reserved

RW-0001

18

PLLM

RW-0000000010011

6 5

PLLD

0

RW-000000

Legend: RW = Read/Write; -n = value after reset

1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

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Table 7-30

Bit Field

31-24 BWADJ[7:0]

23 BYPASS

PASS PLL Control Register 0 Field Descriptions

22-19 Reserved

18-6 PLLM

5-0 PLLD

End of Table 7-30

Description

BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

Enable bypass mode

0 = Bypass disabled

1 = Bypass enabled

Reserved

A 13-bit bus that selects the values for the multiplication factor

A 6-bit bus that selects the values for the reference divider

Figure 7-29 PASS PLL Control Register 1 (PASSPLLCTL1)

31

Reserved

RW-00000000000000000

15

Legend: RW = Read/Write; -n = value after reset

14

RW-0

13

PLLRST PLLSELECT

RW-0

12

Reserved

RW-000000

7 6

ENSAT

RW-0

5

Reserved

4

R-0

3

BWADJ[11:8]

RW-0000

0

Table 7-31 PASS PLL Control Register 1 Field Descriptions

Bit Field

31-15 Reserved

14 PLLRST

13

12-7

6

5-4

3-0

PLLSELECT

Reserved

ENSAT

Reserved

BWADJ[11:8]

Description

Reserved

PLL reset bit.

0 = PLL reset is released

1 = PLL reset is asserted

PASS PLL select bit. Note that this bit must be set before the Ethernet subsystem is configured and used.

0 = Reserved

1 = PASS PLL output clock is used as the input to PASS

Reserved

Must be set to 1 for proper operation of the PLL

Reserved

BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

End of Table 7-31

7.8.2 PASS PLL Device-Specific Information

As shown in

Figure 7-27 , the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Network

Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS

PLL are affected as described in Section 7.5

‘‘Reset Controller’’ on page 130. The PASS PLL is unlocked only during

the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

7.8.3 PASS PLL Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 72 for details on the initialization sequence for PASS PLL.

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7.8.4 PASS PLL Input Clock Electrical Data/Timing

4

4

2

3

5

5

3

2

1

1

Table 7-32 PASS PLL Timing Requirements

(See Figure 7-30

and Figure 7-22

)

No.

tc(PASSCLKN) tc(PASSCLKP) tw(PASSCLKN) tw(PASSCLKN) tw(PASSCLKP) tw(PASSCLKP) tr(PASSCLK_250mv) tf(PASSCLK_250mv) tj(PASSCLKN) tj(PASSCLKP)

PASSCLK[P:N]

Cycle Time _ PASSCLKN cycle time

Cycle Time _ PASSCLKP cycle time

Pulse Width _ PASSCLKN high

Pulse Width _ PASSCLKN low

Pulse Width _ PASSCLKP high

Pulse Width _ PASSCLKP low

Transition time _ PASSCLK differential rise time (250 mV)

Transition time _ PASSCLK differential fall time (250 mV)

Jitter, peak_to_peak _ periodic PASSCLKN

Jitter, peak_to_peak _ periodic PASSCLKP

Min Max Unit

3.2

3.2

25

25

0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)

0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)

0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)

0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)

50

50

350

350 ns ns ns ns ns ns ps ps

0.02*tc(PASSCLKN) ps, pk-pk

0.02*tc(PASSCLKP) ps, pk-pk

Figure 7-30 PASS PLL Timing

1

2 3

PASSCLKN

PASSCLKP

4 5

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7.9 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device CPU.

There are 3 EDMA Channel Controllers on the C6671 DSP, EDMA3CC0, EDMA3CC1, and EDMA3CC2.

• EDMA3CC0 has two transfer controllers: EDMA3TC1 and EDMA3TC2.

• EDMA3CC1 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.

• EDMA3CC2 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.

In the context of this document, EDMA3TCx associated with EDMA3CCy, and is referred to as EDMA3CCy TCx.

Each of the transfer controllers has a direct connection to the switch fabric. Section 4.2

‘‘Switch Fabric Connections’’

lists the peripherals that can be accessed by the transfer controllers.

EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 subsytems. The others are to be used for the remaining traffic.

Each EDMA3 Channel Controller includes the following features:

• Fully orthogonal transfer description

Three transfer dimensions:

Array (multiple bytes)

Frame (multiple arrays)

Block (multiple frames)

Single event can trigger transfer of array, frame, or entire block

Independent indexes on source and destination

• Flexible transfer definition:

Increment or FIFO transfer addressing modes

Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention

Chaining allows multiple transfers to execute with one event

• 128 PaRAM entries for EDMA3CC0, 512 each for EDMA3CC1 and EDMA3CC2

Used to define transfer context for channels

Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

• 16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2

Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another)

• 8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller

Used for software-driven transfers

Triggered upon writing to a single PaRAM set entry

• Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, four transfer controllers and four event queues with programmable system-level priority per channel controller for

EDMA3CC1 and EDMA3CC2

• Interrupt generation for transfer completion and error conditions

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• Debug visibility

Queue watermarking/threshold allows detection of maximum usage of event queues

Error and status recording to facilitate debug

7.9.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases. For most applications, increment mode must be used.

For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3)

Controller for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

For the range of memory addresses that include EDMA3 channel controller (EDMA3CC) control registers and

EDMA3 transfer controller (EDMA3TC) control register see Section Table 2-2 ‘‘Memory Map Summary’’ on page 17. For memory offsets and other details on EDMA3CC and EDMA3TC control registers entries, see the

Enhanced Direct Memory Access 3 (EDMA3) Controller for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

7.9.2 EDMA3 Channel Controller Configuration

Table 7-33

shows the configuration for each of the EDMA3 channel controllers present on the device.

Table 7-33 EDMA3 Channel Controller Configuration

Description

Number of DMA channels in Channel Controller

Number of QDMA channels

Number of interrupt channels

Number of PaRAM set entries

Number of event queues

Number of Transfer Controllers

Memory Protection Existence

Number of Memory Protection and Shadow Regions

End of Table 7-33

128

2

2

Yes

8

EDMA3 CC0 EDMA3 CC1 EDMA3 CC2

16 64 64

8

16

8

64

8

64

512

4

4

Yes

8

512

4

4

Yes

8

7.9.3 EDMA3 Transfer Controller Configuration

Each transfer controller on a device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the transfer controller configurations are:

FIFOSIZE:

Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.

The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.

BUSWIDTH:

The width of the read and write data buses in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.

Default Burst Size (DBS):

The DBS is the maximum number of bytes per read/write command issued by a transfer controller.

DSTREGDEPTH:

This determines the number of destination FIFO register set. The number of destination

FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.

All four parameters listed above are fixed by the design of the device.

Table 7-34

shows the configuration for each of the EDMA3 transfer controllers present on the device.

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Table 7-34 EDMA3 Transfer Controller Configuration

Parameter

FIFOSIZE

TC0

EDMA3 CC0

TC1 TC0 TC1

EDMA3 CC1

TC2 TC3 TC0 TC1

EDMA3 CC2

TC2 TC3

1024 bytes 1024 bytes 1024 bytes 512 bytes 1024 bytes 512 bytes 1024 bytes 512 bytes 512 bytes 1024 bytes

BUSWIDTH 32 bytes

DSTREGDEPTH 4 entries

DBS 128 bytes

End of Table 7-34

32 bytes

4 entries

128 bytes

16 bytes

4 entries

128 bytes

16 bytes

4 entries

64 bytes

16 bytes

4 entries

128 bytes

16 bytes

4 entries

64 bytes

16 bytes

4 entries

128 bytes

16 bytes

4 entries

64 bytes

16 bytes

4 entries

64 bytes

16 bytes

4 entries

128 bytes

7.9.4 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2 that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables lists the source of the synchronization event associated with each of the EDMA EDMA3CC DMA channels. On the C6671, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) Controller for

KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

Table 7-35 EDMA3CC0 Events for C6671

6

7

8

3

4

5

9

10

1

2

Event Number

0

11

12

13

14

15

End of Table 7-35

Event

TINT8L

TINT8H

TINT9L

TINT9H

TINT10L

TINT10H

TINT11L

TINT11H

CIC3_OUT0

CIC3_OUT1

CIC3_OUT2

CIC3_OUT3

CIC3_OUT4

CIC3_OUT5

CIC3_OUT6

CIC3_OUT7

Event Description

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Table 7-36

1

2

Event Number

0

3

EDMA3CC1 Events for C6671 (Part 1 of 3)

Event

SPIINT0

SPIINT1

SPIXEVT

SPIREVT

Event Description

SPI interrupt

SPI interrupt

Transmit event

Receive event

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Table 7-36

30

31

32

33

26

27

28

29

22

23

24

25

18

19

20

21

14

15

16

17

10

11

12

13

8

9

6

7

Event Number

4

5

42

43

44

45

46

47

38

39

40

41

34

35

36

37

EDMA3CC1 Events for C6671 (Part 2 of 3)

TINT10L

TINT10H

TINT11L

TINT11H

TINT12L

TINT12H

TINT13L

TINT13H

Reserved

Reserved

Reserved

Reserved

TINT8L

TINT8H

TINT9L

TINT9H

Event

I2CREVT

I2CXEVT

GPINT0

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT7

SEMINT0

Reserved

Reserved

Reserved

TINT14L

TINT14H

TINT15L

TINT15L

CIC2_OUT44

CIC2_OUT45

CIC2_OUT46

CIC2_OUT47

CIC2_OUT0

CIC2_OUT1

CIC2_OUT2

CIC2_OUT3

CIC2_OUT4

CIC2_OUT5

Event Description

I2C receive event

I2C transmit event

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

Semaphore interrupt

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

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Table 7-36 EDMA3CC1 Events for C6671 (Part 3 of 3)

50

51

52

53

Event Number

48

49

58

59

60

61

54

55

56

57

62

63

End of Table 7-36

Event

CIC2_OUT6

CIC2_OUT7

CIC2_OUT8

CIC2_OUT9

CIC2_OUT10

CIC2_OUT11

CIC2_OUT12

CIC2_OUT13

CIC2_OUT14

CIC2_OUT15

CIC2_OUT16

CIC2_OUT17

CIC2_OUT18

CIC2_OUT19

CIC2_OUT20

CIC2_OUT21

Event Description

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

17

18

19

14

15

16

20

21

22

Table 7-37

11

12

13

7

8

9

10

5

6

3

4

1

2

Event Number

0

EDMA3CC2 Events for C6671 (Part 1 of 2)

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT7

Event

SPIINT0

SPIINT1

SPIXEVT

SPIREVT

I2CREVT

I2CXEVT

GPINT0

Event Description

SPI interrupt

SPI interrupt

Transmit event

Receive event

I2C receive event

I2C transmit event

GPIO interrupt

GPIO interrupt

GPIO Interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

Semaphore interrupt SEMINT0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TINT8L Timer interrupt low

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Table 7-37

49

50

51

52

45

46

47

48

41

42

43

44

37

38

39

40

33

34

35

36

29

30

31

32

25

26

27

28

Event Number

23

24

57

58

59

60

53

54

55

56

61

62

63

End of Table 7-37

EDMA3CC2 Events for C6671 (Part 2 of 2)

TINT15H

CIC2_OUT48

CIC2_OUT49

URXEVT

UTXEVT

CIC2_OUT22

CIC2_OUT23

CIC2_OUT24

CIC2_OUT25

CIC2_OUT26

CIC2_OUT27

CIC2_OUT28

CIC2_OUT29

CIC2_OUT30

CIC2_OUT31

CIC2_OUT32

Event

TINT8H

TINT9L

TINT9H

TINT10L

TINT10H

TINT11L

TINT11H

TINT12L

TINT12H

TINT13L

TINT13H

TINT14L

TINT14H

TINT15L

CIC2_OUT33

CIC2_OUT34

CIC2_OUT35

CIC2_OUT36

CIC2_OUT37

CIC2_OUT38

CIC2_OUT39

CIC2_OUT40

CIC2_OUT41

CIC2_OUT42

CIC2_OUT43

Event Description

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Interrupt Controller output

Interrupt Controller output

UART receive event

UART transmit event

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

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7.10 Interrupts

7.10.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the C6671 device are configured through the C66x CorePac Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs

(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through chip interrupt controller (CIC) blocks. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to the C66x CorePac, plus the

EDMA3CC and CIC0 provide 17 additional events as well as 8 broadcast events to the C66x CorePac, CIC2 provides

26 and 24 additional events to EDMA3CC1 and EDMA3CC2 respectively, and CIC3 provides 8 and 32 additional events to EDMA3CC0 and HyperLink respectively.

There are a large number of events at the chip level. The chip level CIC provides a flexible way to combine and remap those events. Multiple events can be combined to a single event through chip level CIC. However, an event can be mapped only to a single event output from the chip level CIC. The chip level CIC also allows the software to trigger system event through memory writes. For more details on the CIC features, see the Chip Interrupt Controller (CIC)

for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

Note—

Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and EOI handshaking interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.

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Figure 7-31

shows the C6671 interrupt topology.

Figure 7-31 TMS320C6671 Interrupt Topology

15 Reserved Secondary Events

89 Core-only Secondary Events

56 Common Events

56 Common Events

44 Reserved Secondary Events

60 EDMA3CC-only

Secondary Events

CIC0

CIC2

98 Primary Events

17 Secondary Events

5 Reserved Primary Events

8 Broadcast Events from CIC0

31 Primary Events

26 Secondary Events

7 Reserved Primary Events

33 Primary Events

24 Secondary Events

7 Reserved Primary Events

Core0

EDMA3

CC1

EDMA3

CC2

45 Reserved Secondary Events

35 Events

CIC3

32 Primary Events

32 Secondary Events

8 Primary Events

8 Secondary Events

HyperLink

EDMA3

CC0

10

11

12

13

14

15

Figure 7-32

shows the mapping of system events. For more information on the Interrupt Controller, see the C66x

DSP CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

Figure 7-32 TMS320C6671 System Event Inputs — C66x CorePac Primary Interrupts (Part 1 of 4)

5

6

3

4

7

8

9

1

2

Input Event Number Interrupt Event

0 EVT0

EVT1

EVT2

EVT3

TETBHFULLINTn

(1)

TETBFULLINTn

(1)

TETBACQINTn

(1)

TETBOVFLINTn

(1)

TETBUNFLINTn

(1)

EMU_DTDMA

MSMC_mpf_errorn

(2)

EMU_RTDXRX

EMU_RTDXTX

IDMA0

IDMA1

SEMERRn

(3)

Description

Event combiner 0 output

Event combiner 1 output

Event combiner 2 output

Event combiner 3 output

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition interrupt

Underflow condition interrupt

ECM interrupt for:

1. Host scan access

2. DTDMA transfer complete

3. AET interrupt

Memory protection fault indicators for local core

RTDX receive complete

RTDX transmit complete

IDMA channel 0 interrupt

IDMA channel 1 interrupt

Semaphore error interrupt

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Figure 7-32 TMS320C6671 System Event Inputs — C66x CorePac Primary Interrupts (Part 2 of 4)

55

56

57

58

59

51

52

53

54

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

31

32

33

34

27

28

29

30

23

24

25

26

Input Event Number Interrupt Event

16 SEMINTn

(3)

17

18

PCIExpress_MSI_INTn

(4)

TSIP0_ERRINT[n]

(5)

19

20

TSIP1_ERRINT[n]

(5)

INTDST(n+16)

(6)

21

22

CIC0_OUT(32+0+11*n)

CIC0_OUT(32+1+11*n)

CIC0_OUT(32+2+11*n)

CIC0_OUT(32+3+11*n)

CIC0_OUT(32+4+11*n)

CIC0_OUT(32+5+11*n)

CIC0_OUT(32+6+11*n)

CIC0_OUT(32+7+11*n)

CIC0_OUT(32+8+11*n)

CIC0_OUT(32+9+11*n)

CIC0_OUT(32+10+11*n)

QM_INT_LOW_0

QM_INT_LOW_1

QM_INT_LOW_2

QM_INT_LOW_3

QM_INT_LOW_4

QM_INT_LOW_5

QM_INT_LOW_6

QM_INT_LOW_7

QM_INT_LOW_8

QM_INT_LOW_9

QM_INT_LOW_10

QM_INT_LOW_11

QM_INT_LOW_12

QM_INT_LOW_13

QM_INT_LOW_14

QM_INT_LOW_15

QM_INT_HIGH_n

(7)

QM_INT_HIGH_(n+8)

(7)

QM_INT_HIGH_(n+16)

(7)

QM_INT_HIGH_(n+24)

(7)

TSIP0_RFSINT[n]

(5)

TSIP0_RSFINT[n]

(5)

TSIP0_XFSINT[n]

(5)

TSIP0_XSFINT[n]

(5)

TSIP1_RFSINT[n]

(5)

TSIP1_RSFINT[n]

(5)

TSIP1_XFSINT[n]

(5)

TSIP1_XSFINT[n]

(5)

Description

Semaphore interrupt

Message signaled interrupt mode

TSIP0 receive/transmit error interrupt

TSIP1 receive/transmit error interrupt

SRIO Interrupt

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

QM Interrupt for 0~31 Queues

QM Interrupt for 32~63 Queues

QM Interrupt for 64~95 Queues

QM Interrupt for 96~127 Queues

QM Interrupt for 128~159 Queues

QM Interrupt for 160~191 Queues

QM Interrupt for 192~223 Queues

QM Interrupt for 224~255 Queues

QM Interrupt for 256~287 Queues

QM Interrupt for 288~319 Queues

QM Interrupt for 320~351 Queues

QM Interrupt for 352~383 Queues

QM Interrupt for 384~415 Queues

QM Interrupt for 416~447 Queues

QM Interrupt for 448~479 Queues

QM Interrupt for 480~511 Queues

QM Interrupt for Queue 704+n

8

QM Interrupt for Queue 712+n

8

QM Interrupt for Queue 720+n

8

QM Interrupt for Queue 728+n

8

TSIP0 receive frame sync interrupt

TSIP0 receive super frame interrupt

TSIP0 transmit frame sync interrupt

TSIP0 transmit super frame interrupt

TSIP1 receive frame sync interrupt

TSIP1 receive super frame interrupt

TSIP1 transmit frame sync interrupt

TSIP1 transmit super frame interrupt

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Figure 7-32 TMS320C6671 System Event Inputs — C66x CorePac Primary Interrupts (Part 3 of 4)

Description

98

99

100

101

102

103

94

95

96

97

90

91

92

93

86

87

88

89

82

83

84

85

78

79

80

81

74

75

76

77

70

71

72

73

66

67

68

69

62

63

64

65

Input Event Number Interrupt Event

60

61

Reserved

Reserved

CIC0_OUT(2+8*n)

CIC0_OUT(3+8*n)

TINTLn

(8)

TINTHn

(8)

TINT8L

TINT8H

TINT9L

TINT9H

TINT10L

TINT10H

TINT11L

TINT11H

TINT12L

TINT12H

TINT13L

TINT13H

TINT14L

TINT14H

TINT15L

TINT15H

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

GPINTn

(9)

IPC_LOCAL

CIC0_OUT(4+8*n)

CIC0_OUT(5+8*n)

CIC0_OUT(6+8*n)

CIC0_OUT(7+8*n)

INTERR

EMC_IDMAERR

Reserved

Reserved

EFIINTA

EFIINTB

CIC0_OUT0

CIC0_OUT1

EFI Interrupt from side A

EFI Interrupt from side B

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Local timer interrupt low

Local timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Local GPIO interrupt

Inter DSP interrupt from IPCGRn

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Dropped CPU interrupt event

Invalid IDMA parameters

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Figure 7-32 TMS320C6671 System Event Inputs — C66x CorePac Primary Interrupts (Part 4 of 4)

114

115

116

117

110

111

112

113

Input Event Number Interrupt Event

104

105

CIC0_OUT8

CIC0_OUT9

106

107

108

109

CIC0_OUT16

CIC0_OUT17

CIC0_OUT24

CIC0_OUT25

MDMAERREVT

Reserved

EDMA3CC0_EDMACC_AETEVT

PMC_ED

EDMA3CC1_EDMACC_AETEVT

EDMA3CC2_EDMACC_AETEVT

UMC_ED1

UMC_ED2

122

123

124

125

118

119

120

121

126

127

End of Table 7-37

PDC_INT

SYS_CMPA

PMC_CMPA

PMC_DMPA

DMC_CMPA

DMC_DMPA

UMC_CMPA

UMC_DMPA

EMC_CMPA

EMC_BUSERR

Description

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

VbusM error event

EDMA3CC0 AET event

Single bit error detected during DMA read

EDMA3CC1 AET Event

EDMA3CC2 AET Event

Corrected bit error detected

Uncorrected bit error detected

Power down sleep interrupt

SYS CPU memory protection fault event

PMC CPU memory protection fault event

PMC DMA memory protection fault event

DMC CPU memory protection fault event

DMC DMA memory protection fault event

UMC CPU memory protection fault event

UMC DMA memory protection fault event

EMC CPU memory protection fault event

EMC bus error interrupt

1 Core

Pac

[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn.

2 Core

Pac

[n] will receive MSMC_mpf_errorn.CIC.

3 Core

Pac

[n] will receive SEMINTn and SEMERRn.

4 Core

Pac

[n] will receive PCIEXpress_MSI_INTn.

5 Core

Pac

[n] will receive TSIPx_xxx[n].

6 Core

Pac

[n] will receive INTDST(n+16).

7 n is core number.

8 Core

Pac

[n] will receive TINTLn and TINTHn.

9 Core

Pac

[n] will receive GPINTn.

Table 7-38 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 5)

5

6

3

4

7

8

1

2

Input Event# on CIC

0

System Interrupt

EDMA3CC1 CC_ERRINT

EDMA3CC1 CC_MPINT

EDMA3CC1 TC_ERRINT0

EDMA3CC1 TC_ERRINT1

EDMA3CC1 TC_ERRINT2

EDMA3CC1 TC_ERRINT3

EDMA3CC1 CC_GINT

Reserved

EDMA3CC1 CCINT0

Description

EDMA3CC1 error interrupt

EDMA3CC1 memory protection interrupt

EDMA3CC1 TC0 error interrupt

EDMA3CC1 TC1 error interrupt

EDMA3CC1 TC2 error interrupt

EDMA3CC1 TC3 error interrupt

EDMA3CC1 GINT

EDMA3CC1 individual completion interrupt

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Table 7-38 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 5)

46

47

48

43

44

45

49

50

51

35

36

37

38

31

32

33

34

39

40

41

42

27

28

29

30

23

24

25

26

19

20

21

22

15

16

17

18

11

12

13

14

Input Event# on CIC

9

10

System Interrupt

EDMA3CC1 CCINT1

EDMA3CC1 CCINT2

EDMA3CC1 CCINT3

EDMA3CC1 CCINT4

EDMA3CC1 CCINT5

EDMA3CC1 CCINT6

EDMA3CC1 CCINT7

EDMA3CC2 CC_ERRINT

EDMA3CC2 CC_MPINT

EDMA3CC2 TC_ERRINT0

EDMA3CC2 TC_ERRINT1

EDMA3CC2 TC_ERRINT2

EDMA3CC2 TC_ERRINT3

EDMA3CC2 CC_GINT

Reserved

EDMA3CC2 CCINT0

EDMA3CC2 CCINT1

EDMA3CC2 CCINT2

EDMA3CC2 CCINT3

EDMA3CC2 CCINT4

EDMA3CC2 CCINT5

EDMA3CC2 CCINT6

EDMA3CC2 CCINT7

EDMA3CC0 CC_ERRINT

EDMA3CC0 CC_MPINT

EDMA3CC0 TC_ERRINT0

EDMA3CC0 TC_ERRINT1

EDMA3CC0 CC_GINT

Reserved

EDMA3CC0 CCINT0

EDMA3CC0 CCINT1

EDMA3CC0 CCINT2

EDMA3CC0 CCINT3

EDMA3CC0 CCINT4

EDMA3CC0 CCINT5

EDMA3CC0 CCINT6

EDMA3CC0 CCINT7

Reserved

QM_INT_PASS_TXQ_PEND_12

PCIEXpress_ERR_INT

PCIEXpress_PM_INT

PCIEXpress_Legacy_INTA

PCIEXpress_Legacy_INTB

Description

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC1 individual completion interrupt

EDMA3CC2 error interrupt

EDMA3CC2 memory protection interrupt

EDMA3CC2 TC0 error interrupt

EDMA3CC2 TC1 error interrupt

EDMA3CC2 TC2 error interrupt

EDMA3CC2 TC3 error interrupt

EDMA3CC2 GINT

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC2 individual completion interrupt

EDMA3CC0 error interrupt

EDMA3CC0 memory protection interrupt

EDMA3CC0 TC0 error interrupt

EDMA3CC0 TC1 error interrupt

EDMA3CC0 GINT

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

EDMA3CC0 individual completion interrupt

Queue manager pend event

Protocol error interrupt

Power management interrupt

Legacy interrupt mode

Legacy interrupt mode

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Table 7-38

91

92

93

CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 5)

86

87

88

89

90

78

79

80

81

74

75

76

77

81

82

84

85

70

71

72

73

66

67

68

69

62

63

64

65

58

59

60

61

54

55

56

57

Input Event# on CIC

52

53

System Interrupt

PCIEXpress_Legacy_INTC

PCIEXpress_Legacy_INTD

SPIINT0

SPIINT1

SPIXEVT

SPIREVT

I2CINT

I2CREVT

I2CXEVT

Reserved

Reserved

TETBHFULLINT

TETBFULLINT

TETBACQINT

TETBOVFLINT

TETBUNFLINT

MDIO_LINK_INTR0

MDIO_LINK_INTR1

MDIO_USER_INTR0

MDIO_USER_INTR1

MISC_INTR

TRACER_CORE_0_INTD

Reserved

Reserved

Reserved

TRACER_DDR_INTD

TRACER_MSMC_0_INTD

TRACER_MSMC_1_INTD

TRACER_MSMC_2_INTD

TRACER_MSMC_3_INTD

TRACER_CFG_INTD

TRACER_QM_CFG_INTD

TRACER_QM_DMA_INTD

TRACER_SM_INTD

Description

Legacy interrupt mode

Legacy interrupt mode

SPI interrupt0

SPI interrupt1

Transmit event

Receive event

I

2

C interrupt

I

2

C receive event

I

2

C transmit event

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition occur

Underflow condition occur

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MISC interrupt

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for DDR3 EMIF1

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave

Tracer sliding time window interrupt for semaphore

PSC_ALLINT Power/sleep controller interrupt

MSMC_SCRUB_CERROR Correctable (1-bit) soft error detected during scrub cycle

BOOTCFG_INTD Chip-level MMR error register

Reserved

MPU0_INTD (MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

QM_INT_PASS_TXQ_PEND_13

MPU0 addressing violation interrupt and protection violation interrupt.

Queue manager pend event

MPU1 addressing violation interrupt and protection violation interrupt.

MPU1_INTD (MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

QM_INT_PASS_TXQ_PEND_14 Queue manager pend event

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128

129

130

131

132

133

134

135

121

122

123

124

125

126

127

117

118

119

120

113

114

115

116

109

110

111

112

105

105

107

108

101

102

103

104

97

98

99

100

Table 7-38

95

96

CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 5)

Input Event# on CIC

94

System Interrupt

MPU2_INTD (MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

Description

MPU2 addressing violation interrupt and protection violation interrupt.

INTDST1

INTDST2

INTDST3

INTDST4

INTDST5

INTDST6

INTDST7

INTDST8

QM_INT_PASS_TXQ_PEND_15

MPU3_INTD (MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

Queue manager pend event

MPU3 addressing violation interrupt and protection violation interrupt.

QM_INT_PASS_TXQ_PEND_16

MSMC_dedc_cerror

MSMC_dedc_nc_error

MSMC_scrub_nc_error

Reserved

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

MSMC_mpf_error14

MSMC_mpf_error15

DDR3_ERR

VUSR_INT_O

INTDST0

Queue manager pend event

Correctable (1-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected during scrub cycle

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

DDR3 EMIF error interrupt

HyperLink interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

INTDST9

INTDST10

INTDST11

INTDST12

INTDST13

INTDST14

INTDST15

EASYNCERR

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

EMIF16 error interrupt

Reserved

Reserved

Reserved

Reserved

QM_INT_PKTDMA_0

QM_INT_PKTDMA_1

RapidIO_INT_PKTDMA_0

Queue manager Interrupt for packet DMA starvation

Queue manager Interrupt for packet DMA starvation

RapidIO Interrupt for packet DMA starvation

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Table 7-38

Input Event# on CIC

136

137

138

139

140

141

142

CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 5 of 5)

System Interrupt

PASS_INT_PKTDMA_0

SmartReflex_intrreq0

SmartReflex_intrreq1

SmartReflex_intrreq2

SmartReflex_intrreq3

VPNoSMPSAck

VPEqValue

Description

Network coprocessor Interrupt for packet DMA starvation

SmartReflex sensor interrupt

SmartReflex sensor interrupt

SmartReflex sensor interrupt

SmartReflex sensor interrupt

VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval

SRSINTERUPTZ is asserted, but the new voltage is not different from the current SMPS voltage

The new voltage required is equal to or greater than MaxVdd.

The new voltage required is equal to or less than MinVdd.

The FSM of Voltage processor is in idle.

The average frequency error is within the desired limit.

147

148

149

150

143

144

145

146

151

152

153

154

155

156

157

158

159

End of Table 7-38

VPMaxVdd

VPMinVdd

VPINIDLE

VPOPPChangeDone

Reserved

UARTINT

URXEVT

UTXEVT

QM_INT_PASS_TXQ_PEND_17

QM_INT_PASS_TXQ_PEND_18

QM_INT_PASS_TXQ_PEND_19

QM_INT_PASS_TXQ_PEND_20

QM_INT_PASS_TXQ_PEND_21

QM_INT_PASS_TXQ_PEND_22

QM_INT_PASS_TXQ_PEND_23

QM_INT_PASS_TXQ_PEND_24

QM_INT_PASS_TXQ_PEND_25

UART interrupt

UART receive event

UART transmit event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Table 7-39 CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 1 of 5)

8

9

10

5

6

7

11

12

13

3

4

1

2

Input Event # on CIC System Interrupt

0 GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

TETBHFULLINT

TETBFULLINT

TETBACQINT

TETBHFULLINT0

TETBFULLINT0

TETBACQINT0

Description

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

System TETB is half full

System TETB is full

System TETB acquisition has been completed

TETB0 is half full

TETB0 is full

TETB0 acquisition has been completed

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Table 7-39 CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 2 of 5)

52

53

54

55

56

57

48

49

50

51

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

Input Event # on CIC System Interrupt

14

15

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

QM_INT_HIGH_16

QM_INT_HIGH_17

QM_INT_HIGH_18

QM_INT_HIGH_19

QM_INT_HIGH_20

QM_INT_HIGH_21

QM_INT_HIGH_22

QM_INT_HIGH_23

QM_INT_HIGH_24

QM_INT_HIGH_25

QM_INT_HIGH_26

QM_INT_HIGH_27

QM_INT_HIGH_28

QM_INT_HIGH_29

QM_INT_HIGH_30

QM_INT_HIGH_31

MDIO_LINK_INTR0

MDIO_LINK_INTR1

MDIO_USER_INTR0

MDIO_USER_INTR0

MISC_INTR

TRACER_CORE_0_INTD

Reserved

Reserved

Reserved

TRACER_DDR_INTD

TRACER_MSMC_0_INTD

TRACER_MSMC_1_INTD

TRACER_MSMC_2_INTD

TRACER_MSMC_3_INTD

TRACER_CFG_INTD

TRACER_QM_CFG_INTD

TRACER_QM_DMA_INTD

TRACER_SM_INTD

Description

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MDIO interrupt

Network coprocessor MISC interrupt

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for DDR3 EMIF

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave port

Tracer sliding time window interrupt for semaphore

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Table 7-39 CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 3 of 5)

95

96

97

98

91

92

93

94

87

88

89

90

83

84

85

86

79

80

81

82

75

76

77

78

71

72

73

74

60

61

62

63

64

Input Event # on CIC System Interrupt

58

59

SEMERR0

Reserved

Reserved

Reserved

BOOTCFG_INTD

PASS_INT_PKTDMA_0

65

66

MPU0_INTD (MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

MSMC_scrub_cerror

MPU1_INTD (MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

67

68

69

70

RapidIO_INT_PKTDMA_0

MPU2_INTD (MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

QM_INT_PKTDMA_0

MPU3_INTD (MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

QM_INT_PKTDMA_1

MSMC_dedc_cerror

MSMC_dedc_nc_error

MSMC_scrub_nc_error

Reserved

MSMC_mpf_error0

MSMC_mpf_error1

MSMC_mpf_error2

MSMC_mpf_error3

MSMC_mpf_error4

MSMC_mpf_error5

MSMC_mpf_error6

MSMC_mpf_error7

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

MSMC_mpf_error14

MSMC_mpf_error15

Reserved

INTDST0

INTDST1

INTDST2

INTDST3

INTDST4

INTDST5

Description

Semaphore interrupt

BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT

Network coprocessor interrupt for packet DMA starvation

MPU0 addressing violation interrupt and protection violation interrupt.

Correctable (1-bit) soft error detected during scrub cycle

MPU1 addressing violation interrupt and protection violation interrupt.

RapidIO interrupt for packet DMA starvation

MPU2 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

MPU3 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

Correctable (1-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected on SRAM read

Non-correctable (2-bit) soft error detected during scrub cycle

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

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Table 7-39

137

138

139

140

141

142

133

134

135

136

129

130

131

132

125

126

127

128

121

122

123

124

117

118

119

120

113

114

115

116

109

110

111

112

105

106

107

108

Input Event # on CIC System Interrupt

99

100

INTDST6

INTDST7

101

102

103

104

INTDST8

INTDST9

INTDST10

INTDST11

INTDST12

INTDST13

INTDST14

INTDST15

INTDST16

INTDST17

INTDST18

INTDST19

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

INTDST20

INTDST21

INTDST22

INTDST23

EASYNCERR

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

QM_INT_HIGH_0

QM_INT_HIGH_1

QM_INT_HIGH_2

QM_INT_HIGH_3

QM_INT_HIGH_4

CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 4 of 5)

Description

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

RapidIO interrupt

EMIF16 error interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

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Table 7-39 CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 5 of 5)

Input Event # on CIC System Interrupt

143

144

QM_INT_HIGH_5

QM_INT_HIGH_6

145

146

147

148

QM_INT_HIGH_7

QM_INT_HIGH_8

QM_INT_HIGH_9

QM_INT_HIGH_10

149

150

151

152

153

154-159

End of Table 7-39

QM_INT_HIGH_11

QM_INT_HIGH_12

QM_INT_HIGH_13

QM_INT_HIGH_14

QM_INT_HIGH_15

Reserved

Description

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

Table 7-40

21

22

23

18

19

20

24

25

26

11

12

13

14

7

8

9

10

15

16

17

5

6

3

4

1

2

Input Event # on CIC

0

GPINT7

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

System Interrupt

GPINT0

GPINT1

GPINT2

GPINT3

GPINT4

GPINT5

GPINT6

GPINT15

TETBHFULLINT

TETBFULLINT

TETBACQINT

TETBHFULLINT0

TETBFULLINT0

TETBACQINT0

Reserved

Reserved

Reserved

Reserved

Reserved

CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 1 of 2)

Description

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

System TETB is half full

System TETB is full

System TETB acquisition has been completed

TETB0 is half full

TETB0 is full

TETB0 acquisition has been completed

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Table 7-40 CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 2 of 2)

53

54

55

56

49

50

51

52

45

46

47

48

41

42

43

44

37

38

39

40

33

34

35

36

29

30

31

32

Input Event # on CIC

27

28

57

58

59

60

61

62-79

End of Table 7-40

System Interrupt

Reserved

Reserved

Reserved

Reserved

TRACER_CORE_0_INTD

Reserved

Reserved

Reserved

TRACER_DDR_INTD

TRACER_MSMC_0_INTD

TRACER_MSMC_1_INTD

TRACER_MSMC_2_INTD

TRACER_MSMC_3_INTD

TRACER_CFG_INTD

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TRACER_QM_CFG_INTD

TRACER_QM_DMA_INTD

TRACER_SM_INTD

VUSR_INT_O

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

DDR3_ERR

Reserved

Description

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for DDR3 EMIF1

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave port

Tracer sliding time window interrupt for semaphore

HyperLink interrupt

DDR3 EMIF Error interrupt

7.10.2 CIC Registers

This section includes the offsets for CIC registers. The base addresses for interrupt control registers are CIC0 -

0x0260 0000, CIC2 - 0x0260 8000, and CIC3 - 0x0260 C000.

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7.10.2.1 CIC0 Register Map

Table 7-41

0x410

0x414

0x418

0x41c

0x420

0x424

0x380

0x384

0x388

0x38c

0x390

0x400

0x404

0x408

0x40c

0x288

0x28c

0x290

0x300

0x304

0x308

0x30c

0x310

0x38

0x200

0x204

0x208

0x20C

0x210

0x280

0x284

Address Offset

0x0

0x10

0x20

0x24

0x28

0x2C

0x34

0x428

0x42c

0x430

0x434

CIC0 Register

Register Mnemonic

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

Register Name

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

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Table 7-41

0x820

0x824

0x828

0x82c

0x830

0x834

0x490

0x494

0x498

0x49c

0x800

0x804

0x808

0x80c

0x470

0x474

0x478

0x47c

0x480

0x484

0x488

0x48c

0x810

0x814

0x818

0x81c

0x450

0x454

0x458

0x45c

0x460

0x464

0x468

0x46c

Address Offset

0x438

0x43c

0x440

0x444

0x448

0x44c

0x838

0x83c

0x840

CIC0 Register

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

CH_MAP_REG39

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

Register Mnemonic

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

HINT_MAP_REG8

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

HINT_MAP_REG13

HINT_MAP_REG14

HINT_MAP_REG15

HINT_MAP_REG16

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Register Name

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Interrupt Map Register for 52 to 52+3

Host Interrupt Map Register for 56 to 56+3

Host Interrupt Map Register for 60 to 60+3

Host Interrupt Map Register for 64 to 64+3

Peripheral Information and Electrical Specifications 177

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

Table 7-41 CIC0 Register

Address Offset

0x844

0x848

0x1500

0x1504

0x1508

End of Table 7-41

Register Mnemonic

HINT_MAP_REG17

HINT_MAP_REG18

ENABLE_HINT_REG0

ENABLE_HINT_REG1

ENABLE_HINT_REG2

Register Name

Host Interrupt Map Register for 68 to 68+3

Host Interrupt Map Register for 72 to 72+3

Host Int Enable Register 0

Host Int Enable Register 1

Host Int Enable Register 2

7.10.2.2 CIC2 Register Map

Table 7-42

0x384

0x388

0x38c

0x390

0x400

0x404

0x288

0x28c

0x290

0x300

0x304

0x308

0x30c

0x310

0x380

0x38

0x200

0x204

0x208

0x20c

0x210

0x280

0x284

Address Offset

0x0

0x10

0x20

0x24

0x28

0x2c

0x34

0x408

0x40c

0x410

CIC2 Register

Register Mnemonic

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

178 Peripheral Information and Electrical Specifications

Register Name

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

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Table 7-42

0x49c

0x800

0x804

0x808

0x80c

0x810

0x46c

0x470

0x474

0x478

0x47c

0x480

0x484

0x488

0x44c

0x450

0x454

0x458

0x45c

0x460

0x464

0x468

0x48c

0x490

0x494

0x498

0x42c

0x430

0x434

0x438

0x43c

0x440

0x444

0x448

Address Offset

0x414

0x418

0x41c

0x420

0x424

0x428

0x814

0x818

0x81c

CIC2 Register

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

Register Mnemonic

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG39

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

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Register Name

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

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Table 7-42 CIC2 Register

Address Offset

0x820

0x824

0x828

0x82c

0x830

0x1500

0x1504

End of Table 7-42

Register Mnemonic

HINT_MAP_REG8

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

ENABLE_HINT_REG0

ENABLE_HINT_REG1

Register Name

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Int Enable Register 0

Host Int Enable Register 1

7.10.2.3 CIC3 Register Map

Table 7-43

0x418

0x41c

0x420

0x424

0x428

0x42c

0x384

0x400

0x404

0x408

0x40c

0x410

0x414

0x38

0x200

0x204

0x280

0x284

0x300

0x304

0x380

Address Offset

0x0

0x10

0x20

0x24

0x28

0x2c

0x34

0x430

0x434

0x438

CIC3 Register

Register Mnemonic

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

ENA_STATUS_REG0

ENA_STATUS_REG1

ENABLE_REG0

ENABLE_REG1

ENABLE_CLR_REG0

ENABLE_CLR_REG1

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

180 Peripheral Information and Electrical Specifications

Register Name

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Enabled Status Register 0

Enabled Status Register 1

Enable Register 0

Enable Register 1

Enable Clear Register 0

Enable Clear Register 1

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

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Table 7-43 CIC3 Register

Address Offset

0x43c

0x800

0x804

0x808

0x80c

0x810

0x814

0x818

0x81c

0x820

0x824

0x1500

0x1504

End of Table 7-43

Register Mnemonic

CH_MAP_REG15

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

HINT_MAP_REG8

HINT_MAP_REG9

ENABLE_HINT_REG0

ENABLE_HINT_REG1

7.10.3 Inter-Processor Register Map

Table 7-44

Address Start

0x02620200

0x02620204

0x02620208

0x0262020C

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620240

0x02620244

0x02620248

0x0262024C

0x02620250

0x02620254

0x02620258

0x0262025C

0x02620260

0x0262027C

0x02620280

0x02620284

0x02620288

0x0262028C

0x02620290

0x02620294

IPC Generation Registers (IPCGRx) (Part 1 of 2)

Address End

0x02620203

0x02620207

0x0262020B

0x0262020F

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620243

0x02620247

0x0262024B

0x0262024F

0x02620253

0x02620257

0x0262025B

0x0262025F

0x0262027B

0x0262027F

0x02620283

0x02620287

0x0262028B

0x0262028F

0x02620293

0x02620297

4B

4B

4B

4B

4B

32B

4B

4B

4B

4B

4B

4B

Size

4B

4B

4B

4B

4B

4B

4B

4B

4B

28B

4B

4B

4B

Reserved

Reserved

Reserved

IPCGRH

IPCAR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Register Name

NMIGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

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Register Name

Interrupt Channel Map Register for 60 to 60+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Int Enable Register 0

Host Int Enable Register 1

Description

NMI Event Generation Register for CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPC Generation Register for CorePac 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPC Generation Register for Host

IPC Acknowledgement Register for CorePac 0

Reserved

Reserved

Reserved

Reserved

Reserved

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Table 7-44 IPC Generation Registers (IPCGRx) (Part 2 of 2)

Address Start

0x02620298

0x0262029C

0x026202A0

0x026202BC

End of Table 7-44

Address End

0x0262029B

0x0262029F

0x026202BB

0x026202BF

Size

4B

4B

28B

4B

Register Name

Reserved

Reserved

Reserved

IPCARH

Description

Reserved

Reserved

Reserved

IPC Acknowledgement Register for Host

7.10.4 NMI and LRESET

Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One

NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured to select between the CorePacs available as shown in

Table 7-45 .

Table 7-45 LRESET and NMI Decoding

0110

0111

1xxx

0000

0001

0010

0011

0100

CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output

XXXX X X 1 No local reset or NMI assertion.

0000

0001

0

0

X

X

0

0

Assert local reset to CorePac 0

0010

0011

0100

0101

0

0

0

0

X

X

X

X

0

0

0

0

Reserved

0

0

0

1

1

1

1

1

X

X

X

1

1

1

1

1

0

0

0

0

0

0

0

0

Assert local reset to all CorePacs

De-assert local reset & NMI to CorePac 0

Reserved

0101

0110

0111

1xxx

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

End of Table 7-45

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

De-assert local reset & NMI to all CorePacs

Assert NMI to CorePac 0

Reserved

Assert NMI to all CorePacs

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7.10.5 External Interrupts Electrical Data/Timing

Table 7-46

(see Figure 7-33 )

NMI and Local Reset Timing Requirements

(1)

No.

1 tsu(LRESET-LRESETNMIENL)

1 tsu(NMI-LRESETNMIENL)

1 tsu(CORESELn-LRESETNMIENL)

2

2 th(LRESETNMIENL-LRESET) th(LRESETNMIENL-NMI)

2 th(LRESETNMIENL-CORESELn)

3 tw(LRESETNMIEN)

End of Table 7-46

1 P = 1/SYSCLK1 frequency in ns.

Setup Time - LRESET valid before LRESETNMIEN low

Setup Time - NMI valid before LRESETNMIEN low

Setup Time - CORESEL[2:0] valid before LRESETNMIEN low

Hold Time - LRESET valid after LRESETNMIEN high

Hold Time - NMI valid after LRESETNMIEN high

Hold Time - CORESEL[2:0] valid after LRESETNMIEN high

Pulse Width - LRESETNMIEN low width

Min

12*P

12*P

12*P

12*P

12*P

12*P

12*P

Max Unit

ns ns ns ns ns ns ns

Figure 7-33 NMI and Local Reset Timing

1 2

CORESEL[3:0]/

LRESET /

NMI

3

LRESETNMIEN

7.10.6 Host Interrupt Output

The C66x CorePac can assert an event to the external host processor using HOUT.

Table 7-47 shows the timing for

the HOUT pulse. For more details, see section

3.3.15

.

Table 7-47

(see Figure 7-34 )

HOUT Switching Characteristics

No.

1 t w(HOUTH)

2 t w(HOUTL)

End of Table 7-47

1 P = 1/SYSCLK1 frequency in ns.

HOUT pulse duration high

HOUT pulse duration low

Figure 7-34 HOUT Timing

1

HOUT

2

Min

24*P

(1)

24*P

Max Unit

ns ns

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7.11 Memory Protection Unit (MPU)

The C6671 supports four MPUs:

• One MPU is used to protect the main CORE/3 CFG TeraNet (the CFG space of all slave devices on the TeraNet is protected by the MPU).

• Two MPUs are used for QM_SS (one for the DATA PORT port and one for the CFG PORT port).

• One MPU is used for Semaphore.

This section contains MPU register map and details of device-specific MPU registers only. For MPU features and

details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 72.

The following tables show the configuration of each MPU and the memory regions protected by each MPU.

Table 7-48 MPU Default Configuration

Setting

Default permission

Number of allowed IDs supported

Number of programmable ranges supported

Compare width

End of Table 7-48

MPU0

(Main CFG TeraNet)

Assume allowed

16

16

1KB granularity

MPU1

(QM_SS DATA PORT)

Assume allowed

16

5

1KB granularity

MPU2

(QM_SS CFG PORT)

Assume allowed

16

16

1KB granularity

MPU3

(Semaphore)

Assume allowed

16

1

1KB granularity

Table 7-49

MPU0

MPU1

MPU2

MPU3

MPU Memory Regions

Memory Protection

Main CFG TeraNet

QM_SS DATA PORT

QM_SS CFG PORT

Semaphore

Start Address

0x01D00000

0x34000000

0x02A00000

0x02640000

End Address

0x026207FF

0x340BFFFF

0x02ABFFFF

0x026407FF

Table 7-50

shows the privilege ID of each CORE and every mastering peripheral.

Table 7-50 also shows the privilege

level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.

Table 7-50 Privilege ID Settings (Part 1 of 2)

5

6

3

4

7

8

1

2

Privilege ID Master

0 CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Network Coprocessor

Packet DMA

Privilege Level

SW dependant, driven by MSMC

User

Security Level

SW dependant

Non-secure

Access Type

DMA

DMA

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Table 7-50 Privilege ID Settings (Part 2 of 2)

Privilege ID Master

9 SRIO Packet DMA/SRIO_M

Privilege Level

User/Driven by SRIO block, User mode and supervisor mode is determined on a per-transaction basis. Only the transaction with source ID matching the value in the SupervisorID register is granted supervisor mode.

Security Level

Non-secure

User Non-secure 10

11

12

13

14

QM_SS Packet

DMA/QM_SS Second

PCIe

Debug_SS

HyperLink

HyperLink

15 TSIP0/1

End of Table 7-50

Driven by PCIe module

Driven by Debug_SS

Driven by HyperLink

Supervisor

User

Non-secure

Driven by Debug_SS

Non-secure

Non-secure

Non-secure

Access Type

DMA

DMA

DMA

DMA

DMA

DMA

DMA

Table 7-51

shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters, master IDs are unique to each master.

Table 7-51 Master ID Settings (Part 1 of 3)

(1)

19

20

21

22

15

16

17

18

23

24

25

11

12

13

14

7

8

9

10

5

6

3

4

1

2

Master ID

0

Master

CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

CorePac0_CFG

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

EDMA0_TC0 read

EDMA0_TC0 write

EDMA0_TC1 read

EDMA0_TC1 write

EDMA1_TC0 read

EDMA1_TC0 write

EDMA1_TC1 read

EDMA1_TC1 write

EDMA1_TC2 read

EDMA1_TC2 write

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Peripheral Information and Electrical Specifications 185

Table 7-51

134

135

136

137

138

139

130

131

132

133

60 - 85

86

87

88 - 91

92 - 93

94 - 127

128

129

49

50

51

52

53

54

55

56 - 59

32

33

34

35

36 - 37

38 - 39

40 - 47

48

28

29

30

31

Master ID

26

27

140

141

142

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Master ID Settings (Part 2 of 3)

(1)

Master

EDMA1_TC3 read

EDMA1_TC3 write

EDMA2_TC0 read

EDMA2_TC0 write

EDMA2_TC1 read

EDMA2_TC1 write

EDMA2_TC2 read

EDMA2_TC2 write

EDMA2_TC3 read

EDMA2_TC3 write

Reserved

SRIO Packet DMA

Reserved

Debug SS

EDMA3CC0

EDMA3CC1

EDMA3CC2

MSMC

(2)

PCIe

SRIO_Master

HyperLink

Network Coprocessor Packet DMA

Reserved

TSIP0

TSIP1

Queue Manager Packet DMA

Queue Manager Second

Reserved

Tracer_core_0

(3)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

Tracer_DDR

Tracer_SM

Tracer_QM_CFG

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Table 7-51 Master ID Settings (Part 3 of 3)

(1)

Master ID

143

144

End of Table 7-51

Master

Tracer_QM_DMA

Tracer_CFG

1 Some of the Packet DMA-based peripherals require multiple master IDs. Queue Manager Packet DMA is assigned with 88, 89, 90, 91, but only 88 - 89 are actually used. For the network coprocessor packet DMA port, 56, 57, 58, and 59 are assigned, while only one (56) is actually used. There are two master ID values assigned for the queue manager second master port: one master ID for external linking RAM and the other master ID for PDSP/MCDM accesses.

2 The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.

3 All traces are set to the same master ID and bit 7 of the master ID must be 1.

7.11.1 MPU Registers

This section includes the offsets for MPU registers and definitions for device-specific MPU registers.

7.11.1.1 MPU Register Map

Table 7-52

254h

258h

260h

264h

268h

270h

228h

230h

234h

238h

240h

244h

248h

250h

200h

204h

208h

210h

214h

218h

220h

224h

14h

18h

1Ch

20h

Offset

0h

4h

10h

MPU0 Registers (Part 1 of 2)

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

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Table 7-52 MPU0 Registers (Part 2 of 2)

294h

298h

2A0h

2A4h

2A8h

2B0h

2B4h

2B8h

Offset

274h

278h

280h

284h

288h

290h

2C0h

2C4h

2C8h

2D0h

2D4h

2Dh

2E0h

2E4h

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

2E8h

2F0h

2F4h

2F8h

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

PROG15_MPPA

300h

304h

FLTADDRR

FLTSTAT

308h FLTCLR

End of Table 7-52

Name

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

Description

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 7-53

14h

18h

1Ch

20h

Offset

0h

4h

10h

200h

204h

208h

MPU1 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

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Table 7-53 MPU1 Registers (Part 2 of 2)

Offset

210h

214h

218h

220h

224h

228h

Name

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

230h

234h

238h

240h

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

244h

248h

300h

304h

PROG4_MPEAR

PROG4_MPPA

FLTADDRR

FLTSTAT

308h FLTCLR

End of Table 7-53

Description

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Fault address

Fault status

Fault clear

Table 7-54

200h

204h

208h

210h

214h

218h

220h

224h

14h

18h

1Ch

20h

Offset

0h

4h

10h

228h

230h

234h

238h

240h

244h

248h

250h

254h

MPU2 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

PROG5_MPEAR

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

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Table 7-54 MPU2 Registers (Part 2 of 2)

278h

280h

284h

288h

290h

294h

298h

2A0h

Offset

258h

260h

264h

268h

270h

274h

2D0h

2D4h

2Dh

2E0h

2E4h

2E8h

2F0h

2F4h

2A4h

2A8h

2B0h

2B4h

2B8h

2C0h

2C4h

2C8h

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

2F8h

300h

PROG15_MPPA

FLTADDRR

304h FLTSTAT

308h FLTCLR

End of Table 7-54

Name

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

Description

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 7-55

Offset

0h

4h

10h

14h

18h

MPU3 Registers (Part 1 of 2)

Name

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

Description

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

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Table 7-55 MPU3 Registers (Part 2 of 2)

Offset

1Ch

20h

200h

204h

208h

300h

Name

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

FLTADDRR

304h FLTSTAT

308h FLTCLR

End of Table 7-55

Description

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Fault address

Fault status

Fault clear

7.11.1.2 Device-Specific MPU Registers

7.11.1.2.1 Configuration Register (CONFIG)

The configuration register (CONFIG) contains the configuration value of the MPU.

Figure 7-35 Configuration Register (CONFIG)

31

Reset Values

MPU0

MPU1

MPU2

MPU3

ADDR_WIDTH

R-0

R-0

R-0

R-0

Legend: R = Read only; -n = value after reset

24 23 20

NUM_FIXED

R-0

R-0

R-0

R-0

19 16

NUM_PROG

R-16

R-5

R-16

R-1

15 12

NUM_AIDS

R-16

R-16

R-16

R-16

11

Reserved

1

R-0

R-0

R-0

R-0

0

ASSUME_ALLOWED

R-1

R-1

R-1

R-1

Table 7-56 Configuration Register (CONFIG) Field Descriptions

Bit Field

31 – 24 ADDR_WIDTH

23 – 20 NUM_FIXED

19 – 16 NUM_PROG

15 – 12 NUM_AIDS

11 – 1 Reserved

0 ASSUME_ALLOWED

Description

Address alignment for range checking

0 = 1KB alignment

6 = 64KB alignment

Number of fixed address ranges

Number of programmable address ranges

Number of supported AIDs

Reserved. These bits will always reads as 0.

Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not.

0 = Assume disallowed

1 = Assume allowed

End of Table 7-56

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7.11.2 MPU Programmable Range Registers

7.11.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)

The programmable address start register holds the start address for the range. This register is writeable only by a supervisor entity. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also writeable only by a secure entity.

The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines the width of the address field in MPSAR and MPEAR.

Figure 7-36 Programmable Range n Start Address Register (PROGn_MPSAR)

31

START_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

10 9

Reserved

R

0

Table 7-57 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions

Bit

31 – 10

Field

START_ADDR

9 – 0 Reserved

End of Table 7-57

Description

Start address for range n.

Reserved and these bits always read as 0.

7.11.2.2 Programmable Range n End Address Register (PROGn_MPEAR)

The programmable address end register holds the end address for the range. This register is writeable only by a supervisor entity. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also writeable only by a secure entity.

The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field in MPSAR and MPEAR

Figure 7-37 Programmable Range n End Address Register (PROGn_MPEAR)

31

END_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

10 9

Reserved

R

0

Table 7-58 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions

Bit

31 – 10

Field

END_ADDR

9 – 0 Reserved

End of Table 7-58

Description

End address for range n.

Reserved and these bits always read as 3FFh.

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7.11.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

The programmable address memory protection page attribute register holds the permissions for the region. This register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode), then the register is also writeable only by a non-debug secure entity. The NS bit is writeable only by a non-debug secure entity. For debug accesses, the register is writeable only when NS = 1 or EMU = 1.

Figure 7-38 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

31

Reserved

R

26 25 24 23 22 21 20 19

AID15 AID14 AID13 AID12 AID11 AID10 AID9

R/W R/W R/W R/W R/W R/W R/W

18

AID8

R/W

17

AID7

R/W

16

AID6

R/W

15

AID5

R/W

14

AID4

13

AID3

12

AID2

11

AID1

10

AID0

R/W R/W R/W R/W R/W

Legend: R = Read only; R/W = Read/Write

9

AIDX

R/W

8

Reserved

R

7

NS

R/W

6

EMU

R/W

5

SR

R/W

4

SW

R/W

3

SX

R/W

2

UR

R/W

1

UW

R/W

0

UX

R/W

Table 7-59

Bit

31 – 26

25

24

23

22

21

20

19

18

17

16

AID9

AID8

AID7

AID6

Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions

(Part 1 of 2)

Field

Reserved

AID15

AID14

AID13

AID12

AID11

AID10

Description

Reserved. These bits will always reads as 0.

Controls permission check of ID = 15

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 14

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 13

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 12

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 11

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 10

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 9

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 8

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 7

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 6

0 = AID is not checked for permissions

1 = AID is checked for permissions

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Table 7-59

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

AID5

AID4

AID3

AID2

AID1

AID0

AIDX

Reserved

NS

EMU

SR

SW

SX

UR

UW

UX

Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions

(Part 2 of 2)

Description

Controls permission check of ID = 5

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 4

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 3

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 2

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 1

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID = 0

0 = AID is not checked for permissions

1 = AID is checked for permissions

Controls permission check of ID > 15

0 = AID is not checked for permissions

1 = AID is checked for permissions

Always reads as 0.

Non-secure access permission

0 = Only secure access allowed.

1 = Non-secure access allowed.

Emulation (debug) access permission. This bit is ignored if NS = 1

0 = Debug access not allowed.

1 = Debug access allowed.

Supervisor Read permission

0 = Access not allowed.

1 = Access allowed.

Supervisor Write permission

0 = Access not allowed.

1 = Access allowed.

Supervisor Execute permission

0 = Access not allowed.

1 = Access allowed.

User Read permission

0 = Access not allowed.

1 = Access allowed

User Write permission

0 = Access not allowed.

1 = Access allowed.

User Execute permission

0 = Access not allowed.

1 = Access allowed.

End of Table 7-591

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7.11.2.4 MPU Registers Reset Values

Table 7-60 Programmable Range n Registers Reset Values for MPU0

Programmable

Range

Start Address

(PROGn_MPSAR)

PROG0

PROG1

PROG2

PROG3

0x01D0_0000

0x01F0_0000

End Address

(PROGn_MPEAR)

0x01D8_03FF

0x01F7_FFFF

0x0200_0000 0x0209_FFFF

0x01E0_0000 0x01EB_FFFF

MPU0 (Main CFG TeraNet)

Memory Page Protection

Attribute (PROGn_MPPA)

0x03FF_FCB6

0x03FF_FC80

0x03FF_FCB6

0x03FF_FCB6

PROG4

PROG5

PROG6

PROG7

0x021C_0000

0x0231_0000

0x021E_0FFF

0x021F_0000 0x021F_7FFF

0x0220_0000 0x022F_03FF

0x03FF_FC80

0x03FF_FC80

0x03FF_FCB6

0x0231_03FF 0x03FF_FCB4

PROG8

PROG9

PROG10

PROG11

0x0232_0000

0x0233_0000

0x0235_0000

0x0240_0000

0x0232_03FF

0x0233_03FF

0x03FF_FCB4

0x03FF_FCB4

0x0235_0FFF 0x03FF_FCB4

0x024B_3FFF 0x03FF_FCB6

PROG12

PROG13

PROG14

PROG15

End of Table 7-60

0x0250_0000 0x0252_03FF

0x0253_0000 0x0254_03FF

0x0260_0000

0x0262_0000

0x03FF_FCB4

0x03FF_FCB6

0x0260_FFFF 0x03FF_FCB4

0x0262_07FF 0x03FF_FCB4

Memory Protection

Tracers

Reserved

NETCP

TSIP

Reserved

Reserved

Timers

PLL

GPIO

SmartReflex

PSC

DEBUG_SS, Tracer Formatters

Reserved

I

2

C, UART

CICs

Chip-level Registers

Table 7-61 Programmable Range n Registers Reset Values for MPU1

Programmable

Range

Start Address

(PROGn_MPSAR)

PROG0

PROG1

0x3400_0000

0x3402_0000

PROG2

PROG3

0x3406_0000

0x3406_8000

PROG4

End of Table 7-61

0x340B_8000

End Address

(PROGn_MPEAR)

MPU1 (QM_SS DATA PORT)

Memory Page Protection

Attribute (PROGn_MPPA)

0x3401_FFFF

0x3405_FFFF

0x3406_7FFF

0x340B_7FFF

0x340B_FFFF

0x03FF_FC80

0x000F_FCB6

0x03FF_FCB4

0x03FF_FC80

0x03FF_FCB6

Memory Protection

Queue Manager subsystem data

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Table 7-62

Programmable

Range

Start Address

(PROGn_MPSAR)

PROG0

PROG1

0x02A0_0000

0x02A2_0000

PROG2

PROG3

PROG4

PROG5

0x02A4_0000

0x02A6_0000

0x02A6_8000

0x02A6_9000

PROG6

PROG7

PROG8

PROG9

PROG10

PROG11

PROG12

PROG13

0x02A6_A000

0x02A6_B000

0x02A6_C000

0x02A6_E000

0x02A8_0000

0x02A9_0000

0x02AA_0000

0x02AA_8000

PROG14 0x02AB_0000

PROG15

End of Table 7-62

0x02AB_8000

Programmable Range n Registers Reset Values for MPU2

End Address

(PROGn_MPEAR)

MPU2 (QM_SS CFG PORT)

Memory Page Protection

Attribute (PROGn_MPPA)

0x02A1_FFFF

0x02A3_FFFF

0x02A5_FFFF

0x02A6_7FFF

0x03FF_FCA4

0x000F_FCB6

0x000F_FCB6

0x03FF_FCB4

0x02A6_8FFF

0x02A6_9FFF

0x02A6_AFFF

0x02A6_BFFF

0x02A6_DFFF

0x02A6_FFFF

0x02A8_FFFF

0x02A9_FFFF

0x02AA_7FFF

0x02AA_FFFF

0x02AB_7FFF

0x02AB_FFFF

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCA4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB6

Memory Protection

Queue Manager subsystem configuration

Table 7-63 Programmable Range n Registers Reset Values for MPU3

Programmable

Range

Start Address

(PROGn_MPSAR)

PROG0

End of Table 7-63

0x0264_0000

End Address

(PROGn_MPEAR)

0x0264_07FF

MPU3 (Semaphore)

Memory Page Protection

Attributes (PROGn_MPPA)

0x0003_FCB6

Memory Protection

Semaphore

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7.12 DDR3 Memory Controller

The 64-bit DDR3 Memory Controller bus of the TMS320C6671 is used to interface to JEDEC standard-compliant

DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus with any other types of peripherals.

7.12.1 DDR3 Memory Controller Device-Specific Information

The TMS320C6671 includes one 64-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 Mega Transfers per Second (MTS), 1066 MTS, 1333 MTS, and 1600 MTS.

Due to the complicated nature of the interface, a limited number of topologies are supported to provide a 16-bit,

32-bit, or 64-bit interface.

The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3

SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the interface:

• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)

• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)

• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)

• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)

• 64-bit: Four 16-bit SDRAMs

• 64-bit: Eight 8-bit SDRAMs

• 32-bit: Two 16-bit SDRAMs

• 32-bit: Four 8-bit SDRAMs

• 16-bit: One 16-bit SDRAM

• 16-bit: Two 8-bit SDRAM

The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as

I

2

C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible

DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.

7.12.2 DDR3 Memory Controller Race Condition Consideration

A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes, before signaling to master B that the message is ready, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1.

Perform the required write to DDR3 memory space.

2.

Perform a dummy write to the DDR3 memory controller module ID and revision register.

3.

Perform a dummy read to the DDR3 memory controller module ID and revision register.

4.

Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

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7.12.3 DDR3 Memory Controller Electrical Data/Timing

The DDR3 Design Requirements for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 72 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3

electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

Note—

TI supports only designs that follow the board design guidelines outlined in the application report.

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7.13 I

2

C Peripheral

The inter-integrated circuit (I

2

C) module provides an interface between DSP and other devices compliant with

Philips Semiconductors Inter-IC bus (I

2

C bus) specification version 2.1 and connected by way of an I

2

C bus.

External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I

2

C module.

7.13.1 I

2

C Device-Specific Information

The TMS320C6671 device includes an I

2

C peripheral module.

Note—

When using the I

2

C module, ensure there are external pullup resistors on the SDA and SCL pins.

The I

2

C modules on the C6671 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface.

The I

2

C port is compatible with Philips I

2

C specification revision 2.1 (January 2000) and supports:

• Fast mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise filter to remove noise 50 ns or less

• 7-bit and 10-bit device addressing modes

• Multi-master (transmit/receive) and slave (transmit/receive) functionality

• Events: DMA, interrupt, or polling

• Slew-rate limited open-drain output buffers

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Figure 7-39

shows a block diagram of the I

2

C module.

Figure 7-39 I

2

C Module Block Diagram

Clock

Prescale

2

I CPSC

SCL

Noise

Filter

2

I C Data

SDA

Noise

Filter

Bit Clock

Generator

2

I CCLKL

Transmit

2

I CXSR

Transmit

Shift

2

I CDXR

Transmit

Buffer

Peripheral Clock

(CPU/6)

Control

2

I COAR

2

I CSAR

2

I CMDR

Own

Address

Slave

Address

Mode

Data

Count

Extended

Mode

Receive

2

I CRSR

Receive

Buffer

Receive

Shift

Interrupt/DMA

2

I CSTR

2

I CIVR

Interrupt

Mask/Status

Interrupt

Status

Interrupt

Vector

Shading denotes control/status registers.

7.13.2 I

2

C Peripheral Register Description(s)

Table 7-64 I

2

C Registers (Part 1 of 2)

Hex Address Range

0253 0000

0253 0004

0253 0008

0253 000C

0253 0010

0253 0014

0253 0018

0253 001C

0253 0020

0253 0024

0253 0028

0253 002C

Register

ICOAR

ICIMR

ICSTR

ICCLKL

ICCLKH

ICCNT

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

ICEMDR

Register Name

I

2

C Own Address Register

I

2

C Interrupt Mask/Status Register

I

2

C Interrupt Status Register

I

2

C Clock Low-Time Divider Register

I

2

C Clock High-Time Divider Register

I

2

C Data Count Register

I

2

C Data Receive Register

I

2

C Slave Address Register

I

2

C Data Transmit Register

I

2

C Mode Register

I

2

C Interrupt Vector Register

I

2

C Extended Mode Register

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Table 7-64 I

2

C Registers (Part 2 of 2)

Hex Address Range

0253 0030

0253 0034

0253 0038

0253 003C - 0253 007F

End of Table 7-64

Register

ICPSC

ICPID1

ICPID2

-

Register Name

I

2

C Prescaler Register

I

2

C Peripheral Identification Register 1 [Value: 0x0000 0105]

I

2

C Peripheral Identification Register 2 [Value: 0x0000 0005]

Reserved

7.13.3 I

2

C Electrical Data/Timing

7.13.3.1 Inter-Integrated Circuits (I

2

C) Timing

Table 7-65

(see Figure 7-40 )

I

2

C Timing Requirements

(1)

No.

1 t c(SCL)

2

3 t t su(SCLH-SDAL) h(SDAL-SCLL)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated START condition)

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

Standard Mode

Min

10

4.7

4

Max

Fast Mode

Min

2.5

0.6

0.6

Max Units

μs

μs

μs

4 t w(SCLL)

5 t w(SCLH)

Pulse duration, SCL low

Pulse duration, SCL high

6 t su(SDAV-SCLH)

Setup time, SDA valid before SCL high

7 t h(SCLL-SDAV)

Hold time, SDA valid after SCL low (For I

2

C bus devices)

8 t w(SDAH)

9 t r(SDA)

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

10 t r(SCL)

11 t f(SDA)

Rise time, SCL

Fall time, SDA

12 t f(SCL)

Fall time, SCL

13 t su(SCLH-SDAH)

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed) 14 t w(SP)

15 C

b

(5)

End of Table 7-65

Capacitive load for each bus line

250

0

4.7

4

(3)

4.7

4

3.45

400

100

0

1.3

0.6

(2)

(3)

1.3

1000 20 + 0.1C

b

(5)

1000 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

0.6

0

0.9

(4)

300

300

300

300

50

400

μs

μs ns

μs

μs ns ns ns ns

μs ns pF

1 The I

2

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down

2 A Fast-mode I

2

C-bus™ device can be used in a Standard-mode I

2

C-bus™ system, but the requirement tsu(SDA-SCLH)

 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t r

max + t su(SDA-SCLH)

= 1000 + 250 = 1250 ns (according to the Standard-mode I

2

C-Bus Specification) before the SCL line is released.

3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

IHmin of SCL.

of the SCL signal) to bridge the undefined region of the falling edge

4 The maximum t h(SDA-SCLL)

has to be met only if the device does not stretch the low period [t w(SCLL)

] of the SCL signal.

5 C b

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

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Figure 7-40 I

2

C Receive Timings

11

SDA

8

4

10

5

SCL

1

12

7

3

6

2

3

Stop Start Repeated

Start

Table 7-66

(see Figure 7-41 )

I

2

C Switching Characteristics

(1)

No.

16 t c(SCL)

17 t su(SCLH-SDAL)

Parameter

Cycle time, SCL

Setup time, SCL high to SDA low (for a repeated START condition)

18 t h(SDAL-SCLL)

Hold time, SDA low after SCL low (for a START and a repeated

START condition)

19 t w(SCLL)

20 t w(SCLH)

21 t d(SDAV-SDLH)

22 t v(SDLL-SDAV)

23 t w(SDAH)

24 t r(SDA)

25 t r(SCL)

Pulse duration, SCL low

Pulse duration, SCL high

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low (For I

2

C bus devices)

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

Rise time, SCL

26 t f(SDA)

27 t f(SCL)

Fall time, SDA

Fall time, SCL

28 t d(SCLH-SDAH)

Delay time, SCL high to SDA high (for STOP condition)

29 C p

Capacitance for each I

2

C pin

End of Table 7-66

1 C b

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Standard Mode

Min Max

10

4.7

4

4.7

4

250

0

4.7

4

1000

1000

300

300

10

14

13

9

Stop

Fast Mode

Min

2.5

0.6

Max Unit

ms ms

0.6

1.3

0.6

100

0

1.3

20 + 0.1C

b

(1)

20 + 0.1C

b

(1)

20 + 0.1C

b

(1)

20 + 0.1C

b

(1)

0.6

ms ms ms ns

0.9

ms ms

300 ns

300 ns

300 ns

300 ns

ms

10 pF

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Figure 7-41 I

2

C Transmit Timings

26

SDA

23

25

19

SCL

16

18

Stop Start

22

20

27

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24

21

28

Repeated

Start

17

18

Stop

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7.14 SPI Peripheral

The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on

C6671 is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.

The C6671 SPI supports two modes, 3-pin and 4-pin. For the 4-pin chip-select mode, the C6671 supports up to two chip selects.

7.14.1 SPI Electrical Data/Timing

7.14.1.1 SPI Timing

Table 7-67

See

Figure 7-42

)

SPI Timing Requirements

No.

7

7

7

7 tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC)

8

8 th(SPC-SDI) th(SPC-SDI)

8 th(SPC-SDI)

8 th(SPC-SDI)

End of Table 7-67

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1

5

5

5

5

2

2

2

2

Min Max Unit

ns ns ns ns ns ns ns ns

3

4

1

2

Table 7-68 SPI Switching Characteristics (Part 1 of 2)

(See Figure 7-42 and Figure 7-43

)

No.

4

4

4

5

5

5

5 tc(SPC) tw(SPCH) tw(SPCL) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO)

Parameter

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Cycle Time, SPICLK, All Master Modes 3*P2

(1)

Min

Pulse Width High, SPICLK, All Master Modes

Pulse Width Low, SPICLK, All Master Modes

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 0.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 1.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 0

0.5*tc - 1

0.5*tc - 1

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on

SPICLK. Polarity = 0 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 0 Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 1

5

2

2

2

2

5

5

5

Max Unit

ns ns ns ns ns ns ns ns ns ns ns

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Table 7-68 SPI Switching Characteristics (Part 2 of 2)

(See Figure 7-42 and Figure 7-43 )

No.

6 toh(SPC-SDO)

6

6

6 toh(SPC-SDO) toh(SPC-SDO) toh(SPC-SDO)

19 td(SCS-SPC)

19 td(SCS-SPC)

19 td(SCS-SPC)

19 td(SCS-SPC)

20 td(SPC-SCS)

20 td(SPC-SCS)

20 td(SPC-SCS)

20 td(SPC-SCS) tw(SCSH)

Parameter

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 0

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 1

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 0

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 1

Min

0.5*tc - 2

0.5*tc - 2

0.5*tc - 2

0.5*tc - 2

Max Unit

ns ns ns ns

Additional SPI Master Timings — 4 Pin Mode with Chip Select Option

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1

2*P2 - 5 2*P2 + 5 ns

0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1

2*P2 - 5 2*P2 + 5 ns

0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns

1*P2 - 5 1*P2 + 5 ns Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 0

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 1

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 0

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 1

Minimum inactive time on SPISCS[n] pin between two transfers when

SPISCS[n] is not held using the CSHOLD feature.

0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns

1*P2 - 5

0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns

2*P2 - 5

1*P2 + 5 ns ns

End of Table 7-68

1 P2 = 1/SYSCLK7

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Figure 7-42 SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

SPICLK

SPIDOUT

SPIDIN

2

1

3

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

MASTER MODE

POLARITY = 0 PHASE = 0

6

MO(n−1)

MI(n−1)

MO(n)

MI(n)

SPICLK

SPIDOUT

SPIDIN

MASTER MODE

POLARITY = 0 PHASE = 1

4

MO(0)

7

MI(0)

8

5

MO(1)

6

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

SPICLK

SPIDOUT

SPIDIN

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

MASTER MODE

POLARITY = 1 PHASE = 0

6

MO(n−1)

MI(n−1)

MO(n)

MI(n)

MASTER MODE

POLARITY = 1 PHASE = 1

SPICLK

SPIDOUT

SPIDIN

4

MO(0)

7

MI(0)

8

5

MO(1)

6

MI(1)

MO(n−1)

MI(n−1)

Figure 7-43

SPICLK

SPIDOUT

SPIDIN

SPISCSx

SPI Additional Timings for 4 Pin Master Mode with Chip Select Option

MASTER MODE 4 PIN WITH CHIP SELECT

19 20

MO(0)

MI(0)

MO(1)

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

MO(n)

MI(n)

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7.15 HyperLink Peripheral

The TMS320C6671 includes the HyperLink bus for companion chip/die interfaces. This is a four-lane SerDes interface designed to operate at up to 12.5 Gbaud per lane. The supported data rates include 1.25 Gbaud,

3.125 Gbaud, 6.25 Gbaud, 10 Gbaud and 12.5 Gbaud. The interface is used to connect with external accelerators.

The HyperLink links must be connected with DC coupling.

The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.

7.15.1 HyperLink Device-Specific Interrupt Event

The HyperLink has 64 input events. Events 0 to 31come from the chip level interrupt controller and events 32 to 63 are from queue-pending signals from the Queue Manager to monitor some of the transmission queue status.

Table 7-69

24

25

26

21

22

23

27

28

29

16

17

18

13

14

15

19

20

8

9

10

5

6

7

11

12

3

4

1

2

Event Number

0

HyperLink Events for C6671 (Part 1 of 2)

CIC3_OUT21

CIC3_OUT22

CIC3_OUT23

CIC3_OUT24

CIC3_OUT25

CIC3_OUT26

CIC3_OUT27

CIC3_OUT28

CIC3_OUT29

CIC3_OUT30

CIC3_OUT31

CIC3_OUT32

CIC3_OUT33

CIC3_OUT34

CIC3_OUT35

CIC3_OUT36

CIC3_OUT37

Event

CIC3_OUT8

CIC3_OUT9

CIC3_OUT10

CIC3_OUT11

CIC3_OUT12

CIC3_OUT13

CIC3_OUT14

CIC3_OUT15

CIC3_OUT16

CIC3_OUT17

CIC3_OUT18

CIC3_OUT19

CIC3_OUT20

Event Description

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

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Table 7-69 HyperLink Events for C6671 (Part 2 of 2)

53

54

55

56

57

48

49

50

45

46

47

51

52

40

41

42

37

38

39

43

44

32

33

34

Event Number

30

31

35

36

58

59

60

61

62

63

End of Table 7-69

Event

CIC3_OUT38

CIC3_OUT39

QM_INT_PEND_864

QM_INT_PEND_865

QM_INT_PEND_866

QM_INT_PEND_867

QM_INT_PEND_868

QM_INT_PEND_869

QM_INT_PEND_870

QM_INT_PEND_871

QM_INT_PEND_872

QM_INT_PEND_873

QM_INT_PEND_874

QM_INT_PEND_875

QM_INT_PEND_876

QM_INT_PEND_877

QM_INT_PEND_878

QM_INT_PEND_879

QM_INT_PEND_880

QM_INT_PEND_881

QM_INT_PEND_882

QM_INT_PEND_883

QM_INT_PEND_884

QM_INT_PEND_885

QM_INT_PEND_886

QM_INT_PEND_887

QM_INT_PEND_888

QM_INT_PEND_889

QM_INT_PEND_890

QM_INT_PEND_891

QM_INT_PEND_892

QM_INT_PEND_893

QM_INT_PEND_894

QM_INT_PEND_895

Event Description

Interrupt Controller output

Interrupt Controller output

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

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7.15.2 HyperLink Electrical Data/Timing

The tables and figure below describe the timing requirements and switching characteristics of HyperLink peripheral.

Table 7-70 HyperLink Peripheral Timing Requirements

See

Figure 7-44 , Figure 7-45 , Figure 7-46

No.

7

6

7

3

6

1

2

3

6

1

2 tc(MCMTXFLCLK) tw(MCMTXFLCLKH) tw(MCMTXFLCLKL) tsu(MCMTXFLDAT-MCMTXFLCLKH) th(MCMTXFLCLKH-MCMTXFLDAT) tsu(MCMTXFLDAT-MCMTXFLCLKL) th(MCMTXFLCLKL-MCMTXFLDAT) tc(MCMRXPMCLK) tw(MCMRXPMCLK) tw(MCMRXPMCLK)

FL Interface

Clock period - MCMTXFLCLK (C1)

High pulse width - MCMTXFLCLK

Low pulse width - MCMTXFLCLK

Setup time - MCMTXFLDAT valid before MCMTXFLCLK high

Hold time - MCMTXFLDAT valid after MCMTXFLCLK high

Setup time - MCMTXFLDAT valid before MCMTXFLCLK low

Hold time - MCMTXFLDAT valid after MCMTXFLCLK low

PM Interface

Clock period - MCMRXPMCLK (C3)

High pulse width - MCMRXPMCLK

Low pulse width - MCMRXPMCLK tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup time - MCMRXPMDAT valid before MCMRXPMCLK high

7

6 th(MCMRXPMCLKH-MCMRXPMDAT) tsu(MCMRXPMDAT-MCMRXPMCLKL)

Hold time - MCMRXPMDAT valid after MCMRXPMCLK high

Setup time - MCMRXPMDAT valid before MCMRXPMCLK low

7 th(MCMRXPMCLKL-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK low

End of Table 7-70

Min Max Unit

6.4

ns

0.4*C1 0.6*C1 ns

0.4*C1 0.6*C1 ns

1 ns

1

1

1 ns ns ns

6.4

ns

0.4*C3 0.6*C3 ns

0.4*C3 0.6*C3 ns

1 ns

1

1

1 ns ns ns

Table 7-71 HyperLink Peripheral Switching Characteristics

See

Figure 7-44 , Figure 7-45 , Figure 7-46

3

4

1

2

No.

tc(MCMRXFLCLK) tw(MCMRXFLCLKH)

Parameter

FL Interface

Clock period - MCMRXFLCLK (C2)

High pulse width - MCMRXFLCLK tw(MCMRXFLCLKL) Low pulse width - MCMRXFLCLK tosu(MCMRXFLDAT-MCMRXFLCLKH) Setup time - MCMRXFLDAT valid before MCMRXFLCLK high

5

4

5

3

4

1

2 toh(MCMRXFLCLKH-MCMRXFLDAT) Hold time - MCMRXFLDAT valid after MCMRXFLCLK high tosu(MCMRXFLDAT-MCMRXFLCLKL) Setup time - MCMRXFLDAT valid before MCMRXFLCLK low toh(MCMRXFLCLKL-MCMRXFLDAT) Hold time - MCMRXFLDAT valid after MCMRXFLCLK low

PM Interface

tc(MCMTXPMCLK) tw(MCMTXPMCLK) tw(MCMTXPMCLK)

Clock period - MCMTXPMCLK (C4)

High pulse width - MCMTXPMCLK

Low pulse width - MCMTXPMCLK tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup time - MCMTXPMDAT valid before MCMTXPMCLK high

5

4 toh(MCMTXPMCLKH-MCMTXPMDAT) tosu(MCMTXPMDAT-MCMTXPMCLKL)

Hold time - MCMTXPMDAT valid after MCMTXPMCLK high

Setup time - MCMTXPMDAT valid before MCMTXPMCLK low

5 toh(MCMTXPMCLKL-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK low

End of Table 7-71

Min Max Unit

6.4

ns

0.4*C2 0.6*C2 ns

0.4*C2 0.6*C2 ns

0.25*C2-0.4

ns

0.25*C2-0.4

0.25*C2-0.4

0.25*C2-0.4

ns ns ns

6.4

ns

0.4*C4 0.6*C4 ns

0.4*C4 0.6*C4 ns

0.25*C4-0.4

ns

0.25*C4-0.4

0.25*C4-0.4

0.25*C4-0.4

ns ns ns

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Figure 7-44 HyperLink Station Management Clock Timing

Figure 7-45

1

2 3

HyperLink Station Management Transmit Timing

4 5

MCMTX<xx>CLK

MCMTX<xx>DAT

<xx> represents the interface that is being used: PM or FL

Figure 7-46 HyperLink Station Management Receive Timing

6 7

MCMRX<xx>CLK

MCMRX<xx>DAT

<xx> represents the interface that is being used: PM or FL

4 5

6 7

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7.16 UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and

UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element, which, in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate

FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter

(UART) for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

Table 7-72 UART Timing Requirements

(see Figure 7-47 and Figure 7-48 )

No.

5

6

4

5

6

6 tw(RXSTART) tw(RXH) tw(RXL) tw(RXSTOP1) tw(RXSTOP15) tw(RXSTOP2)

Receive Timing

Pulse width, receive start bit

Pulse width, receive data/parity bit high

Pulse width, receive data/parity bit low

Pulse width, receive stop bit 1

Pulse width, receive stop bit 1.5

Pulse width, receive stop bit 2

Autoflow Timing Requirements

Delay time, CTS asserted to START bit transmit 8 td(CTSL-TX)

End of Table 7-72

1 U = UART baud time = 1/programmed baud rate

2 P = 1/SYSCLK7

Min

0.96U

(1)

0.96U

0.96U

0.96U

1.05U

1.05U

1.05U

1.05U

1.5*(0.96U) 1.5*(1.05U)

2*(0.96U) 2*(1.05U)

P

(2)

Max

5P

Unit

ns ns ns ns ns ns ns

Figure 7-47

RXD

UART Receive Timing Waveform

Stop/Idle

4

Start Bit 0

5

Bit 1 Bit N-1 Bit N

5

Parity

6

Stop Idle Start

Figure 7-48

TXD

UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform

8

Bit N-1 Bit N Stop Start Bit 0

CTS

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Table 7-73 UART Switching Characteristics

(See Figure 7-49 and Figure 7-50

)

2

3

3

1

2

3

No.

tw(TXSTART) tw(TXH) tw(TXL) tw(TXSTOP1) tw(TXSTOP15) tw(TXSTOP2)

Parameter

Transmit Timing

Pulse width, transmit start bit

Pulse width, transmit data/parity bit high

Pulse width, transmit data/parity bit low

Pulse width, transmit stop bit 1

Pulse width, transmit stop bit 1.5

Pulse width, transmit stop bit 2

Autoflow Timing Requirements

Delay time, STOP bit received to RTS deasserted 7 td(RX-RTSH)

End of Table 7-73

1 U = UART baud time = 1/programmed baud rate

2 P = 1/SYSCLK7

Figure 7-49

TXD

UART Transmit Timing Waveform

1 2

Stop/Idle

Start Bit 0 Bit 1 Bit N-1 Bit N

2

Parity

Figure 7-50 UART RTS (Request-to-Send Output) — Autoflow Timing Waveform

7

RXD Bit N-1 Bit N Stop

CTS

3

Stop Idle

Start

Min Max Unit

U

(1)

- 2

U - 2

U - 2

U - 2

U + 2

U + 2

U + 2

U + 2

1.5 * (U - 2) 1.5 * ('U + 2)

2 * (U - 2) 2 * ('U + 2) ns ns ns ns ns ns

P

(2)

5P ns

Start

7.17 PCIe Peripheral

The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other

PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral Component

Interconnect Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72. The PCIe electrical requirements are fully specified in the PCI Express Base Specification Revision 2.0

of PCI-SIG. TI has performed the simulation and system characterization to ensure all PCIe interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

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7.18 TSIP Peripheral

The telecom serial interface port (TSIP) module provides a glueless interface to common telecom serial data streams.

For more information, see the Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

7.18.1 TSIP Electrical Data/Timing

Table 7-74

(see Figure 7-51 )

Timing Requirements for TSIP 2x Mode

(1)

No.

1

2

3

4

5

6

7

8 t c

(CLK) t w

(CLKL) t w

(CLKH) t t

(CLK) t su

(FS-CLK) t h

(CLK-FS) t su

(TR-CLK) t h

(CLK-TR)

9 t d

(CLKL-TX)

10 t dis

(CLKH-TXZ)

End of Table 7-74

Cycle time, CLK rising edge to next CLK rising edge

Pulse duration, CLK low

Pulse duration, CLK high

Transition time, CLK high to low or CLK low to high

Setup time, FS valid before rising CLK

Hold time, FS valid after rising CLK

Setup time, TR valid before rising CLK

Hold time, TR valid after rising CLK

Delay time, CLK low to TX valid

Disable time, CLK low to TX Hi-Z

Min

0.4×t c

0.4×t c

61

(2)

(CLK)

(CLK)

5

5

5

5

1

2

Max

2

12

10

1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.

ns ns ns ns

Unit

ns ns ns ns ns ns

Figure 7-51

1

CLKA/B

TSIP 2x Timing Diagram

2

(1)

3

5

6

FSA/B

8

TR[n]

ts127-3 ts127-2

7

ts127-1 ts127-0

9

ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

TX[n]

ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1 and a XMTDATD=1

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Table 7-75

(see Figure 7-52 )

Timing Requirements for TSIP 1x Mode

(1)

No.

11

12

13

14

15

16

17

18 t c

(CLK) t w

(CLKL) t w

(CLKH) t t

(CLK) t su

(FS-CLK) t h

(CLK-FS) t su

(TR-CLK) t h

(CLK-TR)

19 t d

(CLKL-TX)

20 t dis

(CLKH-TXZ)

End of Table 7-75

Cycle time, CLK rising edge to next CLK rising edge

Pulse duration, CLK low

Pulse duration, CLK high

Transition time, CLK high to low or CLK low to high

Setup time, FS valid before rising CLK

Hold time, FS valid after rising CLK

Setup time, TR valid before rising CLK

Hold time, TR valid after rising CLK

Delay time, CLK low to TX valid

Disable time, CLK low to TX Hi-Z

Min

122.1

0.4×t c

0.4×t c

(2)

(CLK)

(CLK)

5

5

5

5

1

2

Max

2

12

10

1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.

ns ns ns ns

Unit

ns ns ns ns ns ns

Figure 7-52 TSIP 1x Timing Diagram

(1)

11 12 13

CLKA/B

16

15

FSA/B

TR[n]

ts127-3 ts127-2 ts127-1 ts127-0

17

18

ts000-7

19

ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

TX[n]

ts127-3 ts127-2 ts127-1 ts127-0 ts000-7 ts000-6 ts000-5 ts000-4 ts000-3 ts000-2 ts000-1 ts000-0

1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.

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7.19 EMIF16 Peripheral

The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

7.19.1 EMIF16 Electrical Data/Timing

18

19

20

21

16

17

16

17

22

23

8

9

6

7

4

5

4

5

10

10

11

12

13

Table 7-76 EMIF16 Asynchronous Memory Timing Requirements

(see Figure 7-53 and Figure 7-54 )

(1) (2)

No.

2

28

14

3

3

15

15

Min Max Unit

t t t w d d

(WAIT)

(WAIT-WEH)

(WAIT-OEH)

General Timing

Pulse duration, WAIT assertion and deassertion minimum time

Setup time, WAIT asserted before WE high

Setup time, WAIT asserted before OE high

Read Timing

EMIF read cycle time when ew = 0, meaning not in extended wait mode

2E

4E + 3

4E + 3 ns ns ns t t

C

C

(CEL)

(CEL)

EMIF read cycle time when ew =1, meaning extended wait mode enabled t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(BEV-OEL) t oh

(OEH-BEIV) t osu

(AV-OEL) t oh

(OEH-AIV)

Output setup time from CE low to OE low. SS = 0, not in select strobe mode

Output hold time from OE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to OE low in select strobe mode, SS = 1

Output hold time from OE high to CE high in select strobe mode, SS = 1

Output setup time from BE valid to OE low

Output hold time from OE high to BE invalid

Output setup time from A valid to OE low

Output hold time from OE high to A invalid t w

(OEL) t w

(OEL)

OE active time low, when ew = 0. Extended wait mode is disabled.

OE active time low, when ew = 1. Extended wait mode is enabled.

t d

(WAITH-OEH) Delay time from WAIT deasserted to OE# high t su

(D-OEH) Input setup time from D valid to OE high t h

(OEH-D) Input hold time from OE high to D invalid

Write Timing

t t c c

(CEL)

(CEL) t osu

(CEL-WEL) t oh

(WEH-CEH) t osu

(CEL-WEL) t oh

(WEH-CEH) t osu

(AV-WEL) t oh

(WEH-AIV)

Output setup time from CE low to WE low. SS = 0, not in select strobe mode

Output hold time from WE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to WE low in select strobe mode, SS = 1

Output hold time from WE high to CE high in select strobe mode, SS = 1 t osu

(RNW-WEL) Output setup time from RNW valid to WE low t oh

(WEH-RNW) Output hold time from WE high to RNW invalid t osu

(BEV-WEL) t oh

(WEH-BEIV)

Output setup time from BE valid to WE low

Output hold time from WE high to BE invalid

Output setup time from A valid to WE low

Output hold time from WE high to A invalid

(RS+RST+RH+3)*

E-3

(RS+RST+RH+3)*

E+3

(RS+RST+WAIT+

RH+3)* E-3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RST+1) * E - 3

(RST+1) * E - 3

3

0.5

EMIF write cycle time when ew = 0, meaning not in extended wait mode (WS+WST+WH+

3)* E-3

EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WAIT

+WH+3)* E-3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(RS+RST+WAIT+

RH+3)* E+3 ns

(RS+1) * E + 3 ns

(RH+1) * E + 3 ns

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RST+1) * E + 3

(RST+1) * E + 3

4E + 3

(WS+WST+WH+

3)* E+3

(WS+WST+WAIT

+WH+3)* E+3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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Table 7-76 EMIF16 Asynchronous Memory Timing Requirements

(see Figure 7-53 and Figure 7-54 )

(1) (2)

No.

24

24

26

27 t w

(WEL) t w

(WEL) t osu

(DV-WEL) t oh

(WEH-DIV)

WE active time low, when ew = 0. Extended wait mode is disabled.

WE active time low, when ew = 1. Extended wait mode is enabled.

Output setup time from D valid to WE low

Output hold time from WE high to D invalid

25 t d

(WAITH-WEH) Delay time from WAIT deasserted to WE# high

End of Table 7-76

1 E = 1/SYSCLK7, RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold.

2 WAIT = number of cycles wait is asserted between the programmed end of the strobe period and wait de-assertion.

Min

(WST+1) * E - 3

(WST+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

Figure 7-53 EMIF16 Asynchronous Memory Read Timing Diagram

3

EMIFCE[3:0]

EMIFR/W

EMIFBE[1:0]

EMIFA[21:0]

8

6

4

10

EMIFOE

9

7

5

12

13

EMIFD[15:0]

EMIFWE

Figure 7-54 EMIF16 Asynchronous Memory Write Timing Diagram

15

EMIFCE[3:0]

EMIFR/W

EMIFBE[1:0]

EMIFA[21:0]

16

18

20

22

24

EMIFWE

26

EMIFD[15:0]

EMIFOE

19

21

23

17

27

Max Unit

ns ns ns ns

4E + 3 ns

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Figure 7-55 EMIF16 EM_WAIT Read Timing Diagram

Setup Strobe

EMIFCE[3:0]

EMIFBE[1:0]

EMIFA[21:0]

EMIFD[15:0]

EMIFOE

Extended Due to EM_WAIT

EMIFWAIT

2

Asserted

Figure 7-56 EMIF16 EM_WAIT Write Timing Diagram

Setup Strobe

EMIFCE[3:0]

EMIFBE[1:0]

EMIFA[21:0]

EMIFD[15:0]

EMIFWE

14

2

Deasserted

11

Extended Due to EM_WAIT

EMIFWAIT

2

Asserted

28

2

Deasserted

25

Strobe Hold

Strobe Hold

7.20 Packet Accelerator

The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN,

MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS capabilities. It can process up to 1.5 M pps. The packet accelerator is coupled with the network coprocessor. For

more information, see the Packet Accelerator (PA) for KeyStone Devices User Guide in ‘‘Related Documentation from

Texas Instruments’’ on page 72.

7.21 Security Accelerator

The security accelerator provides wire-speed processing on 1-Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air interface security protocols. It functions on the packet level with the packet and the associated security context being one of these above three types. The security accelerator is coupled with network coprocessor, and receives the packet descriptor containing the security context in the buffer descriptor, and the data to be encrypted/decrypted in the linked buffer descriptor. For more information, see the Security Accelerator (SA) for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

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7.22 Gigabit Ethernet (GbE) Switch Subsystem

The Gigabit Ethernet (GbE) switch subsystem provide an efficient interface between the TMS320C6671 DSP and the networked community. The GbE switch subsystem supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX

(100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with network coprocessor. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in

‘‘Related

Documentation from Texas Instruments’’ on page 72.

Each device has a unique MAC address. There are two registers to hold these values, MACID1 (0x02620110) and

MACID2 (0x02620114). All bits of these registers are defined as follows:

Figure 7-57 MACID1 Register

31 0

MACID[31:0]

R-xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Legend: R = Read only; -x, value is indeterminate

Table 7-77 MACID1 Register Field Descriptions

Bit Field

31-0 MAC ID[31-0]

End of Table 7-77

Description

MAC ID. A range will be assigned to this device. Each device will consume only one MAC address.

Figure 7-58 MACID2 Register

31

Reserved

R-xxxx xxxx

Legend: R = Read only; -x, value is indeterminate

24

Table 7-78

Bit

31-24

23-18

17

16

Field

Reserved

Reserved

FLOW

BCAST

MACID2 Register Field Descriptions

15-0 MAC ID[47-0]

End of Table 7-78

Description

Reserved. Values will vary.

Reserved. Read as 0.

MAC flow control

0 = Off

1 = On

Default m/b-cast reception

0 = Broadcast

1 = Disabled

MAC ID

23

Reserved

R-0

18 17 16

FLOW BCAST

R-z R-y

15

MACID[47:32]

R-xxxx xxxx xxxx xxxx

0

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There is one Time Synchronization (CPTS) submodule in the Ethernet switch module for time synchronization.

Programming this register selects the clock source for the CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch

Subsystem for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72 for the

register address and other details about the Time Synchronization module. The register CPTS_RFTCLK_SEL for reference clock selection of Time Synchronization submodule is shown in

Figure 7-59 .

Figure 7-59 CPTS_RFTCLK_SEL Register

31

Reserved

R-0

3 2

CPTS_RFTCLK_SEL

0

RW-0

Legend: R = Read only; -x, value is indeterminate

Table 7-79 CPTS_RFTCLK_SEL Register Field Descriptions

Bit

31-3

Field

Reserved

Description

Reserved. Read as 0.

2-0 CPTS_RFTCLK_SEL Reference Clock Select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the

TS_CTL register.

000 = SYSCLK2

001 = SYSCLK3

010 = TIMI0

011 = TIMI1

100 = TSIP0 CLK_A

101 = TSIP0 CLK_B

110 = TSIP1 CLK_A

111 = TSIP1 CLK_B

End of Table 7-79

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7.23 Management Data Input/Output (MDIO)

The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE) Switch

Subsystem for KeyStone Devices User Guide in

‘‘Related Documentation from Texas Instruments’’ on page 72.

Table 7-80

See

Figure 7-60

MDIO Timing Requirements

No.

1

2

3

4

5 tc(MDCLK) tw(MDCLKH) tw(MDCLKL) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) tt(MDCLK)

End of Table 7-80

Cycle time, MDCLK

Pulse duration, MDCLK high

Pulse duration, MDCLK low

Setup time, MDIO data input valid before MDCLK high

Hold time, MDIO data input valid after MDCLK high

Transition time, MDCLK

Min

400

180

180

10

0

Max

5

Unit

ns ns ns ns ns ns

Figure 7-60 MDIO Input Timing

MDCLK

2 3

4 5

MDIO

(Input)

Table 7-81

See

Figure 7-61

MDIO Switching Characteristics

No.

6 td(MDCLKL-MDIO)

End of Table 7-81

Parameter

Delay time, MDCLK low to MDIO data output valid

Figure 7-61 MDIO Output Timing

1

MDCLK

6

MDIO

(Ouput)

Min Max

100

Unit

ns

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7.24 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send synchronization events to the EDMA3 channel controller.

7.24.1 Timers Device-Specific Information

The TMS320C6671 device has nine 64-bit timers in total. Timer0 is dedicated to the CorePac as a watchdog timer and can also be used as a general-purpose timer. Timer1 through Timer7 are reserved. Each of the other eight timers

(Timer8 through Timer15) can also be configured as a general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit timers.

When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable period.

When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two

32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.

When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again. If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming

‘‘Reset

Type Status Register (RSTYPE)’’ on page 144 and the type of reset initiated can set by programming

‘‘Reset

Configuration Register (RSTCFG)’’ on page 145. For more information, see the Timer64P for KeyStone Devices User

Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

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7.24.2 Timers Electrical Data/Timing

The tables and figure below describe the timing requirements and switching characteristics of Timer0 and Timer8 through Timer15 peripherals.

Table 7-82

(see Figure 7-62 )

Timer Input Timing Requirements

(1)

No.

1 t w(TINPH)

2 t w(TINPL)

End of Table 7-82

Pulse duration, high

Pulse duration, low

1 C = 1/SYSCLK1 frequency in ns.

Min

12C

12C

Max Unit

ns ns

Table 7-83

(see Figure 7-62 )

Timer Output Switching Characteristics

(1)

Parameter No.

3 t w(TOUTH)

4 t w(TOUTL)

End of Table 7-83

Pulse duration, high

Pulse duration, low

1 C = 1/SYSCLK1 frequency in ns.

Figure 7-62 Timer Timing

1 2

TIMIx

Min

12C - 3

12C - 3

Max Unit

ns ns

3

4

TIMOx

7.25 Serial RapidIO (SRIO) Port

The SRIO port on the TMS320C6671 device is a high-performance, low pin-count interconnect aimed for embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous interconnect environment, providing even more connectivity and control among the components. RapidIO is based on the memory and device addressing concepts of processor buses where the transaction processing is managed completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency, reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless

interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 72.

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7.26 General-Purpose Input/Output (GPIO)

7.26.1 GPIO Device-Specific Information

On the TMS320C6671, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more detailed information on device/peripheral configuration and the C6671 device pin muxing, see

‘‘Device

Configuration’’ on page 73. For more information on GPIO, see the General Purpose Input/Output (GPIO) for

KeyStone Devices User Guide

‘‘Related Documentation from Texas Instruments’’ on page 72.

7.26.2 GPIO Electrical Data/Timing

Table 7-84 GPIO Input Timing Requirements

No.

1 t w(GPOH)

2 t w(GPOL)

End of Table 7-84

1 C = 1/SYSCLK1 frequency in ns.

Pulse duration, GPOx high

Pulse duration, GPOx low

Min

12C

(1)

12C

Max Unit

ns ns

Table 7-85 GPIO Output Switching Characteristics

No.

3 t w(GPOH)

4 t w(GPOL)

End of Table 7-85

1 C = 1/SYSCLK1 frequency in ns.

Parameter

Pulse duration, GPOx high

Pulse duration, GPOx low

Figure 7-63 GPIO Timing

1 2

GPIx

Min

36C

(1)

- 8

36C - 8

Max Unit

ns ns

3

4

GPOx

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7.27 Semaphore2

The device contains an enhanced semaphore module for the management of shared resources of the DSP C66x

CorePacs. The semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not broken. The semaphore block has unique interrupts to each of the cores to identify when that core has acquired the resource.

Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.

The semaphore module supports 1 master and contains 32 semaphores to be used within the system.

The semaphore module is accessible only by master with privilege ID (privID) 0, which means only CorePac 0 or the EDMA transactions initiated by CorePac 0 can access the semaphore module.

If the remote device wants to access the semaphore module, the HyperLink configuration register must be appropriately configured, so the remote device can send transactions with the desired privID value to the local semaphore module. For more information on HyperLink configuration, see the HyperLink for KeyStone Devices

User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.

There are two methods of accessing a semaphore resource:

• Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the semaphore is not granted.

• Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt notifies the CPU that it is available.

7.28 Emulation Features and Capability

7.28.1 Advanced Event Triggering (AET)

The TMS320C6671 device supports advanced event triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:

Hardware Program Breakpoints:

specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.

Data Watchpoints:

specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.

Counters:

count the occurrence of an event or cycles for performance monitoring.

State Sequencing:

allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.

For more information on AET, see the following documents in

‘‘Related Documentation from Texas Instruments’’ on page 72:

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor

Systems application report

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7.28.2 Trace

The C6671 device supports Trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.

For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and Trace

Headers Technical Reference Manual in

‘‘Related Documentation from Texas Instruments’’ on page 72.

7.28.2.1 Trace Electrical Data/Timing

Table 7-86

(see Figure 7-64 )

DSP Trace Switching Characteristics

(1)

No.

Parameter

1

1

2

2

3 t w

(EMUnH) t w

(EMUnL)

Pulse duration, EMUn high detected at 50% Voh t w

(EMUnH)90% Pulse duration, EMUn high detected at 90% Voh

Pulse duration, EMUn low detected at 50% Voh t w

(EMUnL)10% Pulse duration, EMUn low detected at 10% Voh t sko

(EMUn) Output skew time, time delay difference between EMUn pins configured as trace

t sldp_

(EMUn)

End of Table 7-86

Output slew rate EMUn

1 Over recommended operating conditions.

Min Max Unit

2.4

ns

1.5

2.4

ns ns

1.5

-1

3.3

1 ns ns

V/ns

Table 7-87

(see Figure 7-64 )

STM Trace Switching Characteristics

(1)

No.

Parameter

1

1

2

2

3 t w

(EMUnH) t w

(EMUnL)

Pulse duration, EMUn high detected at 50% Voh with 60/40 duty cycle t w

(EMUnH)90% Pulse duration, EMUn high detected at 90% Voh

Pulse duration, EMUn low detected at 50% Voh with 60/40 duty cycle t w

(EMUnL)10% t sko

(EMUn)

Pulse duration, EMUn low detected at 10% Voh

Output skew time, time delay difference between EMUn pins configured as trace

t sldp_

(EMUn)

End of Table 7-87

Output slew rate EMUn

1 Over recommended operating conditions.

Figure 7-64 Trace Timing

1 2

EMUx

3

EMUy

3

EMUz

EMUx represents the EMU output pin configured as the trace clock output.

EMUy and EMUz represent all of the trace output data pins.

Min Max Unit

4 ns

3.5

4 ns ns

3.5

-1

3.3

1 ns ns

V/ns

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7.28.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes

(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power

Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).

7.28.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6671 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

7.28.3.2 JTAG Electrical Data/Timing

Table 7-88

(see Figure 7-65 )

JTAG Test Port Timing Requirements

No.

1

1a

1b

3

3 t c(TCK) tw(TCKH) tw(TCKL) tsu(TDI-TCK)

4 tsu(TMS-TCK) th(TCK-TDI)

4 th(TCK-TMS)

End of Table 7-88

Cycle time, TCK

Pulse duration, TCK high (40% of tc)

Pulse duration, TCK low(40% of tc) input setup time, TDI valid to TCK high input setup time, TMS valid to TCK high input hold time, TDI valid from TCK high input hold time, TMS valid from TCK high

3.4

3.4

17

17

Min

34

13.6

13.6

Max Unit

ns ns ns ns ns ns ns

Table 7-89

(see Figure 7-65 )

JTAG Test Port Switching Characteristics

(1)

No.

2 t d(TCKL-TDOV)

End of Table 7-89

1 Over recommended operating conditions.

Parameter

Delay time, TCK low to TDO valid

Min Max Unit

13.6

ns

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Figure 7-65 JTAG Test-Port Timing

1a

1

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1b

TCK

TDO

TDI / TMS

3

4

2

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8 Revision History

www.ti.com

Revision E

Updated EDMA addressing mode descriptions. (Page 157)

Updated BWADJ value setting description in MAIN/DDR3/PASS PLL registers (Page 147)

Added info for output clocks to 1.8-V LVCMOS Signal Transition Levels paragraph (Page 117)

Updated Main PLL and PLL Controller figure: removed /2 label from PLL object (Page 137)

Updated Rise and Fall Transition Time Voltage Reference Levels figure to include label for lower transition (Page 117)

Clarified SmartReflex pin output type (Page 53)

Clarified table caption and first column heading (Page 163)

Corrected SmartReflex peripheral I/O Buffer Type from LVCMOS category to Open drain (Page 116)

Revised Main PLL Clock Input Transition Time figure (Page 149)

Corrected EMIF16 Boot Device Configuration Bit Fields (Page 26)

Restored Parameter Information section (Page 117)

Updated Core Before IO Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N (Page 120)

Updated IO Before Core Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N (Page 122)

Updated the PASS PLL Block Diagram (Page 153)

Updated the Trace timing diagram (Page 225)

Updated Parameter Table Index bit field in I2C boot configuration (Page 29)

Updated Parameter Table Index bit field in SPI boot configuration (Page 30)

Updated PKTDMA_PRI_ALLOC register to be CHIP_MSIC_CTL register with new bit field added. (Page 77)

Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section (Page 38)

Updated slow peripherals in SYSCLK7 description (Page 139)

Updated Chip Select field description in SPI boot device configuration table (Page 30)

Added DSP_SUSP_CTL register section (Page 77)

Revision D

Corrected NMI7-0 from bit fields 23-16 to bit fields 15-8 in LRSTNMIPINSTAT and LRSTNMIPINSTAT_CLR registers (Page 80)

Added Extended Boot Mode table in Boot Device Field section (Page 25)

Updated event PO_VP_SMPSACK_INTR to be Reserved in CIC3 event table (Page 175)

Updated Trace Electrical Timing tables and Timing diagrams (Page 225)

Updated event PO_VCON_SMPSERR_INTR be Reserved in CIC0/1 Event Inputs table (Page 168)

Added Boot Parameter Table section (Page 31)

Added new section DDR3 Memory Controller Race Condition Consideration to include the last 3 paragraphs originally in section 7.11.1

(Page 197)

Added REFCLK description in power sequencing section (Page 119)

Added table of Bootloader section in L2 SRAM in Boot Sequence section (Page 23)

Updated SYSCLK1 to REFCLK in power sequencing section to refer to the clock source of main PLL (Page 120)

Updated note in power sequencing that each supply must ramp monotonically and must reach a stable valid level within 20 ms

(Page 120)

Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers (Page 148)

Changed all footnote references from CORECLK to SYSCLK1 (Page 223)

Updated PCIe privilege level from "Supervisor" to "Driven by PCIe module" (Page 185)

Corrected "Reserved" to be "Assert local reset to all CorePacs" in LRESET and NMI Decoding table (Page 182)

Added MPU Registers Reset Values section (Page 195)

Added "Initial Startup" row for CVDD in Recommended Operating Conditions table (Page 114)

Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table (Page 76)

Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table (Page 148)

Corrected tj(CORECLKN/P) max value from 100 to 0.02*tc(CORECLKN/P) (Page 148)

Corrected tj(DDRCLKN/P) max value from 0.025*tc(DDRCLKN/P) to 0.02*tc(DDRCLKN/P) (Page 152)

Corrected tj(PASSCLKN/P) max value from 100 to 0.02*tc(PASSCLKN/P) (Page 155)

Updated the descriptions of how Semaphore module is accessible (Page 224)

Added Debug Subsystem Configuration region to memory map table (Page 19)

Added HOUT timing diagram in Host Interrupt Output section (Page 183)

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Added note to DDR3 PLL initialization sequence (Page 151)

Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF (Page 184)

Revised IPCGRH register description (Page 86)

Corrected DDR3 transfer rate from 1033 MTS to 1066 MTS (Page 197)

Added CVDD and SmartReflex voltage parameter in SmartReflex switching table (Page 125)

Removed DDR3 PLL initialization sequence from data manual to PLL controller user guide (Page 151)

Removed PASS PLL initialization sequence from data manual to PLL controller user guide (Page 154)

Updated chip select from CS[5:2] to CE[3:0] in EMIF16 Peripheral section (Page 215)

Updated EMIF chip select from CS[5:2] to CE[3:0] in Memory Map Summary table (Page 23)

Updated DDR3 PLL initialization sequence (Page 152)

Added footnote for DDR3 EMIF data in memory map summary table (Page 23)

Updated Tracer descriptions across the data manual (Page 17)

Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns (Page 155)

Updated the Timer numbering across the whole document (Page 18)

Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet. (Page 25)

Added clarification for RESETSTATz input current (Page 115)

Added note for VCNTLID register that it is available for debug purpose only (Page 128)

Added STM Trace Switching Characteristics table (Page 225)

Removed the incorrect description of 16-Bit EMIF in Features section (Page 1)

Updated th(MDCLKH-MDIO) value from 10 ns to 0 ns in MDIO Timing Requirements table (Page 220)

Updated the description of NAND in the footnote of memory map summary table (Page 23)

Updated tw(DPnH) and tw(DPnL) descriptions in Trace Switching Characteristics tables (Page 225)

Updated I2C master mode table that bits[9:8] are used for mode selection (Page 28)

Updated the I2C passive mode table that bits[9:8] are used for mode selection and actual value on the bus is 0x19+bits[7:5] (Page 29)

Updated I2C data rate configuration descriptions in I2C Master Mode Configuration table (Page 28)

Added PLLSELECT bit to PASSPLLCTL1 Register (Page 154)

Added SPI device-specific support details (Page 204)

Corrected that only the sticky bits in PCIe MMRs will be retained after soft reset (Page 133)

Revision C

Added note stating that both SGMII ports can be used for boot (Page 27)

Updated the DDR3 MMR descriptions and deleted the unrelated PCIe MMR descriptions for soft reset. (Page 133)

Corrected physical 36-bit addresses of DDR3 EMIF configuration/data (Page 23)

Added TeraNet connection figures and added bridge numbers to the connection tables. (Page 96)

Restricted Output Divide of SECCTL register to max value of divide by 2 (Page 141)

Updated DEVSPEED register for both silicon rev1.0 and 2.0 (Page 93)

Removed RESETFULLz parameter from 4b timing description (Page 121)

Added supported data rates for HyperLink (Page 207)

Changed chip level interrupt controller name from INTC to CIC (Page 162)

Changed TPCC to EDMA3CC and TPTC to EDMA3TC (Page 156)

Added PLLRST bit to DDR3PLLCTL1 register (Page 151)

Added PLLRST bit to PASSPLLCTL1 register (Page 154)

Deleted INTC0 register map address offset 0x4 and 0x8, which are Reserved (Page 176)

Corrected the SGMII SerDes clock to PASS clock in PASS PLL configuration description (Page 38)

Corrected PASS PLL clock from SRIOSGMIICLK to PASSCLK in the boot device values table for Ethernet. (Page 25)

Corrected the SPI and DDR3/HyperLink Config end addressed (Page 23)

Added the DDR3 PLL Initialization Sequence (Page 151)

Added the Main PLL and PLL Controller Initialization Sequence (Page 148)

Added the PASS PLL Initialization Sequence (Page 154)

Added HyperLink interrupt event section (Page 207)

Added events #144-159 to INTC2 event input table (Page 170)

Added DEVSPEED Register section. (Page 93)

Added more description to Boot Sequence section (Page 23)

Corrected a typo, changed DDRCLKN to DDRCLKP (Page 152)

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Revision B

Removed section 7.1 Parameter Information (Page 117)

Corrected PASS PLL clock source description from Main PLL mux to CORECLK clock reference sources (Page 153)

Corrected MACID2 address from 0x02600114 to 0x02620114 (Page 218)

Added EMIF16 Electrical Data/Timing section (Page 215)

Added TSIP Electrical Data/Timing section (Page 213)

Updated SPI Timing section (Page 204)

Changed Data Rate 3 to Reserved from 12.5GBs in HyperLink configuration field table (Page 30)

Corrected the Device ID field to be bits 5 to 3 in Ethernet Configuration Field figure and table (Page 27)

Corrected the field bits of No Boot/EMIF16 configuration field figure and table (Page 26)

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Revision A

Added note to RSISO register that both SRIOISO and SRISO will be set by boot ROM code during boot (Page 146)

Removed AIF2ISO from Reset Isolation Register (Page 146)

Added information of on-chip divider (=3) for PA in the PLL Boot Configuration Settings section (Page 38)

Changed "no support for MSI" to "support for legacy INTx" for PCIe in legacy EP mode description in Device Status Register Field Descriptions table (Page 78)

Changed "no support for MSI" to "support for legacy INTx" for PCIe legacy end point description in Device Configuration Pins table

(Page 73)

Added "The packet accelerator is coupled with network coprocessor" in the Packet Accelerator section (Page 217)

Added Network Coprocessor document link (Page 72)

Changed 2 to OUTPUT_DIVIDE in the clock formula in PLL Boot Configuration Settings section (Page 38)

Changed EMAC to GbE switch subsystem (Page 218)

Changed EMAC to Gigabit Ethernet (GbE) Switch Subsystem (Page 220)

Changed EMAC to Gigabit Ethernet Switch (Page 72)

Changed EMAC to Network Coprocessor Packet DMA (Page 95)

Changed PA_SS into Network Coprocessor Packet DMA in Device Master Settings table (Page 184)

Changed PA_SS into PASS in the Clock Sequencing table (Page 124)

Changed Packet Accelerator into Network Coprocessor and corrected the memory address in the memory map summary table (Page 17)

Changed Packet Accelerator into network coprocessor in Security Accelerator section (Page 217)

Changed Packet Accelerator into Network Coprocessor in the Device Configuration Pins table. (Page 73)

Changed Packet Accelerator subsystem into Network Coprocessor (Page 153)

Changed Packet Subsystem to Network Coprocessor (PASS PLL) in Terminal Functions table (Page 44)

Changed PASS into Network Coprocessor (PASS) (Page 138)

Changed PS_SS_CLK PLL to PASS_CLK PLL in Terminal Functions table (Page 44)

Deleted section 5.5 "C66x CorePac Resets" to avoid confusion and the reset details are covered in "Reset Controller" section (Page 105)

Removed EMAC in Characteristics of the device Processor table (Page 13)

Added BGA Package row into Characteristics of Processor table (Page 13)

Corrected End and Bytes of DDR3 EMIF Configuration section in Memory Map Summary table (Page 17)

Corrected BAR number from BAR1/2 to BAR2/3 and BAR3/4 to BAR4/5 in PCIe Window Sizes table (Page 28)

Deleted EDMA3 Peripheral Register Description section, which is covered in EDMA user guide (Page 156)

Added SerDes PLL Status and Config registers (Page 74)

Added "to DDR3 memory space" to the first step of workaround (Page 197)

Added "with TCCMOD=0" after "e.g. EDMA3 transfer controllers" (Page 197)

Added CPTS_RFTCLK_SEL register in GbE Switch Subsystem section (Page 218)

Changed "DSP/2" to "CPU/2" and "DSP/3" to "CPU/3" (Page 95)

Changed the word "can" to "must" in the sentence "for most applications increment mode can be used" to specify it is a hard rule.

(Page 157)

Corrected the tw(RXSTOP15) and tw(RXSTOP2) values in UART Timing Requirements table (Page 211)

Changed "sleep boot" to "No boot" in Sub-Mode field of No boot/EMIF16 Configuration Bit Field Descriptions table (Page 26)

Changed Section 2.5.2.1 title from "Sleep/EMIF16" to "No Boot/EMIF16" (Page 26)

Corrections Applied to I2C Passive Mode Device Configuration Bit Fields (Page 29)

Corrections Applied to I2C Passive Mode Device Configuration Field Descriptions (Page 29)

Modified description of value 0 to EMIF16/No Boot in Boot Device Values table (Page 25)

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Corrected SRIO configuration memory map from 0x02900000~0x02907FFF to 0x02900000~0x02920FFF (Page 17)

Added thermal values into the Thermal Resistance Characteristics table. (Page 233)

Added DDR3PLLCTL1 register and field description table (Page 151)

Added more description to pin PTV15 in the Terminal Functions table (Page 45)

Added PASSPLLCTL1 register and field descriptions (Page 154)

Added Master ID Settings table. (Page 185)

Added the table of Power Supply to Peripheral I/O Mapping (Page 116)

Changed PROGn_MPEAR register table format and reset value format (Page 192)

Changed PROGn_MPSAR registers table format and reset value format (Page 192)

Modified the figure of SmartReflex 4-Pin VID Interface Timing (Page 125)

Modified the table of SmartReflex 4-Pin VID Interface Switching Characteristics (Page 125)

Added PROG4 registers set into MPU1 Registers table (Page 188)

Changed number of programmable ranges supported from 4 to 5 for MPU1 (Page 184)

Modified reset values in MPU Configuration Register table (Page 191)

Modified Table 2-13 to include 1000 MHz and 1250 MHz columns. (Page 38)

Added BWADJ[11:8] to MAINPLLCTL1 register table and description. (Page 147)

Changed Privilege ID from the second column to the first column (Page 184)

Changed PROG3_MPEA to PROG3_MPEAR in MPU1 Registers table (Page 188)

Changed Programmable range enumeration from 1-N based to 0-N based in MPU Register Map. (Page 187)

Changed SRIO_CPPI and SRIO_M rows to the single row (Page 184)

Changed the master from Reserved to HyperLink with Privilege ID 13 and 14 (Page 184)

Modified BWADJ descriptions in MAINPLLCTL0 and MAINPLLCTL1 registers (Page 147)

Modified SECCTL register reference place in the note. (Page 148)

Corrected Clock Sequencing table - Removed ALTCORECLK reference, Corrected SYSCLK as CORECLK. (Page 124)

Corrections Applied to I2C Boot Device Configuration Bit Fields (Page 28)

Corrections Applied to Sleep / EMIF16 Boot Device Configuration Bit Fields (Page 26)

Updated Device Configuration Pins Table; PACLKSEL Functional Description (Page 73)

Updated Reset Electrical Data / Timing section. Included updated reset requirements. (Page 135)

Updated Reset Electrical Data; Included updated Reset Requirements. (Page 135)

Updated Table 2-3 Boot Mode Pins: Boot Device Values description of the Ethernet (SGMII) boots. (Page 25)

Removed the SRIOSMGIICLK, MCMCLK, and PCIECLK transition timing values with respect to VOH and VOL within the Main PLL Controller timing requirements. (Page 148)

Updated Terminal Descriptions of TSIP Pins (Page 54)

Updated EMIF16 timing requirements table (Page 215)

Added MAINPLLCTL1, Renamed DDR3PLLCTL0 to DDR3PLLCT, Renamed PAPLLCTL0 to PAPLLCTL (Page 74)

Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 17)

Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 17)

Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR (Page 119)

Added section NMI and LRSET. (Page 182)

Corrected Extended Temperature range - Changed 105C to 100C for the top end. (Page 1)

Added BWADJ bit field to DDR3 PLL Control Register. (Page 150)

Added BWADJ bit field to PASS PLL Control Register. (Page 153)

Added MAINPLLCTL1 register table and description. (Page 147)

Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 119)

Added Note on level interrupts and use of EOI handshaking. (Page 162)

Corrected Address Range of I2C MMRs (Page 200)

Corrected PACLKSEL bitfield description. (Page 78)

Corrected RSV01 should be pulled up to 1.8 V and RSV08 should be tied to GND (Page 55)

Changed CVDD Range; Corrected CVDD and CVDD1 Descriptions (CVDD: Core Supply -> SR Core Supply) (CVDD1: SR Core Supply -> Core

Supply) (Page 114)

Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 119)

Added to table "Terminal Functions - Signals and Control by Function", signals - RSV0A and RSV0B. (Page 44)

Corrected the timing pointers to point the correct figure (Page 135)

Changed incorrect reserved address in Memory Map Summary - 02780400 -> 02778400 (Page 17)

Copyright 2014 Texas Instruments Incorporated Revision History 231

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Corrected Commercial Temperature range - Changed 100C to 85C for the top end. (Page 1)

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9 Mechanical Data

9.1 Thermal Data

Table 9-1

shows the thermal resistance characteristics for the CYP PBGA 841-pin package with Pb-free die bumps and Pb-free solder balls.

Table 9-1 Thermal Resistance Characteristics for CYP (PBGA 841-Pin Package)

No.

1 R

JC

Junction-to-case

2 R

JB

Junction-to-board

End of Table 9-1

°C/W

0.18

3.71

9.2 Packaging Information

The following packaging information reflects the most current released data available for the designated device(s).

This data is subject to change without notice and without revision of this document.

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PACKAGE OPTION ADDENDUM

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16-Sep-2014

PACKAGING INFORMATION

Orderable Device

TMS320C6671ACYP

TMS320C6671ACYP25

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

FCBGA

FCBGA

CYP

CYP

841

841

44

44

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

SNAGCU

SNAGCU

MSL Peak Temp

(3)

Level-4-245C-72HR

Level-4-245C-72HR

Op Temp (°C) Device Marking

(4/5)

TMS320C6671CYP

@2010 TI

TMS320C6671CYP

@2010 TI

1.25GHZ

TMS320C6671ACYPA ACTIVE FCBGA CYP 841 1 Green (RoHS

& no Sb/Br)

SNAGCU Level-4-245C-72HR TMS320C6671CYP

@2010 TI

A

TMS320C6671ACYPA25 ACTIVE FCBGA CYP 841 44 Green (RoHS

& no Sb/Br)

SNAGCU Level-4-245C-72HR TMS320C6671CYP

@2010 TI

A1.25GHZ

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

16-Sep-2014

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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TMS320C6671ACYP TMS320C6671ACYP25 TMS320C6671ACYPA TMS320C6671ACYPA25

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