Документация ad5751_eng_tds

Документация ad5751_eng_tds

Industrial I/V Output Driver, Single-Supply,

55 V Maximum Supply, Programmable Ranges

AD5751

FEATURES

Current output ranges: 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA

±0.03% FSR typical total unadjusted error (TUE)

±5 ppm/°C typical output drift

2% overrange

Voltage output ranges: 0 V to 5 V, 0 V to 10 V, 0 V to 40 V

±0.02% FSR typical total unadjusted error (TUE)

±3 ppm/°C typical output drift

Overrange capability on all ranges

Flexible serial digital interface

On-chip output fault detection

PEC error checking

Asynchronous CLEAR function

Power supply range

AV

DD

: 12 V (± 10%) to 55 V (maximum)

Output loop compliance to AV

DD

− 2.75 V

Temperature range: −40°C to +105°C

32-lead 5 mm × 5 mm LFCSP package

APPLICATIONS

Process control

Actuator control

PLCs

GENERAL DESCRIPTION

The AD5751 is a single-channel, low cost, precision, voltage/ current output driver with hardware or software programmable output ranges. The software ranges are configured via an SPI-/

MICROWIRE™-compatible serial interface. The AD5751 targets applications in PLC and industrial process control. The analog input to the AD5751 is provided from a low voltage, single-supply digital-to-analog converter (DAC) and is internally conditioned to provide the desired output current/voltage range.

The output current range is programmable across three current ranges: 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.

Voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, and 0 V to 40 V output ranges. An overrange is available on the voltage ranges.

Analog outputs are short-circuit and open-circuit protected and can drive capacitive loads of 1 μF and inductive loads of 0.1 H.

The device is specified to operate with a power supply range from

10.8 V to 55 V. Output loop compliance is 0 V to AV

DD

− 2.75 V.

The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The interface also features an optional PEC error checking feature using CRC-8 error checking, useful in industrial environments where data communication corruption can occur.

The device also includes a power-on reset function ensuring that the device powers up in a known state (0 V or tristate) and an asynchronous CLEAR pin that sets the outputs to zeroscale/midscale voltage output or the low end of the selected current range.

An HW SELECT pin is used to configure the part for hardware or software mode on power-up.

Table 1. Related Device

Part Number Description

AD5422 Single-channel, 16-bit, serial input current source and voltage output DAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved.

AD5751

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications ....................................................................................... 1

 

General Description ......................................................................... 1

 

Revision History ............................................................................... 2

 

Functional Block Diagram .............................................................. 3

 

Specifications ..................................................................................... 4

 

Timing Characteristics ................................................................ 7

 

Absolute Maximum Ratings ............................................................ 9

 

ESD Caution .................................................................................. 9

 

Pin Configuration and Function Descriptions ........................... 10

 

Typical Performance Characteristics ........................................... 12

 

Current Output ........................................................................... 15

 

Terminology .................................................................................... 20

 

Theory of Operation ...................................................................... 21

 

Software Mode ............................................................................ 21

 

Currrent Output Architecture .................................................. 23

 

Driving Inductive Loads ............................................................ 23

 

Power-On State of the AD5751 ................................................ 23

 

Default Registers at Power-On ................................................. 24

 

Reset Function ............................................................................ 24

 

REVISION HISTORY

5/10—Rev. 0 to Rev. A

Changes to Table 2, Power Requirements ..................................... 6

10/09—Revision 0: Initial Version

OUTEN ........................................................................................ 24

 

Software Control ........................................................................ 24

 

Hardware Control ...................................................................... 26

 

Transfer Function ....................................................................... 26

 

Detailed Description of Features .................................................. 27

 

Output Fault Alert—Software Mode ....................................... 27

 

Output Fault Alert—Hardware Mode ..................................... 27

 

Voltage Output Short-Circuit Protection ................................ 27

 

Asynchronous Clear (CLEAR) ................................................. 27

 

External Current Setting Resistor ............................................ 27

 

Programmable Overrange Modes ............................................ 28

 

Packet Error Checking ............................................................... 28

 

Applications Information .............................................................. 29

 

Transient Voltage Protection .................................................... 29

 

Thermal Considerations ............................................................ 29

 

Layout Guidelines....................................................................... 30

 

Galvanically Isolated Interface ................................................. 30

 

Microprocessor Interfacing ....................................................... 30

 

Outline Dimensions ....................................................................... 31

 

Ordering Guide .......................................................................... 31

 

Rev. A | Page 2 of 32

FUNCTIONAL BLOCK DIAGRAM

DVCC GND AVDD GND COMP1 COMP2

CLEAR

CLRSEL

SCLK/OUTEN*

SDIN/R0*

SYNC/RSET*

SDO/VFAULT*

HW SELECT

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

STATUS

REGISTER

VOUT RANGE

SCALING

VOUT

SHORT FAULT

AVDD

VIN

VREF

R2

R3

RESET

IOUT RANGE

SCALING

VSENSE+

VOUT

IOUT

FAULT/TEMP*

NC/IFAULT*

OVERTEMP

VOUT SHORT FAULT

IOUT OPEN FAULT

AD5751

R

SET

POWER-

ON RESET

IOUT

OPEN FAULT

AD2/R1* AD1/R2* AD0/R3*

*DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE

DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS

PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.

Figure 1. Functional Block Diagram

REXT1

REXT2

AD5751

Rev. A | Page 3 of 32

AD5751

SPECIFICATIONS

AV

DD

= 12 V (± 10%) to 55 V (maximum), DV

CC

= 2.7 V to 5.5 V, GND = 0 V. IOUT: R

LOAD

= 300 Ω. All specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter

1

INPUT VOLTAGE RANGE

Input Leakage Current

REFERENCE INPUT

Reference Input Voltage

Input Leakage Current

VOLTAGE OUTPUT

Output Voltage Ranges

−1

0

0

−1

0 to 4.096

+1

4.096

+1

5

10

μA

V

V

V

μA

V

Output unloaded

External reference must be exactly as stated; otherwise, accuracy errors show up as error in output

AVDD must have minimum 1.3 V headroom or >11.3 V

Output Voltage Overranges

2

0 6 V

Programmable overranges; see Detailed

Description of Features section

Accuracy

Total Unadjusted Error (TUE)

B Version

3

−0.1 +0.1 %

A Version

3

−0.3 +0.3 % FSR

Relative Accuracy (INL)

Dead Band on Output, RTI

Offset Error

Gain Error

Gain Error TC

4

Full-Scale Error

Full-Scale Error TC 4

OUTPUT CHARACTERISTICS

4

Short-Circuit Current

Load

−14

−5

−3

−20

−0.05

−0.09

−0.05

1

5

−0.09

8 +14

+5

+3

+20 mV mV mV mV

Referred to 4.096 V input range

0 V to 10 V range

0 V to 5 V range

0 V to 40 V range

+0.05 % FSR 0 V to 5 V, 0 V to 10 V range

±0.015 T

A

= 25°C

+0.09 % FSR 0 V to 40 V range

±0.5 ppm FSR/°C All ranges

+0.05 % FSR 0 V to 5 V, 0 V to 10 V range

±0.015 T

A

= 25°C

+0.09 % FSR 0 V to 40 V range

±1.5 ppm FSR/°C All ranges

V

15 mA kΩ kΩ

For specified performance, 0 V to 5 V and 0 V to 10 V ranges

For specified performance, 0 V to 40 V range

Rev. A | Page 4 of 32

Parameter

1

Capacitive Load Stability

R

LOAD

= ∞

R

LOAD

= 1 kΩ

R

LOAD

= ∞

DC Output Impedance

Settling Time

0 V to 5 V Range, ¼ to ¾ Step

0 V to 5 V Range, 40 mV Input Step

0 V to 40 V Range, ¼ to ¾ Step

Slew Rate

Output Noise

Output Noise Spectral Density

AC PSRR

DC PSRR

CURRENT OUTPUT

Output Current Ranges 0

0.12

7

4.5

15.8

2

3.5

45.5

165

65

10

1

1

2

24 nF nF

μF

Ω

μs

μs

μs

V/μs

μV rms

μV rms nV/√Hz dB

μV/V mA

AD5751

T

A

= 25°C

External compensation capacitor required;

see Driving Large Capacitive Loads section

Specified with 2 kΩ || 220 pF, ±0.05%

Specified with 2 kΩ || 220 pF, ±0.05%

Specified with 5 kΩ || 220 pF, ±0.05%

Specified with 1 kΩ || 220 pF

0.1 Hz to 10 Hz bandwidth

100 kHz bandwidth; specified with 2 kΩ ||

220 pF

Measured at 10 kHz; specified with 2 kΩ ||

220 pF

200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage

3.92 mA

Output Current Overranges

2

ACCURACY (INTERNAL R

SET

)

Total Unadjusted Error (TUE)

B Version

3

−0.2 +0.2 %

A Version

3

−0.5 +0.5 %

Relative Accuracy (INL)

Offset Error

−0.02

−16

±0.01 +0.02

+16

% FSR

μa

Offset Error TC

4

Dead Band on Output, RTI 8 +14 mV Referred to 4.096 V input range

Gain Error −0.2 +0.2 % FSR

−0.125 %

Gain TC

4

Full-Scale Error −0.2 +0.2 % FSR

−0.125 %

Full-Scale TC

4

ACCURACY (EXTERNAL R

SET

)

Total Unadjusted Error (TUE)

B Version

3

−0.1 +0.1 %

A Version 3

Relative Accuracy (INL)

Offset Error

Offset Error TC

4

Dead Band on Output, RTI

Gain Error

−0.3 +0.3 %

−0.02

−14

±0.01 +0.02

+14

% FSR

μA

−0.08

8 +14

+0.08 mV

% FSR

Referred to 4.096 V input range

±0.02

A

= 25°C

Rev. A | Page 5 of 32

AD5751

Parameter

1

Gain TC

4

Full-Scale Error −0.1 +0.1 % FSR

±0.02

A

= 25°C

Full-Scale TC 4

OUTPUT CHARACTERISTICS

Current Loop Compliance Voltage

Resistive Load

Inductive Load

4

Settling Time

4 mA to 20 mA, Full-Scale Step

120 μA Step, 4 mA to 20 mA Range

DC PSRR

Output Impedance

DIGITAL INPUTS 4

0

8.5

1.2

130

AV

1

DD

− 2.75

See test conditions/comments column

V

H

Chosen such that compliance is not exceeded

Needs appropriate capacitor at higher

inductance values; see Driving Inductive

Loads section

μs

μs

250 Ω load

250 Ω load

μA/V

JEDEC compliant

V Input High Voltage, V

IH

2

Input Low Voltage, V

IL

Input Current

Pin Capacitance

DIGITAL OUTPUTS

4

−1

5

+1 μA pF

Per pin

Per pin

FAULT, IFAULT, TEMP, VFAULT

V

OL

, Output Low Voltage

0.6

V

OL

, Output Low Voltage

V

OH

, Output High Voltage

0.5 0.5

DVCC − 0.5 DVCC − 0.5

High Impedance Output

Capacitance

High Impedance Leakage Current −1

0.4

V

OH

, Output High Voltage 3.6

SDO

+1

V

V

V

V

V

μA

10 kΩ pull-up resistor to DVCC

At 2.5 mA

10 kΩ pull-up resistor to DVCC

Sinking 200 μA

Sourcing 200 μA

POWER REQUIREMENTS

AV

DD

DV

CC

Input Voltage

AI

DD

DI

CC

2.7

4.4

5.2

5.2

5.5

5.6

6.2

6.2

V mA mA mA

Power Dissipation 108 mW

1 Temperature range: −40°C to +105°C; typical at +25°C.

2

Overranges are nominal; gain and offset are not trimmed as per nominal ranges.

3

Specification includes gain and offset errors, over temperature, and drift after 1000 hours, T

A

= 125°C.

4 Guaranteed by characterization, but not production tested.

Output unloaded, output disabled

Current output enabled

Voltage output enabled

AVDD = 24 V, outputs unloaded

Rev. A | Page 6 of 32

AD5751

TIMING CHARACTERISTICS

AV

DD

= 12 V (± 10%) to 55 V (maximum), DV

CC

= 2.7 V to 5.5 V, GND = 0 V. VOUT: R

LOAD

= 2 kΩ (5 kΩ for 0 V to 40 V range),

C

L

= 200 pF, IOUT: R

LOAD

= 300 Ω. All specifications T

MIN

to T

MAX

, unless otherwise noted. t

Table 3.

Parameter

1 , 2

t

1

2 t

3 t

4

Limit at T

MIN

, T

MAX

Unit Description

20

8

8

5 ns min ns min ns min ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time t

5

10 ns th

SCLK falling edge if using PEC) t

6

5 ns min Minimum SYNC high time (write mode) t

7 t

8 t

9

, t

10 t

11

5

5

1.5

5 ns min ns min

μs max ns min

Data setup time

Data hold time

CLEAR pulse low/high activation time

Minimum SYNC high time (read mode) t

12

40 t

13

10 ns max SCLK rising edge to SDO valid (SDO C

L

= 15 pF)

1

Guaranteed by characterization, but not production tested.

2

All input signals are specified with t

R

= t

F

= 5 ns (10% to 90% of DV

CC

) and timed from a voltage level of 1.2 V.

Timing Diagrams

t

1

SCLK

1 2 16 t

3 t

2 t

6 t

4 t

5

SYNC t

8 t

7

D15 SDIN D0

CLEAR t

10 t

9

VOUT

RESET t

13

Figure 2. Write Mode Timing Diagram

Rev. A | Page 7 of 32

AD5751

SCLK t

11

SYNC

SDIN

SDO

A2

X

A1 A0 R = 1

X t

12

X X

0

X

X

R3

X

R2

X

R1

X X X X X X X X

R0

CLRSEL OUTEN

RSET

PEC

ERROR

OVER

TEMP

IOUT

FAULT

VOUT

FAULT

Figure 3. Readback Mode Timing Diagram

Rev. A | Page 8 of 32

ABSOLUTE MAXIMUM RATINGS

T

A

= 25°C, unless otherwise noted. Transient currents of up to

100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to GND −0.3 V to +58 V

DVCC to GND −0.3 V to +7 V

Digital Inputs to GND

Digital Outputs to GND

VREF to GND

VSENSE+ to GND

VIN to GND

VOUT, IOUT to GND

Operating Temperature Range

Industrial

Storage Temperature Range

−0.3 V to DV

CC

+ 0.3 V, or 7 V

(whichever is less)

−0.3 V to DV

CC

+ 0.3 V, or 7 V

(whichever is less)

−0.3 V to +7 V

−0.3 V to AV

DD

−0.3 V to +7 V

−0.3 V to AV

DD

−40°C to +105°C

−65°C to +150°C

Junction Temperature (T

J

max)

32-Lead LFCSP Package

θ

JA

Thermal Impedance

Lead Temperature

125°C

28°C/W

JEDEC industry standard

Soldering J-STD-020

AD5751

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 9 of 32

AD5751

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDO/VFAULT

CLRSEL

CLEAR

DVCC

GND

SYNC/RSET

SCLK/OUTEN

SDIN/R0

4

5

6

7

8

1

2

3

PIN 1

INDICATOR

AD5751

TOP VIEW

(Not to Scale)

24 VSENSE+

23 VOUT

22 GND

21 GND

20 COMP1

19 COMP2

18 IOUT

17 AVDD

6

8

4

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE IS TIED TO GND.

Figure 4. Pin Configuration

readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.

This pin is a CMOS output.

Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. software mode, this pin is implemented as a logic OR with the internal CLRSEL bit.

DVCC

of range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. See the Asynchronous

Clear (CLEAR) section for more details.

In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate.

Digital Power Supply.

SYNC/RSET

SDIN/R0

Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5751, also updating the output.

Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is used.

If RSET = 0, the external sense resistor is chosen.

If RSET = 1, the internal sense resistor is chosen. edge of SCLK. This pin operates at clock speeds up to 50 MHz.

Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.

Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.

Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. eight devices to be addressed on one bus.

Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part.

Rev. A | Page 10 of 32

Pin No.

AD5751

12, 13

14

15

16

17

Mnemonic

REXT2, REXT1

VREF

VIN

GND

AVDD

Description

eight devices to be addressed on one bus.

Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output current/voltage range setting on the part. eight devices to be addressed on one bus.

Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output current/voltage range setting on the part.

A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the IOUT temperature drift performance.

Buffered Reference Input.

Buffered Analog Input (0 V to 4.096 V).

Ground Connection.

Positive Analog Supply.

19, 20

21

22

23

GND

VOUT

24 VSENSE+

25, 26, 27, 28 NC

29

30

COMP2, COMP1 Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when choosing the value of the capacitor connected between the COMP1 and COMP2 pins

because it has a direct influence on the settling time of the output. See the Driving Large Capacitive

Loads section for further details.

GND Ground Connection.

HW SELECT

RESET

Ground Connection.

Buffered Analog Output Voltage.

Sense Connection for the Positive Voltage Output Load Connection.

No Connect. Can be tied to GND.

This part is used to configure the part to hardware or software mode.

HW SELECT = 0 selects software control.

HW SELECT = 1 selects hardware control.

In software mode, this pin resets the part to its power-on state. Active low.

In hardware mode, there is no reset. If using the part in hardware mode, the RESET pin should be tied high.

32

33 (EPAD) open-circuit, short-circuit, overtemperature error, or PEC interface error is detected. This pin is an opendrain output and must be connected to a pull-up resistor.

Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a pull-up resistor.

No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND. NC/IFAULT

Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor.

Exposed paddle The exposed paddle is tied to GND.

Rev. A | Page 11 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

0.010

0.008

0V TO 5V

0V TO 10V

0V TO 40V

0.006

0.004

0.002

0

–0.002

–0.004

–0.006

–0.008

–0.010

–0.002

–0.004

–0.006

–0.008

–0.010

0.010

0.008

0.006

0.004

0.002

0

V

IN

(V)

Figure 5. Integral Nonlinearity Error vs. V

IN

0.010

0.008

0.006

0.004

0.002

0V TO 5V RANGE

0V TO 10V RANGE

0V TO 40V RANGE

0

–0.002

–0.004

–0.006

–0.008

–0.010

–40 25

TEMPERATURE (°C)

105

Figure 6. Integral Nonlinearity Error vs. Temperature

0V TO 5V

0V TO 10V

0V TO 40V

V

IN

(V)

Figure 7. Total Unadjusted Error vs. V

IN

AD5751

0

–0.01

–0.02

–0.03

0.04

0.03

0.02

0.01

–0.04

–0.01

–0.02

–0.03

–0.04

0.05

0.04

0.03

0.02

0.01

0

0.10

0.08

0.06

0.04

0.02

0V TO 5V POSITIVE TUE

0V TO 10V POSITIVE TUE

0V TO 40V POSITIVE TUE

0V TO 5V NEGATIVE TUE

0V TO 10V NEGATIVE TUE

0V TO 40V NEGATIVE TUE

0

–0.02

–0.04

–0.06

–0.08

–0.10

–40 25

TEMPERATURE (°C)

105

Figure 8. Total Unadjusted Error vs. Temperature

0V TO 5V RANGE

0V TO 10V RANGE

0V TO 40V RANGE

–40 25

TEMPERATURE (°C)

105

Figure 9. Full-Scale Error vs. Temperature

0V TO 5V RANGE

0V TO 10V RANGE

0V TO 40V RANGE

–40 25

TEMPERATURE (°C)

Figure 10. Gain Error vs. Temperature

105

Rev. A | Page 12 of 32

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

0V TO 5V RANGE

0V TO 10V RANGE

0V TO 40V RANGE

–40 25

TEMPERATURE (°C)

Figure 11. Offset Error vs. Temperature

105

0

–0.002

–0.004

–0.006

–0.008

–0.010

0.010

0.008

0.006

0.004

0.002

5V LINEARITY, NO LOAD

10V LINEARITY, NO LOAD

40V LINEARITY, NO LOAD

24 48

SUPPLY VOLTAGE (V)

Figure 12. INL Error vs. Supply Voltage

55

0.010

0.008

0.006

0.004

0.002

0

–0.002

–0.004

–0.006

0V TO 5V POSITIVE TUE

0V TO 10V POSITIVE TUE

0V TO 40V POSITIVE TUE

0V TO 5V NEGATIVE TUE

0V TO 10V NEGATIVE TUE

0V TO 40V NEGATIVE TUE

–0.008

–0.010

24 48

SUPPLY VOLTAGE (V)

55

Figure 13. Total Unadjusted Error vs. Supply Voltage

AD5751

1.00

0.95

0.90

0.85

0.80

0.75

V

DD

HEADROOM, LOAD OFF

0.70

–40 25

TEMPERATURE (°C)

105

Figure 14. AVDD Headroom, 0 V to 10 V Range, Output Set to 10 V, Load Off

0.007

5V RANGE

0.006

0.005

0.004

0.003

0.002

0.001

0

–0.001

–0.002

–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

SOURCE/SINK CURRENT (mA)

Figure 15. Source and Sink Capability of Output Amplifier

12

10

8

6

4

2

0

–8 –3 2 7 12

TIME (µs)

17 22 27

Figure 16. Full-Scale Positive Step, 10 V Range

Rev. A | Page 13 of 32

AD5751

12

10

8

6

4

2

0

–8 –3 2 7 12

TIME (µs)

17 22 27

Figure 17. Full-Scale Negative Step, 10 V Range

25

20

15

40

35

30

10

5

0

–5

–1.0

–0.5

0 0.5

1.0

TIME (ms)

1.5

2.0

2.5

Figure 18. V

OUT

vs. Time on Power-Up, Load = 2 kΩ || 200 pF

5µV/DIV

Figure 20. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)

100µV/DIV

1s/DIV

1s/DIV

1

2

CH1 5.00V

CH2 20.0mV

B

W

M1.0µs A CH1 3.00V

Figure 19. V

OUT

Enable Glitch, Load = 2 kΩ || 1 nF

2.5

2.0

1.5

1.0

4.0

3.5

3.0

0.5

0

–1.5

Figure 21. Peak-to-Peak Noise (100 kHz Bandwidth)

V

DD

V

OUT

1.0

0.8

0.6

0.4

0.2

0

–1.0

–0.5

0 0.5

TIME (ms)

1.0

1.5

Figure 22. V

DD

and V

OUT

vs. Time on Power-Up

2.0

–0.2

Rev. A | Page 14 of 32

CURRENT OUTPUT

0.005

0.004

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

RESISTOR

RESISTOR

RESISTOR

0.003

0.002

0.001

0

–0.001

–0.002

–0.003

–0.004

–0.005

V

IN

(V)

Figure 23. Integral Nonlinearity Error vs. V

IN

, External R

SET

Resistor

0.005

0.004

0.003

0.002

0.001

0

–0.001

–0.002

–0.003

–0.004

–0.005

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

RESISTOR

RESISTOR

RESISTOR

V

IN

(V)

Figure 24. Integral Nonlinearity Error vs. V

IN

, Internal R

SET

Resistor

0.010

0.008

0.006

0.004

0.002

0

–0.002

–0.004

–0.006

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

LINEARITY

LINEARITY

LINEARITY

–0.008

–0.010

24V 48V

SUPPLY VOLTAGE (AVDD)

55V

Figure 25. Integral Nonlinearity Current Mode, External R

SET

Sense Resistor

AD5751

0.010

0.008

0.006

0.004

0.002

0

–0.002

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

LINEARITY

LINEARITY

LINEARITY

–0.004

–0.006

–0.008

–0.010

24V 48V

SUPPLY VOLTAGE (AVDD)

55V

Figure 26. Integral Nonlinearity Current Mode, Internal R

SET

Sense Resistor

0.05

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

TUE

TUE

TUE

V

IN

(V)

Figure 27. Total Unadjusted Error vs. V

IN

, External R

SET

Resistor

0.05

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

TUE

TUE

TUE

V

IN

(V)

Figure 28. Total Unadjusted Error vs. V

IN

, Internal R

SET

Resistor

Rev. A | Page 15 of 32

AD5751

0.020

0.005

0.015

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

POSITIVE TUE

POSITIVE TUE

POSITIVE TUE

0.004

0.003

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

LINEARITY

LINEARITY

LINEARITY

0.010

0.005

0.002

0.001

0

0

–0.001

–0.005

–0.002

–0.003

–0.010

–0.015

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

NEGATIVE TUE

NEGATIVE TUE

NEGATIVE TUE

–0.020

24V 48V

SUPPLY VOLTAGE (AVDD)

55V

Figure 29. Total Unadjusted Error Current Mode, External R

SET

Sense Resistor

–0.004

–0.005

–40 25

TEMPERATURE (°C)

105

Figure 32. Integral Nonlinearity Error vs. Temperature,

External R

SET

Sense Resistor

0.010

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

NEGATIVE TUE

NEGATIVE TUE

0.10

0.005

0

–0.005

–0.010

0mA TO 24mA INTERNAL

R

SET

NEGATIVE TUE

4mA TO 20mA INTERNAL

R

SET

POSITIVE TUE

0.08

0.06

0.04

0.02

0

–0.02

4mA TO 20mA INTERNAL R

SET

POSITIVE TUE

0mA TO 20mA INTERNAL R

SET

POSITIVE TUE

0mA TO 24mA INTERNAL R

SET

POSITIVE TUE

4mA TO 20mA INTERNAL R

SET

NEGATIVE TUE

0mA TO 20mA INTERNAL R

SET

NEGATIVE TUE

0mA TO 24mA INTERNAL R

SET

NEGATIVE TUE

–0.015

–0.020

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

POSITIVE TUE

POSITIVE TUE

–0.025

24V 48V

SUPPLY VOLTAGE (AVDD)

55V

Figure 30. Total Unadjusted Error Current Mode, Internal R

SET

Sense Resistor

–0.04

–0.06

–0.08

–0.10

–40 25

TEMPERATURE (°C)

105

Figure 33. Total Unadjusted Error vs. Temperature, Internal R

SET

Sense Resistor

0.005

0.004

0.003

0.002

0.001

0

–0.001

–0.002

–0.003

–0.004

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

LINEARITY

LINEARITY

LINEARITY

–0.005

–40 25

TEMPERATURE (°C)

105

Figure 31. Integral Nonlinearity Error vs. Temperature,

Internal R

SET

Sense Resistor

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

4mA TO 20mA EXTERNAL R

SET

POSITIVE TUE

0mA TO 20mA EXTERNAL R

SET

POSITIVE TUE

0mA TO 24mA EXTERNAL R

SET

POSITIVE TUE

4mA TO 20mA EXTERNAL R

SET

NEGATIVE TUE

0mA TO 20mA EXTERNAL R

SET

NEGATIVE TUE

0mA TO 24mA EXTERNAL R

SET

NEGATIVE TUE

–40 25

TEMPERATURE (°C)

105

Figure 34. Total Unadjusted Error vs. Temperature, External R

SET

Sense Resistor

Rev. A | Page 16 of 32

50

45

40

35

30

25

20

15

10

5

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

0

–40 25

TEMPERATURE (°C)

105

Figure 35. Zero-Scale Error vs. Temperature, External R

SET

Sense Resistor

30

25

40

35

20

15

10

5

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

0

–40 25

TEMPERATURE (°C)

105

Figure 36. Zero-Scale Error vs. Temperature, Internal R

SET

Sense Resistor

3

2

1

0

–1

–2

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

–3

–40 25

TEMPERATURE (°C)

105

Figure 37. Offset Error vs. Temperature, Internal R

SET

Sense Resistor

AD5751

4

3

2

1

0

–1

–2

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

–3

–40 25

TEMPERATURE (°C)

105

Figure 38. Offset Error vs. Temperature, External R

SET

Sense Resistor

0.05

0.04

–0.01

–0.02

–0.03

–0.04

0.03

0.02

0.01

0

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

–0.05

–40 25

TEMPERATURE (°C)

105

Figure 39. Full-Scale Error vs. Temperature, External R

SET

Sense Resistor

0.10

0.08

–0.02

–0.04

–0.06

–0.08

0.06

0.04

0.02

0

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

–0.10

–40 25

TEMPERATURE (°C)

105

Figure 40. Full-Scale Error vs. Temperature, Internal R

SET

Sense Resistor

Rev. A | Page 17 of 32

AD5751

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

4mA TO 20mA EXTERNAL R

SET

0mA TO 20mA EXTERNAL R

SET

0mA TO 24mA EXTERNAL R

SET

–0.10

–40 25

TEMPERATURE (°C)

105

Figure 41. Gain Error vs. Temperature, External R

SET

Sense Resistor

12

10

8

6

4

2

0

–2

–10

I

OUT

0.000010

0.000008

0.000006

0.000004

0.000002

0

–0.000002

–0.000004

–0.000006

V

DD

–0.000008

–8 –6 –4 –2 0

TIME (ms)

2 4 6 8 10

–0.000010

Figure 44. Output Current vs. Time on V

DD

Power-Up

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

4mA TO 20mA INTERNAL R

SET

0mA TO 20mA INTERNAL R

SET

0mA TO 24mA INTERNAL R

SET

–0.10

–40 25

TEMPERATURE (°C)

105

Figure 42. Gain Error vs. Temperature, Internal R

SET

Sense Resistor

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–2 –1 0 1 2 3

TIME (µs)

4 5 6 7 8

Figure 45. Output Current vs. Time on Output Enable, 0 mA to 20 mA Range

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.75

1.70

AV

DD

COMPLIANCE VOLTAGE

1.65

–40 25

TEMPERATURE (°C)

105

Figure 43. Output Compliance vs. Temperature

Tested When I

OUT

= 10.8 mA, 0 mA to 24 mA Range Selected

0.025

0.020

0.015

0.010

0.005

0

–12 –6 1 8 14 21 28 34

TIME (µs)

41 48 54

Figure 46. 4 mA to 20 mA Output Current Step

61 68

Rev. A | Page 18 of 32

3000

2500

2000

1500

DV

CC

= 5V

1000

3.85

3.80

3.75

4.05

4.00

3.95

3.90

500

DV

CC

= 3V

0

0 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

LOGIC LEVEL (V)

Figure 47. DI

CC

vs. Logic Input Voltage

4.5

5.0

4.10

24 48

AV

DD

(V)

Figure 48. AI

DD vs. AV

DD

, V

OUT

= 0 V

55

3.95

3.90

3.85

3.80

3.75

4.10

4.05

4.00

24 48

AV

DD

(V)

Figure 49. AI

DD

vs. AV

DD

, I

OUT

= 0 mA

55

AD5751

Rev. A | Page 19 of 32

AD5751

TERMINOLOGY

Total Unadjusted Error (TUE)

TUE is a measure of the output error taking all the various errors into account: INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed as a percentage of full-scale range (% FSR).

Relative Accuracy or Integral Nonlinearity (INL)

INL is a measure of the maximum deviation, in % FSR, from a straight line passing through the endpoints of the output driver transfer function. A typical INL vs. input voltage plot is shown

in Figure 5.

Full-Scale Error

Full-scale error is the deviation of the actual full-scale analog output from the ideal full-scale output. Full-scale error is expressed as a percentage of full-scale range (% FSR).

Full-Scale TC

Full-scale TC is a measure of the change in the full-scale error with a change in temperature. It is expressed in ppm FSR/°C.

Gain Error

Gain error is a measure of the span error of the output. It is the deviation in slope of the output transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature is

shown in Figure 10.

Gain Error TC

Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm

FSR/°C.

Zero-Scale Error

Zero-scale error is the deviation of the actual zero-scale analog output from the ideal zero-scale output. Zero-scale error is expressed in millivolts (mV).

Zero-Scale TC

Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C.

Offset Error

Offset error is a measurement of the difference between the actual VOUT and the ideal VOUT expressed in millivolts (mV) in the linear region of the transfer function. It can be negative or positive.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a half-scale input change.

Slew Rate

The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/μs.

Current Loop Voltage Compliance

Current loop voltage compliance is the maximum voltage at the

IOUT pin for which the output current is equal to the programmed value.

Power-On Glitch Energy

Power-on glitch energy is the impulse injected into the analog output when the AD5751 is powered on. It is specified as the area of the glitch in nV-sec.

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output is affected by changes in the power supply voltage.

Rev. A | Page 20 of 32

THEORY OF OPERATION

The AD5751 is a single-channel, low cost, precision, voltage/ current output driver with hardware or software programmable output ranges. The software ranges are configured via an SPI-/

MICROWIRE-compatible serial interface. The hardware ranges are programmed using the range pins (R0 to R3). The analog input to the AD5751 is provided from a low voltage, single-supply

DAC (0 V to 4.096 V), which is internally conditioned to provide the desired output current/voltage range.

The output current range is programmable across three ranges:

0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA. The voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, and 0 V to 40 V output ranges.

An overrange of 20% is available on the 5 V and 10 V output voltage ranges, and of 10% on the 0 V to 40 V range. The VOUT and IOUT pins can be connected together. An overrange of 2% is available on the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to

20 mA current ranges. The current and voltage outputs are available on separate pins. Only one output can be enabled at

AD5751

one time. The output range is selected by programming the R3

to R0 bits in the control register (see Table 7 and Table 8).

Figure 50 and Figure 51 show a typical configuration of AD5751 in

software mode and in hardware mode, respectively, in an output module system. The HW SELECT pin chooses whether the part is configured in software or hardware mode. The analog input to the AD5751 is provided from a low voltage, single-supply DAC such as the AD506x or AD566x, which can provide an output range of 0 V to 4.096 V. The supply and reference for the DAC, as well as the reference for the AD5751, can be supplied from a reference such as the ADR392 . The AD5751 can operate with a single supply up to 55 V.

SOFTWARE MODE

In current mode, software-selectable output ranges include 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.

In voltage mode, software-selectable output ranges include 0 V to 5 V, 0 V to 10 V, 0 V to 40 V.

AVDD AGND

ADP1720

AVDD GND

MCU

ADR392

SCLK

SDI/DIN

VDD REFIN

SDO

AD506x

AD566x

SYNC1

AD5751

VREF

VIN

VOUT

RANGE

SCALE

VSENSE+

VOUT

0V TO 5V, 0V TO 10V,

0V TO 40V

IOUT

RANGE

SCALE

IOUT

0mA TO 20mA,

0mA TO 24mA,

4mA TO 20mA SCLK

SDIN

SDO

SYNC

SERIAL

INTERFACE

VOUT SHORT FAULT

IOUT OPEN FAULT

OVERTEMP FAULT

STATUS REGISTER

HW SELECT

FAULT

Figure 50. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)

Rev. A | Page 21 of 32

AD5751

AVDD AGND

MCU

ADP1720

ADR392

SCLK

VDD

SDI/DIN

SDO

SYNC1

REFIN

AD506x

AD566x

DVCC

AD5751

VREF

AVDD GND

VOUT

RANGE

SCALE

VIN

IOUT

RANGE

SCALE

HW SELECT

OUTEN

VSENSE+

TEMP VFAULT IFAULT

R3

R2

R1

R0

VOUT

0V TO 5V, 0V TO 10V,

0V TO 40V

IOUT

0mA TO 20mA,

0mA TO 24mA,

4mA TO 20mA

OUTPUT RANGE

SELECT PINS

Figure 51. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)

Table 6. Suggested Parts for Use with the AD5751

AD5660

AD5664R

AD5668

AD5060

AD5662

AD5064 / AD5066

Internal

Internal

Internal

ADR434

ADR434

ADR392

2

AD5664

ADR3922

1

ADP1720 input range up to 28 V.

2 ADR392 input range up to 15 V.

ADP1720

1

N/A

N/A

ADP1720

N/A

ADR3922

N/A

16-bit/12-bit

16-bit/12-bit

16-bit/12-bit

16-bit/16-bit

16-bit/16-bit

16-bit/12-bit

16-bit/12-bit

Mid end system, single channel, internal reference

Mid end system, quad channel, internal reference

Mid end system, octal channel, internal reference

High end system, single channel, external reference

High end system, quad channel, external reference

Mid end system, single channel, external reference

Mid end system, quad channel, external reference

Rev. A | Page 22 of 32

CURRRENT OUTPUT ARCHITECTURE

The voltage input from the analog input VIN core (0 V to 4.096 V)

is either converted to a current (see Figure 52), which is then

mirrored to the supply rail so that the application simply sees a current source output with respect to an internal reference voltage, or it is buffered and scaled to output a software-selectable

unipolar voltage range (see Figure 53). The reference is used to

provide internal offsets for range and gain scaling. The selectable output range is programmable through the digital interface

(software mode) or via the range pins (R0 to R3) (hardware mode).

AVDD

VIN

VREF

VIN

(0V TO 4.096V)

VREF

RANGE DECODE

FROM INTERFACE

VOUT RANGE

SCALING

Figure 52. Current Output Configuration

RANGE DECODE

FROM INTERFACE

VOUT RANGE

SCALING

A1

T1

R2

R1

A2

T2

R3

IOUT

VSENSE+

VOUT

VOUT SHORT FAULT

GND

Figure 53. Voltage Output

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads, connect a 0.01 μF capacitor between IOUT and GND. This ensures stability with loads beyond 50 mH. There is no maximum capacitance limit.

The capacitive component of the load may cause slower settling.

Voltage Output Amplifier

The voltage output amplifier is capable of driving a load of 1 kΩ

(for 0 V to 5 V and 0 V to 10 V ranges) and a load of 5 kΩ (for

0 V to 40 V range) and capacitive loads up to 2 μF (with an external compensation capacitor on the COMP1 and COMP2 pins). The source and sink capabilities of the output amplifier

can be seen in Figure 15. The slew rate is 2 V/μs.

Internal to the device, there is a 2.5 MΩ resistor connected between VOUT and VSENSE+. If a fault condition occurs, these resistors act to protect the AD5751 by ensuring that the amplifier loop is closed so that the part does not enter into an open-loop condition.

The current and voltage are output on separate pins and cannot be output simultaneously. This allows the user to tie both the current and voltage output pins together and configure the end system as a single-channel output.

Rev. A | Page 23 of 32

AD5751

Driving Large Capacitive Loads

The voltage output amplifier is capable of driving capacitive loads of up to 1 μF with the addition of a nonpolarized compensation capacitor between the COMP1 and COMP2 pins.

Without the compensation capacitor, up to 20 nF capacitive loads can be driven. Care should be taken to choose an appropriate value for the C

COMP

capacitor. This capacitor, while allowing the

AD5751 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and therefore affects the bandwidth of the system. Considered values of this capacitor should be in the range of 0 nF to 4 nF depending on the trade-off required between settling time, overshoot, and bandwidth.

POWER-ON STATE OF THE AD5751

On power-up, the AD5751 senses whether hardware or software mode is loaded and sets the power-up conditions accordingly.

In software SPI mode, the power-up state of the output is dependent on the state of the CLEAR pin. If the CLEAR pin is pulled high, the part powers up, driving an active 0 V on the output. If the CLEAR pin is pulled low, the part powers up with the voltage output channel in tristate mode. In both cases, the current output channel powers up in the tristate condition (0 mA). This allows the voltage and current outputs to be connected together if desired.

To put the part into normal operation, the user must set the

OUTEN bit in the control register to enable the output and, in the same write, set the output range configuration using the R3 to R0 range bits. If the CLEAR pin is still high (active) during this write, the part automatically clears to its normal clear state as defined by the programmed range and by the CLRSEL pin or

the CLRSEL bit (see the Asynchronous Clear (CLEAR) section

for more details). The CLEAR pin must be taken low to operate the part in normal mode.

The CLEAR pin is typically driven directly from a microcontroller.

In cases where the power supply for the AD5751 supply is independent of the microcontroller power supply, the user can connect a weak pull-up resistor to DVCC or a pull-down resistor to ground to ensure that the correct power-up condition is achieved independent of the microcontroller. A 10 kΩ pull-up/ pull-down resistor on the CLEAR pin should be sufficient for most applications.

If hardware mode is selected, the part powers up to the conditions defined by the R3 to R0 range bits and the status of the OUTEN or CLEAR pin. It is recommended to keep the output disabled when powering up the part in hardware mode.

AD5751

DEFAULT REGISTERS AT POWER-ON

The AD5751 power-on-reset circuit ensures that all registers are loaded with zero code.

In software SPI mode, the part powers up with all outputs disabled (OUTEN bit = 0). The user must set the OUTEN bit in the control register to enable the output and, in the same write, set the output range configuration using the R3 to R0 bits.

If hardware mode is selected, the part powers up to the conditions defined by the R3 to R0 bits and the status of the

OUTEN pin. It is recommended to keep the output disabled when powering up the part in hardware mode.

RESET FUNCTION

In software mode, the part can be reset using the RESET pin

(active low) or the reset bit (reset = 1). A reset disables both the current and voltage outputs to their power-on condition. The user must write to the OUTEN bit to enable the output and, in the same write, set the output range configuration. The RESET pin is a level sensitive input; the part stays in reset mode as long as the RESET pin is low. The reset bit clears to 0 following a reset command to the control register.

In hardware mode, there is no reset. If using the part in hardware mode, the RESET pin should be tied high.

OUTEN

disabled, both the current and voltage channels go into tristate.

The user must set the OUTEN bit to enable the output and simultaneously set the output range configuration.

In hardware mode, the output can be enabled or disabled using the OUTEN pin. When the output is disabled, both the current and voltage channels go into tristate. The user must write to the

OUTEN pin to enable the output. It is recommended that the output be disabled when changing the ranges.

SOFTWARE CONTROL

Software control is enabled by connecting the HW SELECT pin to ground. In software mode, the AD5751 is controlled over a versatile 3-wire serial interface that operates at clock rates up to

50 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and

DSP standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the device MSB first as a 16-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK.

The input shift register consists of 16 control bits, as shown in

Table 7. The timing diagram for this write operation is shown in

Figure 2. The first three bits of the input shift register are used to set

the hardware address of the AD5751 device on the printed circuit board (PCB). Up to eight devices can be addressed per board.

Bit D11, Bit D1, and Bit D0 must always be set to 0 during any write sequence.

In software mode, the output can be enabled or disabled using the OUTEN bit in the control register. When the output is

Table 7. Input Shift Register Contents for a Write Operation—Control Register

MSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6

A2 A1 A0 R/W

D5 D4 D3 D2

LSB

D1 D0

0 R3 R2 R1 R0 CLRSEL OUTEN Clear RSET Reset 0 0

Table 8. Input Shift Register Descriptions for Control Register

Bit Description

A2, A1, A0 Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system controller.

R/W

0

0

0

0

1

0

0

1

1

0

0

1

0

1

0

Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0.

Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1.

Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0.

Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1.

Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0.

1

1

1

0

1

1

1

0

1

Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1.

Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0.

Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1.

Indicates a read from or a write to the addressed register.

Rev. A | Page 24 of 32

Bit Description

R3, R2, R1, R0 Selects the output configuration in conjunction with RSET.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0

1

0

1

0

4 mA to 20 mA (external 15 kΩ current sense resistor).

0 mA to 20 mA (external 15 kΩ current sense resistor).

0 mA to 24 mA (external 15 kΩ current sense resistor).

Unused command. Do not program.

Unused command. Do not program.

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0 V to 5 V.

0 V to 10 V.

Unused command. Do not program.

Unused command. Do not program.

0 V to 6.0 V (20% overrange).

0 V to 12.0 V (20% overrange).

Unused command. Do not program.

Unused command. Do not program.

1

1

1

1

0

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

Unused command. Do not program.

0 V to 40 V.

0 V to 44 V.

4 mA to 20 mA (internal current sense resistor).

0 mA to 20 mA (internal current sense resistor).

0 mA to 24 mA (internal current sense resistor).

Unused command. Do not program.

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Unused command. Do not program.

0 V to 5 V.

0 V to 10 V.

Unused command. Do not program.

Unused command. Do not program.

0 V to 6.0 V (20% overrange).

0 V to 12.0 V (20% overrange).

Unused command. Do not program.

1

1

1

1

1

1

1

1

1

0

0

1

0

1

0

Unused command. Do not program.

3.92 mA to 20.4 mA (internal current sense resistor).

0 mA to 20.4 mA (internal current sense resistor).

CLRSEL

1 1 1 1 1 0 mA to 24.5 mA (internal current sense resistor).

Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section.

CLRSEL Function

0 Clear to 0 V.

1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode.

OUTEN

Clear

RSET

Reset

Output enable bit. This bit must be set to 1 to enable the outputs.

Software clear bit; active high.

Select internal/external current sense resistor.

RSET Function

1 Select internal current sense resistor; used with R3 to R0 bits to select range.

0 Select external current sense resistor; used with R3 to R0 bits to select range.

Resets the part to its power-on state.

AD5751

Rev. A | Page 25 of 32

AD5751

Readback Operation

Readback mode is activated by selecting the correct device address

(A2, A1, A0) and then setting the R/W bit to 1. By default, the

SDO pin is disabled. After having addressed the AD5751 for a read operation, setting R/W to 1 enables the SDO pin and SDO data is clocked out on the 5 th

rising edge of SCLK. After the data has been clocked out on SDO, a rising edge on SYNC disables

(tristate) the SDO pin again. Status register data (see Table 9

) and control register data are both available during the same read cycle.

The status bits comprise four read-only bits. They are used to notify the user of specific fault conditions that occur, such as an open circuit or short circuit on the output, overtemperature error, or an interface error. If any of these fault conditions occur, a hardware FAULT is also asserted low, which can be used as a hardware interrupt to the controller.

See the Detailed Description of Features section for a full

explanation of fault conditions.

HARDWARE CONTROL

Hardware control is enabled by connecting the HW SELECT pin to DVCC. In this mode, the R3, R2, R1, and R0 pins, in conjunction with the RSET pin, are used to configure the

output range, as per Table 8.

In hardware mode, there is no status register. The fault conditions (open circuit, short circuit, and overtemperature) are available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any one of these fault conditions is set, a low is asserted on the specific fault pin. IFAULT, VFAULT, and TEMP are open-drain outputs and, therefore, can be connected together to allow the user to generate one interrupt to the system controller to communicate a fault. If hardwired in this way, it is not possible to isolate which fault occurred in the system.

TRANSFER FUNCTION

The AD5751 consists of an internal signal conditioning block that maps the analog input voltage to a programmed output range. The available analog input range is 0 V to 4.096 V.

For all ranges, both current and voltage, the AD5751 implements a straight linear mapping function, where 0 V maps to the lower end of the selected range and 4.096 V maps to the upper end of the selected range.

Table 9. Input Shift Register Contents for a Read Operation—Status Register

MSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

LSB

D0

OUTEN PEC error OVER TEMP IOUT fault VOUT fault

Table 10. Status Bit Options

Bit Description

PEC Error

This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.

OVER TEMP This bit is set if the AD5751 core temperature exceeds approximately 150°C.

IOUT Fault This bit is set if there is an open circuit on the IOUT pin.

VOUT Fault This bit is set if there is a short circuit on the VOUT pin.

Rev. A | Page 26 of 32

DETAILED DESCRIPTION OF FEATURES

OUTPUT FAULT ALERT—SOFTWARE MODE

In software mode, the AD5751 is equipped with one FAULT pin; this is an open-drain output allowing several AD5751 devices to be connected together to one pull-up resistor for global fault detection. In software mode, the FAULT pin is forced active low by any one of the following fault scenarios:

• The voltage at IOUT attempts to rise above the compliance range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability.

Thus, the fault output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active.

• A short is detected on the voltage output pin (VOUT). The short-circuit current is limited to 15 mA.

• An interface error is detected due to the packet error

checking failure (PEC). See the Packet Error Checking

section.

• The core temperature of the AD5751 exceeds approximately 150°C.

OUTPUT FAULT ALERT—HARDWARE MODE

In hardware mode, the AD5751 is equipped with three fault pins:

VFAULT, IFAULT, and TEMP. These are open-drain outputs allowing several AD5751 devices to be connected together to one pull-up resistor for global fault detection. In hardware control mode, these fault pins are forced active by any one of the following fault scenarios:

• An open-circuit is detected. The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active.

Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the fault output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its openloop gain, and an output error does not occur before the fault output becomes active. If this fault is detected, the

IFAULT pin is forced low.

Rev. A | Page 27 of 32

AD5751

• A short is detected on the voltage output pin. The shortcircuit current is limited to 15 mA. If this fault is detected, the VFAULT pin is forced low.

• The core temperature of the AD5751 exceeds approximately 150°C. If this fault is detected, the TEMP pin is forced low.

VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION

Under normal operation the voltage output sinks and sources up to 12 mA and maintains specified operation. The maximum current that the voltage output delivers is 15 mA; this is the short-circuit current.

ASYNCHRONOUS CLEAR (CLEAR)

CLEAR is an active high clear that allows the voltage output to be cleared to either zero-scale code or midscale code, and is user-selectable via the CLRSEL pin or the CLRSEL bit of the

input shift register, as described in Table 8. (The clear select

feature is a logical OR function of the CLRSEL pin and the

CLRSEL bit). The current loop output clears to the bottom of its programmed range. When the CLEAR signal is returned low, the output returns to its programmed value or to a new programmed value. A clear operation can also be performed via the clear command in the control register.

Table 11. CLRSEL Options

Output Clear Value

CLRSEL

0

1

Unipolar Output

Voltage Range

0 V

Midscale

Unipolar Current Output Range

Zero-scale; for example:

4 mA on the 4 mA to 20 mA range

0 mA on the 0 mA to 20 mA

Midscale; for example:

12 mA on the 4 mA to 20 mA range

10 mA on the 0 mA to 20 mA range

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 1, R

SET

is an internal sense resistor and is part of the voltage-to-current conversion circuitry. The nominal value of the internal current sense resistor is 15 kΩ. To allow for overrange capability in current mode, the user can also select the internal current sense resistor to be 14.7 kΩ, giving a nominal

2% overrange capability. This feature is available in the 0 mA to

20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current ranges.

The stability of the output current value over temperature is dependent on the stability of the value of R

SET

. As a method of improving the stability of the output current over temperature, an external low drift resistor can be connected to the REXT1 and REXT2 pins of the AD5751, which can be used instead of the internal resistor. The external resistor is selected via the input shift register. If the external resistor option is not used, the

REXT1 and REXT2 pins should be left floating.

AD5751

PROGRAMMABLE OVERRANGE MODES

The AD5751 contains an overrange mode for most of the available ranges. The overranges are selected by configuring the

R3, R1, R1, and R0 bits (or pins) accordingly.

In voltage mode, depending on selected range, the overranges are 10% or 20%, providing programmable output ranges of 0 V to 6 V, 0 V to 12 V, and 0 V to 44 V. The 0 V to 4.096 V analog input remains the same.

In current mode, the overranges are typically 2%. In current mode, the overrange capability is only available on three ranges,

0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these ranges, the analog input also remains the same (0 V to 4.096 V).

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environments, the AD5751 offers the option of error checking based on an 8-bit (CRC-8) cyclic redundancy check. The device controlling the AD5751 should generate an 8-bit frame check sequence using the following polynomial:

C(x) = x

8

+ x

2

+ x

1

+ 1

This is added to the end of the data-word, and 24 data bits are sent to the AD5751 before taking SYNC high. If the AD5751 receives a 24-bit data frame, it performs the error check when

SYNC goes high. If the check is valid, then the data is written to the selected register. If the error check fails, the FAULT pin goes low and Bit D3 of the status register is set. After reading this register, this error flag is cleared automatically and the FAULT pin goes high again.

UPDATE ON SYNC HIGH

SYNC

SCLK

SDIN

D15

(MSB)

D0

(LSB)

16-BIT DATA

16-BIT DATA TRANSER—NO ERROR CHECKING

SYNC

UPDATE AFTER SYNC HIGH

ONLY IF ERROR CHECK PASSED

SCLK

D23

(MSB)

SDIN

16-BIT DATA

D8

(LSB) D7

8-BIT FCS

D0

FAULT

FAULT GOES LOW IF

ERROR CHECK FAILS

16-BIT DATA TRANSER WITH ERROR CHECKING

Figure 54. PEC Error Checking Timing

Rev. A | Page 28 of 32

APPLICATIONS INFORMATION

TRANSIENT VOLTAGE PROTECTION

The AD5751 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5751 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be

required, as shown in Figure 55. The constraint on the resistor

value is that during normal operation the output level at IOUT must remain within its voltage compliance limit of AV

DD

2.75 V and the two protection diodes and resistor must have appropriate power ratings. Further protection can be added with transient voltage suppressors if needed.

AV

DD

AD5751

THERMAL CONSIDERATIONS

It is important to understand the effects of power dissipation on the package and how it affects junction temperature. The internal junction temperature should not exceed 125°C. The

AD5751 is packaged in a 32-lead, 5 mm × 5 mm LFCSP package. The thermal impedance, θ

JA

, is 28°C/W. It is important that the devices not be operated under conditions that cause the junction temperature to exceed its limit. Worst-case conditions occur when the AD5751 are operated from the maximum AV

DD

(55 V) and driving the maximum current (24 mA) directly to ground. The quiescent current of the AD5751 should also be taken into account, nominally ~4 mA. The following calculations estimate maximum power dissipation under these worst-case conditions, and determine maximum ambient temperature based on this. These figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as

outlined in the Layout Guidelines section.

AV

DD

AD5751

I

OUT

R

P

R

LOAD

Figure 55. Output Transient Voltage Protection

Table 12. Thermal and Supply Considerations

Maximum allowed power dissipation when operating at an ambient temperature of 85°C

Maximum allowed ambient temperature when operating from a supply of

55 V and driving 24 mA directly to ground (include 4 mA for internal AD5751 current)

Maximum allowed supply voltage when operating at an ambient temperature of 85°C and driving 24 mA directly to ground

T

JMAX

T

A

θ

JA

=

125

85

28

=

1 .

42 W

T

JMAX

− (P

D

× θ

JA

) = 125 − ((55 × 0.028) × 28) = 81.8°C

T

JMAX

AI

DD

×

T

A

θ

JA

=

125

(

0 .

028

×

85

28

)

=

51 V

Rev. A | Page 29 of 32

AD5751

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5751 is mounted should be designed so that the AD5751 lies on the analog plane.

The AD5751 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The

10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily.

AD5751

corresponding thermal land paddle on the PCB (GND).

Thermal vias should be designed into the PCB land paddle area to further improve heat dissipation.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The

iCoupler® family of products from Analog Devices, Inc., provides voltage isolation in excess of 5.0 kV. The serial loading structure of the AD5751 makes it ideal for isolated interfaces because the

number of interface lines is kept to a minimum. Figure 57 shows a

4-channel isolated interface to the AD5751 using an ADuM1400 .

For further information, visit http://www.analog.com/icouplers .

CONTROLLER

SERIAL

CLOCK OUT

SERIAL

DATA OUT

ADuM1400 1

V

IA

ENCODE

V

IB

ENCODE

DECODE

DECODE

V

OA

V

OB

TO

SCLK

TO

SDIN

V

OC

SYNC OUT

V

IC

ENCODE DECODE

TO

SYNC

CONTROL OUT

V

ID

ENCODE DECODE

V

OD TO

CLEAR

GND

PLANE

BOARD

Figure 56. Paddle Connection to Board

The AD5751 has an exposed paddle beneath the device.

Connect this paddle to the GND of the AD5751. For optimum performance, special considerations should be used to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package should be soldered to the

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 57. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5751 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a SYNC signal. The AD5751 requires a 16-bit data-word with data valid on the falling edge of SCLK.

Rev. A | Page 30 of 32

OUTLINE DIMENSIONS

ORDERING GUIDE

Model

1

AD5751ACPZ

AD5751ACPZ-REEL7

AD5751BCPZ

AD5751BCPZ-REEL7

1 Z = RoHS Compliant Part.

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING

PLANE

5.00

BSC SQ

0.60 MAX

0.60 MAX

PIN 1

INDICATOR

TOP

VIEW

4.75

BSC SQ

0.50

BSC

25

24

EXPOSED

PAD

(BOTTOM VIEW)

32

1

3.25

3.10 SQ

2.95

0.50

0.40

0.30

17

16 9

8

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

0.30

0.23

0.18

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

Temperature Range

−40°C to +105°C

−40°C to +105°C

−40°C to +105°C

−40°C to +105°C

Package Description

32-Lead LFCSP_VQ

32-Lead LFCSP_VQ

32-Lead LFCSP_VQ

32-Lead LFCSP_VQ

Package Option

CP-32-2

CP-32-2

CP-32-2

CP-32-2

AD5751

Rev. A | Page 31 of 32

AD5751

NOTES

©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D07269-0-5/10(A)

Rev. A | Page 32 of 32

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project