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ADS64XX EVM User's Guide
User's Guide
April 2007
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Contents
1
2
3
4
Overview
1.1
ADS64XX EVM Quick-Start Procedure
.......................................................................
Circuit Description
2.1
2.2
..............................................................................................
ADC Circuit Function
............................................................................................
2.3
Deserialization and the TSW1200
.............................................................................
ADC Evaluation
3.1
3.2
............................................................................................
Coherent Input Frequency Selection
.........................................................................
Physical Description
..................................................................................................
4.1
4.2
PCB Layout
..................................................................................................
4.3
PCB Schematics
................................................................................................
Important Notices
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Table of Contents
3
1
2
3
8
9
10
11
12
13
14
5
6
3
4
7
1
2
List of Figures
Layer 1, Top Silkscreen
...................................................................................................
Layer 4, Power Plane
Layer 5, Bottom Side
Sheet 1 of 5
...............................................................................................
Sheet 2 of 5
Sheet 3 of 5
Sheet 4 of 5
Sheet 5 of 5
List of Tables
Surface Mount Jumpers
...........................................................................................
4
List of Figures
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User's Guide
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1 Overview
This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6445, ADS6444, ADS6443, ADS6425, ADS6424, and ADS6423, which collectively are referred to as ADS64XX. The ADS64XX EVM provides a platform for evaluating the quad-channel
ADS64XX 14- and 12-bit analog-to-digital converters (ADC) under various signal, reference, and supply conditions. In certain instances, the user's guide may offer directions for only the 14-bit ADC family, which is referred to as the ADS644X, or only the 12-bit ADC family, which is referred to as the ADS642X. In addition, this user's guide explains the procedure for hooking up the ADS64XX EVM to TI's high-speed
LVDS deserializer, the TSW1200.
This document should be used in combination with the respective ADC datasheet.
1.1
ADS64XX EVM Quick-Start Procedure
Using the quick-start procedure, many users can begin evaluating the ADC in a minimal amount of time.
The quick-start procedure includes details on how to set up the ADS64XX EVM used in conjunction with
TI's high-speed LVDS deserializer. A complete listing of all EVM features follows in
. The quick-start instructions are delineated as ADS64XX, which refers to instructions pertaining to the ADC
EVM; or TSW1200, which refers to instructions pertaining to the high-speed LVDS deserializer.
1. ADS64XX: Verify all jumper settings against the schematic jumper list in
:
Table 1. Three-Pin Jumper List
JUMPER FUNCTION ADS644X DEFAULT ADS642X DEFAULT
J16 Sets ADC coarse gain mode and ADC reference mode. Use 0-dB gain, internal silkscreen for configuration.
references
0-dB gain, internal references
J17
(1)
Sets ADC output mode to either 1-wire, 2-wire, SDR, or DDR.
DDR, 2-wire
Use silkscreen for configuration.
DDR, 2-wire
J18 Sets ADC output serialization to either 14X or 16X and sets data formatting to rising edge or falling edge when the ADC is used in SDR mode. Use silkscreen for configuration.
16X, rising edge 14X, rising edge
(2)
J19
(1)
This is an ADC reserved pin and should always be set to
divide by 1.
Divide by 1 Divide by 1
J20
(1)
Selects the data output format as MSB- or LSB-first and
2s-complement or offset-binary.
MSB-first, 2s-complement MSB-first, 2s-complement
(1)
(2)
The high-speed LVDS deserializer requires data in a certain output format. Changing these to values other than the default would require a recompilation of the FPGA source code with the appropriate format decoding options and an update to the
FPGA PROM with the compiled file. Changing the default values without loading in a new FPGA design results in improper operation. By default, the PROM stores two FPGA files, one for 12-bit ADCs and one for 14-bit ADCs.
The silkscreen on the EVM only refers to the modes of the ADS644X. When an ADS642X, or 12-bit ADC, is being evaluated, the silkscreen 14X refers to the 12X serialization mode and the silkscreen 16X refers to the 14X serialization mode.
2. ADS64XX: Connect 3.3-V dc supplies to P1 and P3, with the returns to P2 and P4, respectively. The grounds can be shorted together.
3. TSW1200: Connect 5 V dc to J15 and the return to J14.
4. TSW1200: If evaluating the 12-bit ADC, or ADS642X, verify that jumper J11 is set to short pins 1–2, which configures the FPGA for deserialization of a 12-bit ADC serial data stream. On J11, short pins
2–3 for evaluating an ADS644X EVM.
5. Connect the two boards together by connecting J9 on the TSW1200 circuit board to J15 of the
Samtec is a trademark of Samtec, Inc.
Xilinx is a trademark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
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Overview
ADS64XX EVM.
6. ADS64XX and TSW1200: Switch power supplies on.
7. ADS64XX: Using a low-phase-noise, filtered frequency generator with 50-
Ω source output impedance, generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be within the specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as a clock source.
8. TSW1200: Depress SW4 (FPGA reset). This resets the logic inside the FPGA and must be done every time one changes the ADC clock frequency.
9. ADS64XX: Using a low-phase-noise, filtered frequency generator with a 50-
Ω source output impedance, generate a 10-MHz, 0-V offset, –1-dBFS-amplitude sine-wave signal into either J10 (input channel A) or J11 (input channel B). This provides a transformer-coupled differential input signal to the
ADC. TI uses an Agilent 8644B with an LC filter as a signal source.
10. TSW1200: The deserialized parallel output data can be probed using a logic analyzer on J5 for inputs to ADC channel A and on J4 for inputs to ADC channel B. On both output headers, the clock can be found on the respective output header on pin 2, and the LSB can be found on pin 6.
Note:
Any time the clock frequency of the ADC changes during the ADC evaluation, one must reset the FPGA deserializer by depressing SW4. This allows the deserializer to re-align the ADC data capture to the new output clock frequency.
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Circuit Description
2 Circuit Description
2.1
Schematic Diagram
The schematic diagram for the EVM is in
.
2.2
ADC Circuit Function
The following sections describe the function of individual circuits. Refer to the relevant data sheet for device operating characteristics.
2.2.1
ADC Operational Mode
By default, the ADC is configured to operate in parallel-mode operation, because the surface-mount jumper asserts a 3.3-V state to the ADC reset pin. Consequenty, the SW1 reset pushbutton must be pressed only when the device is configured into serial operational mode. Because the ADC is in parallel operation mode, voltages are used to set the ADC modes. Users can use the EVM silkscreen to set the operation modes.
2.2.2
ADC Power
Power is supplied to the EVM via banana jack sockets. Separate connections are provided for a 3.3-V digital buffer supply (P1) and 3.3-V analog supply (P3). In most cases, these can be shorted together for
ADC evaluation. When using the amplifier evaluation path, users must connect the positive rail to J21 and the negative rail to J22. The voltages depend on the coupling method and connection to the ADC. If the
ADC VCM is not supplied to the amplifier and the amplifier is connected to the ADC in a dc-coupled fashion, users should set J21 to 4 V and J22 to –1 V. In ac-coupled configurations where the ADC VCM biases the ADC inputs, users can connect J21 to 5 V and J22 to GND.
2.2.3
ADC Analog Inputs
The EVM is configured to accept a single-ended input souce and convert it to an ac-coupled differential signal using a transformer. The inputs to the ADC must be dc-biased, which is accomplished by using the
ADC VCM output. The inputs are provided via SMA connectors J10 for ADC channel A, J11 for ADC channel B, J13 for ADC channel C, and J14 for ADC channel D. ADC input channel C also includes the option for ADC evaluation using an amplifier signal chain.
TI has tested this ADC with a variety of transformer brands, transorfmer configurations and terminations.
For many applications, a single low-cost transformer can be used in the input signal chain to a very high degree of performance. Customers should select a transformer configuration based on their ADC input bandwidth frequency. To assist in this process, TI has swept the analog input frequency and plotted the resulting ADC SFDR performance with various transformers.
and
show the ADC performance using the Mini-Circuits TC1-1T, Mini-Circuits TC4-1W, and Coilcraft WBC1-1TLB in one- and two-tranformer configurations, respectively. In both plots, the results were taken on an ADS6443, sampling at 80 MSPS and on the same input channel. The termination was changed according to the impedance ratio of the transfomer used.
Using SMA input J2, users can evaluate the ADC using a THS4509 amplifier, which converts a single-ended input into a differential signal while providing 10 dB of signal gain. Users should enable the amplifier path by connecting JP6 1–2 and by shorting positions 1–2 on both surface-mount jumpers JP1 and JP2. At low input frequencies, the ADC represents a high input impedance and R10, R19, and C45 form a low-pass filter with a 3-db cutoff frequency of 70 MHz. Users should change these component values depending on the bandwidth of the signal they are digitizing to band-limit the input noise into the
ADC. Using an excessively high cutoff frequency degrades the SNR of the system. Before users begin evaluation of the amplifier path, one most choose whether to dc-couple or ac-couple to the amplifier path.
In a dc-coupled system, users should replace C46 and C47 with 0-
Ω resistors and remove R9 and R18.
The ADC VCM should be used to set the CM input of the amplifier by making sure R84 is populated with a
0-
Ω resistor. Because the ADC has a common-mode voltage of 1.5 V, and because the THS4509 is not a rail-to-rail amplifier, users should adjust VCC to 4 V and –VCC to –1 V, which can be done by applying the respective voltages to J21 and J22.
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Circuit Description
For an ac-coupled system, users should use the voltage divider R9 and R18 to set the common-mode input of the amplifier, which should be set to the midpoint of the amplifier supply. C46 and C47 ac-couple the system, and the ADC inputs can then be biased by the R14 and R15 combination. Another ac-coupled approach, not supported on this EVM, would be to use a transformer at the outputs of the THS4509. In this case, the transformer would provide for ac-coupling, and one could bias the inputs of the ADC by feeding the ADC VCM to the transformer center tap on the secondary.
It should be noted that the THS4509 used on this EVM is pinout-compatible with the THS4508, THS4511,
THS4513, and THS4520. Users can easily interchange the amplifier on this EVM and should pick the appropriate amplifier based on commmon mode range, power supplies, and frequency of operation. TI application engineers can assist in the best selection of these amplifiers based on the user requirements.
SFDR vs Frequency Using a Single Transformer
100
95
90
85
80
75
70
65
60
55
50
45
9.97
30.13
50.13
69.59
Mini Circuits
TC1−1T
Coilcraft
WBC1−1TLB
89.75
130.13
230.53
f − Frequency − MHz
Mini Circuits
TC4−1W
301.13
401.13
501.13
G001
Figure 1.
SFDR vs Frequency Using a Dual Transformer
8
100
95
90
85
80
75
70
65
60
55
50
45
9.97
30.13
50.13
69.59
Mini Circuits
TC4−1W
Coilcraft
WBC1−1TLB
Mini Circuits
TC1−1T
89.75
130.13
f − Frequency − MHz
230.53
301.13
401.13
501.13
G002
Figure 2.
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Circuit Description
2.2.4
ADC Clock Input
Users should connect a filtered, low-phase-noise clock input to J12. A transformer, T5, provides the conversion from a single-ended clock signal into a differential clock signal. When selecting the clock signal level, users should account for the transformer having an impedance ratio of 4, with a voltage step-up of 2.
2.2.5
ADC Digital Outputs
The ADS64XX ADC outputs serialized data, a bit clock (DCLK), and a frame clock (FCLK). These signals are brought to a high-density Samtec™ connector, J15. Users have three options in processing the ADC data.
1. Customers can use the mating logic analyzer breakout board and capture the ADC data using a logic analyzer. Users would be required to perform a software deserialization of the digital data before conducting analysis. Contact the factory for a breakout board for your logic analyzer.
2. Customers can create their own digital interface card which directly interfaces to the ADC. In this case, customers would design their mating digital interface board with the Samtec part number
QSH-060-01-F-D-A, which is the companion part number to the EVM connector.
3. In most cases, customers can use a hardware deserialization solution such as the TSW1200. The
TSW1200 features a powerful Xilinx™ Virtex 4 that comes preloaded with both 12-bit and 14-bit deserialization routines. In addition, customers can use the FPGA to develop their own deserializer and digital prototypes. The digital output of the TSW1200 easily plugs into logic analyzers or TI's own digital capture and analysis solution, the TSW1100.
2.2.6
Surface-Mount Jumper Selections
The EVM features surface-mount jumpers in cases where either the signal integrity is important or the functions are not often used.
summarizes these options.
ADC
Signal
Reference Designator
RESET J7
Table 2. Surface Mount Jumpers
Default Selection
2–3, parallel mode operation
Optional Selection
SCLK
SEN
PD
INC_P
J6
SDATA J8
J5
J9
INC_M JP1
JP2
Not populated, pin tied low
Not populated, pin tied low
2–3: EVM J16 controls parallel operation modes
Not populated, pin tied low, device operational
2–3, Transformer-coupled analog input to channel C
2–3, Transformer-coupled analog input to channel C
1–2, serial mode operation
1–2, TSW1200 control over SCLK
1–2, TSW1200 control over SDATA
1–2, TSW1200 control over SEN
1–2, TSW1200 control over PD
1–2, Amplifier-coupled path to channel C
1–2, Amplifier-coupled path to channel C
2.3
Deserialization and the TSW1200
While the specifics of the deserializer are out of the scope of this user's guide, TI has partnered up with
Xilinx to deliver an open-source deserializer solution with application note documentation. When designing the deserializer, users should consult Xilinx application note XAPP866, hosted on the Xilinx website. In addition, TI has provided a guide to understanding the different digital output modes of the ADC and how to pick the most appropriate digital output mode for deserialization. Users should consult Demystifying the
Digital Output Choices of the ADS6XXX, TI application note SLAA348 .
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ADC Evaluation
3 ADC Evaluation
This chapter describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for datasheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This chapter covers signal tone analysis, which yields ADC datasheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR).
3.1
Hardware Selection
To reveal the true performance of the ADC under evaluation, tremendous care should be taken in selecting both the ADC signal source and ADC clocking source. The hardware setup that TI uses for its analysis is shown graphically in
3.1.1
Analog Input Signal Generator
When choosing the quality of the ADC analog input source, one should consider both harmonic distortion performance of the signal generator and the noise performance of the source.
In many cases, the harmonic distortion performance of the signal generator is inferior to that of the ADC, and additional filtering is needed if users expect to reproduce the ADC SFDR numbers found in the data sheet. Users can easily evaluate the harmonic distortion of their signal generator by hooking it directly to a spectrum analyzer and measuring the power of the output signal and comparing that to the power of the integer multiples of the output signal's frequency. If the harmonic distortion is worse then the ADC under evaluation, the ADC digitizes the performance of the signal generator and the ADC's true SFDR is masked. To alleviate this, it is recommended that users provide additional LC filtering after the signal generator output.
Another important metric when deciding on a signal generator is its noise performance. As with the distortion performance, if the noise performance is worse than that of the ADC under evaluation, the ADC digitizes the performance of the source. Noise can be broken into two components, broadband noise and close-in phase noise. Broadband noise can be improved by the LC filter added to improve distortion performance; however, the close-in phase noise typically cannot be improved by additional filtering.
Therefore, when selecting an analog signal source it is extremely important to review the manufacturer's phase noise plots, and great care should be taken to choose a signal generator with the best phase-noise performance.
3.1.2
Clock Signal Generator
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.
Most modern ADCs, the ADS64XX included, accept either a sinusoidal or a square-wave clock input. The key metric in selecting a clocking source is selecting a source with the lowest jitter. This becomes increasingly important as the ADC's input frequency (Fin) increases, because the ADC SNR evaluation setups can become jitter-limited (Tj) as shown by the following equation.
SNR (dBc) = 20 log (2
π ×
Fin
×
Tj(rms))
In theory, a square-wave source with femtosecond jitter would be ideal for an ADC evaluation setup.
However, in practical terms, most commercially available square-wave generators offer jitter measured in picoseconds, which is too great for high-resolution ADC evaluation setups. Therefore, most evaluation setups rely on the ADC's internal clock buffer to convert a sinusoidal input signal into a ultralow-jitter square wave. When selecting a sinusoidal clocking source, it has been shown that phase noise has a direct impact on jitter performance. Consequently, great scrutiny should be applied to the phase-noise performance of the clocking signal generator. TI has found that high-Q monolithic crystal filters can improve the phase noise of the signal generator, and they become essential elements of the evaluation setup when high ADC input frequencies are being evaluated.
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ADC Evaluation
3.2
Coherent Input Frequency Selection
Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is not practical when looking at a finite set of ADC samples, usually collected from a logic analyzer. Consequently, users typically apply a window function to minimize the time-domain discontinuities that arise when analyzing a finite set of samples. For ADC analysis, window functions have their own frequency signatures or lobes that distort both SNR and SFDR measurements fo the ADC.
TI uses the concept of coherent sampling to work around the use of a window function. The central premise of coherent sampling entails that the input signal into the ADC is carefully chosen such that when a continuous-time signal is reconstructed from a finite sample set; no time-domain discontinuities exist. To achieve this, the input frequency must be an integer multiple of the ratio of the ADC's sample rate (f s
) and the number of samples collected from the logic analyzer (N s the fundamental frequency (f f
). The ratio of f s to N s is typically referred to as
). Determining the ADC input frequency is a two-step process. First, the users select the frequency of interest for evaluating the ADC; then they divide this by the fundamental frequency. This typically yields a non-integer value, which should be rounded to the nearest odd, preferably prime, integer. Once that integer, or frequency bin (f bin
), has been determined, users multiply this with the fundamental frequency to obtain a coherent frequency to program into their ADC input signal generator. The procedure is summarized as follows.
f f
= f s
/N s f bin
= Odd_round(f desired
/f f
)
Coherent frequency = f f
× f bin
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ADC Evaluation
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Figure 3. ADS64XX EVM Setup
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Physical Description
4 Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM.
4.1
PCB Layout
The EVM comprises six layers and is 62 mils thick. The EVM features a split ground plane, which can be shorted together under the ADC by using the two exposed gold-plated strips seen in
to make a low-impedance connection between ground planes. By default, the ground planes are not connected together and should be connected at the power supply. Although this board uses separate ground planes between analog and digital supplies, it should be noted that TI has conducted experiments with both single and split ground planes and found the performance to be identical. The ADC features a constant-current LVDS output, which minimizes the coupling of digital output switching noise back to the analog inputs.
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Figure 4. Layer 1, Top Silkscreen
K001
13
Physical Description
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Figure 5. Layer 2, Top Side
K002
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Physical Description
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Figure 6. Layer 3, Gound Plane
K003
15
Physical Description
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Figure 7. Layer 4, Power Plane
K004
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Physical Description
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Figure 8. Layer 5, Bottom Side
K005
17
Physical Description
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Figure 9. Layer 6, Bottom Silkscreen
K006
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Physical Description
4.2
Bill of Materials
is the bill of materials for the ADS64XXEVM.
Reference
C1, C5, C8, C10
C2, C9
C3, C6
C4, C7, C12, C13, C14, C15,
C16, C17, C18, C19, C20,
C21, C22, C23, C24, C25,
C26, C27, C28, C29, C30,
C31, C32, C33
C11
C34, C37, C40, C42, C56,
C57
C35, C36, C38, C39, C41,
C43, C46, C47 C48, C53,
C55
C44
C45
C52, C54
D1, D2
J2, J10, J11, J12, J13, J14
Quantity
Not
Installed
4
2
2
22
µ
F
10
µ
F
1
µ
F
24
1
6
11
1
1
2
2
6
0.1
µ
F
2000 pF
10
0.1
µ
0.22
µ
F
18 pF
33
µ
F
SMA
F
µ
Green
F
J5, J7 2
Table 3. ADS64XXEVM Bill of Materials
Part
SMD3P_BRIDGE
Part Number
ECS-T1CC226R
ECS-H1CC106R
ECJ-1VB1A105K
GRM188R71H104KA93D Murata
GRM1885C1H202JA01D Murata
ECJ-2FB1A106K
ECJ-1VB1C104K
ECJ-1VB1A224K
ECJ-1VC1H180J
TPSB336K016R0350
LNJ312G8TRA
142-0701-201
Manufacturer
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
EPCOS Inc.
Panasonic
Johnson Components
Short pins 2 and 3 using 0
Ω
Leave as is J6, J8, J9
J15
J16, J17, J18, J19, J20
3
1
5
SMD3P_BRIDGE No part
CONN_QTH_30X2-D-A QTH-60-02-F-D-A
Header 4x2 90131-0124
JP1, JP2
JP6
L1, L2
L8, L9
2
1
2
2
Jumper_1x3_SMT No part
Molex
Short pins 2 and 3 using 0
Ω
3M
Panasonic
Panasonic
MP2
MP3
P1, P3, J21, J22
P2, P4
R1, R2
R8, R22
R9, R18
R10, R19, R21, R48, R49,
R54, R56, R62, R63, R68,
R69
R13, R16
R12, R17, R31, R35, R37,
R38, R39, R42, R43, R55,
R59
4
4
2
2
2
4
2
11
2
11
Jumper_1x3
Bead, 220–
Ω
68
Screw machine, PH 4-40
×
3/8
Stand-off hex
.5/4-40THR
Banana jack, red
Banana jack, black
750
Ω
348
Ω
499
Ω
929400-01-36
EXC-3BB221H
EXC-ML32A680U
PMS 440 0038 PH
1902C
845R
845B
ERJ-3EKF7500V
ERJ-3EKF3480V
ERJ-3EKF4990V
49.9
Ω
69.8
Ω
100
Ω
ERJ-3EKF49R9V
ERJ-3EKF69R8V
ERJ-3EKF1000V
Building Fasteners
Keystone Electronic
SPC Technology
SPC Technology
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
R14, R15, R20 0
Not installed
200
Ω
ERJ-3EKF2000V Panasonic
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Physical Description
Reference
R28, R29, R32, R36, R72,
R73, R74, R75, R76, R77,
R78, R79, R80, R81, R82
R30, R84
R33, R34, R40, R41, R44,
R83
R45, R46, R51, R52, R58,
R60, R65, R66, R71
R47, R50, R53, R57, R61,
R64, R67, R70
SW1
T1, T2, T3, T4, T5, T6, T7,
T8, T9
TP1, TP2, TP3, TP4, TP9,
TP12
TP5, TP6, TP7, TP8, TP10,
TP11
U1
U2
Table 3. ADS64XXEVM Bill of Materials (continued)
Quantity
Not
Installed
Part Part Number
15
2
6
9
8
1
9
6
6
1
1
5
1 k
Ω
0
Ω
10 k
Ω
10
Ω
200
Ω
Switch, pushbutton
WBC1-1TLB
Test point, black
Test point, white
ADS64XX
THS4509
Conn. jumper, shorting
ERJ-3EKF1001V
ERJ-3GEY0R00V
ERJ-3EKF1002V
ERJ-3EKF10R0V
ERJ-3EKF2000V
KT11P3JM
WBC1-1TLB
5001
5002
THS4509RGTT
S9000-ND
Manufacturer
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
C & K Switch
Coilcraft
Keystone
Keystone
TI
Digi-Key
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4.3
PCB Schematics
1 2
1 2
2 1
1 2
Physical Description
1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1
1 2
2 1 2
Figure 10. Sheet 1 of 5
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Physical Description
1 2 1 2 1 2
CFG4
1 2 1 2 1 2
22
1
1 2 1 2 1 2
CFG3
CFG2
1 2 1 2 1 2
P 1_ DC
DC1_M
DC0_P
DC0_M
_M LK
_M LK DC
DCLK_P
FC
FCLK_P
DB0_P
DB1_M
DB0_M
DB1_P
59
58
60
56
55
57
64
63
62
61
51
50
52
49
54
53
65
D
M
P
P
M
M
P
M
P
_M
_P
ND
_M
_P
ND
0_
0_
1_
1_
DD
1_
1_
0_
0_
DD
LK
LK
LK
LK
LG
LG
LV
LV
DB
DB
DB
DB
DC
DC
DC
DC
DC
DC
FC
FC
GN
1 2
1 2
1 2
G4
KM
KP
ND
ND
G2
G3
G1
DD
ND
DD
AG
CM
CL
AG
CL
NC
AV
CF
AG
AV
AG
CF
AV
CF
AV
CF
ND
DD
DD
25
24
26
28
27
22
21
23
20
19
18
17
30
29
31
32
KM
P LK
ICL
IC
1 2
KM
P LK
ICL
IC
CFG1
CFG2
CFG3
G4 CF
G1 CF
2 1 2 1 2
1 2 1 2
1 2
1 2
1 2
2
2
2
2
2
2
1
1
1
1
1
1
Figure 11. Sheet 2 of 5
SLAU196 – April 2007
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5 2 3 4
Physical Description
5 2 3 4
SLAU196 – April 2007
Submit Documentation Feedback
5 2 3 4
5 2 3 4
Figure 12. Sheet 3 of 5
5 2 3 4
23
www.ti.com
Physical Description
24
1 2
1 2
16
15
14
13
VS
VS
VS
VS
-
-
-
-
VS
VS
VS
VS
+
+
+
+
8
7
6
5
1 2
1 2
5 2 3 4
Figure 13. Sheet 4 of 5
SLAU196 – April 2007
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Figure 14. Sheet 5 of 5
Physical Description
SLAU196 – April 2007
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25
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°
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