Download datasheet for SST39WF1601 by Microchip Technology Inc.

Download datasheet for SST39WF1601 by Microchip Technology Inc.

A Microchip Technology Company

16 Mbit (x16) Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

The SST39WF1601 / SST39WF1602 are a 1M x16 CMOS Multi-Purpose Flash

Plus (MPF+) devices manufactured with SST proprietary, high-performance

CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601 / SST39WF1602 write (Program or Erase) with a 1.65-1.95V power supply. These devices conform to JEDEC standard pin assignments for x16 memories.

Features

• Organized as 1M x16

• Single Voltage Read and Write Operations

– 1.65-1.95V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 5 µA (typical)

– Auto Low Power Mode: 5 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord) for SST39WF1602

– Bottom Block-Protection (bottom 32 KWord) for SST39WF1601

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

– 70 ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 36 ms (typical)

– Block-Erase Time: 36 ms (typical)

– Chip-Erase Time: 140 ms (typical)

– Word-Program Time: 28 µs (typical)

• Automatic Write Timing

– Internal V

PP

Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pin Assignments and

Command Sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm)

• All devices are RoHS compliant

©2011 Silicon Storage Technology, Inc.

www.microchip.com

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Product Description

The SST39WF1601/1602 devices are 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601/1602 write (Program or Erase) with a 1.65-1.95V power supply.

These devices conform to JEDEC standard pin assignments for x16 memories.

Featuring high performance Word-Program, the SST39WF1601/1602 devices provide a typical Word-

Program time of 28 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of

Program operation. To protect against inadvertent write, they have on-chip hardware and Software

Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39WF1601/1602 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball

TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments.

©2011 Silicon Storage Technology, Inc.

2

DS-25014A 04/11

A Microchip Technology Company

Block Diagram

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

X-Decoder

Memory Address

Address Buffer Latches

CE#

OE#

WE#

WP#

RESET#

Control Logic

Figure 1:

Functional Block Diagram

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ15 - DQ0

1297 B1.0

©2011 Silicon Storage Technology, Inc.

3

DS-25014A 04/11

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Block Diagram

TOP VIEW (balls facing down)

6

5

4

3

2

1

A13 A12 A14 A15 A16 NC DQ15 VSS

A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

WE#

RST# NC A19 DQ5

DQ12 VDD DQ4

NC WP# A18 NC DQ2 DQ10 DQ11 DQ3

A7 A17 A6

A3 A4 A2

A5 DQ0 DQ8 DQ9 DQ1

A1 A0 CE# OE# VSS

A B C D E F G H

1297 48-tfbga B3K P1.1

Figure 2:

Pin assignments for 48-ball TFBGA

TOP VIEW (balls facing down)

SST39WF160x

4

3

6

5

2

1

A2 A4 A6 A17 NC NC WE# RST# A9 A11

A1

A0

A3

A5

A7 WP#

A18

NC A10 A13 A14

A8 A12 A15

DQ4 DQ11 A16 CE# DQ8 DQ10

V

SS

OE# DQ9 A19 NC DQ5 DQ6 DQ7

DQ0 DQ1 DQ2 DQ3 V

DD

DQ12 DQ13 DQ14 DQ15 V

SS

A B C D E F G H J K L

1297 48-wfbga MBQ P02.0

Figure 3:

Pin assignments for 48-ball WFBGA

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

4

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Table 1:

Pin Description

RST#

CE#

OE#

WE#

V

DD

V

SS

NC

Symbol

A

MS

1

DQ

15

WP#

-A

0

-DQ

0

Pin Name Functions

Address Inputs To provide memory addresses.

During Sector-Erase A

MS

-A

11

During Block-Erase A

MS

-A

15 address lines will select the sector.

address lines will select the block.

Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.

Reset

Chip Enable

Output Enable

Write Enable

To reset and return the device to Read mode.

To activate the device when CE# is low.

To gate the data output buffers.

To control the Write operations.

To provide power supply voltage: 1.65-1.95V

Power Supply

Ground

No Connection Unconnected pins.

T1.0 25014

1. A

MS

A

MS

= Most significant address

= A

19 for SST39WF1601/1602

©2011 Silicon Storage Technology, Inc.

5

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39WF1601/1602 also have the

Auto Low Power

mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the I

DD active read current from typically 9 mA to typically 5 µA. The Auto Low Power mode reduces the typical I

DD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with

CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.

Refer to the Read cycle timing diagram for further details (Figure 4).

Word-Program Operation

The SST39WF1601/1602 are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps.

The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39WF1601/1602 offer both Sector-Erase and Block-Erase modes. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The

Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

6

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet for timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or

Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the

Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blocks will output DQ

2 toggling and DQ

6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

Erase Resume command (30H) at any address in the last Byte sequence.

Chip-Erase Operation

The SST39WF1601/1602 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence,

WP# should be statically held high or low.

Write Operation Status Detection

The SST39WF1601/1602 provide two software means to detect the completion of a Write (Program or

Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ

7

) and Toggle Bit (DQ

6

). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ

7 or DQ

6

. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

7

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Data# Polling (DQ

7

)

When the SST39WF1601/1602 are in the internal Program operation, any attempt to read DQ

7 produce the complement of the true data. Once the Program operation is completed, DQ

7 will will produce true data. Note that even though DQ

7 may have valid data immediately following the completion of an internal

Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ

7 will produce a ‘0’. Once the internal Erase operation is completed, DQ

7 will produce a ‘1’.

The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For

Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ

6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ

6 bit will stop toggling. The device is then ready for the next operation. For Sector-

, Block-, or Chip-Erase, the toggle bit (DQ

6

) is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ

6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ

6 will toggle.

An additional Toggle Bit is available on DQ

2

, which can be used in conjunction with DQ

6 to check whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status bits information. The Toggle Bit (DQ

2

) is valid after the rising edge of the last WE# (or CE#) pulse of

Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.

Table 2:

Write Operation Status

Status

Normal Operation

Erase-Suspend

Mode

Standard Program

Standard Erase

Read from Erase-Suspended Sector/Block

Read from Non- Erase-Suspended Sector/Block

Program

Note:

DQ

7 and DQ

2 require a valid address when reading status information.

DQ

7

DQ

7

#

0

1

Data

DQ

7

#

DQ

6

Toggle

Toggle

1

Data

Toggle

DQ

2

No Toggle

Toggle

Toggle

Data

N/A

T2.0 25014

©2011 Silicon Storage Technology, Inc.

8

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Data Protection

The SST39WF1601/1602 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

V

DD

Power Up/Down Detection: The Write operation is inhibited when V

DD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39WF1602 support top hardware block protection, which protects the top 32 KWord block of the device. The SST39WF1601 support bottom hardware block protection, which protects the bottom

32 KWord block of the device. The Boot Block address ranges are described in Table 3. Program and

Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block.

Table 3:

Boot Block Address Ranges

Product

Bottom Boot Block

SST39WF1601

Top Boot Block

SST39WF1602

Address Range

000000H-007FFFH

0F8000H-0FFFFFH

T3.0 25014

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T

RP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of T

RHR is driven high before a valid Read can take place (see Figure 16).

is required after RST#

The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39WF1601/1602 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within T

RC.

sequence.

The contents of DQ

15

-DQ

8 can be V

IL or V

IH

, but no other value, during any SDP command

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

9

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Common Flash Memory Interface (CFI)

The SST39WF1601/1602 contain the CFI information to describe the characteristics of the device. The

SST39WF1601/1602 support the original SST CFI Query mode implementation for compatibility with existing SST devices as well as the general CFI Query mode. Both will be explained in subsequent paragraphs.

In order to enter the SST CFI Query mode, the system must write the three-byte sequence, same as the product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

In order to enter the general CFI Query mode, the system must write a one-byte sequence with entry command with 98H to address 55H. Once the device enters the CFI Query mode, the system can read

CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as the SST39WF1601, SST39WF1602 and manufacturer as SST. This mode may be accessed software operations. Users may use the Software

Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 22 for the Software ID Entry command sequence flowchart.

Table 4:

Product Identification

Manufacturer’s ID

Device ID

SST39WF1601

SST39WF1602

Address

0000H

0001H

0001H

Data

BFH

BF274B

BF274A

T4.0 25014

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited.

Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures 22 and 23 for flowcharts.

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

10

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Security ID

The SST39WF1601/1602 devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment.

The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to program as desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details.

©2011 Silicon Storage Technology, Inc.

11

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Operations

Table 5:

Operation Modes Selection

Mode

Read

Program

Erase

CE#

V

IL

V

IL

V

IL

OE#

V

IL

V

IH

V

IH

Standby

Write Inhibit

V

IH

X

X

Product Identification

Software Mode V

IL

1. X can be V

IL or V

IH

, but no other value.

X

V

IL

X

V

IL

WE#

V

IH

V

IL

V

IL

DQ

D

OUT

D

IN

X

1

X

X

V

IH

High Z

High Z/ D

OUT

High Z/ D

OUT

V

IH

X

X

X

Address

A

IN

A

IN

Sector or block address,

XXH for Chip-Erase

See Table 6

T5.0 25014

Table 6:

Software Command Sequence

Command

Sequence

Word-Program

Sector-Erase

Block-Erase

Chip-Erase

Erase-Suspend

Erase-Resume

Query Sec ID

5

User Security ID

Word-Program

User Security ID

Program Lock-Out

Software ID Entry

7,8

SST CFI Query Entry

General CFI Query

Mode

Software ID Exit

9,10

/CFI Exit/Sec ID Exit

Software ID Exit

9,10

/CFI Exit/Sec ID Exit

1st Bus

Write Cycle

Addr

1

Data

2

5555H AAH

5555H

5555H

5555H

XXXXH

XXXXH

5555H

5555H

AAH

AAH

AAH

B0H

30H

AAH

AAH

5555H

5555H

5555H

55H

5555H

XXH

AAH

AAH

AAH

98H

AAH

F0H

2nd Bus

Write Cycle

Addr

1

Data

2

2AAAH 55H

2AAAH

2AAAH

2AAAH

55H

55H

55H

2AAAH

2AAAH

2AAAH

2AAAH

2AAAH

2AAAH

55H

55H

55H

55H

55H

55H

3rd Bus

Write Cycle

Addr

1

Data

2

5555H A0H

5555H

5555H

5555H

80H

80H

80H

5555H

5555H

5555H

5555H

5555H

5555H

88H

A5H

85H

90H

98H

F0H

4th Bus

Write Cycle

Addr

WA

3

1

Data

2

Data

5555H

5555H

5555H

AAH

AAH

AAH

5th Bus

Write Cycle

Addr

1

2AAAH

2AAAH

2AAAH

Data

2

55H

55H

55H

6th Bus

Write Cycle

Addr

1

Data

2

SA

X

4

BA

X

4

5555H

30H

50H

10H

WA

6

XXH

6

Data

0000

H

T6.0 25014

1. Address format A

14

-A

0

(Hex).

Addresses A

2. DQ

15

-DQ

8

15

-A

19 can be V

IL can be V

IL or V

IH or V

IH

, but no other value, for Command sequence for SST39WF1601/1602.

, but no other value, for Command sequence

3. WA = Program Word address

4. SA

X

BA

X for Sector-Erase; uses A

MS

-A

11

, for Block-Erase; uses A

MS

-A

15 address lines address lines

A

MS

A

MS

= Most significant address

= A

19 for SST39WF1601/1602

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

12

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

5. With A

MS

-A

4

= 0; Sec ID is read with A

3

-A

0

,

SST ID is read with A

3

= 0 (Address range = 000000H to 000007H),

User ID is read with A

3

User ID Lock Status is read with A

7

-A

0

= 1 (Address range = 000008H to 00000FH).

= 0000FFH. Unlocked: DQ

3

= 1 / Locked: DQ

3

= 0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH.

7. The device does not remain in Software Product ID Mode if powered down.

8. With A

MS

-A

1

A

MS

=0; SST Manufacturer ID = 00BFH, is read with A

0

= 0,

SST39WF1601 Device ID = BF274BH, is read with A

0

SST39WF1602 Device ID = BF274AH, is read with A

0

= Most significant address

A

MS

= A

19 for SST39WF1601/1602

9. Both Software ID Exit operations are equivalent

= 1,

= 1.

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH.

Table 7:

CFI Query Identification String

1

Address

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

Data

0051H

0052H

0059H

0002H

0000H

0000H

0000H

0000H

0000H

0000H

0000H

Data

Query Unique ASCII string “QRY”

Primary OEM command set

Address for Primary Extended Table

Alternate OEM command set (00H = none exists)

Address for Alternate OEM extended Table (00H = none exits)

1. Refer to CFI publication 100 for more details.

T7.0 25014

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

Table 8:

Address

1BH

1CH

0000H

0000H

0005H

0000H

0005H

0007H

0001H

0000H

0001H

0001H

System Interface Information

Data

0016H

0020H

Data

V

DD

Min (Program/Erase)

DQ

7

-DQ

4

: Volts, DQ

3

-DQ

0

: 100 millivolts

V

DD

Max (Program/Erase)

DQ

7

-DQ

4

: Volts, DQ

3

-DQ

0

: 100 millivolts

V

PP min. (00H = no V

PP pin)

V

PP max. (00H = no V

PP pin)

Typical time out for Word-Program 2

N

µs (2

5

= 32 µs)

Typical time out for min. size buffer program 2

N

µs (00H = not supported)

Typical time out for individual Sector/Block-Erase 2

N ms (2

5

= 30 ms)

Typical time out for Chip-Erase 2

N ms (2

7

= 128 ms)

Maximum time out for Word-Program 2

N times typical (2

1 x 2

5

= 64 µs)

Maximum time out for buffer program 2

N times typical

Maximum time out for individual Sector/Block-Erase 2

N times typical (2

1 x 2

5

= 64 ms)

Maximum time out for Chip-Erase 2

N times typical (2

1 x 2

7

= 256 ms)

T8.0 25014

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

13

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Table 9:

Device Geometry Information

2EH

2FH

30H

31H

32H

33H

34H

Address

27H

28H

29H

2AH

2BH

2CH

2DH

Data

0015H

0001H

0000H

0000H

0000H

0002H

00FFH

0001H

0010H

0000H

001FH

0000H

0000H

0001H

Data

Device size = 2

N

Bytes (15H = 21; 2

21

= 2 MByte)

Flash Device Interface description; 0001H = x16-only asynchronous interface

Maximum number of byte in multi-byte write = 2

N

(00H = not supported)

Number of Erase Sector/Block sizes supported by device

Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FF = 511) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001F = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T9.0 25014

©2011 Silicon Storage Technology, Inc.

14

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Absolute Maximum Stress Ratings

(Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

DD

+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to V

DD

+2.0V

Voltage on A

9

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (T

A

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 10:

Operating Range

Range

Commercial

Industrial

Ambient Temp

0°C to +70°C

-40°C to +85°C

V

DD

1.65-1.95V

1.65-1.95V

T10.1 25014

Table 11:

AC Conditions of Test

1

Input Rise/Fall Time

5ns

1. See Figures 18 and 19

Output Load

C

L

= 30 pF

T11.1 25014

©2011 Silicon Storage Technology, Inc.

15

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Table 12:

DC Operating Characteristics V

DD

= 1.65-1.95V

1

Limits

I

Symbol Parameter

DD

Power Supply Current

Read

Min Max

10

Units

mA

Test Conditions

Address input=V

ILT

/V

IHT,

V

DD

=V

DD

Max at f=5 MHz,

CE#=V

IL

, OE#=WE#=V

IH

, all I/Os open

I

I

SB

ALP

Program and Erase

Standby V

DD

Current

2

Auto Low Power

25

40

40 mA

µA

µA

CE#=WE#=V

IL

, OE#=V

IH

CE#=V

IHC

, V

DD

=V

DD

Max

CE#=V

ILC

, V

DD

=V

DD

All inputs=V

SS or V

Max

DD,

WE#=V

IHC

V

IN

=GND to V

DD

, V

DD

=V

DD

Max

I

I

LI

LIW

I

LO

V

IL

V

V

IH

OL

Input Leakage Current

Input Leakage Current on WP# pin and RST#

Output Leakage Current

Input Low Voltage

Input High Voltage

Output Low Voltage

0.8V

DD

1

10

1

0.2V

0.1

DD

µA

µA

µA

V

V

V

WP#=GND to V

DD or RST#=GND to

V

DD

V

V

OUT

DD

=GND to V

=V

DD

Min

DD

, V

DD

=V

V

DD

=V

DD

Max

I

OL

=100 µA, V

DD

=V

DD

Min

DD

Max

V

OH

Output High Voltage V

DD

-0.1

V I

OH

=-100 µA, V

DD

=V

DD

Min

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

T12.0 25014

(room temperature), and V

DD

= 1.8V. Not 100% tested.

2. For all SST39WF160x commercial and industrial devices, I

SB typical is under 5 µA.

Table 13:

Recommended System Power-up Timings

Symbol

T

PU-READ

1

T

PU-WRITE

1

Parameter

Power-up to Read Operation

Power-up to Program/Erase Operation

Minimum

100

100

Units

µs

µs

T13.0 25014

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Table 14:

Capacitance

(T

A

= 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

C

C

I/O

IN

1

1

I/O Pin Capacitance

Input Capacitance

V

I/O

= 0V

V

IN

= 0V

12 pF

6 pF

T14.0 25014

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Table 15:

Reliability Characteristics

Symbol

N

END

1,2

T

DR

1

I

LTH

1

Parameter

Endurance

Data Retention

Minimum Specification

10,000

100

Units

Cycles

Years

Test Method

JEDEC Standard A117

JEDEC Standard A103

Latch Up 100 + I

DD mA JEDEC Standard 78

T15.0 25014

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. N

END endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

16

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

AC Characteristics

Table 16:

Read Cycle Timing Parameters V

DD

= 1.65-1.95V

Symbol Parameter Min Max Units

T

RC

T

CE

Read Cycle Time

Chip Enable Access Time

70

70 ns ns

T

AA

T

OE

T

CLZ

1

T

OLZ

1

T

CHZ

1

T

OHZ

1

T

OH

1

T

RP

1

T

RHR

1

T

RY

1,2

Address Access Time

Output Enable Access Time

CE# Low to Active Output

OE# Low to Active Output

CE# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

RST# High before Read

RST# Pin Low to Read Mode

0

0

0

500

50

70

35

40

40

20

3 ns ns ns ns ns ns ns ns ns

µs

T16.0 25014

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

3. This parameter is 100 µs if reset after an Erase operation.

Table 17:

Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

T

BP

T

AS

T

AH

T

CS

T

CH

T

OES

T

OEH

T

CP

T

WP

T

WPH

1

T

CPH

1

T

DS

T

DH

1

T

IDA

1

Word-Program Time

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OE# High Setup Time

OE# High Hold Time

CE# Pulse Width

WE# Pulse Width

WE# Pulse Width High

CE# Pulse Width High

Data Setup Time

Data Hold Time

Software ID Access and Exit Time

0

50

0

0

0

10

50

50

30

30

50

0

40

150

µs ns ns ns ns ns ns ns ns ns ns ns ns ns

T

SE

T

BE

Sector-Erase

Block-Erase

50

50 ms ms

T

SCE

Chip-Erase 200 ms

T17.0 25014

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

ADDRESS A

19-0

CE#

OE#

WE#

DQ

15-0

V

IH

HIGH-Z

Figure 4:

Read Cycle Timing Diagram

T

OLZ

T

CLZ

T

RC

T

CE

T

OE

T

OH

DATA VALID

T

AA

T

OHZ

T

CHZ

DATA VALID

HIGH-Z

1297 F03.1

INTERNAL PROGRAM OPERATION STARTS

T

BP

ADDRESS A19-0

5555

T

AH

T

WP

2AAA 5555 ADDR

T

DH

WE#

T

AS

T

WPH

T

DS

OE#

T

CH

CE#

T

CS

DQ15-0 XXAA XX55 XXA0 DATA

SW0 SW1 SW2 WORD

(ADDR/DATA)

Note:

WP# must be held in proper logic state (V

IL or

V

IH

) 1 µs prior to and 1µs after the command sequence.

X can be V

IL or V

IH, but no other value.

Figure 5:

WE# Controlled Program Cycle Timing Diagram

1297 F04.1

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

INTERNAL PROGRAM OPERATION STARTS

T

BP

ADDRESS A19-0 5555

T

AH

T

CP

2AAA 5555 ADDR

T

DH

CE#

T

AS

OE#

T

CPH

T

DS

T

CH

WE#

DQ15-0 XXAA

SW0

T

CS

XX55

SW1

XXA0

SW2

DATA

WORD

(ADDR/DATA)

Note:

WP# must be held in proper logic state (V

IL

X can be V

IL or V

IH, but no other value.

or V

IH

) 1 µs prior to and 1µs after the command sequence.

1297 F05.1

Figure 6:

CE# Controlled Program Cycle Timing Diagram

ADDRESS A

19-0

CE#

OE#

WE#

DQ

7

DATA

T

OEH

T

CE

T

OE

DATA#

Figure 7:

Data# Polling Timing Diagram

DATA# DATA

T

OES

1297 F06.1

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

ADDRESS A

19-0

CE#

OE#

WE#

DQ

6 and DQ

2

T

OEH

T

CE

T

OE

T

OES

TWO READ CYCLES

WITH SAME OUTPUTS

1297 F07.1

Figure 8:

Toggle Bits Timing Diagram

5555 2AAA

SIX-BYTE CODE FOR CHIP-ERASE

5555 5555 2AAA 5555

T

SCE

ADDRESS A

19-0

CE#

OE#

WE#

T

WP

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX10

SW5

Note:

This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.)

WP# must be held in proper logic state (V

IH

) 1 µs prior to and 1µs after the command sequence.

X can be V

IL or V

IH, but no other value.

1297 F08.1

Figure 9:

WE# Controlled Chip-Erase Timing Diagram

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

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A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

5555 2AAA

SIX-BYTE CODE FOR BLOCK-ERASE

5555 5555 2AAA BA

X

T

BE

ADDRESS A

19-0

CE#

OE#

WE#

T

WP

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX50

SW5

Note:

This device also supports CE# controlled Block-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.)

BA

X

= Block Address

WP# must be held in proper logic state (V

IH

) 1 µs prior to and 1 µs after the command sequence.

X can be V

IL or V

IH, but no other value.

Figure 10:

WE# Controlled Block-Erase Timing Diagram

1297 F09.1

5555 2AAA

SIX-BYTE CODE FOR SECTOR-ERASE

5555 5555 2AAA SA

X

T

SE

ADDRESS A

19-0

CE#

OE#

T

WP

WE#

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX30

SW5

Note:

This device also supports CE# controlled Sector-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.)

SA

X

= Sector Address

WP# must be held in proper logic state (V

IH

) 1 µs prior to and 1µs after the command sequence.

X can be V

IL or V

IH, but no other value.

1297 F10.1

Figure 11:

WE# Controlled Sector-Erase Timing Diagram

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

ADDRESS A

14-0

Three-Byte Sequence for Software ID Entry

5555 2AAA 5555

CE#

0000 0001

OE#

T

WP

T

IDA

WE#

DQ

15-0

XXAA

SW0

T

WPH

XX55

SW1

XX90

SW2

T

AA

00BF Device ID

Note:

WP# must be held in proper logic state (V

Device ID - See Table 4 X can be V

IL

IL or V

IH, or V

IH

) 1 µs prior to and 1µs after the command sequence.

but no other value.

1297 F11.1

Figure 12:

Software ID Entry and Read

ADDRESS A

14-0

Three-Byte Sequence for CFI Query Entry

5555 2AAA 5555

CE#

OE#

T

WP

T

IDA

WE#

DQ

15-0

XXAA

SW0

T

WPH

XX55

SW1

XX98

SW2

T

AA

Note:

WP# must be held in proper logic state (V

IL

X can be V

IL or V

IH, but no other value.

or V

IH

) 1 µs prior to and 1µs after the command sequence.

Figure 13:

CFI Query Entry and Read

1297 F12.1

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A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

ADDRESS A

14-0

DQ

15-0

5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

2AAA 5555

XXAA XX55 XXF0

T

IDA

CE#

OE#

T

WP

WE#

SW0

T

WHP

SW1 SW2

Note:

WP# must be held in proper logic state (V

IL

X can be V

IL or V

IH, but no other value.

or V

IH

) 1 µs prior to and 1µs after the command sequence.

1297 F13.1

Figure 14:

Software ID Exit/CFI Exit

ADDRESS A

19-0

5555

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

2AAA 5555

CE#

OE#

T

WP

T

IDA

WE#

DQ

15-0

XXAA

SW0

T

WPH

XX55

SW1

XX88

SW2

T

AA

Note:

WP# must be held in proper logic state (V

IL

X can be V

IL or V

IH, but no other value.

or V

IH

) 1 µs prior to and 1µs after the command sequence.

Figure 15:

Sec ID Entry

1297 F20.1

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

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A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

T

RP

RST#

CE#/OE#

T

RHR

Figure 16:

RST# Timing Diagram (When no internal operation is in progress)

1297 F22.0

T

RP

RST#

T

RY

CE#/OE#

End-of-Write Detection

(Toggle-Bit)

Figure 17:

RST# Timing Diagram (During Program or Erase operation)

1297 F23.1

©2011 Silicon Storage Technology, Inc.

24

DS-25014A 04/11

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

V

IHT

INPUT

V

IT

REFERENCE POINTS

V

OT

OUTPUT

V

ILT

1297 F14.1

AC test inputs are driven at V

IHT

(0.9 V

DD

) for a logic “1” and V

ILT surement reference points for inputs and outputs are V

IT and fall times (10%

90%) are <5 ns.

(0.1 V

DD

) for a logic “0”. Mea-

(0.5 V

DD

) and V

OT

(0.5 V

DD

). Input rise

Note:

V

IT

V

OT

- V

INPUT

- V

Test

OUTPUT

Test

V

IHT

Test

- V

INPUT

HIGH

Figure 18:

AC Input/Output Reference Waveforms

TO TESTER

V

DD

25K

TO DUT

C

L

25K

1297 F15.1

Figure 19:

A Test Load Example

©2011 Silicon Storage Technology, Inc.

25

DS-25014A 04/11

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Note:

X can be V

IL or V

IH, but no other value.

Figure 20:

Word-Program Algorithm

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling bit, or Toggle bit operation)

Program

Completed

1297 F16.0

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

26

A Microchip Technology Company

Internal Timer

Program/Erase

Initiated

Wait TBP,

TSCE, TSE or TBE

Program/Erase

Completed

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Toggle Bit

Program/Erase

Initiated

Data# Polling

Program/Erase

Initiated

Read word

Read same word

No

Does DQ6 match

Yes

Program/Erase

Completed

Read DQ7

No Is DQ7 = true data

Yes

Program/Erase

Completed

1297 F17.0

Figure 21:

Wait Options

©2011 Silicon Storage Technology, Inc.

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DS-25014A 04/11

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

eneral

CFI Query Entry

Command Sequence

CFI Query Entry

Command Sequence

Sec ID Query Entry

Command Sequence

Software Product ID

Entry

Command Sequence

Load data: XX98H

Address: 55H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TIDA

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Read CFI data

Load data: XX98H

Address: 5555H

Load data: XX88H

Address: 5555H

Load data: XX90H

Address: 5555H

Wait TIDA Wait TIDA Wait TIDA

Read CFI data Read Sec ID Read Software ID

1297 F21.0

Note:

X can be V

IL or V

IH, but no other value.

Figure 22:

Software ID/CFI Entry Command Flowcharts

©2011 Silicon Storage Technology, Inc.

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DS-25014A 04/11

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16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXF0H

Address: XXH

Load data: XX55H

Address: 2AAAH

Wait TIDA

Load data: XXF0H

Address: 5555H

Return to normal operation

Wait TIDA

Return to normal operation

Note:

X can be V

IL or V

IH, but no other value.

Figure 23:

Software ID/CFI Exit Command Flowcharts

1297 F18.0

©2011 Silicon Storage Technology, Inc.

29

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Chip-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Sector-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XX30H

Address: SAX

Load data: XX50H

Address: BAX

Wait TSCE Wait TSE Wait TBE

Chip erased to FFFFH

Sector erased to FFFFH

Block erased to FFFFH

1297 F19.0

Note:

X can be V

IL or V

IH, but no other value.

Figure 24:

Erase Command Sequence

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

30

A Microchip Technology Company

Product Ordering Information

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

SST 39

XX

WF

XX

1602

XXXX -

70

XX -

4C

XX -

B3KE

XXXX

Environmental Attribute

E

1

= non-Pb

Package Modifier

K = 48 balls

Q = 48 balls (66 possible positions)

Package Type

B3 = TFBGA (6mm x 8mm)

MB = WFBGA (5mm x 6mm)

MA = WFBGA (4mm x 6mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

160 = 16 Mbit

Voltage

W = 1.65-1.95V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS

Compliant”.

Valid Combinations for SST39WF1601

SST39WF1601-70-4C-B3KE SST39WF1601-70-4C-MAQE

SST39WF1601-70-4I-B3KE SST39WF1601-70-4I-MAQE

Valid Combinations for SST39WF1602

SST39WF1602-70-4C-B3KE SST39WF1602-70-4C-MAQE

SST39WF1602-70-4I-B3KE SST39WF1602-70-4I-MAQE

Note:

Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

31

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

Packaging Diagrams

TOP VIEW

8.00 0.10

BOTTOM VIEW

5.60

0.80

2

1

4

3

6

5

A B C D E F G H

A1 CORNER

SIDE VIEW

SEATING PLANE

6.00 0.10

1.10 0.10

0.35 0.05

0.12

4.00

0.80

H G F E D C B A

3

2

1

6

5

4

0.45 0.05

(48X)

A1 CORNER

1mm

Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

48-tfbga-B3K-6x8-450mic-5

Figure 25:

48-ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

©2011 Silicon Storage Technology, Inc.

32

DS-25014A 04/11

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

Data Sheet

TOP VIEW

6.00

0.08

4

3

6

5

2

1

A B C D E F G H J K L

A1 CORNER

DETAIL

4.00

0.08

0.73 max.

0.636 nom.

2.50

0.50

BOTTOM VIEW

5.00

0.50

4

3

6

5

2

1

0.32 0.05

(48X)

L K J H G F E D C B A

A1 INDICATOR

SIDE VIEW

0.08

SEATING PLANE

0.20 0.06

1mm

Note: 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger and bottom side A1 indicator is triangle at corner.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.29 mm ( 0.05 mm)

48-wfbga-MAQ-4x6-32mic-2.0

Figure 26:

48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm

SST Package Code MAQ

©2011 Silicon Storage Technology, Inc.

33

DS-25014A 04/11

16 Mbit Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

A Microchip Technology Company

Data Sheet

Table 18:

Revision History

Number

00

01

02

03

04

05

06

A

Description

Initial release

Added MBQ package information including product numbers.

Migrated document to Preliminary Specifications

Updated Table 12 on page 16

Added 70 ns to Features: Fast Read Access Time

Added 70 ns columns to Table 16

Edited Product Ordering Information and Valid Combination to include 70 ns and remove leaded parts.

Added YIQE package

Changed 000010H to 000017H to 000008H to 00000FH three places in footnotes of Table 6 on page 12.

EOL of SST39WF1601-70-4C-Y1QE, SST39WF1601-70-4I-Y1QE,

SST39WF1602-70-4C-Y1QE, and SST39WF1602-70-4I-Y1QE.

Replacement parts SST39WF1601-70-4C-MAQE, SST39WF1601-70-4I-

MAQE, SST39WF1602-70-4C-MAQE, and SST39WF1602-70-4I-MAQE in this document.

Added MAQE package drawing and information.

Removed all 90ns speed products

EOL of MBQE products.

Applied new document format

Released document under new letter revision system

Updated spec number S71297 to DS-25014

Date

Oct 2005

Jul 2006

Aug 2007

Jul 2008

Dec 2008

Nov 2009

Jan 2011

Apr 2011

ISBN:978-1-61341-101-8

© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office(s) location and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company www.microchip.com

©2011 Silicon Storage Technology, Inc.

DS-25014A 04/11

34

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