Download datasheet for A29800 by AMIC Technology

Download datasheet for A29800 by AMIC Technology
A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
History
Issue Date
Remark
0.0
Initial issue
May 4, 2001
Preliminary
0.1
Error Correction:
1.0
P.10: Autoselect Command Sequence (line 15), XX11h → XX03h
December 24, 2002
Final version release
October 7, 2003
1.1
Add Pb-Free package type for -70 grade
July 15, 2004
1.2
Add -70I series products
January 24, 2007
1.3
Modify symbol “L” outline dimensions in TSOP 48L package
November 13, 2007
1.4
Update -70I series product working temperature range: read -40°C
February 26, 2009
Final
to +85°C, erase & program 0°C to +85°C
1.5
Error correction: Modify Figure 3. Erase Operation
April 28, 2009
1.6
Modify the latency time of erase suspend from 20 s to 30 s
December 01, 2009
Error correction: Modify the way to check write operation status by
1.7
either OE or CE to by OE and CE
Error correction: Delete tWPH Max. 50 s
December 21, 2009
1.8
Page 1: Change from typical 100,000 cycles to minimum 100,000
December 31, 2010
Cycles
1.9
Replace all non Pb-Free parts with Pb-Free ones
(October, 2011, Version 1.9)
October 21, 2011
AMIC Technology, Corp.
A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
̈ 5.0V ± 10% for read and write operations
̈ Access times:
- 55/70/90 (max.)
̈ Current:
- 28mA read current (word mode)
- 20 mA typical active read current (byte mode)
- 30 mA typical program/erase current
- 1 μA typical CMOS standby
̈ Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector
̈ Extended read operating temperature range: -40°C ~ +85°C
for – I series
̈ Extended erase and program temperature range: 0°C ~
+85°C for – I series
̈ Top or bottom boot block configurations available
̈ Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
̈ Minimum 100,000 program/erase cycles per sector
̈ 20-year data retention at 125°C
- Reliable operation for the life of the system
̈ Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
- Superior inadvertent write protection
̈ Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
̈ Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
̈ Hardware reset pin ( RESET )
- Hardware method to reset the device to reading array
data
̈ Package options
- 44-pin SOP or 48-pin TSOP (I)
- All Pb-free (Lead-free) products are RoHS compliant
General Description
The A29800 is a 5.0 volt only Flash memory organized as
1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The
A29800 offers the RESET function. The 1024 Kbytes of data
are further divided into nineteen sectors for flexible sector
erase capability. The 8 bits of data appear on I/O0 - I/O7 while
the addresses are input on A1 to A18; the 16 bits of data
appear on I/O0~I/O15. The A29800 is offered in 44-pin SOP
and 48-Pin TSOP packages. This device is designed to be
programmed in-system with the standard system 5.0 volt VCC
supply. Additional 12.0 volt VPP is not required for in-system
write or erase operations. However, the A29800 can also be
programmed in standard EPROM programmers.
The A29800 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O6 toggle bit, the A29800
has a second toggle bit, I/O2, to indicate whether the
addressed sector is being selected for erase. The A29800 also
offers the ability to program in the Erase Suspend mode. The
standard A29800 offers access times of 55, 70 and 90 ns,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
chip enable ( CE ), write enable ( WE ) and output enable
( OE ) controls.
(October, 2011, Version 1.9)
1
The device requires only a single 5.0 volt power supply for
both read and write functions.
Internally generated and regulated voltages are provided for
the program and erase operations.
The A29800 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry.
Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation.
During erase, the device automatically times the erase pulse
widths and verifies proper erase margin.
AMIC Technology, Corp.
A29800 Series
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Data Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29800 is fully erased when shipped
from the factory.
The hardware sector protection feature disables operations for
both program and erase in any combination of the sectors
of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data.
Pin Configurations
̈ SOP
̈ TSOP (I)
1
44
RESET
A18
2
43
WE
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
34
A16
33
BYTE
32
VSS
I/O15 (A-1)
A0
11
A29800M
RY/BY
CE
12
VSS
13
OE
14
31
I/O0
15
30
I/O7
I/O8
16
29
I/O14
I/O1
17
28
I/O6
I/O9
18
27
I/O13
I/O2
19
26
I/O5
I/O10
20
25
I/O12
I/O3
21
24
I/O4
I/O11
22
23
VCC
(October, 2011, Version 1.9)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A29800V
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O15 (A-1)
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
VSS
CE
A0
AMIC Technology, Corp.
A29800 Series
Block Diagram
RY/BY
I/O0 - I/O 15 (A-1)
VCC
VSS
Sector Switches
Input/Output
Buffers
Erase Voltage
Generator
RESET
State
Control
WE
BYTE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
CE
OE
VCC Detector
Address Latch
STB
Timer
A0-A18
STB
Data Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
Description
A0 - A18
Address Inputs
I/O0 - I/O14
Data Inputs/Outputs
I/O15
I/O15 (A-1)
A-1
LSB Address Input, Byte Mode
CE
Chip Enable
WE
Write Enable
OE
Output Enable
RESET
(October, 2011, Version 1.9)
Data Input/Output, Word Mode
Hardware Reset
BYTE
Selects Byte Mode or Word Mode
RY/ BY
Ready/ BUSY - Output
VSS
Ground
VCC
Power Supply
3
AMIC Technology, Corp.
A29800 Series
Absolute Maximum Ratings*
*Comments
Ambient Operating Temperature . . . . ….. -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . …. -65°C to + 125°C
Ground to VCC . . . . . . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . …... -2.0V to 7.0V
A9, OE & RESET (Note 2) . . . . . . . . . . ….. -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . ….. . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. These
are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the
operational sections of these specification is not implied or
intended. Exposure to the absolute maximum rating
conditions for extended periods may affect device reliability.
Operating Ranges
Notes:
Commercial (C) Devices
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9, OE and RESET may overshoot
VSS to -2.0V for periods of up to 20ns. Maximum DC input
voltage on A9 and OE is +12.5V which may overshoot to
13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Ambient Temperature (TA) . . . . . . . . …. .. . . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For – I series (read) . . . . . . . . . . . . . . . . . . -40°C to + 85°C
For – I series (erase, program) . . . . . . . . . . . . 0°C to + 85°C
VCC Supply Voltages
VCC for ± 10% devices . . . . . . . . . . . …... . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29800 Device Bus Operations
Operation
CE
OE
Read
L
L
Write
L
WE
RESET
A0 - A18
I/O8 - I/O15
I/O0 - I/O7
DOUT
BYTE =VIH
BYTE =VIL
DOUT
High-Z
H
H
AIN
H
L
H
AIN
DIN
DIN
High-Z
X
High-Z
High-Z
High-Z
VCC ± 0.5 V
X
VCC ± 0.5 V
X
TTL Standby
H
X
X
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Hardware Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Temporary Sector Unprotect
(See Note)
X
X
X
VID
AIN
DIN
DIN
X
CMOS Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:
See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
(October, 2011, Version 1.9)
4
AMIC Technology, Corp.
A29800 Series
Word/Byte Configuration
Program and Erase Operation Status
The BYTE pin determines whether the I/O pins I/O15 - I/O0
operate in the byte or word configuration. If the BYTE pin is
set at logic “1”, the device is in word configuration, I/O15 - I/O0
are active and controlled by CE and OE .
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0 - I/O7 are active and controlled by
CE and OE . I/O8- I/O14 are tri-stated, and I/O15 pin is used as
an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH all the time
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on the
device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the
command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
OE to VIH. An erase operation can erase one sector, multiple
sectors, or the entire device. The Sector Address Tables
indicate the address range that each sector occupies. A
"sector address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
(October, 2011, Version 1.9)
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when the CE &
RESET pins are both held at VCC ± 0.5V. (Note that this is a
more restricted voltage range than VIH.) The device enters the
TTL standby mode when CE is held at VIH, while RESET is
held at VCC±0.5V. The device requires the standard access
time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates all
data output pins, and ignores all read/write attempts for the
duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET parameters
and diagram.
5
AMIC Technology, Corp.
A29800 Series
Table 2. A29800 Top Boot Block Sector Address Table
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x16)
(x8)
Address Range
Address Range
SA0
0
0
0
0
X
X
X
64/32
00000h - 07FFFh
00000h - 0FFFFh
SA1
0
0
0
1
X
X
X
64/32
08000h - 0FFFFh
10000h - 1FFFFh
SA2
0
0
1
0
X
X
X
64/32
10000h - 17FFFh
20000h - 2FFFFh
SA3
0
0
1
1
X
X
X
64/32
18000h - 1FFFFh
30000h - 3FFFFh
SA4
0
1
0
0
X
X
X
64/32
20000h - 27FFFh
40000h - 4FFFFh
SA5
0
1
0
1
X
X
X
64/32
28000h - 2FFFFh
50000h - 5FFFFh
SA6
0
1
1
0
X
X
X
64/32
30000h - 37FFFh
60000h - 6FFFFh
SA7
0
1
1
1
X
X
X
64/32
38000h -3FFFFh
70000h -7FFFFh
SA8
1
0
0
0
X
X
X
64/32
40000h -47FFFh
80000h -8FFFFh
SA9
1
0
0
1
X
X
X
64/32
48000h -4FFFFh
90000h -9FFFFh
SA10
1
0
1
0
X
X
X
64/32
50000h - 57FFFh
A0000h - AFFFFh
SA11
1
0
1
1
X
X
X
64/32
58000h - 5FFFFh
B0000h - BFFFFh
SA12
1
1
0
0
X
X
X
64/32
60000h - 67FFFh
C0000h - CFFFFh
SA13
1
1
0
1
X
X
X
64/32
68000h - 6FFFFh
D0000h - DFFFFh
SA14
1
1
1
0
X
X
X
64/32
70000h - 77FFFh
E0000h - EFFFFh
SA15
1
1
1
1
0
X
X
32/16
78000h - 7BFFFh
F0000h - F7FFFh
SA16
1
1
1
1
1
0
0
8/4
7C000h - 7CFFFh
F8000h - F9FFFh
SA17
1
1
1
1
1
0
1
8/4
7D000h - 7DFFFh
FA000h - FBFFFh
SA18
1
1
1
1
1
1
X
16/8
7E000h - 7FFFFh
FC000h - FFFFFh
Note:
Address range is A18: A-1 in byte mod and A18: A0 in word mode. See the “Word/Byte Configuration” section for more
information.
(October, 2011, Version 1.9)
6
AMIC Technology, Corp.
A29800 Series
Table 3. A29800 Bottom Boot Block Sector Address Table
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes /
Kwords)
Address Range
(x 16)
(x 8)
Address Range
Address Range
SA0
0
0
0
0
0
0
X
16/8
00000h - 01FFFh
00000h - 03FFFh
SA1
0
0
0
0
0
1
0
8/4
02000h - 02FFFh
04000h - 05FFFh
SA2
0
0
0
0
0
1
1
8/4
03000h - 03FFFh
06000h - 07FFFh
SA3
0
0
0
0
1
X
X
32/16
04000h - 07FFFh
08000h - 0FFFFh
SA4
0
0
0
1
X
X
X
64/32
08000h - 0FFFFh
10000h - 1FFFFh
SA5
0
0
1
0
X
X
X
64/32
10000h - 17FFFh
20000h - 2FFFFh
SA6
0
0
1
1
X
X
X
64/32
18000h - 1FFFFh
30000h - 3FFFFh
SA7
0
1
0
0
X
X
X
64/32
20000h - 27FFFh
40000h - 4FFFFh
SA8
0
1
0
1
X
X
X
64/32
28000h - 2FFFFh
50000h - 5FFFFh
SA9
0
1
1
0
X
X
X
64/32
30000h - 37FFFh
60000h - 6FFFFh
SA10
0
1
1
1
X
X
X
64/32
38000h - 3FFFFh
70000h - 7FFFFh
SA11
1
0
0
0
X
X
X
64/32
40000h - 47FFFh
80000h - 8FFFFh
SA12
1
0
0
1
X
X
X
64/32
48000h - 4FFFFh
90000h - 9FFFFh
SA13
1
0
1
0
X
X
X
64/32
50000h - 57FFFh
A0000h - AFFFFh
SA14
1
0
1
1
X
X
X
64/32
58000h - 5FFFFh
B0000h - BFFFFh
SA15
1
1
0
0
X
X
X
64/32
60000h - 67FFFh
C0000h - CFFFFh
SA16
1
1
0
1
X
X
X
64/32
68000h - 6FFFFh
D0000h - DFFFFh
SA17
1
1
1
0
X
X
X
64/32
70000h - 77FFFh
E0000h - EFFFFh
SA18
1
1
1
1
X
X
X
64/32
78000h - 7FFFFh
F0000h - FFFFFh
Note:
Address range is A18: A-1 in byte mode and A18: A0 in word mode. See the “Word/Byte Configuration” section for more
information
(October, 2011, Version 1.9)
7
AMIC Technology, Corp.
A29800 Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method
does not require VID. See "Command Definitions" for details
on using the autoselect mode.
Table 4. A29800 Autoselect Codes (High Voltage Method)
Description
Mode
Manufacturer ID: AMIC
Device ID: A29800
CE
OE
WE
A18
to
A12
A9
A8
to
A7
A6
A5
to
A2
A1
A0
I/O8
to
I/O15
I/O7
to
I/O0
L
L
H
X
X
VID
X
L
X
L
L
X
37h
L
L
H
X
X
VID
X
L
X
L
H
B3h
0Eh
X
0Eh
B3h
8Fh
X
8Fh
X
7Fh
X
01h
(protected)
X
00h
(unprotected)
Word
(Top Boot Block)
Byte
Device ID: A29800
Word
L
(Bottom Boot Block)
A11
to
A10
L
H
X
X
VID
X
L
X
L
H
Byte
Continuation ID
Sector Protection Verification
L
L
L
L
H
H
X
SA
X
X
VID
VID
X
X
L
L
X
X
H
H
H
L
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
(October, 2011, Version 1.9)
8
AMIC Technology, Corp.
A29800 Series
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
START
RESET = VID
(Note 1)
Hardware Data Protection
Perform Erase or
Program Operations
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
RESET = VIH
Write Pulse "Glitch" Protection
Temporary Sector
Unprotect
Completed (Note 2)
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Write cycles are inhibited by holding any one of OE =VIL, CE
= VIH or WE = VIH. To initiate a write cycle, CE and WE
Figure 1. Temporary Sector Unprotect Operation
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of
WE . The internal state machine is automatically reset to
reading array data on the initial power-up.
Temporary Sector Unprotect
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID.
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET pin, all the previously
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
(October, 2011, Version 1.9)
9
AMIC Technology, Corp.
A29800 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising
edge of WE or CE , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A read
cycle containing a sector address (SA) and the address 02h
in returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm. After
the device accepts an Erase Suspend command, the device
enters the Erase Suspend mode. The system can read array
data using the standard read timings, except that if it reads at
an address within erase-suspended sectors, the device
outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See "Erase
Suspend/Erase Resume Commands" for more information on
this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
(October, 2011, Version 1.9)
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE pin. Programming is a
four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the
programmed cell margin. Table 5 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O7, I/O6, or RY/ BY . See “White
Operation Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Not that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5
to “1”, or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
10
AMIC Technology, Corp.
A29800 Series
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
START
Write Program
Command
Sequence
Embedded
Program
algorithm in
progress
Data Poll
from System
Sector Erase Command Sequence
Verify Data ?
No
Yes
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations. The Command Definitions table shows the
address and data requirements for the chip erase command
sequence.
(October, 2011, Version 1.9)
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase timeout of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50μs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50μs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
11
AMIC Technology, Corp.
A29800 Series
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the
50μs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
"don't cares" when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 30μs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete, the
system can once again read array data within non-suspended
sectors. The system can determine the status of the program
operation using the I/O7 or I/O6 status bits, just as in the
standard program operation. See "Write Operation Status" for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
(October, 2011, Version 1.9)
START
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
12
AMIC Technology, Corp.
A29800 Series
Cycles
Table 5. A29800 Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 5)
First
Addr Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Word
Autoselect (Note 8)
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Continuation ID
Sector Protect Verify
(Note 9)
Byte
4
Word
Byte
4
Word
Byte
Word
4
4
AAA
555
AA
AA
AAA
555
555
2AA
555
2AA
55
55
55
555
AA
2AA
555
AAA
555
AAA
555
90
X00
90
X01 B30E
X02 0E
90
X01 B38F
AAA
55
555
X02
90
X03
37
8F
7F
555
AAA
X06
Word
555
2AA
555
(SA) XX00
X02 XX01
4
Byte
Byte
4
6
Word
Byte
AA
AAA
Word
Sector Erase
555
2AA
AAA
Word
Chip Erase
AAA
AA
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Byte
Byte
Program
555
Second
Addr Data
6
555
AAA
555
AAA
555
AAA
55
555
AA
AA
AA
Erase Suspend (Note 9)
1
XXX
B0
Erase Resume (Note 10)
1
XXX
30
2AA
555
2AA
555
2AA
555
90
AAA
55
55
55
555
AAA
555
AAA
555
AAA
A0
80
80
00
(SA)
X04
01
PA
PD
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
(October, 2011, Version 1.9)
13
AMIC Technology, Corp.
A29800 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ BY are provided in
the A29800 to determine the status of a write operation.
Table 6 and the following subsections describe the functions
of these status bits. I/O7, I/O6 and RY/ BY each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
Yes
I/O7 = Data ?
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2μs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
( OE ) is asserted low. The Data Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 6 shows the outputs for Data
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Polling on I/O7. Figure 4 shows the Data Polling algorithm.
(October, 2011, Version 1.9)
PASS
Figure 4. Data Polling Algorithm
14
AMIC Technology, Corp.
A29800 Series
RY/ BY : Read/ Busy
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequence. Since
RY/ BY is an open-drain output, several RY/ BY pins can be
tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 6 shows the outputs for RY/ BY . Refer to “ RESET
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use OE and CE to control the read
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
(October, 2011, Version 1.9)
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use OE and CE to control the read cycles.) But
I/O2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. I/O6, by comparison, indicates
whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs for
I/O2 and I/O6.
Figure 5 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 5 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O7 - I/O0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
5).
15
AMIC Technology, Corp.
A29800 Series
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
START
Read I/O7-I/O0
Read I/O7-I/O0
(Note 1)
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time between
additional sector erase commands will always be less than
50μs. See also the "Sector Erase Command Sequence"
section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 6 shows the outputs for I/O3.
Toggle Bit
= Toggle ?
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 5. Toggle Bit Algorithm
(October, 2011, Version 1.9)
16
AMIC Technology, Corp.
A29800 Series
Table 6. Write Operation Status
I/O7
Operation
I/O6
(Note 1)
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspend Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 2)
I/O2
RY/ BY
(Note 1)
I/O7
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
I/O7
Toggle
0
N/A
N/A
0
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
(October, 2011, Version 1.9)
20ns
17
AMIC Technology, Corp.
A29800 Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Parameter Description
Symbol
ILI
Input Load Current
ILIT
A9, OE & RESET Input Load Current
Test Description
VCC = VCC Max,
A9, OE & RESET =12.5V
VOUT = VSS to VCC. VCC = VCC Max
ILO
Output Leakage Current
ICC3
VCC Active Read Current
(Notes 1, 2)
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
VCC Standby Current (Note 2)
VIL
Input Low Level
VIH
VCC = 5.25 V
VOL
Input High Level
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VOH
Output High Voltage
IOH = -2.5 mA, VCC = VCC Min
VID
Typ.
VIN = VSS to VCC. VCC = VCC Max
ICC1
ICC2
Min.
Max.
Unit
±1.0
μA
100
μA
±1.0
μA
CE = VIL, OE = VIH
20
30
mA
CE = VIL, OE =VIH
30
40
mA
CE = VIH, RESET = VCC ± 0.5V
0.4
1.0
mA
-0.5
0.8
V
2.0
VCC+0.5
V
10.5
12.5
V
0.45
V
IOL = 12mA, VCC = VCC Min
2.4
V
CMOS Compatible
Parameter
Parameter Description
Symbol
ILI
Input Load Current
ILIT
A9, OE & RESET Input Load Current
ILO
Output Leakage Current
ICC1
VCC Active Read Current
(Notes 1,2)
VCC Active Program/Erase Current
(Notes 2,3,4)
VCC Standby Current (Notes 2, 5)
ICC2
ICC3
VIL
VIH
VID
VOL
VOH1
VOH2
Input Low Level
Input High Level
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
Test Description
Min.
Typ.
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max,
A9, OE & RESET = 12.5V
VOUT = VSS to VCC, VCC = VCC Max
Max.
Unit
±1.0
μA
50
μA
±1.0
μA
CE = VIL, OE = VIH
20
30
mA
CE = VIL, OE = VIH
30
40
mA
CE = RESET = VCC ± 0.5 V
1
5
μA
-0.5
0.7 x VCC
0.8
VCC+0.3
V
V
10.5
12.5
V
VCC = 5.25 V
IOL = 12.0 mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
IOH = -100 μA. VCC = VCC Min
0.45
0.85 x VCC
VCC-0.4
V
V
V
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20μA max at extended temperatures (> +85°C).
(October, 2011, Version 1.9)
18
AMIC Technology, Corp.
A29800 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 2)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tOEH
Test Setup
Speed
Unit
-55
-70
-90
Min.
55
70
90
ns
CE = VIL
OE = VIL
Max.
55
70
90
ns
OE = VIL
Max.
55
70
90
ns
Output Enable to Output Delay
Max.
30
30
35
ns
Output Enable Hold
Read
Min.
0
0
0
ns
Time (Note 2)
Toggle and
Data Polling
Min.
10
10
10
ns
Max.
18
20
20
ns
18
20
20
ns
0
0
0
ns
tEHQZ
tDF
Chip Enable to Output High Z
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1,2)
tAXQX
tOH
Output Hold Time from Addresses,
CE or OE , Whichever Occurs First
Min.
Notes:
1. Output driver disable time.
2. Not 100% tested.
(October, 2011, Version 1.9)
19
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
High-Z
Output Valid
RESET
0V
RY/BY
AC Characteristics
Hardware Reset ( RESET )
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
μs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
RESET Pulse Width
RESET High Time Before Read (See Note)
RY/ BY Recovery Time
Min
500
ns
Min
50
ns
Min
0
ns
tRP
tRH
tRB
Note: Not 100% tested.
(October, 2011, Version 1.9)
20
AMIC Technology, Corp.
A29800 Series
RESET Timings
RY/BY
CE, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE, OE
~
~
RESET
tRP
(October, 2011, Version 1.9)
21
AMIC Technology, Corp.
A29800 Series
Temporary Sector Unprotect
Parameter
JEDEC
Description
All Speed Options
Unit
Std
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET Setup Time for Temporary Sector
Unprotect
Min
4
μs
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
~
~
12V
0 or 5V
0 or 5V
RESET
tVIDR
tVIDR
Program or Erase Command Sequence
CE
~
~
WE
~ ~
~
~
tRSP
RY/BY
AC Characteristics
Word/Byte Configuration ( BYTE )
Parameter
JEDEC
All Speed Options
Description
Std
-55
-70
Unit
-90
CE to BYTE Switching Low or High
Max
tFLQZ
BYTE Switching Low to Output High-Z
Max
20
20
20
ns
tFHQV
BYTE Switching High to Output Active
Min
55
70
90
ns
tELFL/tELFH
(October, 2011, Version 1.9)
22
5
ns
AMIC Technology, Corp.
A29800 Series
BYTE Timings for Read Operations
CE
OE
BYTE
tELFL
BYTE
Switching
from word to
byte mode
Data Output
(I/O 0-I/O 14)
I/O0-I/O14
I/O 15
Output
I/O15 (A-1)
Data Output
(I/O 0-I/O 7)
Address Input
tFLQZ
tELFH
BYTE
BYTE
Switching
from byte to
word mode
I/O0-I/O14
Data Output
(I/O 0-I/O 7)
I/O15 (A-1)
Address Input
Data Output
(I/O 0-I/O 14)
I/O 15
Output
tFHQV
BYTE Timings for Write Operations
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
tHOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
(October, 2011, Version 1.9)
23
AMIC Technology, Corp.
A29800 Series
AC Characteristics
Erase and Program Operations
Description
Parameter
Unit
Speed
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVWL
tAS
Address Setup Time
Min.
tWLAX
tAH
Address Hold Time
Min.
45
45
45
ns
tDVWH
tDS
Data Setup Time
Min.
25
30
45
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
Read Recover Time Before Write
Min.
0
ns
tGHWL
tGHWL
-55
-70
-90
55
70
90
0
ns
ns
( OE high to WE low)
tELWL
tCS
CE Setup Time
Min.
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
tWHWL
tWPH
Write Pulse Width High
Min.
20
Byte
Typ.
7
tWHWH1
tWHWH1
Word
Typ.
12
Sector Erase Operation (Note 2)
Typ.
1
sec
tvcs
VCC Set Up Time (Note 1)
Min.
50
μs
tRB
Recovery Time from RY/ BY
Min
0
ns
Program/Erase Valid to RY/ BY Delay
Min
tWHWH2
tWHWH2
tBUSY
Byte Programming Operation
(Note 2)
30
35
45
ns
ns
μs
30
30
35
ns
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(October, 2011, Version 1.9)
24
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Program Operation
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
PA
555h
PA
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
tAH
CE
tCH
~
~
tGHWL
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
Data
A0h
tDH
PD
~
~
tDS
tBUSY
Status
DOUT
tRB
~
~ ~
~
RY/BY
tVCS
VCC
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
(October, 2011, Version 1.9)
25
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
SA
2AAh
VA
555h for chip erase
tAH
VA
~
~ ~
~
Addresses
Read Status Data
CE
~
~
tGHWL
tCH
OE
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
55h
tDH
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
(October, 2011, Version 1.9)
26
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Data Polling (During Embedded Algorithms)
~
~
tRC
Addresses
VA
tACC
CE
VA
~
~ ~
~
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
I/O0 - I/O6
Status Data
~
~
Complement
Complement
True
Valid Data
~
~
High-Z
I/O7
Status Data
True
Valid Data
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
(October, 2011, Version 1.9)
27
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
~
~
tRC
Addresses
VA
VA
tACC
CE
VA
~
~ ~
~
VA
tCE
tCH
tOE
~
~
OE
tDF
~
~
tOEH
WE
I/O6 , I/O2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
~
~
tOH
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
(October, 2011, Version 1.9)
28
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for I/O2 vs. I/O6
~
~
~
~
Erase
Complete
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Erase
~
~
Erase Suspend
Read
~
~
I/O2
Erase
Suspend
Program
Erase Suspend
Read
~
~
I/O6
Erase
Resume
~
~
Erase
Enter Erase
Suspend Program
~
~
WE
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate CE Controlled Writes
Parameter
Speed
Description
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVEL
tAS
Address Setup Time
Min.
Unit
-55
-70
-90
55
70
90
0
ns
ns
tELAX
tAH
Address Hold Time
Min.
40
45
45
ns
tDVEH
tDS
Data Setup Time
Min.
25
30
45
ns
tEHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
( OE High to WE Low)
Min.
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
CE Pulse Width
Min.
30
35
45
ns
tEHEL
tCPH
CE Pulse Width High
Min.
20
20
20
ns
tWHWH1
tWHWH1
tWHWH2
tWHWH2
Programming Operation
(Note 2)
Byte
Typ.
7
Word
Typ.
12
Typ.
1
Sector Erase Operation (Note 2)
μs
sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(October, 2011, Version 1.9)
29
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Alternate CE Controlled Write Operation ( RESET =VIH on A29800)
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
tAS
tAH
tWH
~
~
tWC
~
~
Addresses
WE
~
~
tGHEL
OE
tWHWH1 or 2
~
~
tCP
tBUSY
tCPH
CE
tWS
tDS
~
~
tDH
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
I/O7
DOUT
~
~
Data
RESET
~
~
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Typ. (Note 1)
Max. (Note 2)
Unit
Sector Erase Time
1.0
8
sec
Chip Erase Time (Note 3)
11
Byte Programming Time
7
300
μs
Word Programming Time
12
500
μs
sec
Chip Programming Time
Byte Mode
7.2
21.6
sec
(Note 3)
Word Mode
6.3
18.6
sec
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(October, 2011, Version 1.9)
30
AMIC Technology, Corp.
A29800 Series
Latch-up Characteristics
Description
Input Voltage with respect to VSS on all I/O pins
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
(including A9, OE and RESET )
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
TSOP and SOP Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
Typ.
Max.
Unit
VIN=0
6
7.5
pF
VOUT=0
8.5
12
pF
VIN=0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
(October, 2011, Version 1.9)
31
AMIC Technology, Corp.
A29800 Series
Test Conditions
Test Specifications
Test Condition
-55
Output Load
All others
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
Input Pulse Levels
0.0 - 3.0
0.45 - 2.4
V
Input timing measurement reference levels
1.5
0.8, 2.0
V
Output timing measurement reference levels
1.5
0.8, 2.0
V
Test Setup
5.0 V
2.7 KΩ
Device
Under
Test
CL
(October, 2011, Version 1.9)
Diodes = IN3064 or Equivalent
6.2 KΩ
32
AMIC Technology, Corp.
A29800 Series
Ordering Information
Top Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (μA)
A29800TM-55F
Package
44Pin Pb-Free SOP
A29800TM-55IF
44Pin Pb-Free SOP
55
20
30
1
A29800TV-55F
48Pin Pb-Free TSOP
A29800TV-55IF
48Pin Pb-Free TSOP
A29800TM-70F
44Pin Pb-Free SOP
A29800TM-70IF
44Pin Pb-Free SOP
70
20
30
1
A29800TV-70F
48Pin Pb-Free TSOP
A29800TV-70IF
48Pin Pb-Free TSOP
A29800TM-90F
44Pin Pb-Free SOP
A29800TM-90IF
44Pin Pb-Free SOP
90
20
30
1
A29800TV-90F
48Pin Pb-Free TSOP
A29800TV-90IF
48Pin Pb-Free TSOP
Note: -I is for industrial operating temperature range: -40°C to +85°C
(October, 2011, Version 1.9)
33
AMIC Technology, Corp.
A29800 Series
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (μA)
A29800UM-55F
A29800UM-55IF
Package
44Pin Pb-Free SOP
55
20
30
1
44Pin Pb-Free SOP
A29800UV-55F
48Pin Pb-Free TSOP
A29800UV-55IF
48Pin Pb-Free TSOP
A29800UM-70F
44Pin Pb-Free SOP
A29800UM-70IF
70
20
30
1
44Pin Pb-Free SOP
A29800UV-70F
48Pin Pb-Free TSOP
A29800UV-70IF
48Pin Pb-Free TSOP
A29800UM-90F
44Pin Pb-Free SOP
A29800UM-90IF
90
20
30
1
44Pin Pb-Free SOP
A29800UV-90F
48Pin Pb-Free TSOP
A29800UV-90IF
48Pin Pb-Free TSOP
Note: -I is for industrial operating temperature range: -40°C to +85°C
(October, 2011, Version 1.9)
34
AMIC Technology, Corp.
A29800 Series
Package Information
SOP 44L Outline Dimensions
unit: inches/mm
23
Gauge Plane
HE
E
44
θ
L
0.010"
1
b 22
Detail F
e
y
A
A1
S
D
A2
C
D
L1
Seating Plane
See Detail F
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.118
-
-
3.00
A1
0.004
-
-
0.10
-
-
A2
0.103
0.106
0.109
2.62
2.69
2.77
b
0.013
0.016
0.020
0.33
0.40
0.50
C
0.007
0.008
0.010
0.18
0.20
0.25
D
-
1.122
1.130
-
28.50
28.70
E
0.490
0.496
0.500
12.45
12.60
12.70
e
-
0.050
-
-
1.27
-
HE
0.620
0.631
0.643
15.75
16.03
16.33
L
0.024
0.032
0.040
0.61
0.80
1.02
L1
-
0.0675
-
-
1.71
-
S
-
-
0.045
-
-
1.14
y
-
-
0.004
-
-
0.10
θ
0°
-
8°
0°
-
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(October, 2011, Version 1.9)
35
AMIC Technology, Corp.
A29800 Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
1
48
24
25
y
D1
A1
A2 A
D
0.25
c
S
e
E
b
D
Detail "A"
L
θ
Detail "A"
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.042
0.94
1.00
1.06
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.12
-
0.20
D
0.779
0.787
0.795
19.80
20.00
20.20
D1
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.472
0.476
-
12.00
12.10
e
L
0.020 BASIC
0.020
S
0.024
0.50 BASIC
0.0275
0.50
0.011 Typ.
0.60
0.70
0.28 Typ.
y
-
-
0.004
-
-
0.10
θ
0°
-
8°
0°
-
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(October, 2011, Version 1.9)
36
AMIC Technology, Corp.
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