Download datasheet for AOZ8001A-05 by Alpha and Omega Semiconductor

Download datasheet for AOZ8001A-05 by Alpha and Omega Semiconductor

AOZ8001A

Ultra-Low Capacitance TVS Diode Array

General Description

The AOZ8001A is a transient voltage suppressor array designed to protect high speed data lines from ESD and lightning.

This device incorporates four surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4.

The TVS diodes provide effective suppression of ESD voltages up to ±30kV (air discharge) and ±30kV (contact discharge).

The AOZ8001A comes in RoHS compliant, SOT-143 package and is rated over a -40°C to +85°C ambient temperature range. It is compatible with both lead free and SnPb assembly techniques.

The very small SOT-143 package is ideal for applications where PCB space is a premium. The small size, low capacitance and high ESD protection makes it ideal for protecting high speed video and data communication interfaces.

Features

ESD protection for high-speed data lines:

AOZ8001AJI 5V:

– IEC 61000-4-2, level 4 (ESD) immunity test

– ±30kV (air discharge) and ±30kV (contact discharge)

– IEC 61000-4-5 (Lightning) 18A (8/20µs)

– Human Body Model (HBM) ±30kV

AOZ8001AJI 12V:

– IEC61000-4-2, Level 4 (ESD) immunity test

– ±30kV (air discharge) and ±30kV (contact discharge)

– IEC61000-4-5 (Lightning) ±13A (8/20µs)

– Human Body Model (HBM) ±30kV

Small package saves board space

Low insertion loss

Protects two I/O lines

Low capacitance from IO to Ground: 1.8pF

Low clamping voltage

Low operating voltages: 5V, 12V

Applications

USB 2.0 power and data line protection

Video graphics cards

Monitors and flat panel displays

Digital Video Interface (DVI)

10/100/1000 Ethernet

Notebook computers

Typical Application

USB Controller

+5V

D+

D-

GND

1

4

USB Controller

+5V

D+

D-

GND

Tip

RJ11

Connector

2 3

AOZ8001AJI-05

Figure 1. USB 2.0 High Speed Port

Rev. 3.0 October 2010

Ring

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+12V

1

2

AOZ8001AJI-12

+12V

+12V

xDSL

Controller

Figure 2. xDSL Application

Page 1 of 10

AOZ8001A

Ordering Information

Part Number

AOZ8001AJI-05

AOZ8001AJI-12

Ambient Temperature Range

-40°C to +85°C

-40°C to +85°C

Package

SOT-143

SOT-143

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp

for additional information.

Pin Configuration

4

VP

VN

1

Environmental

RoHS Compliant

Green Product

RoHS Compliant

Green Product

CH1 2

SOT-143

(Top View)

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage the device.

Parameter

Storage Temperature (T

S

)

3

CH2

Rating

-65°C to +150°C

Maximum Transient Rating

Device

AOZ8001AJI-05

AOZ8001AJI-12

HBM

(1)

±30kV

±30kV

ESD (Contact)

±30kV

±30KV

(2)

ESD (Air)

±30kV

±30kV

(2)

Notes:

1. Human Body Discharge per MIL-STD-883, Method 3015 C

Discharge

= 100pF, R

Discharge

= 1.5k

2. IEC 61000-4-2 discharge with C

Discharge

= 150pF, R

Discharge

= 330

.

.

Maximum Operating Ratings

Parameter

Junction Temperature (T

J

)

Surge (8/20µs)

±18A

±13A

Rating

-40°C to +125°C

Rev. 3.0 October 2010

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Page 2 of 10

AOZ8001A

Electrical Characteristics

T

A

= 25°C unless otherwise specified.

Symbol Parameter

I

PP

V

CL

(5)(7)

V

RWM

(3)

I

R

V

BR

(4)

I

F

V

F

P

PK

C

J

(6)

Reverse Peak Pulse Current

Clamping Voltage @ I

PP

Working Peak Reverse Voltage

Maximum Reverse Leakage Current @ V

RWM

Breakdown Voltage

Forward Current

Forward Voltage

Peak Power Dissipation

I/O–GND Capacitance @ V

R

= 0 and f = 1MHz

V

CL

V

BR

V

RWM

Diagram

I

F

I

I

R

I

T

V

F

I

PP

V

Device

AOZ8001AJI-05

AOZ8001AJI-12

Device

Marking

AD

AD

V

RWM

(V)

Max.

5.5

12.5

V

BR

(V)

Typ. @

1mA

8.5

15.0

I

R

(µA)

Max.

1.0

1.0

V

F

(V)

Typ.

0.85

0.85

V

CL

Max.

I

PP

= 1A I

PP

= 5A I

PP

= 12A

12.50

16.00

15.00

18.00

16.00

19.00

C

J

(pF)

Typ.

1.80

1.80

C

J

(pF)

Max.

2.50

2.50

Notes:

3. The working peak reverse voltage, V

RWM

, should be equal to or greater than the DC or continuous peak operating

voltage level.

4. V

BR

is measured at the pulse test current I

T

.

5. Measurements performed with no external capacitor on V

P

(pin 4 floating).

6. Measurements performed with V

P

biased to 3.3 Volts (pin 4 @ 3.3V).

7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.

Rev. 3.0 October 2010

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Page 3 of 10

AOZ8001A

Typical Performance Characteristics

4

2

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0 1

Typical Variation of C

(V

P

IN

vs V

o

R

= 3.3V, f = 1MHz, T = 25 C)

2

5V

8 3 4 5 6

Input Voltage (V)

7

12V

9 10

6

Forward Voltage vs. Forward Current

(t period

= 100ns, t r

= 1ns)

0

0 2 4 6 8

Forward Current (A)

10 12 14

0

-20

-40

-60

-80

-100

-120

1

Crosstalk (I/O–I/O) vs. Frequency

10000 10 100

Frequency (MHz)

1000

20

18

16

14

12

10

8

6

4

2

0

0

Clamping Voltage vs. Peak Pulse Current

(t period

= 100ns, t r

= 1ns)

12V

5V

5 10

Peak Pulse Current, I

PP

(A)

15

5

I/O – Gnd Insertion Loss (S21) vs. Frequency

0

-5

-10

-15

-20

-25

1 10 100

Frequency (MHz)

1000 1000

-5

-10

-15

-20

5

0

-25

1

I/O – I/O Insertion Loss (S21) vs. Frequency

10 100

Frequency (MHz)

1000 1000

Rev. 3.0 October 2010

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Page 4 of 10

AOZ8001A

Application Information

The AOZ8001A TVS is design to protect two data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection.

PCB Layout Guidelines

Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines.

The location of the protection devices on the PCB is the simplest and most important design rule to follow. The

AOZ8001A devices should be located as close as possible to the noise source. The placement of the AOZ8001A devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8001A devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8001A device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces.

The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8001A ultralow capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry.

Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended:

1.

Place the TVS near the IO terminals or connectors to restrict transient coupling.

2.

Fill unused portions of the PCB with ground plane.

3.

Minimize the path length between the TVS and the protected line.

4.

Minimize all conductive loops including power and ground loops.

5.

The ESD transient return path to ground should be kept as short as possible.

6.

Never run critical signals near board edges.

7.

Use ground planes whenever possible.

8.

Avoid running critical signal traces (clocks, resets, etc.) near PCB edges.

9.

Separate chassis ground traces from components and signal traces by at least 4mm.

10. Keep the chassis ground trace length-to-width ratio

<5:1 to minimize inductance.

11. Protect all external connections with TVS diodes.

Rev. 3.0 October 2010

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Page 5 of 10

Rev. 3.0 October 2010

1

AOZ8001A

VCC

4

2

3

VCC

Reset

Clock

I/O

GND

3 2

VCC

4

AOZ8001A

1

SIM Card Port Connection

SIM

TPBIASx

TPAx+

TPAx-

IEEE 1394

PHY

TPBx+

TPBx-

GND

4

AOZ8001A

3

4

1 2

3

IEEE 1394

Connector

1

AOZ8001A

2

IEEE1394 Port Connection

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AOZ8001A

Page 6 of 10

4

AOZ8001A

3

TRD0+

TRD0-

1 2

4

AOZ8001A

3

TRD1+

TRD1-

Ethernet

Controller

TRD2+

TRD2-

1 2

4

AOZ8001A

3

1 2

4

AOZ8001A

3

TRD3+

TRD3-

1 2

10/100 Ethernet Port Connection

RJ45

Connector

AOZ8001A

Rev. 3.0 October 2010

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Page 7 of 10

Package Dimensions, SOT143-4L

D e

S

E e1 b2 b

E1

A1

A c

θ

L1

AOZ8001A

RECOMMENDED LAND PATTERN

0.70

0.70

1.05

0.76

1.92

0.60

1.90

UNIT: mm

Dimensions in millimeters

Symbols

A

A1 b b2 c

D

E

E1 e e1

L1

S

θ

Min.

0.890

0.013

0.370

Nom.

Max.

1.120

0.100

0.510

0.760

0.085

2.800

2.100

1.200

——

1.920 BSC

0.200 BSC

0.940

0.180

3.040

2.640

1.400

0.450

0.550 REF

0.600

Notes:

1. All dimensions are in millimeters.

2. Tolerances are 0.10mm unless otherwise specified.

3. Package body sizes exclude mold flash and gate burrs.

4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

Dimensions in inches

Symbols

A

A1 b b2 c

D

E

E1 e e1

L1

S

θ

Min.

0.035

0.001

0.015

Nom.

Max.

0.044

0.004

0.020

0.030

0.003

0.110

0.083

0.047

——

0.076 BSC

0.008 BSC

0.037

0.007

0.120

0.104

0.055

0.018

0.022 REF

0.024

Rev. 3.0 October 2010

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Page 8 of 10

AOZ8001A

Tape and Reel Dimensions, SOT143-4L

Tape

P1

D0

P2

D1

E1

K0

E2

E

B0

P0

A0

T

UNIT: mm

Package

SOT-143

A0 B0

3.10

2.69

± 0.10

± 0.10

K0

1.30

± 0.10

Feeding Direction

D0 D1 E

1.50

±

0.10

1.00

+0.25/-0.00

8.00

+0.30/-0.10

E1

1.75

± 0.10

E2

3.50

± 0.05

P0

4.00

± 0.10

P1

4.00

± 0.10

P2

2.00

± 0.05

T

0.254

± 0.013

Reel

W1

S

K

R

M

N

J

H

UNIT: mm

Tape Size

8mm

Reel Size

ø177.8

M

ø177.8

Max.

N

55.0

Min.

W1 H

8.4

+1.50 / -0.0

13.0

+0.5 / -0.2

S

1.5

Min

K

10.1

Min.

R

12.7

J

4.0

± 0.1

Leader/Trailer and Orientation

Trailer Tape

300mm min.

Rev. 3.0 October 2010

Components Tape

Orientation in Pocket

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Leader Tape

500mm min.

Page 9 of 10

Part Marking

AOZ8001AJI

(SOT-143)

Top Marking

ADOA

Part Number Code

Option Code

Assembly Location Code

Bottom Marking

YWLT

Year & Week Code

Assembly Lot Code

AOZ8001A

This datasheet contains preliminary data; supplementary data may be published at a later date.

Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Rev. 3.0 October 2010

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Page 10 of 10

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