AD9268 16-bit | AD9258 14-bit | AD9251 40 | AD9251 20 | AD9231 12-bit | AD9204 10-bit | AD9251 65 | Data Sheet | Analog Devices AD9251, AD9251 80, 65, 40, 20 Dual Analog-to-Digital Converter, AD9268, 16-bit, AD9258, 14-bit, AD9231, 12-bit, AD9204, 10-bit ADC Datasheet 36 Pages
AD9268 16-bit | AD9258 14-bit | AD9251 40 | AD9251 20 | AD9231 12-bit | AD9204 10-bit | AD9251 65 | Data Sheet | Analog Devices AD9251, AD9251 80, 65, 40, 20 Dual Analog-to-Digital Converter, AD9268, 16-bit, AD9258, 14-bit, AD9231, 12-bit, AD9204, 10-bit ADC Datasheet
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Below you will find brief information for AD9251 80, AD9251 65, AD9251 40, AD9251 20. The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
advertisement
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9251
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
33 mW per channel at 20 MSPS
73 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.45 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
FUNCTIONAL BLOCK DIAGRAM
AVDD GND SDIO SCLK CSB
REF
SELECT
ADC
ADC
DIVIDE
1 TO 8
AD9251
SPI
PROGRAMMING DATA
DUTY CYCLE
STABILIZER
MODE
CONTROLS
ORA
D13A
D0A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
CLK+ CLK– SYNC DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1.
The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
3.
A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes.
4.
The AD9251 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD9251
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9251-80 .................................................................................. 13
AD9251-65 .................................................................................. 15
AD9251-40 .................................................................................. 16
AD9251-20 .................................................................................. 17
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 20
ADC Architecture ...................................................................... 20
Analog Input Considerations .................................................... 20
REVISION HISTORY
10/09—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Change to Table 1 ............................................................................. 4
Moved Timing Diagrams................................................................. 8
Deleted Table 11; Renumbered Sequentially .............................. 22
Changes to Internal Reference Connection Section .................. 23
Moved Channel/Chip Synchronization Section ......................... 26
Change to Table 15 ......................................................................... 30
Changes to Reading the Memory Map Register
Table Section ................................................................................... 31
Changes to Table 16 ........................................................................ 32
7/09—Revision 0: Initial Version
Rev. A | Page 2 of 36
Voltage Reference ....................................................................... 23
Clock Input Considerations ...................................................... 24
Channel/Chip Synchronization ................................................ 26
Power Dissipation and Standby Mode .................................... 26
Digital Outputs ........................................................................... 27
Timing ......................................................................................... 27
Built-In Self-Test (BIST) and Output Test .................................. 28
Built-In Self-Test (BIST) ............................................................ 28
Output Test Modes ..................................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table ............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
GENERAL DESCRIPTION
The AD9251 is a monolithic, dual-channel, 1.8 V supply,
14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-andhold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
AD9251
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.
The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
Rev. A | Page 3 of 36
AD9251
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 1.
RESOLUTION
ACCURACY
No Missing Codes
Full 14
Full
AD9251-20/AD9251-40 AD9251-65 AD9251-80
Min Typ Max Min Typ Max Unit
14 14 Bits
Differential Nonlinearity (DNL) 2
Full
Full
±0.60 ±0.75
±1.75 ±1.75
MATCHING
TEMPERATURE DRIFT
Voltage Mode) Full 0.981 0.993 1.005
Load Regulation Error at 1.0 mA Full 2
Input Span, VREF = 1.0 V
Full 2
Full
1.3
0.981 0.993 1.005 0.981 0.993 1.005 V
2 2 mV
2 2 V p-p
6 6 pF
0.5 1.3 0.5 1.3 V
AVDD
DRVDD
Supply Current
Full 1.7 1.8 1.9
Full 1.7 3.6
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 3.6 1.7 3.6 V
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK active.
Rev. A | Page 4 of 36
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
AD9251
Table 2.
SIGNAL-TO-NOISE (SNR) f
IN
= 9.7 MHz f
IN
= 30.5 MHz f
IN
= 70 MHz f
IN
= 200 MHz
Temp
AD9251-20/AD9251-40 AD9251-65 AD9251-80
Min Typ Max Min Typ Max Min Typ Max Unit
25°C 74.7 74.5 74.3 dBFS
25°C 74.4 74.3 74.1 dBFS
73.6 dBFS
25°C 73.7 73.7 73.6 dBFS
Full dBFS
25°C 71.5 71.5 71.5 dBFS f
IN
= 9.7 MHz f
IN
= 30.5 MHz f
IN
= 70 MHz f
IN
= 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB) f
IN
= 9.7 MHz f
IN
= 30.5 MHz f
IN
= 70 MHz f
IN
= 200 MHz
25°C
25°C
25°C
25°C
25°C
74.6 74.4
12.0
12.0
11.9
11.3
74.1
12.0
12.0
11.9
11.3 dBFS
25°C
25°C
74.3 74.2 74.0 dBFS
73.4 dBFS
73.6 73.6 73.5 dBFS
Full dBFS
25°C 70.0
12.0
12.0
11.9
11.3
70.0 70.0 dBFS
Bits
Bits
Bits
Bits
WORST SECOND OR THIRD HARMONIC f f f
IN
IN
= 9.7 MHz
= 30.5 MHz f
IN
= 70 MHz
IN
= 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
25°C
25°C
−95
−95
−95
−95
−93
−93 dBc dBc
Full −81
25°C −94 −94 −92 dBc
Full dBc
25°C −80 −80 −80 dBc
25°C
25°C
95
94
95
94
93
93 dBc dBc
Full dBc
WORST OTHER (HARMONIC OR SPUR) f f f f f
IN
= 9.7 MHz f
IN
= 30.5 MHz
IN
IN
IN
= 70 MHz
= 200 MHz
= 9.7 MHz f
IN
= 30.5 MHz f
IN
= 70 MHz
IN
= 200 MHz
25°C 93 93 92 dBc
Full dBc
25°C 80 80 80 dBc
25°C −98 −98 −97 dBc
25°C
25°C
−98
−98
Full −90
−98 −97 dBc
−98 −96 dBc
Full dBc
25°C −95 −95 −95 dBc f
IN
= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc
ANALOG BANDWIDTH
1 See the AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation
, for a complete set of definitions.
2
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. A | Page 5 of 36
AD9251
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 3.
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, I
OH
= 50 µA
High Level Output Voltage, I
OH
= 0.5 mA
Low Level Output Voltage, I
OL
= 1.6 mA
Low Level Output Voltage, I
OL
= 50 µA
DRVDD = 1.8 V
High Level Output Voltage, I
OH
= 50 µA
High Level Output Voltage, I
OH
= 0.5 mA
Low Level Output Voltage, I
OL
= 1.6 mA
Low Level Output Voltage, I
OL
= 50 µA
1 Internal 30 kΩ pull-down.
2
Internal 30 kΩ pull-up.
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
0
−10
40
1.2
0
−50
−10
1.2
−10
−10
8
0.2
GND − 0.3
3.29
3.25
1.79
1.75
1.2
0
−10
40
26
5
26
2
30
2
10
4
CMOS/LVDS/LVPECL
0.9
AD9251-20/AD9251-40/AD9251-65/AD9251-80
Max
3.6
AVDD + 0.2
+10
+10
12
0.8
+10
135
DRVDD + 0.3
0.8
−75
+10
DRVDD + 0.3
0.2
0.05
0.2
0.05
DRVDD + 0.3
0.8
+10
130
V
µA
µA kΩ pF
V
V
µA
µA kΩ pF
V
Unit
V
V p-p
V
µA
µA kΩ pF
V
V
V
V
V
V
V
V
V
V
µA
µA kΩ pF
Rev. A | Page 6 of 36
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
AD9251
Table 4.
AD9251-20/AD9251-40 AD9251-65 AD9251-80
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
CLK Period—Divide-by-1 Mode (t
CLK
) Full 50/25
CLK Pulse Width High (t
CH
)
Aperture Delay (t
A
) Full
25.0/12.5
1.0
7.69 6.25
0.1 ns
1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full
DATA OUTPUT PARAMETERS
Data Propagation Delay (t
PD
) Full 3
DCO Propagation Delay (t
DCO
) Full
DCO to Data Skew (t
SKEW
) Full
Pipeline Delay (Latency)
Full
Full
3
9
350
625
3
3
0.1
9
625
9
625 MHz
Cycles
350 350 µs
Standby Full
Full
600/400
2
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
300 260 ns
2 2 Cycles
Rev. A | Page 7 of 36
AD9251
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS t
SSYNC t
HSYNC
SPI TIMING REQUIREMENTS t
DS t
DH t
CLK t
S t
H t
HIGH t
LOW t
EN_SDIO t
DIS_SDIO
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge
Timing Diagrams
N – 1
N t
A
N + 3
VIN
N + 1
N + 2 t
CH t
CLK
CLK+
CLK– t
DCO
DCOA/DCOB
CH A/CH B DATA t
SKEW
N – 9 N – 8 t
PD
Figure 2. CMOS Output Data Timing
N – 7
N – 1
N t
A
N + 3
VIN
N + 1
N + 2 t
CH t
CLK
CLK+
CLK– t
DCO
DCOA/DCOB
CH A/CH B DATA
Min Typ
0.24
0.40
Max Unit
ns ns
2
2
40
2
2
10 ns ns ns ns ns ns
10 ns
10 ns
10 ns
N + 4
N – 6
N + 4 t
SKEW
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7 t
PD
Figure 3. CMOS Interleaved Output Timing
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N + 5
N – 5
N + 5
Rev. A | Page 8 of 36
CLK+
SYNC t
SSYNC t
HSYNC
Figure 4. SYNC Input Timing Requirements
AD9251
Rev. A | Page 9 of 36
AD9251
ABSOLUTE MAXIMUM RATINGS
Table 6.
AVDD to AGND
DRVDD to AGND
VIN+A, VIN+B, VIN−A, VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB to AGND
PDWN to AGND
D0A/D0B through D13A/D13B to AGND
DCOA/DCOB to AGND
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range (Ambient)
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the AGND plane of the user’s circuit board. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package.
Typical θ
JA
is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θ
JA
. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θ
JA
.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP 0
Airflow
Velocity
(m/sec) θ
23
θ
2.0
θ
Unit
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
ESD CAUTION
Rev. A | Page 10 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK+
CLK–
SYNC
NC
NC
(LSB) D0B
D1B
D2B
D3B
DRVDD
D4B
D5B
D6B
D7B
D8B
D9B
11
12
13
14
15
16
8
9
6
7
10
3
4
1
2
5
PIN 1
INDICATOR
AD9251
TOP VIEW
(Not to Scale)
38
37
36
35
34
33
43
42
41
40
39
48
47
46
45
44
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A
AD9251
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 5. Pin Configuration
Table 8. Pin Function Description
Pin No.
0
1, 2
3
4, 5, 25, 26
6 to 9, 11 to 18, 20, 21
10, 19, 28, 37
22
23
24
27, 29 to 36, 38 to 42
43
Mnemonic
GND
CLK+, CLK−
Description
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
SYNC
NC
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Do Not Connect.
D0B to D13B Channel B Digital Outputs. D13B = MSB.
DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
ORB
DCOB
DCOA
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
D0A to D13A Channel A Digital Outputs. D13A = MSB.
ORA Channel A Out-of-Range Digital Output.
46 CSB down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
49, 50, 53, 54, 59, 60, 63, 64 AVDD
51, 52
1.8 V Analog Supply Pins.
VIN+A, VIN−A Channel A Analog Inputs.
Rev. A | Page 11 of 36
AD9251
Pin No.
55
56
57
58
61, 62
Mnemonic Description
VREF
SENSE
VCM
RBIAS
Voltage Reference Input/Output.
Reference Mode Selection.
Analog output voltage at midsupply to set common mode of the analog inputs.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
VIN−B, VIN+B Channel B Analog Inputs.
Rev. A | Page 12 of 36
AD9251
TYPICAL PERFORMANCE CHARACTERISTICS
AD9251-80
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
0
–15
0
–15
80MSPS
30.5MHz @ –1dBFS
SNR = 73.2dB (74.2dBFS)
SFDR = 93.6dBc
–30
–30
80MSPS
9.7MHz @ –1dBFS
SNR = 73.4dB (74.4dBFS)
SFDR = 94.4dBc
–45
–45
–60
–60
–75
–75
–90
–90 3
–105
2
6
3
5
4
–105
5
2
6 4
–120
–120
4 8 12 16 20 24
FREQUENCY (MHz)
28 32
Figure 6. Single-Tone FFT with f
IN
= 9.7 MHz
36
4 8 12 16 20 24
FREQUENCY (MHz)
28 32
Figure 9. Single-Tone FFT with f
IN
= 30.5 MHz
36
0
–15
–30
80MSPS
70.3MHz @ –1dBFS
SNR = 72.1dB (73.1dBFS)
SFDR = 93.5dBc
0
–15
80MSPS
200MHz @ –1dBFS
SNR = 70.5dB (71.5dBFS)
SFDR = 80.2dBc
–30
–45
–45
–60
–60
–75
–90
–105
2
6
3
5
4
–75
2
–90
4
6
–105
5
3
–120
4 8 12 16 20 24
FREQUENCY (MHz)
28 32
Figure 7. Single-Tone FFT with f
IN
= 70.3 MHz
36
0
–15
80MSPS
30.5MHz @ –7dBFS
32.5MHz @ –7dBFS
SFDR = 89.5dBc (96.5dBFS)
–30
–120
0
–20
4 8 12 16 20 24
FREQUENCY (MHz)
28 32
Figure 10. Single-Tone FFT with f
IN
= 200 MHz
36
SFDR (dBc)
–45
–40
–60
IMD3 (dBc)
–60
–75
–90
F2 – F1
2F1 + F2
2F2 + F1
F1 + F2
2F2 – F1
2F1 – F2
–105
–120
4 8 12 16 20 24
FREQUENCY (MHz)
28 32 36
Figure 8. Two-Tone FFT with f
IN1
= 30.5 MHz and f
IN2
= 32.5 MHz
–80
SFDR (dBFS)
–100
IMD3 (dBFS)
–120
–90 –78 –66 –54 –42 –30
INPUT AMPLITUDE (dBFS)
–18 –6
Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f
IN1
=
30.5 MHz and f
IN2
= 32.5 MHz
Rev. A | Page 13 of 36
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
0.4
0.3
0.2
AD9251
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
100
120
90
SFDR (dBc)
SFDRFS
100
80
70
SNR (dBFS)
80
60
50
60
SNRFS
SFDR
40
30
20
40
SNR
20
10
0
0 50 100
INPUT FREQUENCY (MHz)
150 200
Figure 12. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale
0
–90 –80 –60 –40
INPUT AMPLITUDE (dBFS)
–20 0
Figure 15. SNR/SFDR vs. Input Amplitude (AIN) with f
IN
= 9.7 MHz
120 450,000
400,000
SFDR (dBc)
100
350,000
SNR (dBFS)
80
60
40
20
0
10 20 30 40 50
SAMPLE RATE (MSPS)
60 70
Figure 13. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz
80
300,000
250,000
200,000
150,000
100,000
50,000
0
N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4
OUTPUT CODE
Figure 16. Grounded Input Histogram
2.0
2048 4096 6144 8192 10,240 12,288 14,336 16,384
OUTPUT CODE
Figure 14. DNL Error with f
IN
= 9.7 MHz
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
OUTPUT CODE
Figure 17. INL with f
IN
= 9.7 MHz
Rev. A | Page 14 of 36
AD9251
AD9251-65
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
0 120
–15
65MSPS
9.7MHz @ –1dBFS
SNR = 73.5dB (74.5dBFS)
SFDR = 97.7dBc
100
SFDRFS
–30
80
–45
SNRFS
–60
60
SFDR
–75
40
–90
SNR
3
6
5
2
4
–105
20
–120
0
–15
–30
–45
–60
–75
–90
–105
3 6 9 12 15 18 21
FREQUENCY (MHz)
24 27
Figure 18. Single-Tone FFT with f
IN
= 9.7 MHz
30
2
3
65MSPS
70.3MHz @ –1dBFS
SNR = 72.6dB (73.6dBFS)
SFDR = 94.1dBc
4
5
–120
3 6 9 12 15 18 21
FREQUENCY (MHz)
24 27
Figure 19. Single-Tone FFT with f
IN
= 70.3 MHz
30
0
–15
65MSPS
30.5MHz @ –1dBFS
SNR = 73.3dB (74.3dBFS)
SFDR = 99.3dBc
–30
6
0
–90 –80 –60 –40
INPUT AMPLITUDE (dBFS)
–20 0
Figure 21. SNR/SFDR vs. Input Amplitude (AIN) with f
IN
= 9.7 MHz
100
90
80
70
60
50
40
30
20
10
SFDR (dBc)
SNR (dBFS)
0
0 50 100
INPUT FREQUENCY (MHz)
150
Figure 22. SNR/SFDR vs. Input Frequency (AIN) with
2 V p-p Full Scale
200
–45
–60
–75
–90
–105
–120
2
4 6
5
3
3 6 9 12 15 18 21
FREQUENCY (MHz)
24 27
Figure 20. Single-Tone FFT with f
IN
= 30.5 MHz
30
Rev. A | Page 15 of 36
AD9251
AD9251-40
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
120 0
–15
40MSPS
9.7MHz @ –1dBFS
SNR = 73.5dB (74.5dBFS)
SFDR = 95.4dBc
–30
100
SFDRFS
80
–45
SNRFS
–60
60
SFDR
–75
40
–90
SNR
–105
4
5
3 6
2
20
–120
2 4 6 8 10 12
FREQUENCY (MHz)
14 16
Figure 23. Single-Tone FFT with f
IN
= 9.7 MHz
18
0
–15
40MSPS
30.5MHz @ –1dBFS
SNR = 73.2dB (74.2dBFS)
SFDR = 95.7dBc
–30
0
–90 –80 –60 –40
INPUT AMPLITUDE (dBFS)
–20 0
Figure 25. SNR/SFDR vs. Input Amplitude (AIN) with f
IN
= 9.7 MHz
–45
–60
–75
–90
–105
–120
4 5 3
6
2
2 4 6 8 10 12
FREQUENCY (MHz)
14 16
Figure 24. Single-Tone FFT with f
IN
= 30.5 MHz
18
Rev. A | Page 16 of 36
AD9251
AD9251-20
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
120 0
–15
20MSPS
9.7MHz @ –1dBFS
SNR = 73.5dBFS (74.5dBFS)
SFDR = 97.2dBc
–30
100
SFDR (dBFS)
SNR (dBFS)
–45
80
–60
60
SFDR (dBc)
–75
–90
40
SNR (dBc)
2
4
6 5
3
–105
20
–120
950k 1.90
2.85
3.80
4.75
5.70 6.65 7.60
8.55
9.50
FREQUENCY (MHz)
Figure 26. Single-Tone FFT with f
IN
= 9.7 MHz
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
0
Figure 28. SNR/SFDR vs. Input Amplitude (AIN) with f
IN
= 9.7 MHz
0
–15
20MSPS
30.5MHz @ –1dBFS
SNR = 73.2dB (74.2dBFS)
SFDR = 98.1dBc
–30
–45
–60
–75
–90
–105
–120
2
4 6 5
3
950k 1.90
2.85
3.80
4.75
5.70 6.65 7.60
8.55
9.50
FREQUENCY (MHz)
Figure 27. Single-Tone FFT with f
IN
= 30.5 MHz
Rev. A | Page 17 of 36
AD9251
EQUIVALENT CIRCUITS
AVDD
VIN±x
Figure 29. Equivalent Analog Input Circuit
CLK+
5
Ω
5
Ω
15k
Ω
0.9V
15k
Ω
CLK–
Figure 30. Equivalent Clock Input Circuit
AVDD
SDIO/DCS
DRVDD
350
Ω
30k
Ω
30k
Ω
Figure 31. Equivalent SDIO/DCS Input Circuit
DRVDD
Figure 32. Equivalent Digital Output Circuit
SCLK/DFS, SYNC,
OEB, AND PDWN
DRVDD
350
Ω
30k
Ω
Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit
AVDD
RBIAS
AND VCM
375
Ω
Figure 34. Equivalent RBIAS, VCM Circuit
Rev. A | Page 18 of 36
DRVDD
350
Ω
AVDD
30k
Ω
CSB
Figure 35. Equivalent CSB Input Circuit
AVDD
375
Ω
SENSE
Figure 36. Equivalent SENSE Circuit
AVDD
VREF
375
Ω
7.5k
Ω
Figure 37. Equivalent VREF Circuit
AD9251
Rev. A | Page 19 of 36
AD9251
THEORY OF OPERATION
The AD9251 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f
S
/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to
300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion.
In nondiversity applications, the AD9251 can be used as a baseband or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data.
Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices.
Programming and control of the AD9251 is accomplished using a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9251 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9251 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
H
VIN+x
C
PAR
H
S
S
C
SAMPLE
C
SAMPLE
S
S
VIN–x
C
PAR
H
H
Figure 38. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 38). When the input circuit
is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application.
Rev. A | Page 20 of 36
AD9251
Input Common Mode
The analog inputs of the AD9251 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as
shown in Figure 39 and Figure 40.
An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described
in the Applications Information section.
100
SFDR (dBc)
VIN
76.8
Ω
200
Ω
33
Ω
VIN–x
AVDD
90
Ω
ADA4938 10pF
ADC
0.1µF
120
Ω
33
Ω
VIN+x
VCM
200
Ω
Figure 41. Differential Input Configuration Using the ADA4938-2
For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer-coupling is the recommended
input configuration. An example is shown in Figure 42. To bias
the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.
R
VIN+x
2V p-p
49.9
Ω
C
ADC
90
R
VCM
VIN–x
80
70
60
SNR (dBFS)
50
0.5
0.6
0.7
0.8
0.9
1.0
1.1
INPUT COMMON-MODE VOLTAGE (V)
1.2
Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, f
IN
= 32.1 MHz, f
S
= 80 MSPS
1.3
0.1µF
Figure 42. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9251. For applications above
~10 MHz where SNR is a key parameter, differential double balun
coupling is the recommended input configuration (see Figure 44).
100
90
80
70
SFDR (dBc)
SNR (dBFS)
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 45. See the AD8352 data sheet
for more information.
In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to
be reduced or removed. Table 9 displays the suggested values to set
the RC network. However, these values are dependent on the input signal and should be used only as a starting guide.
60
50
0.5
0.6
0.7
0.8
0.9
1.0
1.1
INPUT COMMON-MODE VOLTAGE (V)
1.2
Figure 40. SNR/SFDR vs. Input Common-Mode Voltage, f
IN
= 10.3 MHz, f
S
= 20 MSPS
1.3
Table 9. Example RC Network
Frequency Range (MHz)
R Series
(Ω Each) C Differential (pF)
0 to 70
70 to 200
33
125
22
Open
Differential Input Configurations
Optimum performance is achieved while driving the AD9251 in a differential input configuration. For baseband applications, the
AD8138 , ADA4937-2 , and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9251 (see Figure 41), and the
driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
Rev. A | Page 21 of 36
AD9251
Single-Ended Input Configuration
A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 43
shows a typical single-ended input configuration.
2V p-p
0.1µF
P
A
1V p-p
49.9
Ω
10µF
10µF AVDD
1k
Ω
R
0.1µF
1k
Ω
AVDD
1k
Ω
R
C
0.1µF
1k
Ω
VIN+x
VIN–x
ADC
Figure 43. Single-Ended Input Configuration
S S
0.1µF
25
Ω
P
0.1µF
25
Ω
R
0.1µF
R
C
Figure 44. Differential Double Balun Input Configuration
VIN+x
VIN–x
ADC
VCM
ANALOG INPUT
C
D
ANALOG INPUT
0.1µF
R
D
0
Ω
0.1µF
0
Ω
R
G
3
4
5
16
1
2
V
CC
8, 13
11
AD8352
10
14
0.1µF
0.1µF
0.1µF
0.1µF
R
200
Ω
C
200
Ω
R
0.1µF
Figure 45. Differential Input Configuration Using the AD8352
VIN+x
VIN–x
ADC
VCM
Rev. A | Page 22 of 36
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9251. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9251 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 46), setting VREF to 1.0 V.
VIN+A/VIN+B
VIN–A/VIN–B
If the internal reference of the AD9251 is used to drive multiple converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 47 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
INTERNAL V
REF
= 0.993V
AD9251
–2.5
–3.0
0 0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
LOAD CURRENT (mA)
Figure 47. V
REF
Accuracy vs. Load Current
1.8
2 .0
ADC
CORE
1.0µF
VREF
0.1µF
SENSE
SELECT
LOGIC
0.5V
ADC
Figure 46. Internal Reference Configuration
Table 10. Reference Configuration Summary
Selected Mode
Fixed Internal Reference
Fixed External Reference
SENSE Voltage (V) Resulting VREF (V)
AGND to 0.2
AVDD
1.0 internal
1.0 applied to external VREF pin
Resulting Differential Span (V p-p)
2.0
2.0
Rev. A | Page 23 of 36
AD9251
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 48 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
0
–1
–2
–3
–4
3
2
1
V
REF
ERROR (mV)
–5
–6
–40 –20 0 20 40
TEMPERATURE (°C)
Figure 48. Typical V
REF
Drift
60 80
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 37). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9251 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally
(see Figure 49) and require no external bias.
AVDD
0.9V
CLK+ CLK–
2pF 2pF
Figure 49. Equivalent Clock Input Circuit
Clock Input Options
The AD9251 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Figure 50 and Figure 51 show two preferred methods for clock-
ing the AD9251 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9251 to approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9251 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.
CLOCK
INPUT
0.1µF
50
Ω
Mini-Circuits
®
ADT1-1WT, 1:1 Z
0.1µF
XFMR
100
Ω
0.1µF
CLK+
ADC
CLK–
0.1µF
SCHOTTKY
DIODES:
HSMS2822
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
1nF 0.1µF
CLOCK
INPUT
CLK+
50
Ω
1nF
0.1µF
ADC
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)
Rev. A | Page 24 of 36
If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 52. The
AD9510 / AD9511 / AD9512 /
AD9513 / AD9514 / AD9515 / AD9516/AD9517 clock drivers offer excellent jitter performance.
0.1µF 0.1µF
CLOCK
INPUT
0.1µF
AD951x
PECL DRIVER
100
Ω
0.1µF
CLK+
ADC
CLK–
CLOCK
INPUT
50k
Ω
50k
Ω
240
Ω
240
Ω
Figure 52. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.
0.1µF 0.1µF
CLOCK
INPUT
0.1µF
AD951x
LVDS DRIVER
100
Ω
0.1µF
CLK+
ADC
CLOCK
INPUT
50k
Ω
50k
Ω
CLK–
Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see
CLOCK
INPUT
50
0.1µF
V
CC
1k
Ω
AD951x
CMOS DRIVER
Ω
1 1k
Ω
OPTIONAL
100
Ω
0.1µF
CLK+
ADC
CLK–
0.1µF
1
50
Ω
RESISTOR IS OPTIONAL.
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
AD9251
Input Clock Divider
The AD9251 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8.
Optimum performance is obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
The AD9251 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.
The AD9251 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9251. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS
Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal.
80
DCS ON
75
70
55
50
65
60
45
40
10
DCS OFF
70 20 30 40 50 60
POSITIVE DUTY CYCLE (%)
Figure 55. SNR vs. DCS On/Off
80
Rev. A | Page 25 of 36
AD9251
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNR
LF
) at a given input frequency (f
INPUT
) due to jitter (t
JRMS
) can be calculated by
SNR
HF
= −10 log[(2π × f
INPUT
× t
JRMS
)
2
+ 10
(
−
SNR
LF
/ 10 )
]
In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 56.
80
75
70
65
0.05ps
0.2ps
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = V
DRVDD
× C
LOAD
× f
CLK
× N where N is the number of output bits (30, in the case of the
AD9251).
This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of f
CLK
/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
150
60 0.5ps
55
1.0ps
130
50
45
1
3.0ps
1.5ps
2.0ps
2.5ps
10 100
FREQUENCY (MHz)
Figure 56. SNR vs. Input Frequency and Jitter
1k
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9251.
To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.
See the AN-501 Application Note and the AN-756 Application
Note available on www.analog.com
for more information.
CHANNEL/CHIP SYNCHRONIZATION
The AD9251 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the analog core power dissipated by
the AD9251 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit.
Rev. A | Page 26 of 36
110
90
70
AD9251-65
AD9251-40
AD9251-80
AD9251-20
50
0 10 20 30 40 50
CLOCK RATE (MSPS)
60
Figure 57. Analog Core Power vs. Clock Rate
70 80
The AD9251 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2.2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9251 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD9251 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of traces required.
The CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI , the data format can be selected for offset binary, twos complement, or gray code when using the SPI control.
Table 11. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin SCLK/DFS
AGND
DRVDD
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9251 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
AD9251 data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output disable (OEB) bit (Bit 4) in Register 0x14.
TIMING
The AD9251 provides latched data with a pipeline delay of
9 clock cycles. Data outputs are available one propagation delay
(t
PD
) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9251. These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9251 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9251 provides two data clock output (DCO) signals intended for capturing the data in an external register. The CMOS data outputs are valid on the rising edge of the DCO, unless the
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
0
0
1
OR
1
0
Rev. A | Page 27 of 36
AD9251
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9251 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9251 is included. Various output test options are also provided to place predictable values on the outputs of the AD9251.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9251 signal path. Perform the BIST test after a reset to ensure the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops.
Once completed, the BIST compares the signature results with a pre-determined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying the test passed. If the BIST test fails,
Bit 0 of Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs.
Writing the value 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in
Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user needs to rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address
0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI .
Rev. A | Page 28 of 36
SERIAL PORT INTERFACE (SPI)
The AD9251 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields,
which are documented in the Memory Map section. For
detailed operational information, see AN-877 Application
Note, Interfacing to High Speed ADCs via SPI .
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK, the SDIO, and
the CSB (see Table 13). The SCLK (a serial clock) is used to
synchronize the read and write data presented from and to the
ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles.
Table 13. Serial Port Interface Pins
Pin Function
SCLK Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame.
CSB Chip Select Bar. An active-low control that gates the read and write cycles.
t
S t
DS t
DH t
HIGH t
LOW t
CLK
CSB
SCLK DON’T CARE
SDIO DON’T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 58 and
Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits as shown in Figure 58.
All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.
In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI .
t
H
AD9251
DON’T CARE
D5 D4 D3 D2 D1 D0
DON’T CARE
Figure 58. Serial Port Interface Timing Diagram
Rev. A | Page 29 of 36
AD9251
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the programming device of the user and the serial port of the AD9251. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Appli- cation Note, Microcontroller-Based Serial Port Interface
(SPI) Boot Circuit .
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9251 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
SDIO/DCS and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
AVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9251.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
Table 14. Mode Selection
Pin
External
Voltage Configuration
SDIO/DCS AVDD (default)
AGND
SCLK/DFS AVDD
AGND (default)
OEB
PDWN
AVDD
AGND (default)
AVDD
AGND (default)
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or standby
Normal operation
SPI ACCESSIBLE FEATURES
Table 15 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI . The AD9251 part-specific features are described in
Table 15. Features Accessible Using the SPI
Feature Description
Mode
Clock
Offset
Test I/O
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
Rev. A | Page 30 of 36
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table (see Table 16) has
eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to
Address 0x02); the device index and transfer registers (Address
0x05 and Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address
0x101).
Table 16 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the Channel Index register, has a hexadecimal default value of 0x03. This means that in Address
0x05 Bit[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
This document details the functions controlled by Register 0x00 to register 0xFF. The remaining registers, Register 0x100 and
Register 0x101, are documented in the Memory Map Register
Descriptions section following Table 16.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written.
AD9251
DEFAULT VALUES
After the AD9251 is reset, critical registers are loaded with default values. The default values for the registers are given in
the memory map register table (see Table 16).
Logic Levels
An explanation of logic level terminology follows:
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
•
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate
Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an
SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels.
The settings in Register 0x05 do not affect the global registers and bits.
Rev. A | Page 31 of 36
AD9251
MEMORY MAP REGISTER TABLE
Table 16.
Address
(Hex)
Register
Name
Chip Configuration Registers
0x00 SPI port configuration
(global)
Bit 7
(MSB) Bit 6 Bit 5
first
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
Bit 0
(LSB)
LSB first 0
Default
Value
(Hex) Comments
0x01 Chip ID (global)
(global)
8-bit chip ID bits [7:0]
AD9251 = 0x23
Open Speed grade ID 6:4
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
0x18 The nibbles are mirrored so that LSB- or
MSB-first mode registers correctly, regardless of shift mode
Unique chip ID used to differentiate devices; read only grade ID used to differentiate devices; read only
Device Index and Transfer Registers
0x05
0xFF Transfer
Program Registers (May or May Not Be Indexed by Device Index)
0x08
0x09
0x0B
Channel index
Modes
Clock (global)
Clock divide
(global)
Open
Open Open
External powerdown enable
(local)
Open
Open
Open
External pin function
0x00 full powerdown
0x01 standby
(local)
Open
Open
Open
Open
Open Open
Open
Open
Open Open ADC B default
ADC A default
0x03 Bits are set to determine which device on chip receives the next write command; the default is all devices on chip transfers data from the master shift register to the slave
Open
Clock divider [2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
00 = chip run
01 = full powerdown
10 = standby
11 = chip wide digital reset
(local)
Open Duty cycle stabilize
0x80 Determines various generic modes of chip operation
0x00
0x00 The ratio is the value plus 1
Rev. A | Page 32 of 36
AD9251
Address
(Hex)
0x0D
0x14
0x15
0x16
Register
Name
Test mode (local)
0x0E BIST
(local)
Output mode
OUTPUT_ADJUST
OUTPUT_PHASE
Bit 7
(MSB)
(local)
00 = single
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Output mux enable
(interleaved)
Output disable
(local)
Open Output invert
(local)
00 = offset binary
01 = twos complement
10 = gray code
11 = offset binary
(local)
3.3 V DCO drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO output polarity
0 = normal
1 = inverted
(local)
1.8 V DCO drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
3.3 V data drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
Input clock phase adjust [2:0]
(Value is number of input clock cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO delay
Bit 6 Bit 5
User test mode
01 = alternate
10 = single once
11 = alternate once
Reset PN long gen
Open data delay
Bit 4
Reset PN short gen
Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1x sync
1011 = one bit high
1100 = mixed bit frequency
INIT
Open BIST enable
Default
Value
(Hex) Comments
0x00 When set, the test data is placed on the output pins in place of normal data
0x00 When Bit 0 is set, the BIST function is initiated
DCO/Data delay [2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
0x00 trim outputs and the format of the data
0x22 Determines
CMOS output drive strength properties
On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock; internal latching is unaffected
This sets the fine output delay of the output clock but does not change internal timing
0x19 USER_PATT1_LSB
0x1A USER_PATT1_MSB pattern, 1 LSB
B12 B11 0x00 User-defined pattern, 1 MSB
0x1B USER_PATT2_LSB
0x1C
0x24
USER_PATT2_MSB
MISR_LSB pattern, 2 LSB
B12 B11 0x00 User-defined pattern, 2 MSB
0x00 Least significant byte of MISR; read only
Rev. A | Page 33 of 36
AD9251
Address
(Hex)
0x2A
Register
Name
Features
0x2E Output assign
Digital Feature Control
(global)
Bit 7
(MSB) Bit 6 Bit 5
Open Open Open
Bit 4
Open
0x101 USR2
OEB
Pin 47
(local)
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI .
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high and the device is operating in continuous sync mode as long as Bit 2 of the sync control is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Open
Bit 3
Open
Bit 2
Open
Enable
GCLK detect divider next sync only
Run
GCLK
Bit 1
Open
Bit 0
(LSB)
(local)
0 = ADC A
1 = ADC B
(local)
Default
Value
(Hex) Comments
0x01
Ch A =
0x00
Ch B =
0x01
Disable the OR pin for the indexed channel
Assign an ADC to an output channel
Clock divider sync enable
Master sync enable
0x01
Open Disable 0x88 Enables
SDIO pulldown internal oscillator for clock rates <
5 MHz
USR2 (Register 0x101)
Bit 7—Enable OEB Pin 47
Normally set high, this bit allows Pin 47 to function as the output enable. If it is set low, it disables Pin 47.
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled ensuring the proper operation of several circuits. If set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus.
Rev. A | Page 34 of 36
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9251 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9251, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies.
Locate these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9251. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance is easily achieved.
Exposed Paddle Thermal Heat Sink Recommendations
The exposed paddle (Pin 0) is the only ground connection for the AD9251; therefore, it must be connected to analog ground
(AGND) on the PCB of the customer. To achieve the best electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9251 exposed paddle, Pin 0.
AD9251
The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP) , at www.analog.com
.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 42.
RBIAS
The AD9251 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the
AD9251 to keep these signals from transitioning at the converter inputs during critical sampling periods.
Rev. A | Page 35 of 36
AD9251
OUTLINE DIMENSIONS
9.00
BSC SQ
0.60
MAX
48
49
0.60 MAX
64
1
PIN 1
INDICATOR
PIN 1
INDICATOR
TOP VIEW
8.75
BSC SQ
0.50
BSC
EXPOSED PAD
(BOTTOM VIEW)
6.35
6.20 SQ
6.05
1.00
0.85
0.80
SEATING
PLANE
12° MAX
0.50
0.40
0.30
33
32 17
16
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
1 Z = RoHS Compliant Part.
2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.
Package Option
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07938-0-10/09(A)
Rev. A | Page 36 of 36
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Key Features
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- Differential input with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- Serial port control options
- Energy-saving power-down modes
- Data clock out with programmable clock and data alignment
- Built-in selectable digital test pattern generation
