Download datasheet for ADP1829 by Analog Devices Inc.

Download datasheet for ADP1829 by Analog Devices Inc.

FEATURES

Fixed frequency operation: 300 kHz, 600 kHz, or synchronized operation up to 1 MHz

Supply input range: 3.0 V to 20 V

Wide power stage input range: 1 V to 24 V

Interleaved operation results in smaller, low cost input capacitor

All-N-channel MOSFET design for low cost

±0.85% accuracy at 0°C to 70°C

Soft start, thermal overload, current-limit protection

10 µA shutdown supply current

Internal linear regulator

Lossless R

DSON

current-limit sensing

Reverse current protection during soft start for handling precharged outputs

Independent Power OK outputs

Voltage tracking for sequencing or DDR termination

Available in 5 mm × 5 mm, 32-lead LFCSP

APPLICATIONS

Telecommunications and networking systems

Medical imaging systems

Base station power

Set-top boxes

Printers

DDR termination

GENERAL DESCRIPTION

The ADP1829 is a versatile, dual, interleaved, synchronous

PWM buck controller that generates two independent output rails from an input of 3.0 V to 20 V, with power input voltage ranging from 1.0 V to 24 V. Each controller can be configured to provide output voltages from 0.6 V to 85% of the input voltage and is sized to handle large MOSFETs for point-of-load regulators. The two channels operate 180° out of phase, reducing stress on the input capacitor and allowing smaller, low cost components. The ADP1829 is ideal for a wide range of high power applications, such as DSP and processor core I/O power, and general-purpose power in telecommunications, medical imaging, PC, gaming, and industrial applications.

The ADP1829 operates at a pin-selectable, fixed switching frequency of either 300 kHz or 600 kHz, minimizing external component size and cost. For noise-sensitive applications, it can also be synchronized to an external clock to achieve switching

Dual, Interleaved, Step-Down

DC-to-DC Controller with Tracking

ADP1829

1.2V,

6A

560µF

V

IN

= 12V

TYPICAL APPLICATION CIRCUIT

180µF

180µF

1µF

PV IN

TRK1

TRK2

VREG

EN1

EN2

BST2

BST1 0.47µF

0.47µF

IRLR7807Z

2.2µH

2k

2k

IRFR3709Z

DH1

DH2

ADP1829

IRLR7807Z

SW1

SW2

CSL2

DL2

2k

CSL1

DL1

PGND1

PGND2

FB2

IRFR3709Z

390pF

FB1

COMP2

2.2µH

2k

1k

390pF

2k

4.53k

3900pF

COMP1

FREQ

GND

LDOSD

SYNC

3900pF 4.53k

1.8V,

8A

560µF

Figure 1. frequencies between 300 kHz and 1 MHz. The ADP1829 includes soft start protection to prevent inrush current from the input supply during startup, reverse current protection during soft start for precharged outputs, as well as a unique adjustable lossless current-limit scheme utilizing external MOSFET sensing.

For applications requiring power supply sequencing, the

ADP1829 also provides tracking inputs that allow the output voltages to track during startup, shutdown, and faults. This feature can also be used to implement DDR memory bus termination.

The ADP1829 is specified over the −40°C to +125°C junction temperature range and is available in a 32-lead LFCSP package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.

ADP1829

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications ....................................................................................... 1

 

Typical Application Circuit ............................................................. 1

 

General Description ......................................................................... 1

 

Revision History ............................................................................... 2

 

Specifications ..................................................................................... 3

 

Absolute Maximum Ratings ............................................................ 5

 

ESD Caution .................................................................................. 5

 

Functional Block Diagram .............................................................. 6

 

Pin Configuration and Function Descriptions ............................. 7

 

Typical Performance Characteristics ............................................. 9

 

Theory of Operation ...................................................................... 13

 

Input Power ................................................................................. 13

 

Start-Up Logic ............................................................................. 13

 

Internal Linear Regulator .......................................................... 13

 

Oscillator and Synchronization ................................................ 13

 

Error Amplifier ........................................................................... 14

 

Soft Start ...................................................................................... 14

 

Power OK Indicator ................................................................... 14

 

REVISION HISTORY

1/11—Rev. A to Rev. B

Changes to VREG Short-Circuit Current Parameter, Table 1 .... 3

Changes to Figure 3 and Table 3 ..................................................... 7

Added Exposed Paddle Notation to Outline Dimensions ........ 29

4/09—Rev. 0 to Rev. A

Changes to Features and General Description Sections .............. 1

Changes to IN Input Voltage; EN1, IN2 Input High Voltage;

EN1, EN2 Input Low Voltage; and EN1, EN2 Input Impedance to 5 V Zener Parameters, Table 1 ................................................... 3

Changes to Table 2 ............................................................................ 5

Changes to Table 3 ............................................................................ 7

Changes to Theory of Operation Section, Input Power Section, and Start-Up Logic Section ........................................................... 13

Changes to Ordering Guide .......................................................... 29

6/07—Revision 0: Initial Version

Tracking ....................................................................................... 14

 

MOSFET Drivers ........................................................................ 15

 

Current Limit .............................................................................. 15

 

Applications Information .............................................................. 16

 

Selecting the Input Capacitor ................................................... 16

 

Selecting the MOSFETs ............................................................. 17

 

Setting the Current Limit .......................................................... 18

 

Feedback Voltage Divider ......................................................... 18

 

Compensating the Voltage Mode Buck Regulator ................. 19

 

Soft Start ...................................................................................... 22

 

Voltage Tracking ......................................................................... 22

 

Coincident Tracking .................................................................. 23

 

Ratiometric Tracking ................................................................. 23

 

Thermal Considerations ............................................................ 24

 

PCB Layout Guidelines .................................................................. 25

 

LFCSP Package Considerations ................................................ 26

 

Application Circuits ....................................................................... 27

 

Outline Dimensions ....................................................................... 29

 

Ordering Guide .......................................................................... 29

 

Rev. B | Page 2 of 32

ADP1829

SPECIFICATIONS

IN = 12 V, ENx = FREQ = PV = VREG = 5 V, SYNC = GND, T

J

= −40°C to +125°C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T

A

= 25°C.

Table 1.

Parameter Conditions

POWER SUPPLY

IN Input Voltage

IN Quiescent Current

IN Shutdown Current

PV = VREG (using internal regulator)

IN = PV = VREG (not using internal regulator)

Not switching, I

VREG

EN1 = EN2 = GND

= 0 mA

VREG Undervoltage Lockout Hysteresis

ERROR AMPLIFIER

FB1, FB2 Regulation Voltage

FB1, FB2 Input Bias Current

Open-Loop Voltage Gain

Gain-Bandwidth Product

COMP1, COMP2 Sink Current

COMP1, COMP2 Source Current

COMP1, COMP2 Clamp High Voltage

COMP1, COMP2 Clamp Low Voltage

LINEAR REGULATOR

VREG Output Voltage

VREG Load Regulation

VREG Line Regulation

VREG Current Limit

VREG Short-Circuit Current

IN to VREG Dropout Voltage

1

VREG Minimum Output Capacitance

PWM CONTROLLER

PWM Ramp Voltage Peak

DH1, DH2 Maximum Duty Cycle

DH1, DH2 Minimum Duty Cycle

SOFT START

SS1, SS2 Pull-Up Resistance

SS1, SS2 Pull-Down Resistance

SS1, SS2 to FB1, FB2 Offset Voltage

SS1, SS2 Pull-Up Voltage

TRACKING

TRK1, TRK2 Common-Mode Input

Voltage Range

TRK1, TRK2 to FB1, FB2 Offset Voltage

TRK1, TRK2 Input Bias Current

T

A

= 25°C, TRK1, TRK2 > 700 mV

T

J

= 0°C to 85°C, TRK1, TRK2 > 700 mV

T

J

= −40°C to +125°C, TRK1, TRK2 > 700 mV

T

J

= 0°C to 70°C, TRK1, TRK2 > 700 mV

T

A

= 25°C, I

VREG

= 20 mA

IN = 7 V to 18 V, I

VREG

= 0 mA to 100 mA

I

VREG

= 0 mA to 100 mA, IN = 12 V

IN = 7 V to 18 V, I

VREG

= 20 mA

VREG = 4 V

VREG < 0.5 V

I

VREG

= 100 mA, IN < 5 V

SYNC = GND

FREQ = GND (300 kHz)

FREQ = GND (300 kHz)

SS1, SS2 = GND

SS1, SS2 = 0.6 V

SS1, SS2 = 0 mV to 500 mV

TRK1, TRK2 = 0 mV to 500 mV

5.5

3.0

20

5.5

V

V

1.5

10

3

20 mA

μA

2.4 2.7 3.0 V

0.125 V

597 600 603 mV

591

588

609 mV

612 mV

595 605 mV

70

20

600

120

2.4

0.75

100 nA dB

MHz

μA

μA

V

V

4.85 5.0 5.15 V

1

91

4.75 5.0

−40

1

220

−45

0.8

140

0.7

1.3

93

1

90

6

5.25 V mV mV mA

3

200 mA

1.4 V

μF

V

%

% kΩ kΩ mV

V

−5 +5 mV

100 nA

Rev. B | Page 3 of 32

ADP1829

Parameter Conditions

OSCILLATOR

Oscillator Frequency SYNC = FREQ = GND (f

SW

= f

OSC

) 240

SYNC Synchronization Range

2

SYNC = GND, FREQ = VREG (f

SW

= f

OSC

) 480

FREQ = GND, SYNC = 600 kHz to 1.2 MHz (f

SW

= f

SYNC

/2) 300 kHz

SYNC Minimum Input Pulse Width

CURRENT SENSE

CSL1, CSL2 Threshold Voltage

CSL1, CSL2 Output Current

Current Sense Blanking Period

FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (f

SW

= f

SYNC

/2) 600 kHz

Relative to PGND

CSL1, CSL2 = PGND

−30

44

0

50

100

200 ns

+30

56 mV

μA ns

GATE DRIVERS

DH1, DH2 Rise Time

DH1, DH2 Fall Time

DL1, DL2 Rise Time

C

DH

= 3 nF, V

BST

− V

SW

= 5 V

C

DH

= 3 nF, V

BST

− V

SW

= 5 V

C

DL

= 3 nF

DL1, DL2 Fall Time

DH to DL, DL to DH Dead Time

LOGIC THRESHOLDS

SYNC, FREQ, LDOSD Input High Voltage

C

DL

= 3 nF

2.2

10

40

15

10

15 ns ns

V ns ns ns

SYNC, FREQ, LDOSD Input Low Voltage

SYNC, FREQ Input Leakage Current

LDOSD Pull-Down Resistance

EN1, EN2 Input High Voltage

SYNC, FREQ = 0 V to 5.5 V

IN = 3.0 V to 20 V

EN1, EN2 Input Low Voltage

EN1, EN2 Current Source

IN = 3.0 V to 20 V

EN1, EN2 = 0 V to 3.0 V

EN1, EN2 Input Impedance to 5 V Zener EN1, EN2 = 5.5 V to 20 V

THERMAL SHUTDOWN

Thermal Shutdown Threshold

3

Thermal Shutdown Hysteresis

3

POWER GOOD

FB1, UV2 Overvoltage Threshold

FB1, UV2 Overvoltage Hysteresis

FB1, UV2 Undervoltage Threshold

FB1, UV2 Undervoltage Hysteresis

POK1, POK2 Propagation Delay

V

FB1,

V

UV2

rising

V

FB1,

V

UV2

rising

2.0

100

0.4

1

V

μA kΩ

V

0.8 V

−0.3 −0.6 −1.5 μA

100 kΩ

15

145

°C

°C

750 mV

50

550

50

8 mV mV mV

μs

POK1, POK2 Off Leakage Current

POK1, POK2 Output Low Voltage

UV2 Input Bias Current

V

POK1,

V

POK2

= 5.5 V

I

POK1,

I

POK2

= 10 mA 150

10

1 μA

500 mV

100 nA

1 Not recommended to use the LDO in dropout when V

IN

< 5.5 V because of the dropout voltage. Connect IN to VREG when V

IN

< 5.5 V.

2 SYNC input frequency is 2× single-channel switching frequency. The SYNC frequency is divided by 2 and the separate phases were used to clock the controllers.

3

Guaranteed by design and not subject to production test.

Rev. B | Page 4 of 32

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

IN, EN1, EN2 −0.3 V to +20.5 V

BST1, BST2

BST1, BST2 to SW1, SW2

CSL1, CSL2

SW1, SW2

DH1

DH2

DL1, DL2 to PGND

PGND to GND

−0.3 V to +30 V

−0.3 V to +6 V

−1 V to +30 V

−2 V to +30 V

SW1 − 0.3 V to BST1 + 0.3 V

SW2 − 0.3 V to BST2 + 0.3 V

−0.3 V to PV + 0.3 V

±2 V

LDOSD, SYNC, FREQ, COMP1,

COMP2, SS1, SS2, FB1, FB2, VREG,

PV, POK1, POK2, TRK1, TRK2

−0.3 V to +6 V

θ

JA

4-Layer

(JEDEC Standard Board)

1, 2

45°C/W

Operating Ambient Temperature −40°C < T

A

< +85°C

Operating Junction Temperature

3

<

Storage Temperature −65°C to +150°C

1

Measured with exposed pad attached to PCB.

2 Junction-to-ambient thermal resistance (θ

JA

) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is application and board-layout dependent. In applications where high maximum power dissipation exists, attention to thermal dissipation issues in board design is required. For more information, refer to

Application Note AN-772, A Design and Manufacturing Guide for the Lead

Frame Chip Scale Package (LFCSP) .

3 In applications where high power dissipation and poor package thermal resistance are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T

A_MAX

) is dependent on the maximum operating junction temperature (T

J_MAX_OP

= 125 o

C), the maximum power dissipation of the device in the application (P

D_MAX

), and the junctionto-ambient thermal resistance of the part/package in the application (θ

JA

) and is given by the following equation: T

A_MAX

= T

J_MAX_OP

– (θ

JA

× P

D_MAX

).

ADP1829

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 5 of 32

ADP1829

FUNCTIONAL BLOCK DIAGRAM

IN

VREG

LDOSD

EN1

EN2

FREQ

SYNC

COMP1

FB1

TRK1

SS1

COMP2

FB2

TRK2

UV2

SS2

ADP1829

LINEAR REG

0.6V

0.8V

REF

0.75V

0.55V

VREG

VREG

UVLO

THERMAL

SHUTDOWN

OSCILLATOR

PHASE 1 = 0°

PHASE 2 = 180°

0.6V

+

+

+

0.6V

+

+

+

0.8V

FAULT1

0.8V

LOGIC

ILIM2

CK1

S

PWM

Q

R Q

CK1

RAMP1

CK2

RAMP2

RAMP1

FAULT1 FAULT2

0.75V

0.55V

+

+

+

VREG

50µA

ILIM1

+

RAMP2

0.75V

CK2

VREG

50µA

ILIM2

S Q

R

PWM

Q

+

0.55V

+

+

+

FAULT2

PV

BST1

DH1

SW1

PV

DL1

PGND1

CSL1

POK1

BST2

DH2

SW2

DL2

PGND2

CSL2

POK2

GND

BOTTOM PADDLE

OF LFCSP

Figure 2.

Rev. B | Page 6 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP1829

FB1

SYNC

FREQ

GND

UV2

FB2

COMP2

TRK2

3

4

1

2

5

6

7

8

PIN 1

INDICATOR

ADP1829

TOP VIEW

(Not to Scale)

24 POK1

23 BST1

22 DH1

21 SW1

20 CSL1

19 PGND1

18 DL1

17 PV

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

3 FREQ the tap to FB1 to set the output voltage. and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.

Frequency Select Input. Low for 300 kHz or high for 600 kHz. this GND. directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.

7

9

COMP2

SS2 tie the tap to FB2 to set the output voltage.

Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2. voltage. If the tracking function is not used, connect TRK2 to VREG.

Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period. resistor from POK2 to VREG.

12

13

21

22

DH2

SW2

SW1

DH1 ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.

High-Side (Switch) Gate Driver Output for Channel 2.

Switch Node Connection for Channel 2.

15

16

PGND2

DL2 current-limit offset.

Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1829.

Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.

17 PV Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground with a 1 μF capacitor.

18

19

DL1

PGND1

Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.

Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1829. current-limit offset.

Switch Node Connection for Channel 1.

High-Side (Switch) Gate Driver Output for Channel 1.

Rev. B | Page 7 of 32

ADP1829

Pin No. Mnemonic Description

ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1. resistor from POK1 to VREG.

Enabling starts the internal LDO. Tie to IN for automatic startup.

Enabling starts the internal LDO. Tie to IN for automatic startup.

32

Otherwise, connect LDOSD to GND or leave it open, as it has an internal 100 kΩ pull-down resistor.

28 IN Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1829 from the LDO.

For input voltages between 3.0 V and 5.5 V, tie IN to VREG and PV.

30 SS1

Bypass VREG to ground plane with 1 μF ceramic capacitor.

Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.

COMP1

EPAD

If the tracking function is not used, connect TRK1 to VREG.

Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.

The exposed pad must be connected to AGND.

Rev. B | Page 8 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

95

V

IN

= 5V

V

IN

= 12V

90

85

80

75

V

IN

= 20V

V

IN

= 15V

70

0 5 10 15 2 0

LOAD CURRENT (A)

Figure 4. Efficiency vs. Load Current, V

OUT

= 1.8 V, 300 kHz Switching

95

90

V

OUT

= 3.3V

V

OUT

= 1.8V

85

80

75

V

OUT

= 1.2V

70

0 5 10 15 2 0

LOAD CURRENT (A)

Figure 5. Efficiency vs. Load Current, V

IN

= 12 V, 300 kHz Switching

84

82

80

90

88

94

92

SWITCHING FREQUENCY = 300kHz

86 SWITCHING FREQUENCY = 600kHz

78

0 5 10 15

LOAD CURRENT (A)

Figure 6. Efficiency vs. Load Current, V

IN

= 5 V, V

OUT

= 1.8 V

2 0

ADP1829

4.975

4.970

4.965

88

86

92

90

84

82

80

SWITCHING FREQUENCY = 300kHz

SWITCHING FREQUENCY = 600kHz

78

0 5 10 15

LOAD CURRENT (A)

Figure 7. Efficiency vs. Load Current, V

IN

= 12 V, V

OUT

= 1.8 V

2 0

4.980

4.960

–40 –15 10 35 60

TEMPERATURE (°C)

Figure 8. VREG Voltage vs. Temperature

85

4.970

4.968

4.966

4.964

4.962

4.960

4.958

4.956

4.954

4.952

4.950

5 8 11 14 17

INPUT VOLTAGE (V)

Figure 9. VREG vs. Input Voltage, 10 mA Load

2 0

Rev. B | Page 9 of 32

ADP1829

4.960

4.956

4.952

4.948

4.944

4.940

0 20 40 60

LOAD CURRENT (mA)

80

Figure 10. VREG vs. Load Current, V

IN

= 12 V

100

5

4

3

2

1

0

0 50 100 150 200

LOAD CURRENT (mA)

Figure 11. VREG Current-Limit Foldback

250

T

VREG, AC-COUPLED, 1V/DIV

SW1 PIN, V

OUT

= 1.8V, 10V/DIV

SW2 PIN, V

OUT

= 1.2V, 10V/DIV

200ns/DIV

Figure 12. VREG Output During Normal Operation

0.6010

0.6005

0.6000

0.5995

0.5990

0.5985

0.5980

–40 –15 10 35

TEMPERATURE (°C)

60

Figure 13. Feedback Voltage vs. Temperature, V

IN

= 12 V

85

330

320

310

300

290

280

270

260

–40 –15 10 35

TEMPERATURE (°C)

60

Figure 14. Switching Frequency vs. Temperature, V

IN

= 12 V

85

3

2

5

4

1

0

2 5 8 11 14

SUPPLY VOLTAGE (V)

17

Figure 15. Supply Current vs. Input Voltage

2 0

Rev. B | Page 10 of 32

T

V

OUT1

, AC-COUPLED,

100mV/DIV

LOAD ON

LOAD OFF LOAD OFF

100µs/DIV

Figure 16. 1.5 A to 15 A Load Transient Response, V

IN

= 12 V

T

SS1, 0.5V/DIV

V

OUT1

, 0.5V/DIV

INPUT CURRENT, 0.2A/DIV

SHORT CIRCUIT APPLIED

4ms/DIV

SHORT CIRCUIT REMOVED

Figure 17. Output Short-Circuit Response

T

SWITCH NODE

CHANNEL 1

SWITCH NODE CHANNEL 2

400ns/DIV

Figure 18. Out-of-Phase Switching, Internal Oscillator

ADP1829

T

EXTERNAL CLOCK, FREQUENCY = 1MHz

SW PIN, CHANNEL 1

SW PIN, CHANNEL 2

400ns/DIV

Figure 19. Out-of-Phase Switching, External 1 MHz Clock

T

EXTERNAL CLOCK, FREQUENCY = 2MHz

SW PIN, CHANNEL 1

SW PIN, CHANNEL 2

200ns/DIV

Figure 20. Out-of-Phase Switching, External 2 MHz Clock

V

IN

= 12V

T

V

OUT1

, 2V/DIV

EN1, 5V/DIV

10ms/DIV

Figure 21. Enable Pin Response, V

IN

= 12 V

Rev. B | Page 11 of 32

ADP1829

T

V

IN

, 5V/DIV

V

OUT

, 2V/DIV

SOFT START, 1V/DIV

4ms/DIV

Figure 22. Power-On Response, EN Tied to IN

TRACK PIN VOLTAGE,

200mV/DIV

T

FEEDBACK PIN

VOLTAGE, 200mV/DIV

20ms/DIV

Figure 23. Output Voltage Tracking Response

EN2 PIN, 5V/DIV

V

OUT2

, 2V/DIV

V

OUT1

, 2V/DIV

EN1 = 5V 40ms/DIV

Figure 24. Coincident Voltage Tracking Response

Rev. B | Page 12 of 32

ADP1829

THEORY OF OPERATION

The ADP1829 is a dual, synchronous, PWM buck controller capable of generating output voltages down to 0.6 V and output currents in the tens of amps. The switching of the regulators is interleaved for reduced current ripple. It is ideal for a wide range of applications, such as DSP and processor core I/O supplies, general-purpose power in telecommunications, medical imaging, gaming, PCs, set-top boxes, and industrial controls. The ADP1829 controller operates directly from 3.0 V to 20 V, and the power stage input voltage range is 1 V to 24 V, which applies directly to the drain of the high-side external power MOSFET. It includes fully integrated MOSFET gate drivers and a linear regulator for internal and gate drive bias. and it should otherwise be grounded or left open. LDOSD has an internal 100 kΩ pull-down resistor.

While IN is limited to 20 V, the switching stage can run from up to 24 V and the BST pins can go to 30 V to support the gate drive.

This can provide an advantage, for example, in the case of high frequency operation from a high input voltage. Dissipation on the

ADP1829 can be limited by running IN from a low voltage rail while operating the switches from the high voltage rail.

The ADP1829 operates at a fixed 300 kHz or 600 kHz switching frequency. The ADP1829 can also be synchronized to an external clock to switch at up to 1 MHz per channel. The

ADP1829 includes soft start to prevent inrush current during startup, as well as a unique adjustable lossless current limit.

The ADP1829 offers flexible tracking for startup and shutdown sequencing. It is specified over the −40°C to +85°C temperature range and is available in a space-saving, 5 mm × 5 mm,

32-lead LFCSP.

INPUT POWER

The ADP1829 is powered from the IN pin up to 20 V. The internal low dropout linear regulator, VREG, regulates the IN voltage down to 5 V. The control circuits, gate drivers, and external boost capacitors operate from the LDO output. Tie the

PV pin to VREG and bypass VREG with a 1 μF or greater capacitor.

START-UP LOGIC

The ADP1829 features independent enable inputs for each channel. Drive EN1 or EN2 high to enable their respective controllers. The LDO starts when either channel is enabled.

When both controllers are disabled, the LDO is disabled and the IN quiescent current drops to about 10 μA. For automatic startup, connect EN1 and/or EN2 to IN. The enable pins are

20 V compliant, but they sink current through an internal

100 kΩ resistor once the EN pin voltage exceeds about 5 V.

INTERNAL LINEAR REGULATOR

The internal linear regulator, VREG, is low dropout, meaning it can regulate its output voltage close to the input voltage. It powers up the internal control and provides bias for the gate drivers. It is guaranteed to have more than 100 mA of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETs driven at up to 1 MHz. Bypass VREG with a 1 μF or greater capacitor.

The ADP1829 phase shifts the switching of the two step-down converters by 180°, thereby reducing the input ripple current.

This reduces the size and cost of the input capacitors. The input voltage should be bypassed with a capacitor close to the high-

side switch MOSFETs (see the Selecting the Input Capacitor

section). In addition, a minimum 0.1 μF ceramic capacitor should be placed as close as possible to the IN pin.

The VREG output is sensed by the undervoltage lockout

(UVLO) circuit to be certain that enough voltage headroom is available to run the controllers and gate drivers. As VREG rises above about 2.7 V, the controllers are enabled. The IN voltage is not directly monitored by UVLO. If the IN voltage is insufficient to allow VREG to be above the UVLO threshold, the controllers are disabled but the LDO continues to operate.

The LDO is enabled whenever either EN1 or EN2 is high, even if VREG is below the UVLO threshold.

If the desired input voltage is between 3.0 V and 5.5 V, connect the IN directly to the VREG and PV pins, and drive LDOSD high to disable the internal regulator. The ADP1829 requires that the voltage at VREG and PV be limited to no more than

5.5 V. This is the only application where the LDOSD pin is used,

Because the LDO supplies the gate drive current, the output of

VREG is subjected to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the

VREG output for other auxiliary system loads is not recommended.

The LDO includes a current limit well above the expected maximum gate drive load. This current limit also includes a short-circuit foldback to further limit the VREG current in the event of a fault.

OSCILLATOR AND SYNCHRONIZATION

The ADP1829 internal oscillator can be set to either 300 kHz or

600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for

600 kHz. The oscillator generates a start clock for each switching phase and also generates the internal ramp voltages for the PWM modulation.

The SYNC input is used to synchronize the converter switching frequency to an external signal. The SYNC input should be driven with twice the desired switching frequency because the

SYNC input is divided by 2 and the resulting phases are used to clock the two channels alternately.

Rev. B | Page 13 of 32

ADP1829

If FREQ is driven low, the recommended SYNC input frequency is between 600 kHz and 1.2 MHz. If FREQ is driven high, the recommended SYNC frequency is between 1.2 MHz and 2 MHz. The FREQ setting should be carefully observed for these SYNC frequency ranges, as the PWM voltage ramp scales down from about 1.3 V based on the percentage of frequency overdrive. Driving SYNC faster than recommended for the

FREQ setting results in a small ramp signal, which could affect the signal-to-noise ratio and the modulator gain and stability.

When an external clock is detected at the first SYNC edge, the internal oscillator is reset and clock control shifts to SYNC. The

SYNC edges then trigger subsequent clocking of the PWM outputs. The DH rising edges appear about 400 ns after the corresponding SYNC edge, and the frequency is locked to the external signal. Depending on the startup conditions of

Channel 1 and Channel 2, either Channel 1 or Channel 2 can be the first channel synchronized to the rising edge of the SYNC clock. If the external SYNC signal disappears during operation, the ADP1829 reverts back to its internal oscillator and experiences a delay of no more than a single cycle of the internal oscillator.

ERROR AMPLIFIER

The ADP1829 error amplifiers are operational amplifiers. The

ADP1829 senses the output voltages through external resistor dividers at the FB1 and FB2 pins. The FB pins are the inverting inputs to the error amplifiers. The error amplifiers compare these feedback voltages to the internal 0.6 V reference, and the outputs of the error amplifiers appear at the COMP1 and

COMP2 pins. The COMP pin voltages then directly control the duty cycle of each respective switching converter.

A series/parallel RC network is tied between the FB pins and their respective COMP pins to provide the compensation for the buck converter control loops. A detailed design procedure

for compensating the system is provided in the Compensating the Voltage Mode Buck Regulator section.

The error amplifier outputs are clamped between a lower limit of about 0.7 V and a higher limit of about 2.4 V. When the

COMP pins are low, the switching duty cycle goes to 0%, and when the COMP pins are high, the switching duty cycle goes to the maximum.

The SS and TRK pins are auxiliary positive inputs to the error amplifiers. Whichever has the lowest voltage, SS, TRK, or the internal 0.6 V reference, controls the FB pin voltage and thus the output. Therefore, if two or more of these inputs are close to each other, a small offset is imposed on the error amplifier. For example, if TRK approaches the 0.6 V reference, the FB sees about 18 mV of negative offset at room temperature. For this reason, the soft start pins have a built-in negative offset and they charge to 0.8 V. If the TRK pins are not used, they should be tied high to VREG.

SOFT START

The ADP1829 employs a programmable soft start that reduces input current transients and prevents output overshoot. The SS1 and SS2 pins drive auxiliary positive inputs to their respective error amplifiers, thus the voltage at these pins regulate the voltage at their respective feedback control pins.

Program soft start by connecting capacitors from SS1 and SS2 to GND. On startup, the capacitor charges from an internal

90 kΩ resistor to 0.8 V. The regulator output voltage rises with the voltage at its respective soft start pin, allowing the output voltage to rise slowly, reducing inrush current. See the informa-

tion about Soft Start in the Applications Information section.

When a controller is disabled or experiences a current fault, the soft start capacitor is discharged through an internal 6 kΩ resistor, so that at restart or recovery from fault, the output voltage soft starts again.

POWER OK INDICATOR

The ADP1829 features open-drain, Power OK outputs (POK1 and POK2) that sink current when their respective output voltages drop, typically 8% below the nominal regulation voltage. The POK pins also go low for overvoltage of typically

25%. Use this output as a logical power-good signal by connecting pull-up resistors from POK1 and POK2 to VREG.

The POK1 comparator directly monitors FB1, and the threshold is fixed at 550 mV for undervoltage and 750 mV for over- voltage. However, the POK2 undervoltage and overvoltage comparator input is connected to UV2 rather than FB2. For the default thresholds at FB2, connect UV2 directly to FB2.

In a ratiometric tracking configuration, however, Channel 2 can be configured to be a fraction of a master voltage, and thus FB2 regulated to a voltage lower than the 0.6 V internal reference. In this configuration, UV2 can be tied to a different tap on the feedback divider, allowing a POK2 indication at an appropriate

output voltage threshold. See the Setting the Channel 2

Undervoltage Threshold for Ratiometric Tracking section.

TRACKING

The ADP1829 features tracking inputs (TRK1 and TRK2) that make the output voltages track another, master voltage. This is especially useful in core and I/O voltage sequencing applications where one output of the ADP1829 can be set to track and not exceed the other, or in other multiple output systems where specific sequencing is required.

The internal error amplifiers include three positive inputs, the internal 0.6 V reference voltage and their respective SS and TRK pins. The error amplifiers regulate the FB pins to the lowest of the three inputs. To track a supply voltage, tie the TRK pin to a

resistor divider from the voltage to be tracked. See the Voltage

Tracking section.

Rev. B | Page 14 of 32

MOSFET DRIVERS

The DH1 and DH2 pins drive the high-side switch MOSFETs.

These are boosted 5 V gate drivers that are powered by bootstrap capacitor circuits. This configuration allows the highside, N-channel MOSFET gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the MOSFET. The bootstrap capacitors are connected from the SW pins to their respective BST pins. The bootstrap

Schottky diodes from the PV pins to the BST pins recharge the bootstrap capacitors every time the SW nodes go low. Use a bootstrap capacitor value greater than 100× the high-side

MOSFET input capacitance.

In practice, the switch node can run up to 24 V of input voltage, and the boost nodes can operate more than 5 V above this to allow full gate drive. The IN pin can be run from 3.0 V to 18 V.

This can provide an advantage, for example, in the case of high frequency operation from very high input voltage. Dissipation on the ADP1829 can be limited by running IN from a lower voltage rail while operating the switches from the high voltage rail.

The switching cycle is initiated by the internal clock signal. The high-side MOSFET is turned on by the DH driver, and the SW node goes high, pulling up on the inductor. When the internally generated ramp signal crosses the COMP pin voltage, the switch

MOSFET is turned off and the low-side synchronous rectifier

MOSFET is turned on by the DL driver. Active break-beforemake circuitry, as well as a supplemental fixed dead time, are used to prevent cross-conduction in the switches.

The DL1 and DL2 pins provide gate drive for the low-side

MOSFET synchronous rectifiers. Internal circuitry monitors the external MOSFETs to ensure break-before-make switching to prevent cross-conduction. An active dead time reduction circuit reduces the break-before-make time of the switching to limit the losses due to current flowing through the synchronous rectifier body diode.

The PV pin provides power to the low-side drivers. It is limited to 5.5 V maximum input and should have a local decoupling capacitor.

The synchronous rectifiers are turned on for a minimum time of about 200 ns on every switching cycle in order to sense the current. This and the nonoverlap dead times put a limit on the maximum high-side switch duty cycle based on the selected switching frequency. Typically, this is about 90% at 300 kHz switching; at 1 MHz switching, it reduces to about 70% maximum duty cycle.

Because the two channels are 180° out of phase, if one is operating around 50% duty cycle, it is common for it to jitter when the other channel starts switching. The magnitude of the jitter depends somewhat on layout, but it is difficult to avoid in practice.

When the ADP1829 is disabled, the drivers shut off the external

MOSFETs, so that the SW node becomes three-stated or changes to high impedance.

Rev. B | Page 15 of 32

ADP1829

CURRENT LIMIT

The ADP1829 employs a unique, programmable, cycle-by-cycle lossless current-limit circuit that uses a small, ordinary, inexpensive resistor to set the threshold. Every switching cycle, the synchronous rectifier turns on for a minimum time and the voltage drop across the MOSFET R

DSON

is measured during the off cycle to determine if the current is too high.

This measurement is done by an internal current-limit comparator and an external current-limit set resistor. The resistor is connected between the switch node (that is, the drain of the rectifier MOSFET) and the CSL pin. The CSL pin, which is the inverting input of the comparator, forces 50 μA through the resistor to create an offset voltage drop across it.

When the inductor current is flowing in the MOSFET rectifier, its drain is forced below PGND by the voltage drop across its

R

DSON

. If the R

DSON

voltage drop exceeds the preset drop on the external resistor, the inverting comparator input is similarly forced below PGND and an overcurrent fault is flagged.

The normal transient ringing on the switch node is ignored for

100 ns after the synchronous rectifier turns on, so the overcurrent condition must also persist for 100 ns in order for a fault to be flagged.

When an overcurrent event occurs, the overcurrent comparator prevents switching cycles until the rectifier current has decayed below the threshold. The overcurrent comparator is blanked for the first 100 ns of the synchronous rectifier cycle to prevent switch node ringing from falsely tripping the current limit. The

ADP1829 senses the current limit during the off cycle. When the current-limit condition occurs, the ADP1829 resets the internal clock until the overcurrent condition disappears. This suppresses the start clock cycles until the overload condition is removed. At the same time, the SS cap is discharged through a

6 kΩ resistor. The SS input is an auxiliary positive input of the error amplifier, so it behaves like another voltage reference. The lowest reference voltage wins. Discharging the SS voltage causes the converter to use a lower voltage reference when switching is allowed again. Therefore, as switching cycles continue around the current limit, the output looks roughly like a constant current source due to the rectifier limit, and the output voltage droops as the load resistance decreases. In the event of a short circuit, the short circuit output current is the current limit set by the R

CL

resistor and is monitored cycle by cycle. When the overcurrent condition is removed, operation resumes in soft start mode.

In the event of a short circuit, the ADP1829 also offers a technique for implementing a current-limit foldback with the

use of an additional resistor. See the Setting the Current Limit

section for more information.

ADP1829

APPLICATIONS INFORMATION

SELECTING THE INPUT CAPACITOR

Choose the inductor value using the equation

The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. The input capacitor needs sufficient ripple current rating to handle the input ripple and also ESR that is low enough to mitigate input voltage ripple. For the usual current ranges for these converters, good practice is to use two parallel capacitors placed close to the drains of the high-side switch

MOSFETs, one bulk capacitor of sufficiently high current rating as calculated in Equation 1, along with 10 μF of ceramic capacitor.

Select an input bulk capacitor based on its ripple current rating.

If both Channel 1 and Channel 2 maximum output load currents are about the same, the input ripple current is less than half of the higher of the output load currents. In this case, use an input capacitor with a ripple current rating greater than half of the highest load current.

I

RIPPLE

>

I

L

2

If the Output 1 and Output 2 load currents are significantly different (if the smaller is less than 50% of the larger), then the procedure in Equation 1 yields a larger input capacitor than required. In this case, the input capacitor can be chosen as in the case of a single phase converter with only the higher load current, so first determine the duty cycle of the output with the larger load current.

L

=

V

IN

Δ I

L

V

OUT f

SW

⎜⎜

V

OUT

V

IN

⎟⎟

(4) where:

L is the inductor value. f

SW

is the switching frequency.

V

OUT

is the output voltage.

V

IN

is the input voltage.

ΔI

L

is the inductor ripple current, typically 1/3 of the maximum dc load current.

Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL). The output voltage ripple can be approximated with

Δ

V

OUT

= Δ

I

L

ESR

+

1

8 f

SW

C

OUT

+

4 f

SW

ESL

(5) where:

ΔV

OUT

is the output ripple voltage.

ΔI

L

is the inductor ripple current.

ESR is the equivalent series resistance of the output capacitor

(or the parallel combination of ESR of all output capacitors).

ESL is the equivalent series inductance of the output capacitor

D =

V

OUT

V

IN

In this case, the input capacitor ripple current is approximately

I

RIPPLE

I

L

D ( 1

D ) (3) types of capacitors, for example, a large aluminum electrolytic where I

L

is the maximum inductor or load current for the in parallel with MLCCs, may give different results. channel and D is the duty cycle. Use this method to determine the input capacitor ripple current rating for duty cycles between

20% and 80%.

Usually, the impedance is dominated by ESR at the switching frequency, as stated in the maximum ESR rating on the capacitor data sheet, so this equation reduces to

For duty cycles less than 20% or greater than 80%, use an input capacitor with ripple current rating I

RIPPLE

> 0.4 I

L

.

Δ

V

OUT

≈ Δ

I

L

ESR (6)

Electrolytic capacitors have significant ESL also, on the order of

Selecting the Output LC Filter

The output LC filter attenuates the switching voltage, making the output an almost dc voltage. The output LC filter characteristics determine the residual output ripple voltage.

Choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current.

5 nH to 20 nH, depending on type, size, and geometry. PCB traces contribute some ESR and ESL as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required.

Using a larger value inductor results in a physical size larger than is required, and using a smaller value results in increased losses in the inductor and MOSFETs.

Note that the factors of 8 and 4 in Equation 5 would normally be 2π for sinusoidal waveforms, but the ripple current waveform

Rev. B | Page 16 of 32

In the case of output capacitors where the impedance of the

ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple equation reduces to

Δ

V

OUT

Δ

I

L

8 C

OUT f

SW

Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current.

During a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation due to a change in load is dependent on the output capacitor characteristics.

Again, usually the capacitor ESR dominates this response, and the ΔV

OUT

in Equation 6 can be used with the load step current value for ΔI

L

.

SELECTING THE MOSFETS

The choice of MOSFET directly affects the dc-to-dc converter performance. The MOSFET must have low on resistance

(R

DSON

) to reduce I

2

R losses and low gate-charge to reduce switching losses. In addition, the MOSFET must have low thermal resistance to ensure that the power dissipated in the

MOSFET does not result in overheating.

The power switch, or high-side MOSFET, carries the load current during the PWM on-time, carries the transition loss of the switching behavior, and requires gate charge drive to switch.

Typically, the smaller the MOSFET R

DSON

, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances those two losses. The conduction loss of the high-side MOSFET is determined by the equation

I

L

2

R

DSON

V

OUT

V

IN where:

P

C

is the conduction power loss.

R

DSON

is the MOSFET on resistance.

The gate charge losses are dissipated by the ADP1829 regulator and gate drivers and affect the efficiency of the system. The gate charge loss is approximated by the equation

V

IN

Q

G f

SW where:

P

G

is the gate charge power.

Q

G

is the MOSFET total gate charge. f

SW

is the converter switching frequency.

Making the conduction losses balance the gate charge losses usually yields the most efficient choice.

ADP1829

Furthermore, the high-side MOSFET transition loss is approximated by the equation

P

T

V

IN

I

L t

(

R

+

2 t

F

) f

SW

(10) where t

R

and t

F

are the rise and fall times of the selected

The total power dissipation of the high-side MOSFET is the sum of the previous losses.

P

D

=

P

C

+

P

G

+

P

T

(11) where P

D

is the total high-side MOSFET power loss. This dissipation heats the high-side MOSFET.

The conduction losses may need an adjustment to account for the MOSFET R

DSON

variation with temperature. Note that

MOSFET R

DSON

increases with increasing temperature. The

MOSFET data sheet should list the thermal resistance of the package, θ

JA

, along with a normalized curve of the temperature coefficient of the R

DSON

. For the power dissipation estimated in

Equation 11, calculate the MOSFET junction temperature rise over the ambient temperature of interest.

T

J

=

T

A

+

θ

JA

P

D

(12)

Then calculate the new R

DSON

from the temperature coefficient curve and the R

DSON

specification at 25°C. A typical value of the temperature coefficient (TC) of the R

DSON

is 0.004/°C, so an alternate method to calculate the MOSFET R

DSON

at a second temperature, T

J

, is

R

DSON

@ T

J

=

R

DSON

@ 25

°

C [ 1

+

TC ( T

J

25

°

C )] (13)

Then the conduction losses can be recalculated and the procedure iterated once or twice until the junction temperature calculations are relatively consistent. inductor current when the high-side MOSFET is off. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time, and therefore, to achieve high efficiency, it is critical to optimize the low-side MOSFET for small on resistance. In cases where the power loss exceeds the MOSFET rating, or lower resistance is required than is available in a single MOSFET, connect multiple low-side

P

LS

I

L

2

R

DSON

1

V

OUT

V

IN

(14) where:

P

LS

is the low-side MOSFET on resistance.

R

DSON

is the parallel combination of the resistances of the lowside MOSFETs.

Check the gate charge losses of the synchronous rectifier(s) using the P

G

equation (Equation 9) to be sure they are reasonable.

Rev. B | Page 17 of 32

ADP1829

SETTING THE CURRENT LIMIT

The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current.

ADP1829

V

IN

DH

M1

L

V

OUT

The current limit is set through the current-limit resistor, R

CL

.

The current sense pins, CSL1 and CSL2, source 50 μA through their respective R

CL

. This creates an offset voltage of R

CL

multiplied by the 50 μA CSL current. When the drop across the low-side

MOSFET R

DSON

is equal to or greater than this offset voltage, the

ADP1829 flags a current-limit event.

DL

CSL

M2

R

LO

R

HI

C

OUT

Figure 25. Short Circuit Current Foldback Scheme

Because the CSL current and the MOSFET R

DSON

vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. To do this, use the peak current in the inductor,

Because the buck converters are usually running fairly high current, PCB layout and component placement may affect the current-limit setting. An iteration of the R

CL

or R

LO

and R

HI values may be required for a particular board layout and

MOSFET selection. If alternate MOSFETs are substituted at which is the desired current-limit level plus the ripple current, the maximum R

DSON

of the MOSFET at its highest expected temperature, and the minimum CSL current. some point in production, these resistor values may also need an iteration.

FEEDBACK VOLTAGE DIVIDER

R where I

CL

LPK

=

I

LPK

R

DSON

44 μA

( MAX )

(15) voltage divider. The output voltage is reduced through the

is the peak inductor current. voltage divider and drives the FB feedback input. The regulation threshold at FB is 0.6 V. The maximum input bias current into

In addition, the ADP1829 offers a technique for implementing a current-limit foldback in the event of a short circuit with the

use of an additional resistor, as shown in Figure 25. Resistor R

LO

FB is 100 nA. For a 0.15% degradation in regulation voltage and with 100 nA bias current, the low-side resistor, R

BOT

, needs to be less than 9 kΩ, which results in 67 μA of divider current. For

R

BOT

, use 1 kΩ to 10 kΩ. A larger value resistor can be used, but is largely responsible for setting the foldback current limit during a short circuit, and R

HI

is mainly responsible for setting up the normal current limit. R

LO

is lower than R

HI

. These current-limit sense resistors can be calculated by would result in a reduction in output voltage accuracy due to the input bias current at the FB pin, while lower values cause increased quiescent current consumption. Choose R

TOP

to set where:

I

R

R

LO

HI

PKFOLDBACK

=

=

I

I

PKFOLDBACK

LPK

R

44

V

R

DSON

μA

R

LO

OUT

DSON ( MAX )

(MAX ) the output voltage by using the following equation:

(16)

R

TOP

=

(17)

R

BOT

V

OUT

V

FB

V

FB

(18)

44 μA where:

R

TOP

is the high-side voltage divider resistance. is the desired short circuit peak inductor current limit.

I

LPK

is the peak inductor current limit during normal operation and is also used in Equation 15.

R

BOT

is the low-side voltage divider resistance.

V

OUT

is the regulated output voltage.

V

FB

is the feedback regulation threshold, 0.6 V.

Rev. B | Page 18 of 32

ADP1829

COMPENSATING THE VOLTAGE MODE BUCK

REGULATOR

Assuming the LC filter design is complete, the feedback control system can then be compensated. Good compensation is critical to proper operation of the regulator. Calculate the quantities in

Equation 19 through Equation 47 to derive the compensation values. The goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase margin for stable operation. Additionally, at frequencies above the crossover frequency, f

CO

, guaranteeing sufficient gain margin and attenuation of switching noise are important secondary goals. For initial practical designs, a good choice for the crossover frequency is 1/10 of the switching frequency, so first calculate

GAIN

PHASE

0dB

LC FILTER BODE PLOT f

LC

–40dB/dec f

ESR

–20dB/dec f

CO

A

FILTER f

SW

FREQUENCY

f

CO

= f

SW

10

(19)

This gives sufficient frequency range to design a compensation that attenuates switching artifacts, while also giving sufficient control loop bandwidth to provide good transient response.

–90°

FILTER

The output LC filter is a resonant network that inflicts two poles upon the response at a frequency f

LC

, so next calculate

–180°

f

LC

=

2 π

1

LC

Generally speaking, the LC corner frequency is about two orders of magnitude below the switching frequency, and

To compensate the control loop, the gain of the system must be brought back up so that it is 0 dB at the desired crossover frequency. Some gain is provided by the PWM modulation itself. therefore, about one order of magnitude below crossover. To achieve sufficient phase margin at crossover to guarantee stability, the design must compensate for the two poles at the

A

MOD

=

20 log

V

IN

V

RAMP

(23)

LC corner frequency with two zeros to boost the system phase prior to crossover. The two zeros require an additional pole or two above the crossover frequency to guarantee adequate gain margin and attenuation of switching noise at high frequencies.

For systems using the internal oscillator, this becomes

A

MOD

=

20 log

1

V

.

3

IN

V

(24)

Depending on component selection, one zero might already be generated by the equivalent series resistance (ESR) of the output capacitor. Calculate this zero corner frequency, f f

ESR

=

2 π R

1

ESR

C

OUT

ESR

, as

Figure 26 shows a typical Bode plot of the LC filter by itself.

Note that if the converter is being synchronized, the ramp voltage, V

V

RAMP

RAMP

=

, is lower than 1.3 V by the percentage of frequency increase over the nominal setting of the FREQ pin.

1 .

3 V

2 f f

FREQ

SYNC

(25)

The gain of the LC filter at crossover can be linearly approxi-

mated from Figure 26 as

A

FILTER

A

FILTER

=

=

A

LC

+

A

ESR

40 dB

× log

⎜ f

ESR f

LC

20 dB

× log

⎜ f

CO f

ESR

(22)

The factor of 2 in the numerator takes into account that the

SYNC frequency is divided by 2 to generate the switching frequency. For example, if the FREQ pin is set high for the

600 kHz range and a 2 MHz SYNC signal is applied, the ramp voltage is 0.78 V. This increases the gain of the modulator by

4.4 dB in this example.

If f

ESR

≈ f

CO

, then add another 3 dB to account for the local difference between the exact solution and the linear approximation in Equation 22.

Rev. B | Page 19 of 32

ADP1829

The rest of the system gain is needed to reach 0 dB at crossover.

LC FILTER BODE PLOT

PHASE CONTRIBUTION AT CROSSOVER

OF VARIOUS ESR ZERO CORNERS

The total gain of the system, therefore, is given by

GAIN

A

T

= A

MOD

+ A

FILTER

+ A

COMP

(26)

f

ESR1 f

ESR2 f

ESR3 f

CO

where:

A

MOD

is the gain of the PWM modulator.

A

FILTER

is the gain of the LC filter including the effects of the ESR zero.

A

COMP

is the gain of the compensated error amplifier.

–40dB/dec

–20dB/dec

Additionally, the phase of the system must be brought back up to guarantee stability. Note from the bode plot of the filter that the LC contributes −180° of phase shift. Additionally, because the error amplifier is an integrator at low frequency, it contributes an initial −90°. Therefore, before adding compensation or accounting for the ESR zero, the system is already down −270°.

To avoid loop inversion at crossover, or −180° phase shift, a good initial practical design is to require a phase margin of 60°, which is therefore an overall phase loss of −120° from the initial low frequency dc phase. The goal of the compensation is to boost the phase back up from −270° to −120° at crossover.

PHASE

–90°

1

The two common compensation schemes used are sometimes referred to as Type II or Type III compensation, depending on whether the compensation design includes two or three poles.

(Dominant-pole compensations, or single-pole compensation, is referred to as Type I compensation, but unfortunately, it is not very useful for dealing successfully with switching regulators.)

If the zero produced by the ESR of the output capacitor provides sufficient phase boost at crossover, Type II compensation is adequate. If the phase boost produced by the ESR of the output capacitor is not sufficient, another zero is added to the compensation network, and thus, Type III is used.

In Figure 27, the location of the ESR zero corner frequency

gives significantly different net phase at the crossover frequency.

The following equations were used for the calculation of the

compensation components as shown in Figure 28 and Figure 29:

f

–180°

f

Z1

Z2

=

=

1

2

π

R

Z

C

I

2

3

Figure 27. LC Filter Bode Plot

f

SW

FREQUENCY

(27)

1

2

π

C

FF

( R

TOP

+

R

FF

)

(28)

Use the following guidelines for selecting between Type II and

Type III compensators:

If f

ESRZ

If f

ESRZ

≤ f

CO

2

, use Type II compensation.

> f

CO

2

, use Type III compensation. f

P1

=

2

π

R

Z

1

C

I

C

I

C

HF

+

C

HF

(29) f

P2

=

1

2

π

R

FF

C

FF

(30) where: f

Z1

is the zero produced in the Type II compensation. f

Z2

is the zero produced in the Type III compensation. f

P1

is the pole produced in the Type II compensation. f

P2

in the pole produced in the Type III compensation.

Rev. B | Page 20 of 32

ADP1829

Type II Compensator

FROM

V

OUT

G

(dB)

PHASE

–180°

–270°

R

TOP

R

BOT

–1 S

LO

PE

R

Z f

Z

C

HF

EA

C

I f

P

–1 S

LO

PE

COMP

TO PWM

Next choose the high frequency pole, f

P1

, to be 1/2 of f

SW

. f

P1

=

1

2 f

SW

(36)

Because C

HF

<< C

I

, Equation 29 is simplified to f

P1

=

1

2

π

R

Z

C

HF

(37)

Solving for C

HF

in Equation 36 and Equation 37 yields

C

HF

=

1

π f

SW

R

Z

(38)

Type III Compensator

VREF

VRAMP

0V

Figure 28. Type II Compensation

G

(dB)

–1

SL

OP

E

+1

S

LO

PE

–1

SL

OP

E

If the output capacitor ESR zero frequency is sufficiently low (≤1/2 of the crossover frequency), use the ESR to stabilize the

regulator. In this case, use the circuit shown in Figure 28.

Calculate the compensation resistor, R

Z

, with the following equation:

–90°

PHASE

–270°

R

FF

C

FF f

Z

R

Z

C

HF

C

I f

P

R

Z

=

R

TOP

V

RAMP f

ESR f

CO

V

IN f

LC

2

FROM

V

OUT

R

TOP

(31)

R

BOT

EA

COMP

TO PWM

where: f

CO

is chosen to be 1/10 of f

SW.

V

RAMP

is 1.3 V.

VREF

0V

VRAMP

Next choose the compensation capacitor to set the compensation zero, f frequency or 1/2 of the LC resonant frequency: or f

Z 1

= f

Z

1

= f

CO

4 f

LC

2

=

= f

SW

40

Z1

, to the lesser of 1/4 of the crossover

=

1

2

π

R

Z

C

I

1

2

π

R

Z

C

I

Solving for C

I

in Equation 32 yields

If the output capacitor ESR zero frequency is greater than 1/2 of the crossover frequency, use Type III compensator as shown in

Figure 29. Set the poles and zeros as follows:

(32) f

P1

= f

P2

=

1

2 or f

= f

= f

CO

4 f

SW

=

(39) f

SW

40

=

1

2

π

R

Z

C

I

(40)

C

I

=

20

π

R

Z f

SW

Figure 29. Type III Compensation f

Z 1

= f

Z 2

= f

LC

2

=

2

π

R

1

Z

C

I

(41)

Solving for C

I

in Equation 33 yields

C

I

=

π

R

Z

1 f

LC

(35)

Use the larger value of C

I

from Equation 34 or Equation 35.

Use the lower zero frequency from Equation 40 or Equation 41.

Calculate the compensator resistor, R

Z

.

R

Z

=

TOP

V

RAMP

IN f

LC

2

Z1 CO

(42)

Because of the finite output current drive of the error amplifier,

C

I

needs to be less than 10 nF. If it is larger than 10 nF, choose a larger R

TOP

and recalculate R

Z

and C

I

until C

I

is less than 10 nF.

Next calculate C

C

I

=

1

I

.

(43)

2 π R

Z f

Z1

Rev. B | Page 21 of 32

ADP1829

Because of the finite output current drive of the error amplifier,

C

I

needs to be less than 10 nF. If it is larger than 10 nF, choose a larger R

TOP

and recalculate R

Z

and C

I

until C

I

is less than 10 nF.

V

CSS

=

0 .

8 V

1

− t e

RC

SS

(48)

Because C yields solution.

HF

<< C

I

, combining Equation 29 and Equation 39

The soft start period ends when the voltage on the soft start pin reaches 0.6 V. Substituting 0.6 V for V

SS

and solving for the

C

HF

=

π f

1

SW

R

Z

(44)

Next, calculate the feedforward capacitor, C

FF.

. Assume R

FF

<<

R

TOP

, then Equation 28 is simplified to number of RC time constants,

0 .

6 V

=

0 .

8 V

1

− e

90 t

SS kΩ

( ) f

Z2

=

1 t

SS

=

1 .

386 RC

SS

(49)

(50)

2 π C

FF

R

TOP

Solving C

FF

in Equation 45 yields

C

SS

= t

SS

×

8 μF/ sec (51)

C

FF

=

2 π

1

R

TOP f

Z2 where t

SS

is the desired soft start time in seconds. where f

Z2

is obtained from Equation 40 or Equation 41.

The ADP1829 includes a tracking feature that prevents an output voltage from exceeding a master voltage. This is

The feedforward resistor, R

FF

, can be calculated by combining especially important when the ADP1829 is powering separate

Equation 30 and Equation 39 power supply voltages on a single integrated circuit, such as the

R

FF

=

π C

1

FF f

SW core and I/O voltages of a DSP or microcontroller. In these cases, improper sequencing can cause damage to the load.

Check that the calculated component values are reasonable. For instance, capacitors smaller than about 10 pF should be avoided.

The ADP1829 tracking input is an additional positive input to the error amplifier. The feedback voltage is regulated to the lower of

In addition, the ADP1829 error amplifier has finite output the 0.6 V reference or the voltage at TRK, so a lower voltage on

TRK limits the output voltage. This feature allows implementation current drive, so R

Z

values less than 3 kΩ and C

I

values greater than 10 nF should be avoided. If necessary, recalculate the of two different types of tracking: coincident tracking, where the output voltage is the same as the master voltage until the compensation network with a different starting value of R

TOP

.

If R

Z

is too small and C

I

is too big, start with a larger value of R

TOP

. master voltage reaches regulation, or ratiometric tracking, where

This compensation technique should yield a good working the output voltage is limited to a fraction of the master voltage.

In all tracking configurations, the master voltage should be higher than the slave voltage.

In general, aluminum electrolytic capacitors have high ESR, and a Type II compensation is adequate. However, if several aluminum electrolytic capacitors are connected in parallel, producing a low effective ESR, then Type III compensation is needed. In addition,

Note that the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the ceramic capacitors have very low ESR, in the order of a few milliohms. Type III compensation is needed for ceramic output capacitors. Type III compensation offers better performance than Type II in terms of more low frequency gain and more phase margin and less high frequency gain at the cross-over rise time of the master voltage to be imposed on the slave voltage.

If the soft start setting of the slave voltage is longer, the slave comes up more slowly and the tracking relationship is not seen at the output. The slave channel should still have a soft start capacitor to give a small but reasonable soft start time to protect in case of restart after a current-limit event. frequency.

V

OUT

For a more exact method or to optimize for other system characteristics, a number of references and tools are available from your Analog Devices, Inc. applications support team.

COMP

R

TOP

R

BOT

SOFT START

The ADP1829 uses an adjustable soft start to limit the output voltage ramp-up period, thus limiting the input inrush current.

The soft start is set by selecting the capacitor, C

SS

, from SS1 and

SS2 to GND. The ADP1829 charges C

SS

to 0.8 V through an internal 90 kΩ resistor. The voltage on the soft start capacitor while it is charging is

ERROR

AMPLIFIER

FB

TRK

0.6V

SS

R

TRKT

DETAIL VIEW OF

ADP1829

Figure 30. Voltage Tracking

R

TRKB

MASTER

VOLTAGE

Rev. B | Page 22 of 32

COINCIDENT TRACKING

The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications.

Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage.

For coincident tracking, use R

TRKT

= R

TOP

and R

TRKB

= R

BOT

, where R

TOP

and R

BOT

are the values chosen in the Compensating the Voltage Mode Buck Regulator section

.

MASTER VOLTAGE

SLAVE VOLTAGE

TIME

Figure 31. Coincident Tracking

As the master voltage rises, the slave voltage rises identically.

Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the

TRK input continues to increase and thus removes itself from influencing the output voltage. To ensure that the output voltage accuracy is not compromised by the TRK pin being too close in voltage to the 0.6 V reference, make sure that the final value of the master voltage is greater than the slave regulation voltage by at least 10%, or 60 mV, as seen at the FB node, and the higher, the better. A difference of 60 mV between TRK and the 0.6 V reference produces about 3 mV of offset in the error amplifier, or 0.5%, at room temperature, while 100 mV between them produces only 0.6 mV or 0.1% offset.

RATIOMETRIC TRACKING

Ratiometric tracking limits the output voltage to a fraction of the master voltage. For example, the termination voltage for

DDR memories, VTT, is set to half the VDD voltage.

MASTER VOLTAGE

SLAVE VOLTAGE

TIME

Figure 32. Ratiometric Tracking

ADP1829

For ratiometric tracking, the simplest configuration is to tie the

TRK pin of the slave channel to the FB pin of the master channel.

This has the advantage of having the fewest components, but the accuracy suffers as the TRK pin voltage becomes equal to the internal reference voltage and an offset is imposed on the error amplifier of about −18 mV at room temperature.

A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0.6 V at regulation, for example, 0.5 V. The slave channel can be viewed as having a 0.5 V external reference supplied by the master voltage.

Once this is complete, the FB divider for the slave voltage is

designed as in the Compensating the Voltage Mode Buck

Regulator section, except to substitute the 0.5 V reference for

the V

FB

voltage. The ratio of the slave output voltage to the master voltage is a function of the two dividers.

V

V

OUT

MASTER

=

1

1

+

+

R

R

TOP

BOT

R

TRKT

R

TRKB

(52)

Another option is to add another tap to the divider for the master voltage. Split the R

BOT

resistor of the master voltage into two pieces, with the new tap at 0.5 V when the master voltage is in regulation. This saves one resistor, but be aware that Type III compensation on the master voltage causes the feedforward signal of the master voltage to appear at the TRK input of the slave channel.

By selecting the resistor values in the divider carefully, Equation 52 shows that the slave voltage output can be made to have a faster ramp rate than that of the master voltage by setting the TRK voltage at the slave larger than 0.6 V and R

TRKB

greater than

R

TRKT

. Make sure that the master SS period is long enough (that is, sufficiently large SS capacitor) such that the input inrush current does not run into the current limit of the power supply during startup.

Rev. B | Page 23 of 32

ADP1829

Setting the Channel 2 Undervoltage Threshold for

Ratiometric Tracking

If FB2 is regulated to a voltage lower than 0.6 V by configuring

TRK2 for ratiometric tracking, the Channel 2 undervoltage threshold can be set appropriately by splitting the top resistor in

the voltage divider, as shown in Figure 33. R

BOT

is the same as calculated for the compensation in Equation 52, and

R

TOP

=

R

A

+

R

B

CHANNEL 2

OUTPUT

VOLTAGE

550mV

UV2

R

A

THERMAL CONSIDERATIONS

The current required to drive the external MOSFETs comprises the vast majority of the power dissipation of the ADP1829. The on-chip LDO regulates down to 5 V, and this 5 V supplies the drivers. The full gate drive current passes through the LDO and is then dissipated in the gate drivers. The power dissipated on the gate drivers on the ADP1829 is

P

D

=

V

IN f

SW

Q

DH 1

+

Q

DL 1

+

Q

DH 2

+

Q

DL 2

) (57) where:

V

IN

is the voltage applied to IN. f

SW

is the switching frequency.

Q numbers are the total gate charge specifications from the selected MOSFET data sheets.

POK2

TO ERROR

AMPLIFIER

750mV

FB2

R

B

R

BOT

Figure 33. Setting the Channel 2 Undervoltage Threshold

The power dissipation heats the ADP1829. As the switching frequency, the input voltage, and the MOSFET size increase, the power dissipation on the ADP1829 increases. Care must be taken not to exceed the maximum junction temperature. To calculate the junction temperature from the ambient temperature and power dissipation,

T

J

=

T

A

+

P

D

θ

JA

(58)

The current in all the resistors is the same:

V

FB 2

R

BOT

=

V

UV 2

R

B

V

FB 2

=

V

OUT 2

R

A

V

UV 2

The thermal resistance, θ

JA

, of the package is typically 40°C/W depending on board layout, and the maximum specified where:

V

UV2

is 600 mV.

V

FB2

is the feedback voltage value set during the ratiometric tracking calculations.

V

OUT2

is the Channel 2 output voltage. ambient of 85°C without airflow, the maximum dissipation allowed is about 1 W.

A thermal shutdown protection circuit on the ADP1829 shuts off the LDO and the controllers if the die temperature exceeds approximately 145°C, but this is a gross fault protection only and should not be relied upon for system reliability.

Solving for R

A

and R

B

,

R

A

=

R

BOT

(

V

OUTA 2

V

FB 2

R

B

=

R

BOT

(

V

UV 2

V

FB 2

V

UV

V

FB 2

)

2

)

(55)

(56)

Rev. B | Page 24 of 32

PCB LAYOUT GUIDELINES

In any switching converter, some circuit paths carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. Still others carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and copper area accordingly.

When designing PCB layouts, be sure to keep high current loops small. In addition, keep compensation and feedback components away from the switch nodes and their associated components.

The following is a list of recommended layout practices for the

ADP1829, arranged by decreasing order of importance:

The current waveform in the top and bottom FETs is a pulse with very high dI/dt, so the path to, through, and from each individual FET should be as short as possible and the two paths should be commoned as much as possible. In designs that use a pair of D-Pak or SO-8 FETs on one side of the

PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high-side drain can be bypassed to the low-side source with a suitable ceramic bypass capacitor, placed as close as possible to the FETs in order to minimize inductance around this loop through the

FETs and capacitor. The recommended bypass ceramic capacitor values range from 1 μF to 22 μF depending upon the output current. This bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGND plane.

GND, VREG bypass, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to an (almost isolated) small AGND plane. All of these connections should have connections from the pin to the

AGND plane that are as short as possible. No high current or high dI/dt signals should be connected to this AGND plane. The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors.

The PGND pin handles high dI/dt gate drive current returning from the source of the low-side MOSFET. The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection (OCP) function and the CSL pin. A small PGND plane should connect the PGND pin and the PVCC bypass capacitor through a wide and direct path to the source of the low-side MOSFET. The placement of C

IN

is critical for controlling ground bounce. The negative terminal of C

IN

needs to be placed very close to the source of the low-side MOSFET.

Rev. B | Page 25 of 32

ADP1829

Avoid long traces or large copper areas at the FB and CSL pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. It is best to position any series resistors and capacitors as closely as possible to these pins. Avoid running these traces close and parallel to high dI/dt traces.

The switch node is the noisiest place in the switcher circuit with large ac and dc voltage and current. This node should be wide to keep resistive voltage drop down. However, to minimize the generation of capacitively coupled noise, the total area should be small. Place the FETs and inductor all close together on a small copper plane in order to minimize series resistance and keep the copper area small.

Gate drive traces (DH and DL) handle high dI/dt, so tend to produce noise and ringing. They should be as short and direct as possible. If possible, avoid using feedthrough vias in the gate drive traces. If vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. If the overall

PCB layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. It is occasionally helpful to place small value resistors (such as

5 Ω or 10 Ω) in series with the gate leads, mainly DH traces to the high-side FET gates. These can be populated with 0 Ω resistors if resistance is not needed. Note that the added gate resistance increases the switching rise and fall times, and that also increases the switching power loss in the MOSFET.

The negative terminal of output filter capacitors should be tied closely to the source of the low-side FET. Doing this helps to minimize voltage difference between GND and

PGND at the ADP1829.

Generally, be sure that all traces are sized according to the current that will be handled as well as their sensitivity in the circuit. Standard PCB layout guidelines mainly address heating effects of current in a copper conductor. These are completely valid, but they do not fully cover other concerns such as stray inductance or dc voltage drop. Any dc voltage differential in connections between ADP1829 GND and the converter power output ground can cause a significant output voltage error because it affects converter output voltage according to the ratio with the 600 mV feedback reference. For example, a 6 mV offset between ground on the ADP1829 and the converter power output causes a 1% error in the converter output voltage.

ADP1829

LFCSP PACKAGE CONSIDERATIONS

The LFCSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. To achieve the optimum performance from the LFCSP package, give special consideration to the layout of the PCB. Use the following layout guidelines for the LFCSP package.

The pad pattern is given in Figure 36. The pad dimension

should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging.

The thermal pad of the LFCSP package provides a low thermal impedance path to the PCB. Therefore, the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner

or bottom layers. See Figure 36 for the recommended via

pattern. Note that the via diameter is small. This prevents the solder from flowing through the via and leaving voids in the thermal pad solder joint.

Note that the thermal pad is attached to the die substrate, so the planes that the thermal pad is connected to must be electrically isolated or connected to GND.

The solder mask opening should be about 120 microns

(4.7 mils) larger than the pad size, resulting in a minimum

60 microns (2.4 mils) clearance between the pad and the solder mask.

The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package.

This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm.

The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the large size of the thermal pad, eliminating voids may not be possible. In addition, if the solder paste coverage is too large, solder joint defects may occur.

Therefore, it is recommended to use multiple small openings instead of a single big opening in designing the paste mask. The recommended paste mask pattern is given

in Figure 36. This pattern results in about 80% coverage,

which should not degrade the thermal performance of the package significantly.

The recommended paste mask stencil thickness is 0.125 mm.

A laser cut stainless steel stencil with trapezoidal walls should be used.

A no clean, Type 3 solder paste should be used for mounting the LFCSP package. In addition, a nitrogen purge during the reflow process is recommended.

The package manufacturer recommends that the reflow temperature not exceed 220°C and the time above liquid be less than 75 seconds. The preheat ramp should be 3°C/sec or lower. The actual temperature profile depends on the board density; the assembly house must determine what works best.

Rev. B | Page 26 of 32

APPLICATION CIRCUITS

The ADP1829 controller can be configured to regulate outputs with loads of more than 20 A if the power components, such as the inductor, MOSFETs and the bulk capacitors, are chosen carefully to meet the power requirement. The maximum load and power dissipation are limited by the powertrain components.

Figure 1 shows a typical application circuit that can drive an

output load of 8 A.

Figure 34 shows an application circuit that can drive 20 A loads.

Note that two low-side MOSFETs are needed to deliver the 20 A load. The bulk input and output capacitors used in this example are Sanyo OSCON™ capacitors, which have low ESR and high current ripple rating. An alternative to the OSCON capacitors

V

IN

= 5.5V TO 18V

1µF

1.2V, 20A

C

OUT2

820µF

25V

×2

1µF 5600pF

390

2k

C

IN2

180µF

20V

1µF

M4

D2

0.47µF

L2

1µH

2k

2k

M6 M5

120nF

10k

4.7nF

PV IN

TRK1

TRK2

VREG

EN1

EN2

BST1 BST2

DH1

ADP1829

SW1

CSL1

SW2

CSL2

DL1

DH2

DL2

PGND1

FB1

PGND2

FB2

COMP1

COMP2

are the polymer aluminum capacitors that are available from other manufacturers such as United Chemi-con. Aluminum electrolytic capacitors, such as Rubycon’s ZLG low ESR series, can also be paralleled up at the input or output to meet the ripple current requirement. Because the aluminum electrolytic capacitors have higher ESR and much larger variation in capacitance over the operating temperature range, a larger bulk input and output capacitance is needed to reduce the effective

ESR and suppress the current ripple. Figure 34 shows that the

polymer aluminum or the aluminum electrolytic capacitors can be used at the outputs.

D1

0.47µF

M1

1µF

C

IN1

180µF

20V

PGND

L1

1µH

2k

M2 M3

2k

1.5nF

6.8nF

47k

1k

ADP1829

10nF 1µF

200

1.8V, 20A

C

OUT1

1200µF

6.3V

×3

GND

FREQ

LDOSD

SYNC

AGND f

OSC

= 300kHz

M1, M4: IRLR7807Z

L1, L2: TOKO, FDA1254-1ROM

C

OUT1

: SANYO, 2R5SEPC820M

D1, D2: VISHAY, BAT54

M2, M3, M5, M6: IRFR3709Z

C

IN1

, C

IN2

: SANYO, 20SP180M

C

OUT2

: RUBYCON, 6.3ZLG1200M10×16

Figure 34. Application Circuit with 20 A Output Loads

Rev. B | Page 27 of 32

ADP1829

The ADP1829 can also be configured to drive an output load of

less than 1 A. Figure 35 shows a typical application circuit that

drives 1.5 A and 3 A loads in all multilayer ceramic capacitor

(MLCC) solutions. Note that the two MOSFETs used in this example are dual-channel MOSFETs in a PowerPAK® SO-8

V

IN

= 3V TO 5.5V

1µF

1.0V, 3A

C

OUT3

100µF

C

OUT2

47µF

1µF

10µF

×2

1µF

L2

2.2µH

M3

D2

0.22µF

8.2nF

4.12k

84.5

M4

1.33k

120nF

2k

6.65k

1.5nF

PV IN

TRK1

TRK2

VREG

EN1

EN2

BST1

BST2

DH1 DH2

ADP1829

SW1

SW2

CSL1 CSL2

DL1

PGND1

FB1

DL2

PGND2

FB2

COMP1

COMP2

package, which reduces cost and saves layout space. An alternative to using the dual-channel SO-8 package is using two single MOSFETs in SOT-23 or TSOP-6 packages, which are low cost and small in size.

D1

1µF

10µF

×2

0.22µF

PGND

M1

L1

2.5µH

1.4k

8.2nF

M2

2k

84.5

120nF

1µF

1k

6.65k

1.5nF

IN

10µF

1.8V, 1.5A

C

OUT1

100µF

GND

FREQ

LDOSD

SYNC f

OSC

= 600kHz

M1 TO M4: DUAL-CHANNEL SO-8 IRF7331

L2: TOKO, FDV0602-2R2M

C

OUT2

: MURATA, GRM31CR60J476M

AGND

L1: SUMIDA, CDRH5D28-2R5NC

C

OUT1

, C

OUT3

: MURATA, GRM31CR60J107M

D1, D2: VISHAY BAT54

Figure 35. Application Circuit with all Multilayer Ceramic Capacitors (MLCC)

Rev. B | Page 28 of 32

OUTLINE DIMENSIONS

ADP1829

5.00

BSC SQ

0.60 MAX

0.60 MAX

PIN 1

INDICATOR

TOP

VIEW

4.75

BSC SQ

25

24

EXPOSED

PAD

(BOTTOM VIEW)

32

1

PIN 1

INDICATOR

0.50

BSC

3.25

3.10 SQ

2.95

0.50

0.40

0.30

17

16 9

8

0.25 MIN

12° MAX

0.80 MAX

0.65 TYP

3.50 REF

1.00

0.85

0.80

0.30

0.23

0.18

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

1 , 2 Temperature

Package Description Package Option

ADP1829ACPZ-R7 −40°C to +85°C

ADP1829-EVALZ

ADP1829-BL1-EVZ

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

Low Current Blank Evaluation Board (0 A to 20 A)

ADP1829-BL2-EVZ High Current Blank Evaluation Board (20 A to 30 A)

1

Z = RoHS Compliant Part.

2 For the ADP1829-BL1-EVZ and the ADP1829-BL2-EVZ, users can generate schematic design and build of materials from the Analog Devices, Inc., ADIsimPower™ at www.analog.com/ADIsimPower .

3

Operating junction temperature range is −40°C to +125°C.

Rev. B | Page 29 of 32

ADP1829

NOTES

Rev. B | Page 30 of 32

NOTES

ADP1829

Rev. B | Page 31 of 32

ADP1829

NOTES

©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D06784-0-1/11(B)

Rev. B | Page 32 of 32

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