Download datasheet for R1LV1616RBA-5SI by Renesas Electronics Corporation

Download datasheet for R1LV1616RBA-5SI by Renesas Electronics Corporation
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R1LV1616RBA-5SI
16Mb Advanced LPSRAM (1M wordx16bit / 2M wordx8bit)
REJ03C0340-0001
Rev.0.01
2007.10.31
Description
The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit,
fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies.
The R1LV1616R Series is suitable for memory applications where a simple interfacing , battery operating and
battery backup are the important design objectives.
The R1LV1616RBA Series is packaged in a 48balls Wafer Level Chip Scale Package[WL-CSP / 5.62mm x 5.84mm
with the ball-pitch of 0.55mm and the height of 0.79mm]. It gives the best solution for a compaction of mounting area
as well as flexibility of wiring pattern of printed circuit boards.
Features
• Single 2.7-3.6V power supply
• Small stand-by current:2µA (3.0V, typ.)
• Data retention supply voltage =2.0V
• No clocks, No refresh
• All inputs and outputs are TTL compatible
• Easy memory expansion by CS1#, CS2, LB# and UB#
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE# prevents data contention on the I/O bus
• Process technology: 0.15um CMOS
REJ03C0340-0001 Rev.0.01 2007.10.31
page 1 of 14
R1LV1616RBA Series
Ordering Information
Type No.
R1LV1616RBA-5SI
Access time
Package
55 ns
5.62mmx5.84mm WL-CSP with 0.55mm pitch 48balls
Pin Arrangement
48-pin WL-CSP (bottom view)
6
5
4
3
A
A0
A4
A11
BYTE#
UB# LB#
B
CS1#
A5
A12
DQ14
DQ7
DQ15/
A-1
C
WE#
A6
A13
DQ5
DQ13
DQ6
D
Vcc
A7
A14
DQ4
DQ12
Vss
E
Vss
A8
A15
Vss
DQ11
Vcc
F
A1
CS2
A16
DQ9
DQ10
DQ2
G
A2
A9
A17
DQ8
DQ3
OE#
H
A3
A10
A18
A19
DQ1
DQ0
REJ03C0340-0001 Rev.0.01 2007.10.31
page 2 of 14
2
1
R1LV1616RBA Series
Pin Description
Pin name
Function
A0 to A19
Address input
DQ 0 to DQ15
Data input/output
CS1# &CS2
Chip select
WE#
Write enable
OE#
Output enable
LB#
Lower byte select
UB#
Upper byte select
Vcc
Power supply
Vss
Ground
BYTE#
Byte (x8 mode) enable input
NC
Non connection
LB#
UB#
BYTE#
WE#
OE#
REJ03C0340-0001 Rev.0.01 2007.10.31
page 3 of 14
x8/x16
SWITCHING
CIRCUIT
OUTPUT
BUFFER
OUTPUT
BUFFER
SENSE Amp.
DATA SELECTOR
DQ8
DATA INPUT
BUFFER
CS1#
DQ7
DATA INPUT
BUFFER
CLOCK
GENERATOR
DQ0
DATA SELECTOR
CS2
1048576 Words
x 16BITS
OR
2097152 Words
x 8BITS
SENSE Amp.
A19
Memory Array
DECODER
A0
ADDRESS BUFFER
Block Diagram
DQ15
/ A-1
Vcc
Vss
R1LV1616RBA Series
Operating Table
CS1#
CS2
BYTE#
LB#
UB#
WE#
OE#
DQ0-7
DQ8-14
DQ15
Operation
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
Stand by
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
Stand by
X
X
H
H
H
X
X
High-Z
High-Z
High-Z
Stand by
L
H
H
L
H
L
X
Din
High-Z
High-Z
Write in lower byte
L
H
H
L
H
H
L
Dout
High-Z
High-Z
Read from lower byte
L
H
X
X
X
H
H
High-Z
High-Z
High-Z
Output disable
L
H
H
H
L
L
X
High-Z
Din
Din
Write in upper byte
L
H
H
H
L
H
L
High-Z
Dout
Dout
Read from upper byte
L
H
H
L
L
L
X
Din
Din
Din
Write
L
H
H
L
L
H
L
Dout
Dout
Dout
Read
L
H
L
L
L
L
X
Din
High-Z
A-1
Write
L
H
L
L
L
H
L
Dout
High-Z
A-1
Read
Note 1. H:VIH L:VIL X: VIH or VIL
2. When applying BYTE# =“L” , please assign LB#=UB#=“L”.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to Vss
Vcc
-0.5 to +4.6
V
Terminal voltage on any pin relation toVss
VT
-0.5*1 to Vcc+0.3*2
V
Power dissipation
PT
0.7
W
Operation temperature
Topr
-40 to +85
ºC
Storage temperature
Tstg
-65 to +150
ºC
Storage temperature range under bias
Tbias
-40 to +85
ºC
Note 1. -2.0V in case of AC (Pulse width ≤ 30ns)
2. Maximum voltage is +4.6V
REJ03C0340-0001 Rev.0.01 2007.10.31
page 4 of 14
R1LV1616RBA Series
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vcc
2.7
3.0
3.6
V
Vss
0
0
0
V
Input high voltage
VIH
2.4
-
Vcc+0.2
V
Input low voltage
VIL
-0.2
-
0.4
V
1
Ambient temperature range
Ta
-40
-
+85
ºC
2
Supply voltage
Note
Note 1. –2.0V in case of AC (Pulse width ≤ 30ns)
DC Characteristics
Symbol
Min.
Typ.*1
Max.
Unit
Input leakage current
|ILI|
-
-
1
µA
Vin=Vss to Vcc
Output leakage current
|ILo|
-
-
1
µA
CS1# =VIH or CS2=VIL or
OE# = VIH or WE# =VIL or
LB# =UB# =VIH,VI/O=Vss to Vcc
Icc1
-
25
40
mA
Min. cycle, duty =100%
I I/O = 0 mA, CS1# =VIL,
CS2=VIH Others = VIH / VIL
Parameter
Average operating
current
Standby current
Standby current
Test conditions*2
Icc2
-
2
5
mA
Cycle time = 1 µs, I I/O = 0 mA,
CS1#≤ 0.2V, CS2 ≥ VCC-0.2V
VIH ≥ VCC-0.2V , VIL ≤ 0.2V,
duty=100%
ISB
-
0.1
0.3
mA
CS2=VIL
-
2
6
µA
~+25ºC V in ≥ 0V
-
4
12
µA
~+40ºC
-
-
25
µA
~+70ºC
-
-
40
µA
~+85ºC
ISB1
(1) 0V≤CS2≤0.2V or
(2) CS2≥Vcc-0.2V,
CS1# ≥Vcc-0.2V or
(3)LB# =UB# ≥Vcc-0.2V,
CS2≥Vcc-0.2V,
CS1# ≤0.2V
Average value
Output hige voltage
VOH
2.4
-
-
V
IOH = -1mA
Output Low voltage
VOL
-
-
0.4
V
IOL = 2mA
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V
REJ03C0340-0001 Rev.0.01 2007.10.31
page 5 of 14
R1LV1616RBA Series
Capacitance
(Ta = +25ºC, f =1MHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test conditions
Note
Input capacitance
C in
-
-
10
pF
V in = 0V
1
Input / output capacitance
C I/O
-
-
10
pF
V I/O = 0V
1
Note 1:This parameter is sampled and not 100% tested.
AC Characteristics
Test Conditions (Vcc=2.7~3.6V, Ta = -40~+85ºC *)
• Input pulse levels: VIL= 0.4V,VIH=2.4V
• Input rise and fall time : 5ns
• Input and output timing reference levels : 1.4V
• Output load : See figures (Including scope and jig)
1.4V
RL=500Ω
DQ
CL=30pF
REJ03C0340-0001 Rev.0.01 2007.10.31
page 6 of 14
R1LV1616RBA Series
Read Cycle
Parameter
Read cycle time
Address access time
Chip select access time
Output enable to output valid
Output hold from address change
LB#,UB# access time
Chip select to output in low-Z
LB#,UB# enable to low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
LB#,UB# disable to high-Z
Output disable to output in high-Z
REJ03C0340-0001 Rev.0.01 2007.10.31
page 7 of 14
Symbol
(note0)
Unit
Notes
Min.
Max.
tRC
tAA
55
-
ns
-
70
ns
tACS1
tACS2
tOE
tOH
tBA
tCLZ
tBLZ
tOLZ
tCHZ1
tCHZ2
tBHZ
tOHZ
-
55
ns
-
55
ns
-
35
ns
10
-
ns
-
55
ns
10
-
ns
2,3
5
-
ns
2,3
5
-
ns
2,3
0
20
ns
1,2,3
0
20
ns
1,2,3
0
20
ns
1,2,3
0
20
ns
1,2,3
R1LV1616RBA Series
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip selection to end of write
Write pulse width
LB#,UB# valid to end of write
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
Write to output in high-Z
Symbol
tWC
tAW
tCW
tWP
tBW
tAS
tWR
tDW
tDH
tOW
tOHZ
tWHZ
Vcc=2.7V to 3.6V
Unit
Notes
Min.
Max.
55
-
ns
50
-
ns
55
-
ns
5
40
-
ns
4
50
-
ns
0
-
ns
6
0
-
ns
7
25
-
ns
0
-
ns
5
-
ns
2
0
20
ns
1,2
0
20
ns
1,2
Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on
customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.
In case of tAA =70ns, tRC =70ns.
1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. AT any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and
form device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#
going low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
REJ03C0340-0001 Rev.0.01 2007.10.31
page 8 of 14
R1LV1616RBA Series
Timing condition for Byte enable
Parameter
Byte setup time
Byte recovery time
Symbol
Min.
Max.
Unit
tBS
tBR
5
-
ms
5
-
ms
BYTE# Timing Waveform
CS2
CS1#
tBS
BYTE#
REJ03C0340-0001 Rev.0.01 2007.10.31
page 9 of 14
tBR
Notes
R1LV1616RBA Series
Timing Waveform
Read Cycle
tRC
A0~19
(Word Mode)
A-1~19
(Byte Mode)
Valid address
tAA
tBA
tOH
LB#,UB#
tBHZ
tACS1
CS1#
tCHZ1
tACS2
CS2
tCHZ2
tOE
OE#
WE# = "H" level
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
REJ03C0340-0001 Rev.0.01 2007.10.31
page 10 of 14
tOLZ
tCLZ
tBLZ
tOHZ
Valid data
R1LV1616RBA Series
Write Cycle (1) (WE# Clock)
tWC
A 0~19
(Word Mode)
Valid address
A -1~19
(Byte Mode)
tBW
LB#,UB#
tCW
CS1#
tCW
CS2
tAW
tAS
tWR
tWP
tWHZ
WE#
tOW
tDW
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
REJ03C0340-0001 Rev.0.01 2007.10.31
page 11 of 14
tDH
Valid data
R1LV1616RBA Series
Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH)
tWC
A0~19
(Word Mode)
Valid address
A-1~19
(Byte Mode)
tBW
LB#,UB#
CS1#
tAS
CS2
WE#
DQ0~15
tCW
tWR
tCW
tWP
tDW
tDH
(Word Mode)
DQ0~7
(Byte Mode)
REJ03C0340-0001 Rev.0.01 2007.10.31
page 12 of 14
Valid data
R1LV1616RBA Series
Write Cycle (3) ( LB#,UB# Clock, OE#=VIH)
tWC
A0~19
(Word Mode)
A-1~19
(Byte Mode)
Valid address
tAS
tBW
tWR
LB#,UB#
CS1#
tCW
tCW
CS2
WE#
DQ0~15
tWP
tDW
tDH
(Word Mode)
DQ0~7
(Byte Mode)
REJ03C0340-0001 Rev.0.01 2007.10.31
page 13 of 14
Valid data
R1LV1616RBA Series
Data Retention Characteristics
Parameter
Symbol
VDR
Vcc for data retention
MIn.
Typ.*1
Max.
Test conditions*2,3
Unit
V in ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS2 ≥ Vcc-0.2V,
CS1# ≥ Vcc-0.2V or
(3) LB# =UB# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V,
CS1# ≤ 0.2V
2.0
-
3.6
V
-
2
6
µA
~+25ºC
-
4
12
µA
~+40ºC
-
-
25
µA
~+70ºC
-
-
40
µA
~+85ºC
0
-
-
ns
5
-
-
ms
IccDR
Data retention current
Chip deselect to data retention time
Operation recovery time
tCDR
tR
Vcc=3.0V,Vin≥0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS2 ≥ Vcc-0.2V,
CS1# ≥ Vcc-0.2V or
(3) LB# =UB# ≥Vcc-0.2V,
CS2 ≥ Vcc-0.2V,
CS1# ≤ 0.2V
Average value
See retention waveform
Note 1. Typical parameter of IccDR indicates the value for the center of distribution at Vcc=3.0V and not 100% tested.
2. BYTE# pin supported only by TSOP and uTSOP types. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V
3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2
controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance
state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
Data Retention timing Waveform (1) (LB#,UB# Controlled)
Vcc
tCDR
2.70V
tR
2.4V
2.4V
LB# =UB# ≥ Vcc-0.2V
LB#
UB#
Data Retention timing Waveform (2) (CS1# Controlled)
Vcc
tCDR
2.70V
tR
2.4V
2.4V
CS1# ≥ Vcc-0.2V
CS1#
Data Retention timing Waveform (3) (CS2 Controlled)
Vcc
tCDR
CS2
2.70V
0.2V
0.2V
0V ≤ CS2 ≤ 0.2V
REJ03C0340-0001 Rev.0.01 2007.10.31
page 14 of 14
tR
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2
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