Download datasheet for ML2256X by LAPIS Semiconductor

Download datasheet for ML2256X by LAPIS Semiconductor
FEDL2256XDIGEST-04
Issue Date: Feb. 9, 2011
ML22Q563-NNNMB/ML22Q563-xxxMB/ML2256X-xxxMB
Datasheet
2-Channel Mixing Speech Synthesis LSI with Built-in FLASH/MASK ROM
GENERAL DESCRIPTION
The ML22Q563-NNN, ML22Q563-xxx and ML2256X-xxx are 2-channel mixing speech synthesis LSIs with
built-in FLASH/MASK ROM for voice data. These LSIs incorporate into them an HQ-ADPCM decoder that
enables high sound quality, 16-bit D/A converter, low-pass filter, and 1.0 W monaural speaker amplifier for
driving speakers. Since functions necessary for voice output are all integrated into a single chip, a system can
be upgraded with audio features by only using one of these LSIs.
 Capacity of internal memory and the maximum voice production time (when HQ-ADPCM
1
method used)
Maximum voice production time (sec)
Product name
ROM capacity
fsam = 8.0 kHz
fsam = 16.0 kHz
fsam = 32.0 kHz
ML22Q563-NNN
ML22Q563-xxx
ML22563-xxx
4 Mbits
161
80
40
ML22562-xxx
2 Mbits
79
39
19
FEATURES
 Speech synthesis method:
Can be specified for each phrase.
HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
 Sampling frequency:
Can be specified for each phrase.
12.0/24.0/48.0 kHz, 8.0 / 16.0/32.0 kHz, 6.4/12.8/25.6 kHz
 Built-in low-pass filter and 16-bit D/A converter
 Built-in speaker driver amplifier:
1.0 W, 8 (at DVDD = 5 V)
 External analog voice input (built-in analog mixing function)
 CPU command interface:
Clock synchronous serial interface
 Maximum number of phrases:
1024 phrases, from 000h to 3FFh
 Edit ROM
 Volume control:
CVOL command: Adjustable through 32 levels (including OFF)
AVOL command: Adjustable through 50 levels (including OFF)
 Repeat function:
LOOP command
 Channe mixing function:
2channels
 Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the
OFF setting)
 Source oscillation frequency:
4.096 MHz
 Power supply voltage:
2.7 to 5.5 V
 Operating temperature range:
–40C to +85C 2
 Package:
30-pin plastic SSOP(P-SSOP30-56-0.65-6K-MC)
Product name:
ML22Q563-NNNMB/ML22Q563-xxxMB
ML22563-xxxMB/ML22562-xxxMB
(“xxx” denotes ROM code number)
1
HQ-ADPCM is a high sound quality audio compression technology of "Ky's".
“Ky’s” is a Registered trademark of National Universities corporate Kyushu
Institute of Technology
2 The limitation on the operation time changes by the using condition. (Refer to Page62)
1/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225X and
ML2282X) and the ML22Q563/ML2256X.
Item
CPU interface
ROM type
ROM capacity
Playback method
Maximum number of
phrases
Sampling frequency
(kHz)
Clock frequency
ML225X
Parallel/Serial
MASK
3/4/6 Mbits
2-bit ADPCM2
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
256
4.0/5.3/6.4/8.0/
10.7/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
4.096 MHz (has a
crystal oscillator
circuit built-in)
14-bit voltage-type
ML2282X
Serial/I2C
P2ROM
4/8/16 Mbits
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
ML22Q563
Serial
FLASH
4 Mbits
ML2256X

MASK
2/4 Mbits
HQ-ADPCM
HQ-ADPCM
8-bit straight PCM
8-bit straight PCM
8-bit non-linear PCM 8-bit non-linear PCM
16-bit straight PCM 16-bit straight PCM
1024



6.4/8.0/12.0/
12.8/16.0/24.0/
25.6/32.0/48.0




16-bit voltage-type

Low-pass filter
FIR interpolation
filter
FIR interpolation
filter
(SRC)
Speaker driving
amplifier
No
Built-in
0.7 W
(8, DVDD = 5 V)

FIR interpolation
filter
(High-pass
interpolation)
Built-in
1.0 W
(8, DVDD = 5 V)
2-channel



Yes
29 levels
20 to 1024 ms
(4 ms steps)
Yes

32 levels










No
Yes


Yes
No


No



2.7 V to 5.5 V



40C to +105C
40C to +85C


44-pin QFP
30-pin SSOP


D/A converter
Simultaneous sound
production function
(mixing function)
Edit ROM
Volume control
Silence insertion
Repeat function
External analog
input
External speech
data input
Interval at which a
seam is silent during
continuous playback
Power supply
voltage
Ambient
temperature
Package


2/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
BLOCK DIAGRAM
TESTI0
TESTI1
TESTI2
TESTI3
TESTI4
TESTO
The block diagrams of the ML22Q563-NNN/ML22Q563-xxx/ML2256X-xxx are shown below.
DVDD
DGND
VDDL
VDDR
RESETB
CSB
SCK
SI
SO
CBUSYB
STATUS
ERR
DIPH
TESTI1
Cmd
Analyzer
JTAG
Interface
Address Controller
18/19bit
4Mbit FLASH
PCM Synthesizer
I/O
Timing
Controller
LPF(CVOL)
Interface
16bit DAC
PLL
VPP
SP-AMP
(AVOL)
OSC
SPVDD
SPGND
XT XTB
SPM SPP
AIN
SG
Block Diagram of ML22Q563-NNN/ML22Q563-xxx
DVDD
DGND
VDDL
Cmd
Analyzer
2/4-Mbit ROM
Address Controller
18/19 bits
RESETB
CSB
SCK
SI
SO
CBUSYB
STATUS
ERR
DIPH
TESTI1
PCM Synthesizer
I/O
Interface
Timing
Controller
LPF (CVOL)
16-bit DAC
PLL
OSC
SP-AMP
(AVOL)
SPVDD
SPGND
XT XTB
SPM SPP
AIN
SG
Block Diagram of
3/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
PIN CONFIGURATION (TOP VIEW)
ML22Q563-NNN/ML22Q563-xxx
AIN
SG
V DDR
DV DD
DGND
VDDL
DIPH
STATUS
ERR
CSB
SCK
SI
SO
CBUSYB
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30-Pin Plastic SSOP
SPVDD
SPGND
SPP
SPM
TESTO
TESTI4
TESTI3
TESTI2
TESTI1
TESTI0
RESETB
VPP
DVDD
XT
XTB
NC Unused pin
ML2256X -xxx
AIN
SG
NC
DV DD
DGND
VDDL
DIPH
STATUS
ERR
CSB
SCK
SI
SO
CBUSYB
DGND
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SPVDD
SPGND
SPP
SPM
TESTO
NC
NC
NC
TESTI1
TESTI0
RESETB
NC
DVDD
XT
XTB
NC Unused pin
30-Pin Plastic SSOP
4/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
PIN DESCRIPTION (1)
Pin
Symbol
1
AIN
2
SG
2
3*
VDDR
4,18
DVDD
5,15
DGND
6
VDDL
7
DIPH
8
STATUS
9
ERR
10
CSB
11
SCK
12
SI
13
SO
I/O Attribute
I
—
Description
Speaker amplifier input pin.
Built-in speaker amplifier’s reference voltage output pin.
O
—
Connect a capacitor of 0.1 F or more between this pin and
DGND.
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for ROM). Connect a
capacitor of 10 F or more between this pin and DGND.
Digital power supply pin.
—
—
Connect a bypass capacitor of 10F or more between this
pin and DGND.
—
—
Digital ground pin
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for logic). Connect a
capacitor of 10 F or more between this pin and DGND.
Serial interface switching pin.
Pin for choosing between rising edges and falling edges as
to the edges of the SCK pulses used for shifting serial data
input to the SI pin into the inside of the LSI.
When this pin is at a “L” level, SI input data is shifted into the
LSI on the rising edges of the SCK clock pulses and a status
I
Positive
signal is output from the SO pin on the falling edges of the
SCK clock pulses.
When this pin is at a “H” level, SI input data is shifted into the
LSI on the falling edges of the SCK clock pulses and a status
signal is output from the SO pin on the rising edges of the
SCK clock pulses.
Channel status output pin.
O Positive Outputs the BUSYB or NCR signal for each channel by
inputting the OUTSTAT command.
Error output pin.
O Positive
Outputs a “H” level if an error occurs.
Chip select pin.
A “L” level on this pin accepts the SCK or SI inputs. When
I Negative
this pin is at a “H” level, neither the SCK nor SI signal is input
to the LSI.
I
Positive Synchronous serial clock input pin.
Synchronous serial data input pin.
When the DIPH pin is at a “L” level, data is shifted in on the
I
—
rising edges of the SCK clock pulses.
When the DIPH pin is at a “H” level, data is shifted in on the
falling edges of the SCK clock pulses.
Channel status serial output pin.
Outputs a status signal on the falling edges of the SCK clock
pulses when the DIPH pin is at a ”L” level; outputs a status
signal on the rising edges of the SCK clock pulses when the
O Positive
DIPH pin is at a ”H” level.
When the CSB pin is at a ”L” level, the status of each channel
is output serially in sync with the SCK clock. When the CSB
pin is at a ”H” level, this pin goes into a high impedance state.
analog
Initial
value
0
analog
0
analog
0
power
—
gnd
—
power
0
digital
0
digital
1
digital
0
digital
1
clk
0
digital
0
digital
Hi-Z
Attribute
5/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
PIN DESCRIPTION (2)
Pin
Symbol
I/O Attribute
Description
14
CBUSYB
O
Negative
16
XTB
O
Negative
17
XT
I
Positive
19*
VPP
I
—
20
RESETB
I
Negative
21
TESTI0
(MODE)
I
Positive
22
TESTI1
(nTRST)
I
Negative
Command processing status signal output pin.
This pin outputs a “L” level during command processing.
Be sure to enter commands with the CBUSYB pin driven
at a “H” level.
Connects to a crystal or a ceramic resonator.
When using an external clock, leave this pin open.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
Connects to a crystal or a ceramic resonator.
A feedback resistor of around 1 M is built in between this
XT pin and the XTB pin. When using an external clock,
input the clock from this pin.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
Pin for FLASH analysis.
Should be connected to DGND.
Reset input pin.
At “L” level input, the LSI enters the initial state. After a
reset input, the entire circuit is stopped and enters a
power down state. Upon power-on, input a “L” level to
this pin. After the power supply voltage is stabilized,
drive this pin at a “H” level.
This pin has a pull-up resistor built in.
Input pin for testing. Also acts as a Flash rewrite enable
pin.
Has a pull-down resistor built in.
Used as either an input pin for testing or a reset input pin
for Flash rewriting. Has a pull-down resistor built in.
TESTI2
(TMS)
I
Positive
Used as either an input pin for testing or a state transition
pin for Flash rewriting. Has a pull-up resistor built in.
I
Positive
I
Positive
O
Positive
O
—
2
2
23*
27
TESTI3
(TDI)
TESTI4
(TCK)
TESTO
(TSO)
SPM
28
SPP
O
—
29
SPGND
—
—
30
SPVDD
—
—
2
24*
2
25*
2
26*
Used as either an input pin for testing or a data input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an input pin for testing or a clock input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an output pin for testing or a data output
pin for Flash rewriting.
Output pin of the built-in speaker amplifier.
Output pin of the built-in speaker amplifier.
Can be configured as an AOUT amplifier output by
command setting.
Speaker amplifier ground pin.
Speaker amplifier power supply pin.
Connect a bypass capacitor of 10F or more between this
pin and SPGND.
Attribute
digital
Initial
(*1)
value
0
(*1)
clk
1
clk
0
analog
0
digital
0
(*1)
digital
0
digital
0
digital
1
digital
1
digital
0
digital
Hi-Z
analog
Hi-Z
analog
0
gnd
—
power
—
*1: Indicates the initial value at reset input or during power down.
*2: These are NC pins in the ML2256X.
6/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
DVDD
SPVDD
VIN
Power dissipation
PD
Output short-circuit current
IOS
Storage temperature
TSTG
Condition
DGND = SPGND = 0 V, Ta = 25C
Rating
Unit
—
0.3 to +7.0
V
—
When the LSI is mounted on
JEDEC 4-layer board.
When SPVDD = 5V
Applies to all pins except
SPM, SPP, VDDL, and VDDR.
Applies to SPM and SPP pins.
Applies to VDDL and VDDR pins.
—
0.3 to DVDD+0.3
V
1000
mW
10
mA
500
50
55 to +150
mA
mA
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
DVDD, SPVDD
Power supply voltage
DVDD
SPVDD
—
Operating temperature
Top
—
Master clock frequency
DGND = SPGND = 0 V
Range
Unit
2.7 to 5.5
Min.
3.5
40 to +85
Typ.
4.096
V
°C
Max.
4.5
fOSC
—
MHz
Parameter
Symbol
Condition
Range
At write/erase
0 to +70
°C
Operating temperature
TOP
At read
40 to +85
°C
FLASH Conditions
DGND = SPGND = 0 V
Unit
Maximum rewrite count
CEP
10
times
Data retention period
YDR
10
years
7/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
ELECTRICAL CHARACTERISTICS
DC Characteristics (3 V)
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
Output leakage current(*2)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
Symbol
VIH
VIL
VOH1
VOH2
VOL1
VOL2
IOOH
IOOL
IIH1
IIH2
IIH3
IIL1
IIL2
IIL3
Supply current during
playback 1
IDD1
Supply current during
playback 2
IDD2
Power-down supply
current (*6)
Power-down supply
current (*7)
IDDS1
IDDS1
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
—
0.86DVDD
—
DVDD
V
—
0
—
0.14DVDD
V
IOH = 1 mA
DVDD 0.4
—
—
V
IOH = 50 µA
DVDD 0.4
—
—
V
IOL = 2 mA
—
—
0.4
V
IOL = 50 µA
—
—
0.4
V
VOH = DVDD (CSB=“H”)
—
—
10
µA
VOL = DGND(CSB=“H”)
10
—
—
µA
VIH = DVDD
—
—
10
µA
VIH = DVDD
0.3
2.0
15
µA
VIH = DVDD
2
30
200
µA
VIL = DGND
10
—
—
µA
VIL = DGND
15
2.0
0.3
µA
VIL = DGND
200
–30
–2
µA
fOSC = 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM
—
—
41
mA
Playback
No output load
fOSC = 4.096 MHz
—
—
38
mA
During silence playback
No output load
Ta = 40 to +55°C
—
—
10
µA
Ta = 40 to +85°C
—
—
20
µA
Ta = 40 to +55°C
—
—
50
µA
Ta = 40 to +85°C
—
—
100
µA
*1: Applies to the XTB pin.
*2: Applies to the SO and TESTO pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 and TESTI1 pins.
*5: Applies to the RESETB, TEST2, TEST3 and TEST4 pins.
*6: Applies to the ML2256X.
*7: Applies to the ML22Q563.
8/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
DC Characteristics (5 V)
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
Output leakage
current(*2)
“L” output voltage 2 (*1)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
Symbol
VIH
VIL
VOH1
VOH2
VOL1
IOOH
IOOL
VOL2
IIH1
IIH2
IIH3
IIL1
IIL2
IIL3
Supply current during
playback 1
IDD1
Supply current during
playback 3
IDD3
Power-down supply
current (*6)
Power-down supply
current (*7)
IDDS1
IDDS1
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
—
0.8DVDD
—
DVDD
V
—
0
—
0.2DVDD
V
IOH = 1 mA
DVDD0.4
—
—
V
IOH = 50 µA
DVDD0.4
—
—
V
IOL = 2 mA
—
—
0.4
V
VOH = DVDD (CSB=“H”)
—
—
10
µA
VOL = DGND (CSB=“H”)
IOL = 50 µA
VIH = DVDD
VIH = DVDD
VIH = DVDD
VIL = DGND
VIL = DGND
VIL = DGND
fOSC = 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM
Playback
No output load
fOSC = 4.096 MHz
During silence playback
No output load
Ta = 40 to +55°C
Ta = 40 to +85°C
Ta = 40 to +55°C
Ta = 40 to +85°C
10
—
—
0.8
20
–10
–20
–400
—
—
—
5
100
—
5.0
–100
—
0.4
10
20
400
—
0.8
–20
µA
V
µA
µA
µA
µA
µA
µA
—
—
55
mA
—
—
48
mA
—
—
—
—
—
—
—
—
10
20
50
100
µA
µA
µA
µA
*1: Applies to the XTB pin.
*2: Applies to the SO and TESTO pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 and TESTI1 pins.
*5: Applies to the RESETB, TEST2, TEST3 and TEST4 pins.
*6: Applies to the ML2256X.
*7: Applies to the ML22Q563.
9/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Analog Section Characteristics (3 V)
Parameter
AIN input resistance
AIN input voltage range
Line output resistance
LINE output load
resistance
LINE output voltage range
SG output voltage
SG output resistance
SPM, SPP output load
resistance
Speaker amplifier output
power
Output offset voltage
between SPM and SPP
with no signal present
Regulator output voltage
Symbol
RAIN
VAIN
RLA
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
Input gain: 0 dB
10
20
30
k
—
—
SPVDD2/3 Vp-p
At 1/2SPVDD output
—
—
100

RLA
At SPGND10k
load
10
—
VAO
At SPGND10k
load
SPVDD/6
—
—
k
VSG
RSG
—
—
0.95DVDD/2
DVDD/2
57
96
SPVDD
5/6
1.05DVDD/2
135
RLSP
—
6
8
—

PSPO
SPVDD = 3.3V, f = 1 kHz
10%
RSPO = 8, THD
100
300
—
mW
VOF
SPIN–SPM gain = 0 dB
With a load of 8
50
—
+50
mV
VDDL
VDDR
Output load current =
35 mA
2.25
2.5
2.75
V
V
V
k
10/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Analog Section Characteristics (5 V)
Parameter
AIN input resistance
Symbol
RAIN
AIN input voltage range
VAIN
Line output resistance
LINE output load
resistance
LINE output voltage range
RLA
SG output voltage
SG output resistance
SPM, SPP output load
resistance
Speaker amplifier output
power
Output offset voltage
between SPM and SPP
with no signal present
Regulator output voltage
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
Input gain: 0 dB
10
20
30
k
SPVDD
Vp-p
—
—
2/3
At 1/2SPVDD output
—
—
100

RLA
At SPGND10k
load
10
—
VAO
At SPGND10k
load
SPVDD /6
—
0.95x
VSG
—
RSG
—
SPVDD /2
57
RLSP
—
PSPO
SPVDD /2
—
SPVDD
5/6
1.05x
k
V
V
96
SPVDD /2
135
k
6
8
—

SPVDD = 5.0V, f = 1 kHz
RSPO = 8, THD
10%
800
1000
—
mW
VOF
SPIN–SPM gain = 0 dB
With a load of 8
50
—
+50
mV
VDDL
VDDR
Output load current =
35 mA
2.25
2.5
2.75
V
11/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
FUNCTIONAL DESCRIPTION
Synchronous Serial Interface
The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device.
For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in
sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK
clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock.
For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the
SCK clock signal.
Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by
the signal input through the DIPH pin:
- When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges
of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock
pulses.
- When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling
edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock
pulses.
It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses
caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a
failure in normal input of command. In addition, the serial interface can be brought back to its initial state by
driving the CSB pin at a “H” level.
When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock.
When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state.
 C om ma nd In pu t Timi ng : SCK r isin g e dge ope ra tion (wh e n D IPH p in = “L” le vel )
CSB
SCK
SI
D7
D6
D5
D4
D3
D2
D1
(MSB)
D0
(LSB )
 C om ma nd In pu t Timi ng : SCK fa lling edg e o pe ra tio n (whe n DIPH pin = “H” le vel )
CSB
SCK
SI
D7
D6
D5
D4
D3
D2
D1
(MSB)
D0
(LSB )
 C om ma nd O u tpu t T imi ng : SC K fa llin g ed g e o pe ra tio n (w he n D IPH pin = “L ” le ve l)
CSB
SCK
(MSB)
SO
D7
(LSB )
D6
D5
D4
D3
D2
D1
D0
Co m ma nd O utp ut Tim in g: S CK ris ing ed g e op era tio n ( wh en DIPH pi n = “H ” le vel )
CSB
SCK
(MSB)
SO
D7
(LSB )
D6
D5
D4
D3
D2
D1
D0
12/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
To prevent malfunction caused by serial interface pin noise, the ML22Q563/ML2256X is provided with the
two-time command input mode, where the user inputs one command two times. Use the PUP command to set
the two-time command input mode. For the method of setting the two-time command input mode, see the the
section on “1. PUP command” described later.
In two-time command input mode, input one command two times in succession. Then, the command becomes
valid only when the data input first matches the data input second. After the first data input, if a data mismatch
occurs when the second data is input, a ”H” level is output from the ERR pin. An error, if occurred, can be
cleared by the ERCL command.
PLAY command
1st byte
PLAY command
1 st byte
PLAY command
2nd byte
PLAY command
2nd byte
CSB
SCK
SI
t CB1
tCB2
CBUSYB VOH
VOL
NCRn
(internal)
VOH
BUSYBn
(internal)
VOH
SPM
SPP
Status
VOL
VOL
1/2VDD
1/2VDD
Awaiting command
Command is being
processed
Awaiting command
Command is being
processed
Awaiting command
Awaiting command
Address is being
controlled
Playing
Awaiting command
Command is being
processed
13/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Voice Synthesis Algorithm (Common to ML22Q563 and ML2256X)
The ML22Q563/ML2256X contains four algorithm types to match the characteristic of playback voice:
HQ-ADPCM algorithm, 8-bit straight PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight PCM
algorithm.
Key feature of each algorithm is described in the table below.
Voice synthesis
algorithm
HQ-ADPCM
8-bit Nonlinear PCM
8-bit PCM
16-bit PCM
Feature
Algorithm that enables high sound quality and high
compression, which have been achieved by the improved
4-bit ADPCM that uses variable bit-length coding.
Algorithm that plays back mid-range of waveform as 10-bit
equivalent voice quality.
Normal 8-bit PCM algorithm
Normal 16-bit PCM algorithm
14/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Memory Allocation and Creating Voice Data
The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM
area.
The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses
of voice data for 1024 phrases, use/non-use of the edit ROM function and so on.
The test area contains data for testing.
The voice area contains actual waveform data.
The edit ROM area contains data for effective use of voice data. For the details, refer to the section on “Edit
ROM Function.”
No edit ROM area is available unless the edit ROM is used.
The ROM data is created using a dedicated tool.
Configuration of ROM data (for ML22Q563/ML22563)
0x00000
Voice control area
(Fixed 64 Kbits)
0x01FFF
0x02000
Test area
0x0206F
0x02070
Voice area
max: 0x7FEBF
max: 0x7FEBF
0x7FEC0
Edit ROM area
Depends on creation
of ROM data.
Filter area
max: 0x7FFFF
Playback Time and Memory Capacity
The playback time depends on the memory capacity, sampling frequency, and playback method.
The equation showing the relationship is given below.
The equation below gives the playback time when the edit ROM function is not used.
Playback time =
1.024  (Memory capacity  64) (Kbits)
Sampling frequency (kHz)  Bit length
(sec)
Example: Let the sampling frequency be 16 kHz and HQ-ADPCM algorithm.
approx. 80 seconds, as shown below.
Playback time =
1.024  (4096 64) (Kbits)
16 (kHz)  3.2 (bits) (average)
Then the playback time is
 80 (sec)
15/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Edit ROM Function
With the edit ROM function, multiple phrases can be played in succession.
configured using the edit ROM function:
The following functions can be
 Continuous playback:
There is no limit to the continuous playback count that can be specified.
depends on the memory capacity only.
 Silence insertion: 20 to 1024 ms
It
Using the edit ROM function enables an effective use of the memory capacity of voice ROM.
Below is an example of the ROM configuration in the case of using the edit ROM function.
Examples of Phrases Using the Edit ROM Function
Phrase 1
A
B
D
Phrase 2
A
C
D
Phrase 3
E
B
D
Phrase 4
E
C
D
Phrase 5
A
B
D
Silence
E
B
D
Example of ROM Data Where the Contents Above Are Stored in ROM
Address control
area
A
B
D
C
E
Editing area
16/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Mixing Function
The ML22Q563/ML2256X can perform simultaneous mixing of four channels.
PLAY, STOP, and CVOL for each channel separately.
It is possible to specify FADR,
 Precautions for Waveform Clamp at the Time of Channel Mixing
If channel mixing is done, the possibility of an occurrence of a clamp increases from the mixing calculation point
of view. If it is known beforehand that a clamp will occur, then adjust the sound volume of each channel using
the VOL command.
 Mixing of Different Sampling Frequency
It is not possible to perform channel mixing by a different sampling frequency group.
When performing channel mixing, the sampling frequency group of the first playback channel is selected.
Therefore, note that if channel mixing is performed by a sampling frequency group other than the selected
sampling frequency group, then the playback will not be of constant speed: some times faster and at other times
slower.
The available sampling groups for channel mixing by a different sampling frequency are listed below.
8.0 kHz, 16.0 Hz, 32.0 kHz
 (Group 1)
12.0 kHz, 24.0 kHz, 48 kHz
 (Group 2)
6.4 kHz, 12.8 kHz, 25.6 kHz
 (Group 3)
Figures below show cases where a phrase is played at a sampling frequency belonging to a different sampling
frequency group.
fs
fs
16.0kHz
16.0kHz Invalid Will be played as fs
12.8kHz
Channel 0
fs
25.6kHz
Channel 1
Figure 1
Case where a phrase is played at a sampling frequency belonging to a different
sampling frequency group during playback on channels 0 and 1
fs = 16.0 kHz
Played normally if not being played by
other channel.
Channel 0
fs = 25.6 kHz (Valid)
Channel 1
End of channel 1
Figure 2
Case where a phrase is played at a sampling frequency belonging to a different
sampling frequency group after playback is finished at the other channel
17/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Command List
Each command is configured in 1-byte (8-bit) units. Each of the AMODE, AVOL FADR, PLAY, MUON, and
CVOL commands forms one command by two bytes. Be sure to input the following commands only.
Input each command with CBUSYB set to a ”H” level.
Command
PUP
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
WCM
0
0
0
0
0
1
HPF1
HPF0
0
DAG1
DAG0
AIG1
AIG0
DAEN
SPEN
POP
0
0
0
0
1
0
0
0
—
—
AV5
AV4
AV3
AV2
AV1
AV0
0
0
0
0
1
1
0
0
0
0
0
0
FAD3
FAD2
FAD1
FAD0
0
0
1
0
0
0
0
0
0
0
1
1
0
C0
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
0
1
0
0
0
C0
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
START
0
1
0
1
0
0
CH1
CH0
STOP
0
1
1
0
0
0
CH1
CH0
AMODE
AVOL
FAD
PDWN
FADR
PLAY
Description
Shifts the device currently
powered down to a command
wait state. Also the two-time
command input mode is set
by this command.
Analog section control
command.
Configures settings for
power-up operation and
analog input/output.
Selects the type of HPF.
Analog mixing signal volume
setting command. Use the
data of the 2nd byte to
specify volume.
Sets the fade-in time in cases
where the speaker amplifier
is enabled by the AMODE
command.
Shifts the device from a
command wait state to a
power-down state.
Playback phrase specification
command.
Can be specified for each
channel.
Playback start command.
Use the data of the 2nd byte
to specify a phrase number.
Can be specified for each
channel.
Playback start command
without phrase specification.
Used to start playback on
multiple channels at the same
time after phrases are
specified with the FADR
command. After a phrase is
played with the PLAY
command, the same phrase
can be played with this
command.
Playback stop command.
Can be specified for each
channel.
18/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
CH1
CH0
M7
M6
M5
M4
M3
M2
M1
M0
SLOOP
1
0
0
0
0
0
CH1
CH0
CLOOP
1
0
0
1
0
0
CH1
CH0
1
0
1
0
0
0
CH1
CH0
—
—
—
CV4
CV3
CV2
CV1
CV0
RDSTAT
1
0
1
1
0
0
0
ERR
OUTSTAT
1
1
0
0
0
BUSY/NCR
0
C0
1
1
0
1
0
0
0
0
TM2
TM1
TM0
TSD1
TSD0
BLD2
BLD1
BLD0
1
1
1
1
1
1
1
1
MUON
CVOL
SAFE
ERCL
Description
Silence insertion command.
Use the data of the 2nd byte
to specify the length of
silence. Can be specified
for each channel.
Repeat playback mode
setting command. The
setting is enabled during
playback.
Can be specified for each
channel.
Repeat playback mode
release command. When
the STOP command is input,
repeat playback mode is
released automatically. Can
be specified for each
channel.
Volume setting command.
Use the data of the 2nd byte
to specify volume. Can be
specified for each channel.
Status serial read command.
This command reads the
command status and the
status of the fail safe function
for each channel.
Status output command.
This command outputs the
command status of each
channel from the STATUS
pin.
Fail safe setting command.
Sets settings for power
supply voltage detection,
temperature detection, and
monitoring time.
This command clears error
while the fail safe function is
operating.
19/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
APPLICATION CIRCUIT
At using internal speaker amplifier (speaker output)
( VDDR is only ML22Q563 )
RESETB
CSB
SCK
SI
SO
CBUSYB
ERR
STATUS
MCU
SPM
SPP
speaker
0.1F
SG
AIN
0.1F
DIPH
VPP
TESTI1
VDDL
VDDR
DVDD
SPVDD
15pF
XT
4.096MHz
XTB
0.1 F
DGND
15pF
10 F
10 F
10 F
10 F
5V
0.1 F
SPGND
At using external speaker amplifier (line output)
( VDDR is only ML22Q563 )
RESETB
CSB
SCK
SI
SO
CBUSYB
ERR
STATUS
MCU
SPM
SPP
0.1F
SP-AMP
speaker
SG
0.1F
AIN
0.1F
DIPH
VPP
TESTI1
VDDL
VDDR
DVDD
SPVDD
15pF
XT
0.1 F
4.096MHz
XTB
DGND
15pF
10 F
10 F
10 F
10 F
5V
0.1 F
SPGND
20/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
PACKAGE DIMENSIONS
(Unit: mm)
heat sink area
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
21/22
FEDL2256XDIGEST-04
ML22Q563/ML2256X
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
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The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However,
should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS
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The technical information specified herein is intended only to show the typical functions of and examples of
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license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
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Please be sure to implement in your equipment using the Products safety measures to guard against the
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Copyright
2011 LAPIS Semiconductor Co., Ltd.
22/22
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